April 2002 Preliminary AS7C33512PFD16A AS7C33512PFD18A (R) 3.3V 512K x 16/18 pipeline burst synchronous SRAM Features * Asynchronous output enable control * Available in 100-pin TQFP and 119-pin BGA package * Byte write enables * Multiple chip enables for easy expansion * 3.3V core power supply * 2.5V or 3.3V I/O operation with separate VDDQ * 30 mW typical standby power in power down mode * NTDTM1pipeline architecture available (AS7C33512NTD16A/AS7C33512NTD18A) * Organization: 524,288 words x 16 or 18 bits * Fast clock speeds to 166 MHz in LVTTL/LVCMOS * Fast clock to data access: 3.5/3.8/4.0/5.0 ns * Fast OE access time: 3.5/3.8/4.0/5.0 ns * Fully synchronous register-to-register operation * Single register "Flow-through" option * Dual-cycle deselect - Single-cycle deselect also available (AS7C33512PFS16A/ AS7C33512PFS18A) * Available in both 2 chip enable and 3 chip enable 1. *Pentium(R) is a registered trademark of Intel Corporation. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. - 2 CE part number is AS7C33512PFD16A or AS7C33512PFD18A2 * Pentium(R)1 compatible architecture and timing Logic block diagram LBO CLK CS CLR CLK ADV ADSC ADSP 19 A[18:0] Burst logic Q D CS 19 512K x 16/18 Memory array 17 19 Address register CLK 16/18 16/18 GWE BWb D DQb Q Byte Write registers BWE CLK D DQa Q BWa Byte Write registers CE0 CE1 CE2 D 2 CLK OE Enable Q register CE CLK D ZZ Power down Input registers Output registers CLK CLK Enable Q delay register CLK OE FT 16/18 DQ[a,b] Selection guide -166 -150 -133 -100 Units 6 6.6 7.5 10 ns Maximum pipelined clock frequency 166.7 150 133.3 100 MHz Maximum pipelined clock access time 3.5 3.8 4 5 ns Maximum operating current 475 450 425 325 mA Maximum standby current 130 110 100 90 mA Maximum CMOS standby current (DC) 30 30 30 30 mA Minimum cycle time 4/15/02; 4 v.1.5 Alliance Semiconductor 1 of 14 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C33512PFD16A AS7C33512PFD18A (R) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 Pin arrangement for 3 chip enable TQFP TQFP 14 x 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A17 NC NC VDDQ VSSQ NC DQpa/NC DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC A18 A10 A11 A12 A13 A14 A15 A16 VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQpb/NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC Note: pins 24, 74 are NC for x16. TQFP 14 x 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A17 NC NC VDDQ VSSQ NC DQpa/NC DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb FT VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DQpb/NC NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE0 CE1 NC NC BWb BWa A 18 VDD VSS CLK GWE BWE OE ADSC ADSP ADV A8 A9 Pin arrangement for 2 chip enable TQFP Note: pins 24, 74 are NC for x16. 4/15/02; v.1.5 Alliance Semiconductor 2 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Pin Configuration for 512 x 181 for 119-ball BGA 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC CE2 A ADSC A A NC C NC A A VDD A A NC D DQb NC VSS NC VSS DQPa NC E NC DQb VSS CE1 VSS NC DQa F VDDQ NC VSS OE VSS DQa VDDQ G NC DQb BWb ADV VSS NC DQa H DQb NC VSS GWE VSS DQa NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQb VSS CLK VSS NC DQa L DQb NC VSS NC BWa DQa NC M VDDQ DQb VSS BWE VSS NC VDDQ VSS 2 VSS DQa NC 2 N DQb NC A1 P NC DQPb VSS A0 VSS NC DQa R NC A LBO VDD FT A NC T NC A A NC A A ZZ U VDDQ NC NC NC NC NC VDDQ 1 Note pins 6D and 2P are NC for x16. 2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. 4/15/02; v.1.5 Alliance Semiconductor 3 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Functional description The AS7C33512PFD16A and AS7C33512PFD18A are high performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM) devices organized as 524,288 words x 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology. Timing for this device is compatible with existing Pentium(R) synchronous cache specifications. This architecture is suited for ASIC, DSP (TMS320C6X), and PowerPCTM1-based systems in computing, datacom, instrumentation, and telecommunications systems. Fast cycle times of 6/6.6/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses. Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register. When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes are HIGH. Burst mode is selectable with the LBO input. With LBO unconnected or driven HIGH, burst operations use a Pentium(R) count sequence. With LBO driven LOW the device uses a linear count sequence suitable for PowerPCTM and many other applications. Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/ 18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s). BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW. Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow. * ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC. * WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH). * Master chip select CE0 blocks ADSP, but not ADSC. The AS7C33512PFD16A and AS7C33512PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14x20 mm TQFP packaging 119-ball 14x20 mm BGA. Capacitance Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN Address and control pins VIN = 0V 5 pF I/O capacitance CI/O I/O pins VIN = VOUT = 0V 7 pF Write enable truth table (per byte) GWE BWE BWn WEn L X X T H L L T H H X F* H L H F* Key: X = Don't Care, L = Low, H = High, T=True, F=False; * valid read; n = a,b, WE, WEn = internal write signal Burst Order Starting Address First increment Second increment Third increment Interleaved Burst Order Linear Burst Order LBO=1 01 10 00 11 11 00 10 01 LBO=0 01 10 10 11 11 00 00 01 00 01 10 11 11 10 01 00 Starting Address First increment Second increment Third increment 00 01 10 11 1. PowerPCTM is a trademark International Business Machines Corporation 4/15/02; v.1.5 Alliance Semiconductor 4 of 14 11 00 01 10 AS7C33512PFD16A AS7C33512PFD18A (R) Signal descriptions Signal I/O Properties Description CLK I CLOCK A0-A18 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted. DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active. CE0 I SYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information. CE1, CE2 I SYNC Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock edges when ADSC is active or when CE0 and ADSP are active. ADSP I SYNC Address strobe (processor). Asserted LOW to load a new address or to enter standby mode. ADSC I SYNC Address strobe (controller). Asserted LOW to load a new address or to enter standby mode. ADV I SYNC Burst advance. Asserted LOW to continue burst read/write. GWE I SYNC Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and BW[a,b] control write enable. BWE I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs. BW[a,b] I SYNC Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all BW[a,b] are inactive, the cycle is a read cycle. OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read mode. LBO I STATIC Count mode. When driven HIGH, count sequence follows Intel XOR convention. When driven LOW, count sequence follows linear convention. This signal is internally pulled HIGH. FT I STATIC Flow-through mode.When LOW, enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused. Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock. Absolute maximum ratings Parameter Symbol Min Max Unit VDD, VDDQ -0.5 +4.6 V Input voltage relative to GND (input pins) VIN -0.5 VDD + 0.5 V Input voltage relative to GND (I/O pins) VIN -0.5 VDDQ + 0.5 V Power dissipation PD - 1.8 W DC output current IOUT - 50 mA Storage temperature (plastic) Tstg -65 +150 C Temperature under bias Tbias -65 +135 C Power supply voltage relative to GND Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability. 4/15/02; v.1.5 Alliance Semiconductor 5 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Synchronous truth table CE0 CE1 CE2 ADSP ADSC ADV WEn1 OE Address accessed CLK Operation DQ H X X X L X X X NA L to H Deselect Hi-Z L L X L X X X X NA L to H Deselect Hi-Z L L X H L X X X NA L to H Deselect Hi-Z L X H L X X X X NA L to H Deselect Hi-Z L X H H L X X X NA L to H Deselect Hi-Z L H L L X X X L External L to H Begin read Hi-Z2 L H L L X X X H External L to H Begin read Hi-Z L H L H L X F L External L to H Begin read Hi-Z2 L H L H L X F H External L to H Begin read Hi-Z X X X H H L F L Next L to H Cont. read Q X X X H H L F H Next L to H Cont. read Hi-Z X X X H H H F L Current L to H Suspend read Q X X X H H H F H Current L to H Suspend read Hi-Z H X X X H L F L Next L to H Cont. read Q H X X X H L F H Next L to H Cont. read Hi-Z H X X X H H F L Current L to H Suspend read Q H X X X H H F H Current L to H Suspend read Hi-Z L H L H L X T X External L to H Begin write D3 X X X H H L T X Next L to H Cont. write D H X X X H L T X Next L to H Cont. write D X X X H H H T X Current L to H Suspend write D H X X X H H T X Current L to H Suspend write D 1 See "Write enable truth table" on page 4 for more information. 2 Q in flow through mode 3 For WRITE operation following a READ, OE must be HIGH before the input data set up time and held HIGH throughout the input hold time Key: X = Don't Care, L = Low, H = High. 4/15/02; v.1.5 Alliance Semiconductor 6 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Recommended operating conditions Parameter Symbol Min Nominal Max VDD 3.135 3.3 3.465 VSS 0.0 0.0 0.0 3.3V I/O supply voltage VDDQ 3.135 3.3 3.465 VSSQ 0.0 0.0 0.0 2.5V I/O supply voltage VDDQ 2.35 2.5 2.9 VSSQ 0.0 0.0 0.0 VIH 2.0 - VDD + 0.3 Supply voltage Input Address and control pins voltages1 I/O pins Ambient operating temperature 2 Unit V V V V VIL -0.5 - 0.8 VIH 2.0 - VDDQ + 0.3 VIL -0.52 - 0.8 TA 0 - 70 C Symbol Typical Units 1-layer JA 40 C/W 4-layer JA 22 C/W JC 8 C/W V 1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications. 2 VIL min. = -2.0V for pulse width less than 0.2 x tRC. TQFP thermal resistance Description Conditions Thermal resistance (junction to ambient)1 Thermal resistance (junction to top of case)1 Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 1 This parameter is sampled. DC electrical characteristics -166 Parameter -150 -133 -100 Symbol Test conditions Input leakage current1 |ILI| VDD = Max, VIN = GND to VDD - 2 - 2 - 2 - 2 A Output leakage current |ILO| OE VIH, VDD = Max, VOUT = GND to VDD - 2 - 2 - 2 - 2 A Operating power supply current CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA - 475 - 450 - 425 - 325 mA (Pipelined) Operating power supply current ICC (Flow- CE0 = VIL, CE1 = VIH, CE2 = VIL, f = fMax, IOUT = 0 mA Through) - 325 - 325 - 300 - 300 mA Standby power supply current Output voltage ICC Min Max Min Max Min Max Min Max Unit ISB Deselected, f = fMax, ZZ VIL - 130 - 110 - 100 - 90 ISB1 Deselected, f = 0, ZZ 0.2V all VIN 0.2V or VDD - 0.2V - 30 - 30 - 30 - 30 ISB2 Deselected, f = fMax, ZZ VDD - 0.2V All VIN VIL or VIH - 30 - 30 - 30 - 30 VOL IOL = 8 mA, VDDQ = 3.465V - 0.4 - 0.4 - 0.4 - 0.4 VOH IOH = -4 mA, VDDQ = 3.135V 2.4 - 2.4 - 2.4 - 2.4 - mA 1 LBO pin has an internal pull-up and input leakage = 10 A. Note: ICC given with no output loading. ICC increases with faster cycle times and greater output loading. 4/15/02; v.1.5 Alliance Semiconductor 7 of 14 V AS7C33512PFD16A AS7C33512PFD18A (R) DC electrical characteristics for 2.5V I/O operation -166 Parameter Output leakage current Output voltage -150 -133 -100 Symbol Test conditions Min Max Min Max Min Max Min Max Unit |ILO| OE VIH, VDD = Max, VOUT = GND to VDD -1 1 -1 1 -1 1 -1 1 VOL IOL = 2 mA, VDDQ = 2.65V - 0.7 - 0.7 - 0.7 - 0.7 VOH IOH = -2 mA, VDDQ = 2.35V 1.7 - 1.7 - 1.7 - 1.7 - A V Timing characteristics over operating range -166 -150 -133 -100 Parameter Sym Min Max Min Max Min Max Min Max Unit Notes1 - 166 - 150 - 133 - 100 MHz Clock frequency fMax Cycle time (pipelined mode) tCYC 6 - 6.6 - 7.5 - 10 - ns Cycle time (flow-through mode) tCYCF 10 - 10 - 12 - 12 - ns Clock access time (pipelined mode) tCD - 3.5 - 3.8 - 4.0 - 5.0 ns Clock access time (pipelined mode)- 3.3V VDDQ tCD 3.3V 3.5 3.8 4.0 5.0 ns Clock access time (pipelined mode)- 2.5V VDDQ tCD 2.5V 4.0 4.3 4.5 5.0 ns Output enable LOW to data valid tOE - 3.5 - 3.8 - 4.0 - 5.0 ns Clock HIGH to output Low Z tLZC 0 - 0 - 0 - 0 - ns 2,3,4 Data output invalid from clock HIGH tOH 1.5 - 1.5 - 1.5 - 1.5 - ns 2 Output enable LOW to output Low Z tLZOE 0 - 0 - 0 - 0 - ns 2,3,4 Output enable HIGH to output High Z tHZOE - 3.5 - 3.8 - 4.0 - 4.5 ns 2,3,4 Clock HIGH to output High Z tHZC - 3.5 - 3.8 - 4.0 - 5.0 ns 2,3,4 Output enable HIGH to invalid output tOHOE 0 - 0 - 0 - 0 - ns Clock HIGH pulse width tCH 2.4 - 2.5 - 2.5 - 3.5 - ns 5 Clock LOW pulse width tCL 2.4 - 2.5 - 2.5 - 3.5 - ns 5 Address setup to clock HIGH tAS 1.5 - 1.5 - 1.5 - 2.0 - ns 6 Data setup to clock HIGH tDS 1.5 - 1.5 - 1.5 - 2.0 - ns 6 Write setup to clock HIGH tWS 1.5 - 1.5 - 1.5 - 2.0 - ns 6,7 Chip select setup to clock HIGH tCSS 1.5 - 1.5 - 1.5 - 2.0 - ns 6,8 Address hold from clock HIGH tAH 0.5 - 0.5 - 0.5 - 0.5 - ns 6 Data hold from clock HIGH tDH 0.5 - 0.5 - 0.5 - 0.5 - ns 6 Write hold from clock HIGH tWH 0.5 - 0.5 - 0.5 - 0.5 - ns 6,7 Chip select hold from clock HIGH tCSH 0.5 - 0.5 - 0.5 - 0.5 - ns 6,8 ADV setup to clock HIGH tADVS 1.5 - 1.5 - 1.5 - 2.0 - ns 6 ADSP setup to clock HIGH tADSPS 1.5 - 1.5 - 1.5 - 2.0 - ns 6 ADSC setup to clock HIGH tADSCS 1.5 - 1.5 - 1.5 - 2.0 - ns 6 ADV hold from clock HIGH tADVH 0.5 - 0.5 - 0.5 - 0.5 - ns 6 ADSP hold from clock HIGH tADSPH 0.5 - 0.5 - 0.5 - 0.5 - ns 6 ADSC hold from clock HIGH tADSCH 0.5 - 0.5 - 0.5 - 0.5 - ns 6 1 "Notes" column refers to "notes" on page 12 4/15/02; v.1.5 Alliance Semiconductor 8 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Key to switching waveforms Rising input Falling input Undefined/don't care Timing waveform of read cycle tCH tCYC tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC tAS LOAD NEW ADDRESS tAH Address A1 A2 A3 tWS tWH GWE, BWE tCSS tCSH CE0, CE2 CE1 tADVS tADVH ADV OE tCD tHZOE tOH ADV INSERTS WAIT STATES tHZC DOUT (pipelined mode) tOE tLZOE DOUT (flow-through mode) Q(A1) Q(A1) Q(A2) Q(A2Y01) Q(A2Y01) Q(A2Y10) Q(A2Y10) Q(A2Y11) Q(A2Y11) Q(A3) Q(A3) Q(A3Y01) Q(A3Y01) Q(A3Y10) Q(A3Y10) Q(A3Y11) tHZC Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. BW[a:b] is don't care. 4/15/02; v.1.5 Alliance Semiconductor 9 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Timing waveform of write cycle tCYC tCH tCL CLK tADSPS tADSPH ADSP tADSCS tADSCH ADSC ADSC LOADS NEW ADDRESS tAS tAH Address A1 A3 A2 tWS tWH BWE BWa,b tCSS tCSH CE0, CE2 CE1 tADVS ADV SUSPENDS BURST tADVH ADV OE tDS tDH Data In D(A1) D(A2) D(A2Y01) D(A2Y01) D(A2Y10) D(A2Y11) D(A3) D(A3Y01) D(A3Y10) Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. 4/15/02; v.1.5 Alliance Semiconductor 10 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Timing waveform of read/write cycle tCYC tCH tCL CLK tADSPS tADSPH ADSP tAS tAH Address A2 A1 A3 tWS tWH . . GWE CE0, CE2 CE1 tADVS tADVH ADV OE tDS tDH D(A2) DIN tLZC tHZOE tCD Q(A1) DOUT (pipeline mode) tOH tLZOE tOE Q(A3) Q(A3Y01) Q(A3Y10) Q(A3Y11) tCDF DOUT (flow-through mode) Q(A1) Q(A3Y01) Q(A3Y10) Q(A3Y11) Note: Y = XOR when LBO = HIGH/No Connect; Y = ADD when LBO = LOW. 4/15/02; v.1.5 Alliance Semiconductor 11 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) AC test conditions * Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. * Input pulse level: GND to 3V. See Figure A. Thevenin equivalent: * Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. +3.3V for 3.3V I/O; /+2.5V for 2.5V I/O * Input and output timing reference levels: 1.5V. Z0 = 50 +3.0V 90% 10% GND 90% 10% Figure A: Input waveform DOUT 50 VL = 1.5V for 3.3V I/O; 30 pF* = VDDQ/2 for 2.5V I/O Figure B: Output load (A) DOUT 353 / 1538 319 / 1667 5 pF* GND *including scope and jig capacitance Figure C: Output load (B) Notes: 1) For test conditions, see "AC Test Conditions", Figures A, B, C 2) This parameter measured with output load condition in Figure C. 3) This parameter is sampled, but not 100% tested. 4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage. 5) tCH measured HIGH above VIH and tCL measured as LOW below VIL 6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled. 7) Write refers to GWE, BWE, BW[a,b]. 8) Chip select refers to CE0, CE1, CE2. 4/15/02; v.1.5 Alliance Semiconductor 12 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Package Dimensions 100-pin quad flat pack (TQFP) Hd TQFP Min Max A1 A2 b c D E e Hd He L L1 a 0.05 0.15 1.35 1.45 0.22 0.38 0.09 0.20 13.90 14.10 19.90 20.10 0.65 nominal 15.90 16.10 21.90 22.10 0.45 0.75 D b e He E 1.00 nominal 0 c 7 Dimensions in millimeters L1 L A1 A2 119-ball BGA (ball grid array) All measurements are in mm. Min Typ Max 1.27 A B 13.90 14.00 14.10 7.62 B1 C 21.90 22.00 22.10 20.32 C1 0.60 0.75 0.90 D 1.70 E 0.56 E1 0.60 0.70 E2 0.50 4/15/02; v.1.5 Alliance Semiconductor 13 of 14 AS7C33512PFD16A AS7C33512PFD18A (R) Ordering information Package -166 MHz -150 MHz -133 MHz -100 MHz x16 TQFP AS7C33512PFD16A166TQC AS7C33512PFD16A150TQC AS7C33512PFD16A133TQC AS7C33512PFD16A100TQC x16 TQFP AS7C33512PFD16A166TQI AS7C33512PFD16A150TQI AS7C33512PFD16A133TQI AS7C33512PFD16A100TQI x18 TQFP AS7C33512PFD18A166TQC AS7C33512PFD18A150TQC AS7C33512PFD18A133TQC AS7C33512PFD18A100TQC x18 TQFP AS7C33512PFD18A166TQI AS7C33512PFD18A150TQI AS7C33512PFD18A133TQI AS7C33512PFD18A100TQI x16 BGA AS7C33512PFD16A2166BC AS7C33512PFD16A2150BC AS7C33512PFD16A2133BC AS7C33512PFD16A2100BC x16 BGA AS7C33512PFD16A2166BI AS7C33512PFD16A2150BI AS7C33512PFD16A2133BI AS7C33512PFD16A2100BI x18 BGA AS7C33512PFD18A2166BC AS7C33512PFD18A2150BC AS7C33512PFD18A2133BC AS7C33512PFD18A2100BC x18 BGA AS7C33512PFD18A2166BI AS7C33512PFD18A2150BI AS7C33512PFD18A2133BI AS7C33512PFD18A2100BI x16 TQFP (2 CE) AS7C33512PFD16A2166TQC AS7C33512PFD16A2150TQC AS7C33512PFD16A2133TQC AS7C33512PFD16A2100TQC x16 TQFP (2 CE) AS7C33512PFD16A2166TQI AS7C33512PFD16A2150TQI AS7C33512PFD16A2133TQI AS7C33512PFD16A2100TQI x18 TQFP (2 CE) AS7C33512PFD18A2166TQC AS7C33512PFD18A2150TQC AS7C33512PFD18A2133TQC AS7C33512PFD18A2100TQC x18 TQFP (2 CE) AS7C33512PFD18A2166TQI AS7C33512PFD18A2150TQI AS7C33512PFD18A2133TQI AS7C33512PFD18A2100TQI Part numbering guide AS7C 33 512 PF D 16/18 A blank or 2 -XXX TQ or B C/I 1 2 3 4 5 6 7 8 9 10 11 1.Alliance Semiconductor SRAM prefix 2.Operating voltage: 33=3.3V 3.Organization: 512=512K 4.Pipeline-Flowthrough (each device works in both modes) 5.Deselect: D=Dual cycle deselect 6.Organization: 16=x16; 18=x18 7.Production version: A=first production version 8. Blank is the default:3 CE (chip enable), 2 is 2 CE (2 chip enable) 9. Clock speed (MHz) 10. Package type: TQ=TQFP; B=BGA 11. Operating temperature: C=Commercial (0 C to 70 C); I=Industrial (-40 C to 85 C) 4/15/02; v.1.5 Alliance Semiconductor 14 of 14 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. 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