April 2002
Preliminary
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C33512PFD16A
AS7C33512PFD18A
3.3V 512K × 16/18 pipeline burst synchronous SRAM
4/15/02; 4 v.1.5 Alliance Semiconductor 1 of 14
Features
• Organization: 524,288 words × 16 or 18 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
•Fast OE
access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” option
• Dual-cycle deselect
- Single-cycle deselect also available (AS7C33512PFS16A/
AS7C33512PFS18A)
• Available in both 2 chip enable and 3 chip enable
- 2 CE part number is AS7C33512PFD16A or AS7C33512PFD18A2
•Pentium®
1 compatible architecture and timing
• Asynchronous output enable control
• Available in 100-pin TQFP and 119-pin BGA package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• 30 mW typical standby power in power down mode
•NTD™
1pipeline architecture available
(AS7C33512NTD16A/AS7C33512NTD18A)
1. *Pentium® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks men-
tioned in this document are the property of their respective owners.
Selection guide
–166 –150 –133 –100 Units
Minimum cycle time 6 6.6 7.5 10 ns
Maximum pipelined clock frequency 166.7 150 133.3 100 MHz
Maximum pipelined clock access time 3.5 3.8 4 5 ns
Maximum operating current 475 450 425 325 mA
Maximum standby current 130 110 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
19
17
19
A[18:0]
19
Address
DQ
CS
CLK
register
512K × 16/18
Memory
array
16/18
16/18
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
2
CE0
CE1
CE2
BWb
BWa
OE
ZZ
OE
FT
CLK CLK
BWE
GWE
16/18
DQ[a,b]
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AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 2 of 14
Pin arrangement for 3 chip enable TQFP
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A18
A10
A11
A12
A13
A14
A15
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
NC
NC
BWb
BWa
CE2
V
DD
V
SS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
A16
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQb
DQb
V
SSQ
V
DDQ
DQb
DQb
FT
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SSQ
DQb
DQb
DQpb/NC
NC
V
SSQ
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DDQ
V
SSQ
NC
DQpa/NC
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
VSS
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
V
DD
TQFP 14 × 20mm
Note: pins 24, 74 are NC for ×16.
LBO
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A6
A7
CE0
CE1
NC
NC
BWb
BWa
A 18
V
DD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A8
A9
A16
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
FT
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQpb/NC
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
VDDQ
VSSQ
NC
DQpa/NC
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
NC
VDD
TQFP 14 × 20mm
Pin arrangement for 2 chip enable TQFP
Note: pins 24, 74 are NC for ×16.
®
AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 3 of 14
Pin Configuration for 512 x 181 for 119-ball BGA
1 Note pins 6D and 2P are NC for x16.
1234567
AVDDQ AAADSPAAV
DDQ
BNC CE2 A ADSC AANC
CNC A A VDD AANC
DDQbNC VSS NC VSS DQPa NC
ENC DQb VSS CE1 VSS NC DQa
FVDDQ NC VSS OE VSS DQa VDDQ
GNC DQb BWb ADV VSS NC DQa
HDQbNC VSS GWE VSS DQa NC
JVDDQ VDD NC VDD NC VDD VDDQ
KNC DQb VSS CLK VSS NC DQa
LDQb NC VSS NC BWa DQa NC
MVDDQ DQb VSS BWE VSS NC VDDQ
NDQb NC VSS A12
2 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst
counter if burst is desired.
VSS DQa NC
PNC DQPb VSS A02VSS NC DQa
RNC A LBO VDD FT ANC
TNC A A NC A A ZZ
UVDDQ NC NC NC NC NC VDDQ
®
AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 4 of 14
Functional description
The AS7C33512PFD16A and AS7C33512PFD18A are high performance CMOS 8-Mbit synchronous Static Random Access Memory (SRAM)
devices organized as 524,288 words × 16 or 18 bits and incorporate a pipeline for highest frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is suited for ASIC, DSP
(TMS320C6X), and PowerPC™1-based systems in computing, datacom, instrumentation, and telecommunications systems.
Fast cycle times of 6/6.6/7.5/10 ns with clock access times (tCD) of 3.5/3.8/4.0/5.0 ns enable 166, 150, 133 and 100 MHz bus frequencies.
Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC),
or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register.
When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data
accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and driven
on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all
subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both address strobes
are HIGH. Burst mode is selectable with the
LBO
input. With
LBO
unconnected or driven HIGH, burst operations use a Pentium® count
sequence. With
LBO
driven LOW the device uses a linear count sequence suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 16/
18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when GWE is HIGH, one or more bytes may be written by asserting
BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled LOW. Address is incremented
internally to the next burst address if BWn and ADV are sampled LOW.
Read or write cycles may also be initiated with
ADSC
instead of
ADSP
. The differences between cycles initiated with
ADSC
and
ADSP
follow.
• ADSP must be sampled HIGH when
ADSC
is sampled LOW to initiate a cycle with
ADSC
.
•
WE
signals are sampled on the clock edge that samples
ADSC
LOW (and
ADSP
HIGH).
• Master chip select
CE0
blocks
ADSP
, but not
ADSC
.
The AS7C33512PFD16A and AS7C33512PFD18A operate from a 3.3V supply. I/Os use a separate power supply that can operate at 2.5V or
3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging 119-ball 14×20 mm BGA.
Key: X = Don’t Care, L = Low, H = High, T=True, F=False; * valid read; n = a,b, WE, WEn = internal write signal
1. PowerPC™ is a trademark International Business Machines Corporation
Capacitance
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN Address and control pins VIN = 0V 5 pF
I/O capacitance CI/O I/O pins VIN = VOUT = 0V 7 pF
Write enable truth table (per byte)
GWE BWE BWn WEn
LXXT
HLLT
HHXF*
HLHF*
Burst Order
Interleaved Burst Order
LBO
=1
Linear Burst Order
LBO
=0
Starting Address 00 01 10 11 Starting Address 00 01 10 11
First increment 01 00 11 10 First increment 01 10 11 00
Second increment 10 11 00 01 Second increment 10 11 00 01
Third increment 11 10 01 00 Third increment 11 00 01 10
®
AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 5 of 14
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions may affect reliability.
Signal descriptions
Signal I/O Properties Description
CLK I CLOCK Clock. All inputs except OE,
FT
, ZZ,
LBO
are synchronous to this clock.
A0–A18 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active.
CE0 ISYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.
CE1, CE2 ISYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on clock edges
when ADSC is active or when CE0 and ADSP are active.
ADSP I SYNC Address strobe (processor). Asserted LOW to load a new address or to enter standby mode.
ADSC I SYNC Address strobe (controller). Asserted LOW to load a new address or to enter standby mode.
ADV I SYNC Burst advance. Asserted LOW to continue burst read/write.
GWE ISYNC
Global write enable. Asserted LOW to write all 16/18 bits. When HIGH, BWE and BW[a,b]
control write enable.
BWE I SYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a,b] inputs.
BW[a,b] ISYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE = LOW.
If any of BW[a,b] is active with GWE = HIGH and BWE = LOW the cycle is a write cycle. If all
BW[a,b] are inactive, the cycle is a read cycle.
OE IASYNC
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read
mode.
LBO ISTATIC
Count mode. When driven HIGH, count sequence follows Intel XOR convention. When
driven LOW, count sequence follows linear convention. This signal is internally pulled HIGH.
FT
ISTATIC
Flow-through mode.When LOW, enables single register flow-through mode. Connect to VDD
if unused or for pipelined operation.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V
Power dissipation PD–1.8W
DC output current IOUT –50mA
Storage temperature (plastic) Tstg –65 +150 °C
Temperature under bias Tbias –65 +135 °C
®
AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 6 of 14
Key: X = Don’t Care, L = Low, H = High.
Synchronous truth table
CE0 CE1 CE2 ADSP ADSC ADV
WEn
1
1 See “Write enable truth table” on page 4 for more information.
OE
Address
accessed CLK Operation DQ
H X X X L X X X NA L to H Deselect Hi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Hi−Z2
2 Q in flow through mode
L H L L X X X H External L to H Begin read Hi−Z
LHLHLX F L ExternalL to HBegin readHi
−Z2
LHLHLX F H ExternalL to HBegin readHi
−Z
X X X H H L F L Next L to H Cont. read Q
X X X H H L F H Next L to H Cont. read Hi−Z
X X X H H H F L Current L to H Suspend read Q
X X X H H H F H Current L to H Suspend read Hi−Z
H X X X H L F L Next L to H Cont. read Q
H X X X H L F H Next L to H Cont. read Hi−Z
H X X X H H F L Current L to H Suspend read Q
H X X X H H F H Current L to H Suspend read Hi−Z
LHLHLX T X ExternalL to HBegin write D
3
3 For WRITE operation following a READ,
OE
must be HIGH before the input data set up time and held HIGH throughout the input hold time
X X X H H L T X Next L to H Cont. write D
H X X X H L T X Next L to H Cont. write D
X X X H H H T X Current L to H Suspend write D
H X X X H H T X Current L to H Suspend write D
®
AS7C33512PFD16A
AS7C33512PFD18A
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Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VDD 3.135 3.3 3.465 V
VSS 0.0 0.0 0.0
3.3V I/O supply
voltage
VDDQ 3.135 3.3 3.465 V
VSSQ 0.0 0.0 0.0
2.5V I/O supply
voltage
VDDQ 2.35 2.5 2.9 V
VSSQ 0.0 0.0 0.0
Input voltages1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
Address and
control pins
VIH 2.0 – VDD + 0.3 V
VIL –0.52
2 VIL min. = –2.0V for pulse width less than 0.2 × tRC.
–0.8
I/O pins VIH 2.0 – VDDQ + 0.3 V
VIL –0.52–0.8
Ambient operating temperature TA0–70
°C
TQFP thermal resistance
Description Conditions Symbol Ty p i c a l Units
Thermal resistance
(junction to ambient)1
1 This parameter is sampled.
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
1–layer θJA 40 °C/W
4–layer θJA 22 °C/W
Thermal resistance
(junction to top of case)1θJC 8°C/W
DC electrical characteristics
Parameter Symbol Test conditions
–166 –150 –133 –100
UnitMin Max Min Max Min Max Min Max
Input leakage
current1
1 LBO pin has an internal pull-up and input leakage = ±10 µA.
Note: ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
|ILI|V
DD = Max, VIN = GND to VDD –2–2–2–2µA
Output leakage
current |ILO|OE ≥ VIH, VDD = Max,
VOUT = GND to VDD –2–2–2–2µA
Operating power
supply current
ICC
(Pipelined)
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA – 475 – 450 – 425 – 325 mA
Operating power
supply current
ICC (Flow-
Through)
CE0 = VIL, CE1 = VIH, CE2 = VIL,
f = fMax, IOUT = 0 mA – 325 – 325 – 300 – 300 mA
Standby power
supply current
ISB Deselected, f = fMax, ZZ ≤ VIL – 130 – 110 – 100 – 90
mA
ISB1 Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V –30–30–30–30
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
– 0.2V
All VIN ≤ VIL or ≥ VIH –30–30–30–30
Output voltage VOL IOL = 8 mA, VDDQ = 3.465V – 0.4 – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA, VDDQ = 3.135V 2.4 – 2.4 – 2.4 – 2.4 –
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AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 8 of 14
DC electrical characteristics for 2.5V I/O operation
Parameter Symbol Test conditions
–166 –150 –133 –100
UnitMin Max Min Max Min Max Min Max
Output leakage
current |ILO|OE ≥ VIH, VDD = Max,
VOUT = GND to VDD –11–11–11–11µA
Output voltage VOL IOL = 2 mA, VDDQ = 2.65V –0.7–0.7–0.7–0.7V
VOH IOH = –2 mA, VDDQ = 2.35V 1.7 – 1.7 – 1.7 – 1.7 –
Timing characteristics over operating range
Parameter Sym
–166 –150 –133 –100
Unit Notes1
1 “Notes” column refers to “notes” on page 12
Min Max Min Max Min Max Min Max
Clock frequency fMax – 166 – 150 – 133 – 100 MHz
Cycle time (pipelined mode) tCYC 6 – 6.6 – 7.5 – 10 – ns
Cycle time (flow-through mode) tCYCF 10 – 10 – 12 – 12 – ns
Clock access time (pipelined mode) tCD –3.5–3.8–4.0–5.0ns
Clock access time (pipelined mode)- 3.3V VDDQ
tCD 3.3V - 3.5 - 3.8 - 4.0 - 5.0 ns
Clock access time (pipelined mode)- 2.5V VDDQ
tCD 2.5V - 4.0 - 4.3 - 4.5 - 5.0 ns
Output enable LOW to data valid tOE –3.5–3.8–4.0–5.0ns
Clock HIGH to output Low Z tLZC 0 – 0 – 0 – 0 – ns 2,3,4
Data output invalid from clock HIGH tOH 1.5 – 1.5 – 1.5 – 1.5 – ns 2
Output enable LOW to output Low Z tLZOE 0 – 0 – 0 – 0 – ns 2,3,4
Output enable HIGH to output High Z tHZOE –3.5–3.8–4.0–4.5ns2,3,4
Clock HIGH to output High Z tHZC –3.5–3.8–4.0–5.0ns2,3,4
Output enable HIGH to invalid output tOHOE 0–0–0–0–ns
Clock HIGH pulse width tCH 2.4 – 2.5 – 2.5 – 3.5 – ns 5
Clock LOW pulse width tCL 2.4 – 2.5 – 2.5 – 3.5 – ns 5
Address setup to clock HIGH tAS 1.5 – 1.5 – 1.5 – 2.0 – ns 6
Data setup to clock HIGH tDS 1.5 – 1.5 – 1.5 – 2.0 – ns 6
Write setup to clock HIGH tWS 1.5 – 1.5 – 1.5 – 2.0 – ns 6,7
Chip select setup to clock HIGH tCSS 1.5 – 1.5 – 1.5 – 2.0 – ns 6,8
Address hold from clock HIGH tAH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Data hold from clock HIGH tDH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
Write hold from clock HIGH tWH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,7
Chip select hold from clock HIGH tCSH 0.5 – 0.5 – 0.5 – 0.5 – ns 6,8
ADV setup to clock HIGH tADVS 1.5 – 1.5 – 1.5 – 2.0 – ns 6
ADSP setup to clock HIGH tADSPS 1.5 – 1.5 – 1.5 – 2.0 – ns 6
ADSC setup to clock HIGH tADSCS 1.5 – 1.5 – 1.5 – 2.0 – ns 6
ADV hold from clock HIGH tADVH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
ADSP hold from clock HIGH tADSPH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
ADSC hold from clock HIGH tADSCH 0.5 – 0.5 – 0.5 – 0.5 – ns 6
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Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
BW[a:b] is don’t care.
Undefined/don’t careFalling inputRising input
tCYC
tCH tCL
tADSPS
tADSPH
tAS
tAH
tWS
tADVS
tOH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
DOUT
tCSS
tCSH
tHZC
tCD
tWH
tADVH
tHZOE
tADSCS
tADSCH
LOAD NEW ADDRESS
ADV INSERTS WAIT STATES
Q(A2Ý10)
Q(A2Ý11) Q(A3)
Q(A2)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A1)
A2A1 A3
CE1
(pipelined mode)
DOUT Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A3Ý11)
Q(A1)
(flow-through mode)
tHZC
tOE
tLZOE
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Timing waveform of write cycle
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
tCYC
tCL
tADSPS
tADSPH
tADSCS
tADSCH
tAS
tAH
tWS
tWH
tCSS
tADVS
tDS
tDH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Data In
tCSH
tADVH
D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
D(A1) D(A2Ý11)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1 A2 A3
tCH
CE1
BWa,b
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4/15/02; v.1.5 Alliance Semiconductor 11 of 14
Timing waveform of read/write cycle
Note: Ý = XOR when LBO = HIGH/No Connect; Ý = ADD when LBO = LOW.
tCH
tCYC
tCL
tADSPS
tADSPH
tAS
tAH
tWS
tWH
tADVS
tDS
tDH
tOH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
DIN
DOUT
tLZC
tADVH
tLZOE
tOE
tCD
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1 A2 A3
CE1
tHZOE
(pipeline mode)
DOUT Q(A1)
Q(A3Ý01) Q(A3Ý10)
(flow-through mode)
tCDF
Q(A3Ý11)
.
.
®
AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 12 of 14
AC test conditions
Z0 = 50
Ω
DOUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
for 2.5V I/O
Notes:
1) For test conditions, see “AC Test Conditions”, Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) tHZOE is less than tLZOE and tHZC is less than tLZC at any given temperature and voltage.
5) tCH measured HIGH above VIH and tCL measured as LOW below VIL
6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must mee
t
the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to GWE, BWE, BW[a,b].
8) Chip select refers to CE0, CE1, CE2.
353
Ω / 1538Ω
5 pF*
319
Ω / 1667Ω
DOUT
GND
Figure C: Output load (B)
*including scope
and jig capacitance
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
®
AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 13 of 14
Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b0.22 0.38
c0.09 0.20
D13.90 14.10
E19.90 20.10
e0.65 nominal
Hd 15.90 16.10
He 21.90 22.10
L0.45 0.75
L1 1.00 nominal
a0°7°
Dimensions in millimeters
A1 A2
L1
L
c
He E
Hd
D
b
e
α
All measurements are in
mm.
Min Ty p Max
A-1.27-
B13.90 14.00 14.10
B1 -7.62-
C21.90 22.00 22.10
C1 - 20.32 -
D0.60 0.75 0.90
E--1.70
E1 -0.56-
E2 0.50 0.60 0.70
119-ball BGA (ball grid array)
AS7C33512PFD16A
AS7C33512PFD18A
4/15/02; v.1.5 Alliance Semiconductor 14 of 14
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks
of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties
related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not
convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-
supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes
all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
®
1.Alliance Semiconductor SRAM prefix
2.Operating voltage: 33=3.3V
3.Organization:
512
=
512
K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: D=Dual cycle deselect
6.Organization: 16=x16; 18=x18
7.Production version: A=first production version
8. Blank is the default:3 CE (chip enable), 2 is 2 CE (2 chip enable)
9. Clock speed (MHz)
10. Package type: TQ=TQFP; B=BGA
11. Operating temperature: C=Commercial (
0
°
C to 70
°
C);
I=Industrial (
-40
°
C to 85
°
C)
Ordering information
Package –166 MHz –150 MHz –133 MHz –100 MHz
x16 TQFP
AS7C33512PFD16A-
166TQC
AS7C33512PFD16A-
150TQC
AS7C33512PFD16A-
133TQC
AS7C33512PFD16A-
100TQC
x16 TQFP
AS7C33512PFD16A-
166TQI
AS7C33512PFD16A-
150TQI
AS7C33512PFD16A-
133TQI
AS7C33512PFD16A-
100TQI
x18 TQFP
AS7C33512PFD18A-
166TQC
AS7C33512PFD18A-
150TQC
AS7C33512PFD18A-
133TQC
AS7C33512PFD18A-
100TQC
x18 TQFP
AS7C33512PFD18A-
166TQI
AS7C33512PFD18A-
150TQI
AS7C33512PFD18A-
133TQI
AS7C33512PFD18A-
100TQI
x16 BGA
AS7C33512PFD16A2-
166BC
AS7C33512PFD16A2-
150BC
AS7C33512PFD16A2-
133BC
AS7C33512PFD16A2-
100BC
x16 BGA
AS7C33512PFD16A2-
166BI
AS7C33512PFD16A2-
150BI
AS7C33512PFD16A2-
133BI
AS7C33512PFD16A2-
100BI
x18 BGA
AS7C33512PFD18A2-
166BC
AS7C33512PFD18A2-
150BC
AS7C33512PFD18A2-
133BC
AS7C33512PFD18A2-
100BC
x18 BGA
AS7C33512PFD18A2-
166BI
AS7C33512PFD18A2-
150BI
AS7C33512PFD18A2-
133BI
AS7C33512PFD18A2-
100BI
x16 TQFP
(2 CE)
AS7C33512PFD16A2-
166TQC
AS7C33512PFD16A2-
150TQC
AS7C33512PFD16A2-
133TQC
AS7C33512PFD16A2-
100TQC
x16 TQFP
(2 CE)
AS7C33512PFD16A2-
166TQI
AS7C33512PFD16A2-
150TQI
AS7C33512PFD16A2-
133TQI
AS7C33512PFD16A2-
100TQI
x18 TQFP
(2 CE)
AS7C33512PFD18A2-
166TQC
AS7C33512PFD18A2-
150TQC
AS7C33512PFD18A2-
133TQC
AS7C33512PFD18A2-
100TQC
x18 TQFP
(2 CE)
AS7C33512PFD18A2-
166TQI
AS7C33512PFD18A2-
150TQI
AS7C33512PFD18A2-
133TQI
AS7C33512PFD18A2-
100TQI
Part numbering guide
AS7C 33 512 PF D16/18 Ablank or 2 –XXX TQ or B C/I
1
23
4
5
678910
11
