74VHC14MTC-NL - Fairchild Semiconductor Corporation

74VHC14

Hex Schmitt Inverter

General Description

The VHC14 is an advanced high speed CMOS Hex

Schmitt Inverter fabricated with silicon gate CMOS technol-

ogy. It achieves the high speed operation similar to equiva-

lent Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. Pin configuration and function are the

same as the VHC04 but the inputs have hysteresis

between the positive-going and negative-going input

thresholds, which are capable of transforming slowly

changing input signals into sharply defined, jitter-free out-

put signals, thus providing greater noise margin than con-

ventional inverters.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply volt-

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery back up. This cir-

cuit prevents device destruction due to mismatched supply

and input voltages.

Features

■High Speed: tPD = 5.5 ns (typ) at VCC = 5V

■Low power dissipation: ICC = 2 μA (Max) at TA = 25°C

■High noise immunity: VNIH = VNIL = 28% VCC (Min)

■Power down protection is provided on all inputs

■Low noise: VOLP = 0.8V (Max)

■Pin and function compatible with 74HC14

Ordering Code:

Order Number Package

Number Package Description

74VHC14M

(Note 1)

M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC14MX_NL

(Note 2)

M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC14SJ

(Note 1)

M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC14MTC

(Note 1)

MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC14MTC_NL

(Note 3)

MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC14MTCX_NL

(Note 2)

MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

74VHC14N

(Obsolete)

N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Pb-Free package per JEDEC J-STD-020B.

Note 1: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Note 2: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.

Note 3: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B).

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Logic Symbol/s

IEEE/IEC

Pin Descriptions

Pin Names Description

AnInputs

OnOutputs

Connection Diagram/s

Truth Table/s

A O

L H

H L

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Absolute Maximum Ratings(Note 4)

Supply Voltage (VCC)−0.5V to +7.0V

DC Input Voltage (VIN)−0.5V to +7.0V

DC Output Voltage (VOUT)−0.5V to VCC + 0.5V

Input Diode Current (IIK)−20 mA

Output Diode Current (IOK)±20 mA

DC Output Current (IOUT)±25 mA

DC VCC/GND Current (ICC)±50 mA

Storage Temperature (TSTG)−65°C to +150°C

Lead Temperature (TL)

Soldering (10 seconds) 260°C

Recommended Operating

Conditions (Note 5)

Supply Voltage (VCC)+2.0V to +5.5V

Input Voltage (VIN)0V to +5.5V

Output Voltage (VOUT)0V to VCC

Operating Temperature (TOPR)−40°C to +85°C

Note 4: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. The data book specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 5: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Symbol Parameter VCC

TA = 25°C TA = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

VPPositive Threshold Voltage 3.0 2.20 2.20

4.5 3.15 3.15 V

5.5 3.85 3.85

VNNegative Threshold Voltage 3.0 0.90 0.90

4.5 1.35 1.35 V

5.5 1.65 1.65

VHHysteresis Voltage 3.0 0.30 1.20 0.30 1.20

4.5 0.40 1.40 0.40 1.40 V

5.5 0.50 1.60 0.50 1.60

VOH HIGH Level Output Voltage 2.0 1.9 2.0 1.9 VIN =VIL

3.0 2.9 3.0 2.9 V IOH = −50 μA

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH = −4 mA

4.5 3.94 3.80 IOH = −8 mA

VOL LOW Level Output Voltage 2.0 0.0 0.1 0.1 VIN = VIH

3.0 0.0 0.1 0.1 V IOL = 50 μA

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL = 4 mA

4.5 0.36 0.44 IOL = 8 mA

IIN Input Leakage Current 0–5.5 ±0.1 ±1.0 μA VIN = 5.5V or GND

ICC Quiescent Supply Current 5.5 2.0 20.0 μA VIN = VCC or GND

Noise Characteristics

Symbol Parameter VCC

TA = 25°CUnits Conditions

Typ Limits

VOLP

(Note 6)

Quiet Output Maximum Dynamic VOL 5.0 0.4 0.8 VCL = 50 pF

VOLV

(Note 6)

Quiet Output Minimum Dynamic VOL 5.0 −0.4 −0.8 VCL = 50 pF

VIHD

(Note 6)

Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 VCL = 50 pF

VILD

(Note 6)

Maximum LOW Level Dynamic Input Voltage 5.0 1.5 VCL = 50 pF

Note 6: Parameter guaranteed by design.

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AC Electrical Characteristics

Symbol Parameter VCC

TA = 25°C TA = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

tPLH Propagation Delay 3.3 ± 0.3 8.3 12.8 1.0 15.0 ns CL = 15 pF

tPHL Time 10.8 16.3 1.0 18.5 CL = 50 pF

5.0 ± 0.5 5.5 8.6 1.0 10.0 ns CL = 15 pF

7.0 10.6 1.0 12.0 CL = 50 pF

CIN Input Capacitance 410 10 pF VCC = Open

CPD Power Dissipation Capacitance 21 pF (Note 7)

Note 7: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average

operating current can be obtained by the equation: ICC (Opr) = CPD * VCC * fIN + ICC/6 (per Gate)

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Physical Dimensions

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PAC KAG E CONFO RMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X 45°

0.10

BCA

14 B

SEE DETAIL A

5.60

0.65

1.70 1.27

8.75

8.50

7.62

6.00 4.00

3.80

(0.33)

1.27 0.51

0.35

1.75 MAX

1.50

1.25

0.25

0.10

0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

0.50

0.25

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

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Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

F. DRAWING FILE NAME: MTC14REV6

R0.09 min

12.00°

TOP & BOTTOM

0.43 TYP

1.00

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

R0.09min

E. LANDPATTERN STANDARD: SOP65P640X110-14M

0.65

6.10

1.65

0.45

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

B. DIMENSIONS ARE IN MILLIMETERS

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14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC14

14 8

NOTES: UNLESS OTHERWISE SPECIFIED

THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BA

B) ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR EXTRUSIONS.

D) DIMENSIONS AND TOLERANCES PER

ASME Y14.5-1994

E) DRAWING FILE NAME: MKT-N14AREV7

6.60

6.09

8.12

7.62

0.35

0.20

19.56

18.80

3.56

3.30 5.33 MAX

0.38 MIN

1.77

1.14

0.58

0.35 2.54

3.81

3.17 8.82

(1.74)

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14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

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