90
80
70
60
50
40
30
20
10
0
01234
Load Current (A)
Efficiency (%)
VOUT = 2.5 V
VOUT = 1.8 V
VOUT = 1.06 V
Approximate Scale 1:1
A8697
A8697-DS, Rev. 3
Wide Input Voltage 4.0 A Step Down Regulator
Typical Application
Package: 8-Lead SOIC with exposed
thermal pad (suffix LJ)
Features and Benefits
▪ 8 to 25 V input range
▪ Integrated DMOS switch
▪ Adjustable fixed off-time
▪ Adjustable output
VIN
LX
BOOT
ENB
TSET
GND
VBIAS
FB
V
IN
+12 V
150 μF
56 mΩ
V
OUT
1.06 V/ 4.0 A
COUT
2 k7
R1
L
D1
R2
6.14 k7
0.01 μF
CBOOT CIN
47 μF
25 V
RTSET
51.1 k7
3.8 μH
A8697
+
+
Ratings:
L: CDRH104R-3R8
COUT: EEUFM1V151
CIN: EEVFC1H470P
Circuit for 12 V step down to 1.06 V at 4 A Efficiency curve for circuit at left
Efficiency versus Load Current
Description
The A8697 is a constant off-time current mode step-down
regulator with a wide input voltage range. Regulation voltage is
set by external resistors, to output voltages as low as 0.8 V.
The A8697 includes an integrated power DMOS switch to
reduce the total solution footprint. It also features internal
compensation, allowing users to design stable regulators with
minimal design efforts.
The off-time can be set with an external resistor, allowing
flexibility in inductor selection. Additionally, the A8697 has
a logic level enable pin which can shut the device down and
put it into a low quiescent current mode for power sensitive
applications.
The A8697 is supplied in a low-profile 8-lead SOIC with
exposed pad (package LJ). Applications include:
▪ Applications with 8 to 25 V input
▪ Consumer electronics, networking equipment
▪ 12 V lighter-powered applications (portable DVD, etc.)
▪ Point of Sale (POS) applications
Wide Input Voltage 4.0 A Step Down Regulator
A8697
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Conditions Min. Typ. Max. Units
VIN Supply Voltage VIN – – 25 V
VBIAS Input Voltage VBIAS –0.3 – 7 V
Switching Voltage VS–1 – – V
ENB Input Voltage VENB –0.3 – 7 V
Operating Ambient Temperature Range TA Range E –40 – 85 °C
Junction Temperature TJ(max) – – 150 °C
Storage Temperature TS–55 – 150 °C
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed
the specified current ratings, or a junction temperature, TJ, of 150°C.
Package Thermal Characteristics*
Package RθJA
(°C/W) PCB
LJ 35 4-layer
* Additional information is available on the Allegro website.
Ordering Information
Use the following complete part numbers when ordering:
Part NumberaPackingbDescription
A8697ELJTR-T 13 in. reel, 3000 pieces/reel LJ package, SOIC surface mount with
exposed thermal pad
aLeadframe plating 100% matte tin.
bContact Allegro for additional packing options.
Wide Input Voltage 4.0 A Step Down Regulator
A8697
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Functional Block Diagram
+
–
+
–
+–
Switch PWM Control
μC
Soft Start
Ramp Generation
COMP
0.8 V
Boot Charge
GND
D1
L1
VIN
COUT
VOUT
VIN
ESR
VBB UVLO
TSD
Switch
Disable
Bias Supply
I_Peak I_Demand
Clamp
Error
BOOT
ENB
TSET
VIN
LX
FB
VBIAS
Wide Input Voltage 4.0 A Step Down Regulator
A8697
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Units
VIN Quiescent Current IVIN(Q)
VENB = LOW, VIN = 12 V, VBIAS = 3.2 V,
VFB = 1.5 V (not switching) – 1.0 – mA
VENB = LOW, VIN = 12 V, VBIAS < 3 V,
VFB = 1.5 V – 4.1 – mA
VENB = HIGH – – 100 A
VBIAS Input Current IBIAS VBIAS = VOUT – 3.8 5 mA
Buck Switch On Resistance RDS(on) TA = 25°C, IOUT = 3 A – 180 – m
Fixed Off-Time Proportion Based on calculated value –15 – 15 %
Feedback Voltage VFB 0.784 0.8 0.816 V
Output Voltage Regulation VOUT IOUT = 0 mA to 3 A –3 – 3 %
Feedback Input Bias Current IFB –400 –100 100 nA
Soft Start Time tss 51015ms
Buck Switch Current Limit ICL
VFB > 0.4 V 4.8 6.2 7.2 A
VFB < 0.4 V – 2.7 – A
ENB Open Circuit Voltage VOC Output disabled 2.0 – 7 V
ENB Input Voltage Threshold VENB(0) LOW level input (Logic 0), output enabled – – 1.0 V
ENB Input Current IENB(0) VENB = 0 V –10 – –1 A
VIN Undervoltage Threshold VUVLO VIN rising 6.6 6.9 7.2 V
VIN Undervoltage Hysteresis VUVLO(hys) VIN falling 0.7 – 1.1 V
Thermal Shutdown Temperature TJTSD Temperature increasing – 165 – °C
Thermal Shutdown Hysteresis TJTSD(hys) Recovery = TJTSD – TJTSD(hys) –15–°C
1Negative current is defined as coming out of (sourcing) the specified device pin.
2Specifications over the junction temperature range of 0ºC to 125ºC are assured by design and characterization.
ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 25 V (unless noted otherwise)
Wide Input Voltage 4.0 A Step Down Regulator
A8697
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Performance Characteristics
Start-up Power Off
EN; 5.00 V/div.
IOUT; 2.00 A/div.
VOUT; 1.00 V/div.
Output Ripple with Electrolytic Capacitor
IOUT = 4 A
VOUTAC; 100 mV/div.
IOUT; 1.00 A/div.
Switching
IOUT = 4 A
IOUT; 1.00 A/div.
VSW; 10.0 V/div.
EN; 5.00 V/div.
IOUT; 2.00 A/div.
VOUT; 1.00 V/div.
tt = 5.00 ms/div. tt = 5.00 ms/div.
tt = 2.00 s/div.
tt = 2.00 s/div.
Wide Input Voltage 4.0 A Step Down Regulator
A8697
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Load Transient, Step Up
IOUT = 0.8 to 1.6 A
VOUTAC; 200 mV/div.
IOUT; 500 mA/div.
Load Transient, Step Down
IOUT = 1.6 to 0.8 A
Short Circuit
IOUT; 2.00 A/div.
VOUT; 1.00 V/div.
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
V
OUT
Error (%)
Load Current (A)
012345
Load Regulation
tt = 100 s/div.
tt = 100 s/div.
VOUTAC; 200 mV/div.
IOUT; 500 mA/div.
tt = 100 s/div.
Wide Input Voltage 4.0 A Step Down Regulator
A8697
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Functional Description
The A8697 is a fixed off-time, current-mode–controlled buck
switching regulator. The regulator requires an external clamping
diode, inductor, and filter capacitor, and operates in both continu-
ous and discontinuous modes. An internal blanking circuit is used
to filter out transients resulting from the reverse recovery of the
external clamp diode. Typical blanking time is 200 ns.
The value of a resistor between the TSET pin and ground deter-
mines the fixed off-time (see graph in the tOFF section).
VOUT. The output voltage is adjustable from 0.8 to 20 V, based on
the combination of the value of the external resistor divider and
the internal 0.8 V ±2% reference. The voltage can be calculated
with the following formula:
V
OUT = VFB × (1 + R1/R2) (1)
Light Load Regulation. To maintain voltage regulation during
light load conditions, the switching regulator enters a cycle-skip-
ping mode. As the output current decreases, there remains some
energy that is stored during the power switch minimum on-time.
In order to prevent the output voltage from rising, the regulator
skips cycles once it reaches the minimum on-time, effectively
making the off-time larger.
Soft Start. An internal ramp generator and counter allow the out-
put to slowly ramp up. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any dc load at startup.
Internally, the ramp is set to 10 ms nominal rise time. During soft
start, current limit is 3.5 A minimum.
The following conditions are required to trigger a soft start:
• VIN > 6 V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
VBIAS. To improve overall system efficiency, the regulator output,
VOUT, is connected to the VBIAS input to supply the operating
bias current during normal operating conditions. During startup
the circuitry is run off of the VIN supply. VBIAS should be con-
nected to VOUT when the VOUT target level is between 3.3 and
5 V. If the output voltage is less than 3.3 V, then the A8697 can
operate with an internal supply and pay a penalty in efficiency,
as the bias current will come from the high voltage supply, VIN.
VBIAS can also be supplied with an external voltage source. No
power-up sequencing is required for normal operation.
ON/OFF Control. The ENB pin is externally pulled to ground
to enable the device and begin the soft start sequence. When the
ENB is open circuited, the switcher is disabled and the output
decays to 0 V.
Protection. The buck switch will be disabled under one or more
of the following fault conditions:
• VIN < 6 V
• ENB pin = open circuit
• TSD fault
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
tOFF. The value of a resistor between the TSET pin and ground
determines the fixed off-time. The formula to calculate tOFF (μs)
is:
,
tOFF RSET
=
⎟
⎠
⎞
⎜
⎝
⎛
10.2 × 10
9
1–0.03 V
BIAS
(2)
where RTSET (kΩ) is the value of the resistor. Results are shown
in the following graph:
0
20
40
60
80
100
120
140
160
180
200
1 2 3 4 5 6 7 8 9 10 1112131415 16
Off-Time Setting versus Resistor Value
R
TSET
(kΩ)
t
OFF
(µs)
V
BIAS
= 5 V
V
BIAS
= 3.3 V
tON. From the volt-second balance of the inductor, the turn-on
time, ton , can be calculated approximately by the equation:
=
t
ON
(VOUT + Vf + IOUT RL) tOFF
VIN – IOUT RDS(on) – IOUT RL – VOUT
(3)
where
Vf is the voltage drop across the external Schottky diode,
RL is the winding resistance of the inductor, and
RDS(on) is the on-resistance of the switching MOSFET.
Wide Input Voltage 4.0 A Step Down Regulator
A8697
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
L1. The inductor must be rated to handle the total load current.
The value should be chosen to keep the ripple current to a reason-
able value. The ripple current, IRIPPLE, can be calculated by:
IRIPPLE = VL(OFF) × tOFF / L (5)
V
L(OFF) = VOUT + Vf + IL(AV) × RL (6)
Example:
Given VOUT = 1.06 V, Vf = 0.3 V, VIN = 12 V, ILOAD = 4.0 A,
power inductor with L = 3.8 μH and RL = 0.05 Ω Rdc at 55°C,
tOFF = 5.0 μs, and RDS(on) = 0.2 Ω.
Substituting into equation 6:
VL(OFF) = 1.06 V + 0.3 V+ 4 A × 0.05 Ω = 1.56 V
Substituting into equation 5:
IRIPPLE = 1.56 V × 5 μs / 3.8 μH = 2.05 A
The switching frequency, fSW, can then be estimated by:
f
SW = 1 / ( tON + tOFF ) (7)
t
ON = IRIPPLE × L / VL(ON) (8)
V
L(ON) = VIN – IL(AV) × RDS(on) – IL(AV) × RL– VOUT (9)
Substituting into equation 9:
VL(ON) = 12 V – 4 A × 0.2 Ω – 4 A × 0.05 Ω – 1.06 V = 9.94 V
Substituting into equation 8:
tON = 2.05 A × 3.8 μH / 9.94 V = 0.785 μs
Substituting into equation 7:
fSW = 1 / (5 μs + 0.785 μs) = 173 kHz
Higher inductor values can be chosen to lower the ripple cur-
rent. This may be an option if it is required to increase the total
maximum current available above that drawn from the switching
regulator. Please refer to the Maximum Load Current graph for
the maximum load recommended.
D1. The Schottky catch diode should be rated to handle 1.2 times
the maximum load current. The voltage rating should be higher
than the maximum input voltage expected during all operating
conditions. The duty cycle for high input voltages can be very
close to 100%.
COUT. The main consideration in selecting an output capacitor
is voltage ripple on the output. For electrolytic output capacitors,
a low-ESR type is recommended.
The peak-to-peak output voltage ripple is simply IRIPPLE × ESR.
Note that increasing the inductor value can decrease the ripple
current. The ESR should be in the range from 50 to 500 mΩ.
The switching frequency is calculated as follows:
=
f
SW
1
tON + tOFF
(4)
Shorted Load. If the voltage on the FB pin falls below 0.4 V, the
regulator will invoke a 1.5 A typical overcurrent limit to handle
the shorted load condition at the regulator output. For low output
voltages at power up and in the case of a shorted output, the off-
time is extended to prevent loss of control of the current limit due
to the minimum on-time of the switcher.
The extension of the off-time is based on the value of the TSET
multiplier and the FB voltage, as shown in the following table:
VFB (V) TSET Multiplier
< 0.16 8 × tOFF
< 0.32 4 × tOFF
< 0.5 2 × tOFF
> 0.5 tOFF
Component Selection
Wide Input Voltage 4.0 A Step Down Regulator
A8697
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
RTSET Selection. Correct selection of RTSET values will
ensure that minimum on-time of the switcher is not violated and
prevent the switcher from cycle skipping. For a given VIN to
VOUT ratio, the RTSET value must be greater than or equal to the
value defined by the curve in the plot below.
Note. The curve represents the minimum RTSET value. When
calculating RTSET , be sure to use VIN(max) / VOUT(min). Resistor
tolerance should also be considered, so that under no operating
conditions the resistance on the TSET pin is allowed to go below
the minimum value.
FB Resistor Selection. The impedance of the FB network
should be kept low to improve noise immunity. Large value resis-
tors can pick up noise generated by the inductor, which can affect
voltage regulation of the switcher.
RTSET (k7)
VIN / V
OUT
Violation of
Minimum On-Time
Safe Operating Area
Minimum Value of R
TSET
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
70.0
67.5
65.0
62.5
60.0
57.5
55.0
52.5
50.0
47.5
45.0
42.5
40.0
37.5
35.0
32.5
30.0
27.5
25.0
22.5
20.0
17.5
15.0
12.5
10.0
Maximum Load Current
Using Allegro A8698 Evaluation Board*
6
5
4
3
2
1
0
021345
Load Current (A)
VOUT (V)
*To test maximum load current, the A8697 IC was mounted on
an A8698 Evaluation Board (see next page), and a thermocouple
attached to the IC case to measure TC. The assembly was placed in
an environmental chamber in still air. The initial air temperature in
the chamber temperature was 60°C (TA), and during the test, IOUT
was adjusted until TC = 115°C.
Wide Input Voltage 4.0 A Step Down Regulator
A8697
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Application Circuit
Evaluation Board for the A8697
VIN
FB
TSET
ENB
BOOT
LX
VBIAS D1
EN
R1
R2
R4
R3
R5
J3
3.3 V / 3.0 A
J4
GND
V
OUT
J1
8 to 24 Vdc
J2
GND
C3
C1.1
C2
GND PAD
P1
L1 C4.2
C4.3
C4.1
A8697
C1.3C1.2
Silkscreen Layer Bottom Layer
Top and Silkscreen Layers
Wide Input Voltage 4.0 A Step Down Regulator
A8697
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
Evaluation Board Bill of Materials
Designator Quantity Description Manufacturer Footprint Part Number
C1.1 0 Ceramic chip, 22 F, 25 V, ±20%, X5R Panasonic 1210 ECJ4YB1E226M
C1.2, C1.3 2 Aluminum electrolytic capacitor, 25 V / 47 F Rubycon 8 mm × 12 mm EEVFC1H470P
C2 1 Ceramic capacitor, X7R, ±10%, 0.1 F / 50 V Murata 0603 GRM188R71H104KA93D
C3 1 Ceramic capacitor, X7R, ±10%, 0.01 F / 50 V Kemet 0603 C0603C103K5RACTU
C4.2 0 Special polymer capacitor, 120 F / 6.3 V, 15 mPanasonic 7.3 mm × 4.3 mm
× 3.1 mm EEFUD0J121R
C4.1 0 Ceramic capacitor, 47 F / 6.3 V, ±20%, X5R Panasonic 1210 ECJ4YB0J476M
C4.3 1 Aluminum electrolytic capacitor, 35 V / 150 F, 56 mPanasonic 8 mm × 10.2 mm EEFM1V151
L1 1 Inductor, 3.8 H, 13 m, 6 A, ±20% Sumida 10.3 mm ×
10.5 mm × 4 mm CDRH104R-3R8
D1 1 Schottky diode, 20 V / 4.0 A Diodes, Inc. SMA SL42-9C
R1 1
Chip resistor, 1/16 W, 1% Std. 0603 Std.
2 k at VOUT = 1.06 V
2.55 k at VOUT = 1.8 V
6.34 k at VOUT = 3.3 V
10.5 k at VOUT = 5.0 V
R2 1
Chip resistor,1/16W, 1% Std. 0603 Std.
6.14 k at VOUT = 1.06 V
2 k at VOUT = 1.8, 3.3, or 5.0 V
R3 1 Chip resistor, 51.1 k, 1/16 W, 1% Std. 0603 Std.
R4 1 Chip resistor, 10 k, 1/16 W, 1% Std. 0603 Std.
R5 1 Chip resistor, 0 , 1/16 W, 1% Std. 0603 Std.
J1, J2, J3,
J4 4 Header, 2-pin, 100 mil spacing Sullins 0.100 in. × 2 PTC36SAAN
P1 1 Test point, Red, 1 mm Farnell 0.038 in. 240-345
EN 1 Test point, Black, 1 mm Farnell 0.038 in. 240-333
U1 1 Wide Input Voltage Step Down Regulator Allegro ESOIC8 A8697
Wide Input Voltage 4.0 A Step Down Regulator
A8697
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-
5000
www.allegromicro.com
5.60
NOM .220
0.65
MAX .026
0.25
0.10 .010
.004
1.75
1.35 .069
.053
0.51
0.31 .020
.012
4.00
3.80 .157
.150
3.30
NOM .130
3.30
NOM .130
2.41
NOM .095
2.41
NOM .095
0.25
0.17 .010
.007
8º
0º
1.27
0.40 .050
.016
5.00
4.80 .197
.189
C
SEATING
PLANE
A
B
8X
0.25 [.010] M C A B
6.20
5.80 .244
.228
C0.10 [.004]
8X
0.25 [.010] M B M
1.27 .050
0.25 .010
1.27
NOM .050
1.75
NOM .069
2X 0.20
MIN .008
6X 0.20
MIN .008
21
21
8
GAUGE PLANE
SEATING PLANE
B
A
ATerminal #1 mark area
BExposed thermal pad (bottom surface)
All dimensions reference, not for tooling use
(reference JEDEC MS-012 AA)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
C
The products described herein are man u fac tured under one or more patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to permit improvements in the per for mance, reli-
ability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support ap pli anc es, devices, or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any infringements of pat ents or
other rights of third parties that may result from its use.
Copyright © 2006 Allegro MicroSystems, Inc.
Package LJ 8-Pin SOIC
Terminal List Table
Number Name Description
1 BOOT Gate drive boost node
2 ENB On/off control; logic input
3 TSET Off-time setting
4 GND Ground
5 FB Feedback for adjustable regulator
6 VBIAS Bias supply input
7 LX Buck switching node
8 VIN Supply input
– Pad Exposed pad for enhanced thermal dissipation
Pin-out Diagram
1
2
3
4
8
7
6
5
BOOT
ENB
TSET
GND
VIN
LX
VBIAS
FB
Pad
(Top View)
