Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Introduction Lucent Technologies Microelectronics Group's T7504 and T5504 devices are monolithic, four-channel PCM codecs with filters. These integrated circuits provide the A/D and D/A conversion and the filtering necessary to interface a voice telephone circuit to a timedivision multiplexed system using a standard PCM interface. The digital strobing architecture minimizes pinout, allowing the quad codec to be assembled in a small 28-pin package that requires minimal board area. Other features include full time-slot assignment, delayed (T7504) or nondelayed (T5504) timing mode, pin-selectable -law or A-law companding, low-power +5 V-only operation, and automatic adaptation to master clock frequencies of either 2.048 MHz or 4.096 MHz. For added flexibility in interfacing with transmission systems, each channel also provides an uncommitted op amp that can be programmed for transmit gain using external resistors. These devices are fabricated in Lucent's highperformance analog CMOS technology with doublepoly capacitors. Coding and decoding is performed using charge redistribution with successive approximation. Gain, termination impedance, and hybrid balance are set by external components. These quad codecs are ideal for high-density circuit-board applications where high integration, low crosstalk, and minimal cost are required. Digital Interface The digital interfacing to the device consists of the PCM interface block, the internal timing and control block, and the powerdown control block. See Figure 1 for a functional block diagram of this codec. GSX0 VFXIN0 - FILTER NETWORK + +2.4 V VFRO0 ENCODER PCM INTERFACE CHANNEL 0 FILTER NETWORK GSX1 VFXIN1 VFRO1 CHANNEL 1 GSX2 VFXIN2 VFRO2 CHANNEL 2 GSX3 VFXIN3 VFRO3 CHANNEL 3 DX DR FSX0 FSX1 FSX2 FSX3 FSEP GNDD DECODER POWERDOWN CONTROL INTERNAL TIMING & CONTROL BIAS CIRCUITRY & REFERENCE MCLK ASEL VDD (2) GNDA (4) 5-3579F Figure 1. Functional Block Diagram T7504 and T5504 Quad PCM Codecs with Filters Digital Interface (continued) PCM Interface The PCM interface block administers transmit and receive PCM data as well as frame separation and frame sync controlling. PCM Data PCM data occurs once every 125 s frame period. The frame period is the standard set by doubling the telephone channel bandwidth of 4000 Hz, to provide a minimum sampling rate of 8000 samples per second (Nyquist criterion). The codecs provide fixed data rate timing. Data clocks at the master clock rate (MCLK). In a frame period, there are 32 data time slots when a 2.048 MHz MCLK rate is used and 64 data time slots when a 4.096 MHz MCLK rate is used. Each time slot contains eight clock cycles. Data is transmitted and received serially with the first bit (bit 1) defined as the MSB and the last bit (bit 8) as the LSB. The T7504 provides only one half bit of data for the LSB in order to ensure no bus contention with the subsequent time slot. On both codecs, the width of bit 1 is dependent upon when frame sync goes high. The eighth bit is put into 3-state by the DX port between 15 ns and 100 ns after the eighth MCLK goes low. This bit could be as short as 210 ns in 2.048 MHz mode (40% duty cycle MCLK + 15 ns). Bit 1 is the sign bit, bits 2 through 4 are the chord bits, and bits 5 through 8 are the interval bits. PCM data can be companded as -law or A-law, programmable via pin-strap. Some codecs provide a mute circuit for idle conversations in A-law that can be annoying as it turns on and off. Therefore, mute has not been implemented in these codecs. Maximum transmit and receive noise levels for -law and A-law are specified in the T7504 and T5504 Quad PCM Codecs with Filters Data Sheet. DX remains in a high-impedance state when not transmitting data. This allows the codec to operate with a single transmit port and also allows use with other codecs on a shared PCM bus. Since DX and DR are CMOS nodes, these buses can be tied to a known state through a pull-up resistor (approximately 100 k), if desired. Data is transmitted from the codec through DX and received to the codec through DR. DR remains inactive until data is to be received. For analog loopback, DX and DR can be shorted together. If using this feature, transmit and receive data must be aligned. Data alignment and time-slot assignment are discussed next. Frame Separation and Synchronization Most single-channel codecs utilize separate frame sync pulses for transmitting and receiving data. The T7504 and T5504 quad codecs require a once-per-frame sync pulse (FSx) for data transmission and a frame separation pulse (FSEP) for frame synchronization. There is 2 Application Note November 1999 one FSx per channel, and one FSEP per codec or board. FSEP requires no more than 10 A current drive per codec. FSxN and FSEP pulses must be synchronous with MCLK. Refer to Figures 2 and 3 for the following discussion. The presence of FSEP signifies the start of a new frame. FSEP is latched by a negative-going MCLK pulse. The subsequent rising MCLK pulse defines the start of frame and byte boundary for time slot 0. Data will transmit upon the arrival of FSx. FSx determines the time slot in which data will be transmitted. With the T7504, FSx is latched by the same negativegoing MCLK edge as FSEP for time slot 0. With regard to FSx, the byte boundary (as defined by FSEP) occurs on the first positive-going MCLK edge after FSx is detected. FSx must occur at one of the byte boundaries; that is, coincident with the FSEP pulse (time slot 0) or multiples of eight clock cycles thereafter (time slot 1, 2, 3, etc.). Data is valid one MCLK cycle after FSx is detected. This is referred to as delayed timing mode. The MSB of data is latched on the first negative-going MCLK edge following the negative-going edge that latches FSx. With the T5504, FSx occurs one MCLK cycle after FSEP for time slot 0. FSx is latched by the next negative-going MCLK edge after FSEP is latched. With regard to FSx, the byte boundary as defined by FSEP occurs coincident with the rising edge of FSx. FSx must occur at one of the byte boundaries; that is, one clock cycle after FSEP (time slot 0) or multiples of eight clock cycles thereafter (time slot 1, 2, 3, etc.). Data is valid coincident with FSx. This is referred to as nondelayed timing mode. The MSB of data is latched on the same negative-going MCLK edge that latches FSx. The width of FSEP designates when data is received. For 2.048 MHz MCLK operation, FSEP can be anywhere from 1 clock cycle to 255 clock cycles wide. For 4.096 MHz operation, the width of FSEP will range from 1 clock cycle to 511 clock cycles. FSEP widths of 256 clock pulses (2 MHz MCLK) or 512 clock pulses (4 MHz MCLK) are not permitted. FSEP must go low for at least one clock cycle during a frame. The width of FSEP determines the delay in clock cycles between when data is transmitted and when data is received. This delay applies to all four channels. The number of MCLK cycles, minus one, defines the delay. For instance, in Figure 2, FSEP is one clock cycle long. This sets data receive coincident with data transmit. If FSEP were five clock cycles wide, receive data would execute four clock cycles after the data was transmitted. Like transmit data, receive data is latched by negative-going MCLK edges. FSx for a given channel can occur only one time per frame. Unlike FSEP, the falling edge of FSx has no relevance; therefore, the width of FSx is not critical. The digital interface will operate satisfactorily as long as FSx goes to low at least one clock cycle prior to it going high again. FSx is edge triggered and must be glitch free. Lucent Technologies Inc. Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Digital Interface (continued) TIME SLOT MCLK 1 2 3 4 5 6 7 8 1 FSXN (7504) FSXN (5504) T7504 DX BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 T5504 BIT 1 DR BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 FSEP 5-3581sF Figure 2. Digital Interface Timing MCLK MASTER CLOCK REQUIRED FOR OVERALL OPERATION. WITH ONLY MCLK APPLIED, CODEC WILL ASSUME POWERDOWN MODE. 488 ns (2.048 MHz) OR 244 ns (4.096 MHz) ALLOWABLE DUTY CYCLE 40% TO 60% FSEP FRAME SEPARATION DEFINES START OF FRAME. WIDTH DETERMINES WHEN DATA IS RECEIVED. WITH MCLK AND FSEP APPLIED, CODEC ASSUMES STANDBY MODE. ABSENCE FOR 4 FRAMES POWERS DOWN CODEC. DEFINES START OF FRAME & TIME SLOT 0 (ON NEXT POSITIVE-GOING MCLK PULSE) WIDTH DETERMINES DELAY (# OF MCLK PULSES MINUS 1 UNTIL DATA IS RECEIVED) ALLOWABLE WIDTH: MCLK = 2.048 MHz, 488 ns TO 124.5 s (1 MCLK TO 258 MCLKS) MCLK = 4.096 MHz, 244 ns TO 124.75 s (1 MCLK TO 511 MCLKS) FSxN (FSx0, FSx1, FSx2, FSx3) FRAME SYNC ASSIGNS TIME SLOT. REQUIRED FOR PER-CHANNEL OPERATION. WITH MCLK, FSEP, AND FSx APPLIED, CODEC ASSUMES POWERUP MODE. FSx ONLY NEEDS TO BE PRESENT WHEN DATA IS TO BE TRANSMITTED AND/OR RECEIVED. ABSENCE FOR 4 FRAMES POWERS DOWN CHANNEL. 5-8870F 5-8871F DEFINES START OF CHANNEL N TRANSMIT DATA MUST OCCUR ON BYTE BOUNDARY (T5504: DATA TRANSMITS IMMEDIATELY) (T7504: DATA TRANSMITS AFTER 1 MCLK CYCLE) ALLOWABLE WIDTH: MCLK = 2.048 MHz, 488 ns TO 124.5 s (1 MCLK TO 258 MCLKS) MCLK = 4.096 MHz, 244 ns TO 124.75 s (1 MCLK TO 511 MCLKS) 5-8872F Figure 3. User-Supplied Timing Pulses--Definition and Relevance Lucent Technologies Inc. 3 Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Digital Interface (continued) Internal Timing and Control Master Clock The T7504 and T5504 are configured to operate at MCLK rates of 2.048 MHz or 4.096 MHz. Internal circuitry determines the master-clock frequency during a powerup reset interval. The MCLK is used by various internal circuits including the filters. For instance, operating at higher than specified MCLK rates will affect the device's filter characteristics by shifting the filter poles to higher frequencies. Lower than specified MCLK rates are not recommended because there will be an inadequate number of pulses to perform normal codec operations. MCLK duty cycle should be maintained between 40% to 60%. A-Law/-Law Select The ASEL pin provides pin-strap programmability of the companding operation. Logic low selects -law coding, and logic high selects alternate bit inversion Alaw coding. Companding selection can be changed in real time. ASEL is monitored every 125 s, so a change in logic level will change the companding state on the next frame sync pulse. A pull-down device is included within the codec, thereby defaulting the part to -law companding. Powerdown Control The quad codec exhibits three power dissipation modes: powerup, standby, and powerdown. Operation in standby mode or powerdown mode reduces power consumption and heat dissipation when device operation is not required. The device is at full powerup when MCLK, FSEP, and all FSx pulses are present. Under full powerup, the codec typically dissipates 150 mW (worst case 262.5 mW). Absence of an FSx pulse institutes a powerdown of that given channel. When FSx is absent for four frames (500 s), the channel it is associated with will power down. As each channel powers down, each channel reduces overall power dissipation by 30 mW (worst case 52.5 mW). If all FSx pulses are absent, the codec will go into standby mode where the entire part will typically dissipate 30 mW (worst case 52.5 mW). If the MCLK is present but FSEP is absent for four frames (500 s), the codec will assume powerdown mode. In this mode, the codec typically dissipates only 1 mW (worst case 5.25 mW). Powerdown is not guaranteed if MCLK is lost. Powerdown is achieved by removing the FSx pulse for at least 500 s with MCLK active, after which MCLK can be removed. 4 When an absent FSEP or FSx reappears, the codec immediately powers back up to the appropriate state without losing a frame. VFRO is held at the voltage reference potential during powerdown to ensure noise free transmission upon powerup. Analog Interface See Figure 1 for a functional block diagram of this codec. Bias Circuit and Reference The quad codec requires only a +5 V supply to operate. This eliminates the necessity of a -5 V supply and bypass capacitor for codec use. It also eliminates the signal reference of 0 V like codecs that require +5 V and -5 V supplies use. With a single supply, the analog input and output signal 0 V reference becomes a dc +2.4 V reference. This +2.4 V is internally generated by a precision band gap voltage reference. This voltage reference requires no additional external components. A single band gap voltage reference is used throughout the codec circuitry in order to provide very accurate gains and a wide dynamic range. This voltage reference is heavily buffered using unity gain op amps. The reference is used as the input to the noninverting node of the transmit uncommitted op amp and the reference output of the receive op amp. Each channel is provided with its own individually buffered transmit and receive voltage references in order to minimize interchannel and intrachannel crosstalk. The voltage reference powers down upon the absence of MCLK. Transmit Operation (A-D) The transmit path consists of an input op amp, bandpass filtering, and an encoder. RF CI RI GSX VFxIN - + TO CODEC FILTERS 2.4 V GAIN = RF RI 5-3786a(F) Figure 4. Typical Analog Input Section Lucent Technologies Inc. Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Analog Interface (continued) The quad codec supplies one uncommitted op amp per channel. A schematic of an input circuit is shown in Figure 4. Inverting input (VFxIN) and output leads (GSx) are user accessible. The input is self-biasing. The band gap voltage reference is applied to the noninverting input. External pull-up resistors are not required. Passband gain is set by simply dividing the op amp's feedback resistor (Rf) by the op amp's input resistor (RI). For best transmission performance, gain values should range from 0 dB to +20 dB (gain between 1 to 10). Feedback resistance values should range from 10 k to 200 k, and capacitance from GSx to ground should be kept less than 50 pF. A low-value picofarad capacitor can be used across the feedback resistor to increase stability or to reduce the gain of injected high-frequency noise. Maintaining these values will minimize crosstalk while still providing acceptable loading on GSx. An encoder milliwatt is defined as 0.775 Vrms on this part. This convenient value (1 mW into 600 is 0.775 Vrms) referenced to +2.4 V still allows acceptable headroom for the maximum signal transmission, which is +3 dBm0 (3.145 Vp-p max, A-law; 3.169 Vp-p max, law). The minimum transmission signal level is determined by the signal-to-noise ratio. The quad codecs are measured at -50 dBm0 signal levels in production test and pass ITU-T quantization distortion plus noise specifications. If phase inversion of the analog signal is required for transhybrid balance considerations, then an external op amp must be employed. Many SLICs, like Lucent's ATTL7551 and ATTL7554 Low-Power SLICs, include a spare op amp that can be used to supply the necessary phase inversion. VFxIN must be capacitively coupled to its signal source since the codec analog inputs are referenced to internal +2.4 V. Filtering within the codec forms the frequency spectrum shaping, but the input capacitor selection can impact on the low-frequency pole. The codec contains fifth-order bandpass filtering. This filtering is required in order to prevent high frequencies from folding over and distorting the encoding process. Additional low-frequency loss contributed by the input network can be calculated using the following equation: loss f in 20 log 10 ---------------------------------------- [ 1 / ( 2p i R i C i ) ] = ---------------------------------------------------------------2 10 0.5 f in 1 + ---------------------------------------- [ 1 / ( 2p i R i C i ) ] Where fin is the low-frequency pole of interest (e.g., 300 Hz), and RI and CI are the input resistor and input capacitor, respectively (see Figure 4). For an input Lucent Technologies Inc. resistor of 50 k and an input capacitor of 0.1 F, the additional loss provided by the input network at 300 Hz would be -0.05 dB. For SLIC use, the ac impedance of the transmit and receive coupling capacitors becomes a factor in the effective transhybrid balance. Coupling capacitor values should be selected according to component selection criteria defined by the SLIC. The output of the op amp feeds the bandpass filter network. Transmit filtering consists of an antialiasing filter followed by a fifth-order elliptic low-pass filter and a third-order high-pass filter. The filters are all switched capacitor filters. The high-pass filter effectively attenuates low-frequency noise like ac and ringing signals, yet typically provides only -0.5 dB of attenuation at 200 Hz (see Transmit Filter Characteristics in the data sheet). The passband frequencies adhere to ITU-T G.712 requirements. Passband frequencies are then encoded via quantization. The analog signal is sampled and converted to a digital PCM representation using charge redistribution with successive approximation. Companding is user selectable as either A-law or -law. The encoded signal is now presented to the PCM interface block. If a given transmit channel is not to be used, tie GSx to VFxIN. Receive Operation (D-A) The decoder converts the digital PCM stream to an analog signal using charge redistribution and sample and hold capacitors. The reconstructed analog signal passes through a fifth-order elliptic low-pass filter compliant with ITU-T G.712 and Lucent PUB43801 D3/D4 requirements. The filtered analog signal is now provided to the output amplifier. The output amplifier provides a single-ended output capable of driving a load of 2000 or greater and a capacitance of up to 100 pF. The output signal is referenced to its channel's analog ground. Like the analog input, common-mode reference is a dc +2.4 V. Receive gain of the codec itself is fixed at unity. A decoder milliwatt with a PCM input of 0 dBm0 is 0.775 Vrms. Maximum signal level output is +3 dBm0 (3.145 Vp-p max, A-law; 3.169 Vp-p max, -law). Receive gain can be attenuated external to the output op amp by simply employing a resistive voltage divider. For determining a proper value of capacitive coupling, follow the same procedure as with the transmit coupling capacitor. To minimize power dissipation, let unused receive outputs float. 5 Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Board Layout and Decoupling Concentrating four sets of analog/digital conversions in an integrated device places an extra burden on the board layout. Highly sensitive analog nodes and noisy digital circuits are placed in close proximity. The high dynamic range of the codec, which allows low noise transmission of very small signal levels with minimal crosstalk, could be jeopardized if proper grounding and decoupling practices are not followed. Furthermore, the codec will fail distortion and noise requirements if proper grounding is not provided. For best performance, a multilayer board is recommended. One inner layer should be used for a common, low-impedance ground plane. It is perfectly acceptable to short SLIC AGND and the codec GNDA and GNDD pins directly to the inner ground layer. The codec's GNDA pins and its GNDD pin must be tied together at the chip. Use individual vias for each device ground pin. If a two-layer board is to be used, a low-impedance ground plane must be established. A micro-island (flooded ground plane) and fat ground traces must be used. To get the lowest-impedance ground plane possible, tie GNDA and GNDD leads together at the chip. Provide a dedicated ground plane under the device to connect these pins together. Fill unused areas around the device and board with ground. Minimize the use of vias in ground planes. If the ground plane must transfer to the other layer, use multiple vias for a better connection. Give the ground planes routing priority over signal traces. Keep clock traces short and guard, if possible. VDD serves both analog and digital circuits. It is important to place a 0.1 F ceramic capacitor on both of these pins to ground. Keep leads short by placing vias as close to solder pads as possible. Use individual vias for each power pin. Use two capacitors, one for each VDD pin. VDD is the demarcation point for analog and digital circuitry. Digital circuits are grouped together in one area of the package. Runners for analog and digital circuitry should diverge from this point. Not following this practice could result in harmonic frequencies from carrier modulation or digital transitions coupling into VFXIN and the passband frequencies. Digital traces require a continuous adjacent return path to minimize emissions. Decouple any power or ground discontinuities. Special consideration is required with regard to layout of analog input leads to output leads. Interchannel and intrachannel crosstalk into VFxIN can be significantly affected by parasitic capacitance feeds from GSx and VFRO. PWB layouts should be arranged to keep these parasitics low. The T7504/T5504 Evaluation Board can 6 be used as a guide for correct layout technique. The evaluation board achieves interchannel crosstalk values of < -80 dB. For general board layout, other general rules of digitally controlled, audio frequency circuits apply. Digital circuitry should be placed as close to the edge connector as possible. Clock leads should be kept as short as possible. And a large bulk storage capacitor (47 F or thereabouts) in parallel with the 0.1 F ceramics should be placed at distribution points located near the connector. Specifications Specifications and typical performance characteristics are presented in the data sheet. For group delay, envelope delay distortion (Table 8 of data sheet), a range of values is given. The following discussion allows a user to determine a specific group delay value for a given set of conditions. Group Delay To determine absolute round trip delay for FSEP 1 MCLK pulse wide, use the following formula and Table 1. DRTA = DC + DX + DR For f = 1600 Hz, where: DRTA = absolute round trip delay in microseconds. DC = delay of the internal filter circuitry (times 2 for round trip) in microseconds. For transmit channels of 0 or 2, use a constant of 327. For transmit channels of 1 or 3, use a constant of 392. DX = digital delay for transmit path in microseconds. Obtain appropriate value for a given transmit channel and time slot from Table 1. DR = digital delay for receive path in microseconds. Obtain appropriate value for a given receive channel and time slot from Table 1. For absolute round trip delays for a single channel and a single time-slot assignment with FSEP = 1 MCLK pulse wide, DX = DR, and MCLK = 2.048 MHz, delays will calculate as follows: Channels 0, 2 Time Slots 0--3, 16--31 405 s Time Slots 4--15 530 s Channels 1, 3 Time Slots 0--19 Time Slots 20--31 470 s 595 s Lucent Technologies Inc. Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Specifications (continued) Table 1. Digital Delay Periods Channel 0, 2 Time Slot: MCLK = 2.048 MHz 4.096 MHz DX (Transmit Digital Delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 32, 33 34, 35 36, 37 38, 39 40, 41 42, 43 44, 45 46, 47 48, 49 50, 51 52, 53 54, 55 56, 57 58, 59 60, 61 62, 63 62.5 66 70 74 78 82 86 90 94 98 101.5 105.5 109 113 117 121 0 4 8 12 15.5 19.5 23 27 31 35 39 43 47 51 55 58.5 Lucent Technologies Inc. DR (Receive Digital Delay) 15.5 12 8 4 125 121 117 113 109 105 101.5 97.5 94 90 86 82 78 74 70 66 62.5 58.5 55 51 47 43 39 35 31 27 23 19.5 Channel 1, 3 Time Slot: MCLK = 2.048 MHz 4.096 MHz DX (Transmit Digital Delay) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 32, 33 34, 35 36, 37 38, 39 40, 41 42, 43 44, 45 46, 47 48, 49 50, 51 52, 53 54, 55 56, 57 58, 59 0 4 8 12 15.5 19.5 23 27 31 35 39 43 47 51 55 58.5 62.5 66 70 74 78 82 86 90 94 98 101.5 105 109 113 DR (Receive Digital Delay) 78 74 70 66 62.5 58.5 55 51 47 43 39 35 31 27 23 19.5 15.5 12 8 4 125 121 117 113 109 105 101.5 98 94 90 7 Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Applications bit of the time slot. Frame sync pulses can be set anywhere from one clock pulse wide to 255 or 511 clock pulses wide (2.048 MHz and 4.096 MHz operation, respectively). To generate a time-slot enable pulse, the frame sync pulse should be set eight clock pulses wide. Inverting the frame sync pulse generates an 8-bit wide active-low pulse that can be used for time slot enable (see Figure 5). Please note that for codec operation, the FSEP pulse still needs to be supplied. For the T5504, FSEP occurs one clock pulse prior to the timeslot byte boundary. Time-Slot Enable Strobe Some codecs provide a time-slot enable strobe. This strobe is useful in enabling external 3-state buffers that could be required to drive heavily loaded bus lines. This strobe provides an active-low pulse that envelops an 8-bit transmit PCM time slot. The quad codec does not provide a time-slot enable output. A time-slot enable pulse can be derived, however, from the T5504 frame sync pulse. The T5504 operates in nondelayed timing mode. The rising edge of frame sync envelops the first To create a time-slot enable for the T7504, insert a Dtype flip-flop clocked by MCLK at node 1C in Figure 5. MCLK FSxN Dx AND SDx 1 2 3 4 5 6 7 8 DERIVED TIME-SLOT ENABLE STROBE AT 1C 5-4713F BUFFERED Dx FROM OTHER CODECS T5504 1/4 745125A Dx 1A 1Y SDx DR 1C FSx0 PCM INTERFACE FSx1 1/2 74S260 FSx2 FSx3 FSEP INTERNAL TIMING AND CONTROL MCLK 5-4714 Figure 5. Time-Slot Enable Strobe Timing Diagram and Circuit 8 Lucent Technologies Inc. Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Applications (continued) nel 0 is complete, channel 0 must be kept active until the other channel is no longer in use. The width of FSx0 determines in what time slot data is received. All data will be transmitted in delayed timing mode. Codec Use Without FSEP Pulse The T7504 codec can be used without using a separate frame separation (FSEP) pulse. Operating in this fashion, however, places restraints on operation and complicates the digital interface by requiring a more intelligent control. For operation, tie FSEP pin 1 to FSx0 pin 25. FSx0 will now function as the FSEP pulse. (Any other channel can be selected; for this discussion, channel 0 was chosen.) FSx0 must occur every 125 s as time slot 0. It will therefore become the first channel on and the last channel off on this codec. If the codec is idle, the lack of FSx0 will power down the codec. When data is to be transmitted and FSx0 reappears, channel 0 will power up and time slot 0 will become active while the other three channels will go into standby power mode. Other channels and time slots become active as their respective FSx pulses are transmitted. If there is activity on another channel after transmission on chan- SLIC Interface Interfacing a codec to a SLIC is discussed in detail in application materials relating to the SLIC. A basic interface circuit for 600 resistive termination and hybrid balance, with TX and RX gains set at 0 dB, is shown in Figure 6. RT6 and RX set up the transmit gain of the codec. The value of RHB1 needs to be appropriately selected according to loop gains to set up hybrid balance. RRCV and RGP (with RT3 in parallel) provide attenuation of the codec receive signal. RT3 (with RRCV and RGP in parallel) sets up the termination impedance. CC1 and CC2 provide dc blocking of the codec reference level and ac signal coupling. RGP2 and CGP are added for SLIC stability. L8560 RX 182 k RT6 121 k VITR RT3 174 k - + RCVN RGN 48.7 k CC1 0.1 F RGP 48.7 k GSX VFXIN RGP2 1.78 k - + RHB1 182 k RRCV 113 k RCVP T7504 +2.4 V VFRO CC2 0.1 F CGP 150 pF 5-4716F Figure 6. SLIC Interface (600 Resistive) Lucent Technologies Inc. 9 Application Note November 1999 T7504 and T5504 Quad PCM Codecs with Filters Applications (continued) readily interface the T7504/T5504 to a speaker, however, by using a generic dual 5 V op amp and a few resistors and capacitors. Speaker Driver The T7504/T5504 quad codecs have single-ended analog inputs and outputs. The analog output can drive a minimum of 2000 . The T7502 and T7503 dual codecs have differential analog inputs and outputs. The differential output in these devices can drive a minimum of 300 (600 single ended). The T7502 and T7503 are the preferred choice for direct connection to microphones and transformer drive applications. One can Figure 7 shows the T7504 interfacing a small speaker. The LM358 op amp (or equivalent) is set up for unity gain push-pull drive. The output of the codec is capacitively coupled to the op amps with a large value capacitor suitable for audio frequencies. This capacitor removes the output's dc content. Another midpoint reference level is provided for the op amps by the R1/R2 voltage divider. +5 V T7504 8 - 1 3 + 2 C1 10 F VFRO0 R2 10 k SMALL EFFICIENT SPEAKER R4 10 k +5 V R1 10 k 1 LM358 R3 10 k 6 5 C2 10 F - + 2 4 7 GND GNDA0 5-4715F Figure 7. Speaker Driver Circuit For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. N o liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright (c) 1999 Lucent Technologies Inc. All Rights Reserved November 1999 AP00-004ALC (Replaces AP96-026ALC)