Application Note
November 1999
T7504 and T5504 Quad PCM Codecs with Filters
Introduction
Lucent Technologies Microelectronics Group’s T7504
and T5504 devices are monolithic, f our-channel PCM
codecs with filters. These integrated circuits provide
the A/D and D/A conversion and the filtering neces-
sary to interface a voice telephone circuit to a time-
division multiplex ed system using a standard PCM
interface. The digital strobing architecture minimizes
pinout, allowing the quad codec to be assembled in a
small 28-pin package that requires minimal board
area. Other features include full time-slot assign-
ment, dela yed (T7504) or nondelay ed (T5504) timing
mode, pin-selectable µ-law or A-law companding,
low-power +5 V-only operation, and automatic adap-
tation to master cloc k frequencies of either
2.048 MHz or 4.096 MHz. For added flexibility in
interfacing with transmission systems, each channel
also provides an uncommitted op amp that can be
programmed for transmit gain using external resis-
tors. These devices are fabricated in Lucent’s high-
performance analog CMOS technology with double-
poly capacitors. Coding and decoding is perf ormed
using charge redistribution with successive appro xi-
mation. Gain, termination impedance, and h ybrid bal-
ance are set by external components. These quad
codecs are ideal for high-density circuit-board appli-
cations where high integration, low crosstalk, and
minimal cost are required.
Digital Interface
The digital interfacing to the device consists of the
PCM interface block, the internal timing and control
block, and the powerdown control block. See Figure
1 for a functional block diagram of this codec.
5-3579F
Figure 1. Functional Block Diagram
GSX0
VFXIN0
VFRO0
GSX1
VFXIN1
VFRO1
GSX2
VFXIN2
VFRO2
GSX3
VFXIN3
VFRO3
–
+FILTER ENCODER
CHANNEL 0
+2.4 V
PCM
POWERDOWN
INTERNAL TIMING
BIAS
CHANNEL 1
CHANNEL 2
CHANNEL 3
DX
DR
FSX0
FSX1
FSEP
GNDD
MCLK
ASEL
VDD (2)
GNDA (4)
NETWORK INTERFACE
CONTROL
& CONTROL
CIRCUITRY
&
REFERENCE
FILTER
NETWORK DECODER
FSX2
FSX3
22 Lucent Technologies Inc.
Application Note
November 1999
T7504 and T5504 Quad PCM Codecs with Filters
Digital Interface (continued)
PCM Interface
The PCM interface block administers transmit and
receive PCM data as well as frame separation and
frame sync controlling.
PCM Data
PCM data occurs once ev ery 125 µs frame period. The
frame period is the standard set by doubling the tele-
phone channel bandwidth of 4000 Hz, to provide a min-
imum sampling rate of 8000 samples per second
(Nyquist criterion). The codecs provide fixed data rate
timing. Data clocks at the master clock rate (MCLK). In
a frame period, there are 32 data time slots when a
2.048 MHz MCLK rate is used and 64 data time slots
when a 4.096 MHz MCLK rate is used. Each time slot
contains eight clock cycles. Data is transmitted and
received serially with the first bit (bit 1) defined as the
MSB and the last bit (bit 8) as the LSB. The T7504 pro-
vides only one half bit of data for the LSB in order to
ensure no bus contention with the subsequent time
slot. On both codecs, the width of bit 1 is dependent
upon when frame sync goes high. The eighth bit is put
into 3-state by the DX port between 15 ns and 100 ns
after the eighth MCLK goes low. This bit could be as
short as 210 ns in 2.048 MHz mode (40% duty cycle
MCLK + 15 ns). Bit 1 is the sign bit, bits 2 through 4 are
the chord bits, and bits 5 through 8 are the interval bits.
PCM data can be companded as µ-law or A-law, pro-
grammable via pin-strap . Some codecs provide a mute
circuit for idle conversations in A-law that can be
annoying as it turns on and off. Theref ore, mute has not
been implemented in these codecs. Maximum transmit
and receive noise levels for µ-law and A-law are speci-
fied in the
T7504 and T5504 Quad PCM Codecs with
Filters
Data Sheet.
DX remains in a high-impedance state when not trans-
mitting data. This allows the codec to operate with a
single transmit port and also allows use with other
codecs on a shared PCM bus. Since DX and DR are
CMOS nodes, these buses can be tied to a known
state through a pull-up resistor (appro ximately 100 kΩ),
if desired. Data is transmitted from the codec through
DX and received to the codec through DR. DR remains
inactive until data is to be received. For analog loop-
back, DX and DR can be shorted together. If using this
feature, transmit and receive data must be aligned.
Data alignment and time-slot assignment are dis-
cussed next.
Frame Separation and Synchronization
Most single-channel codecs utilize separate frame sync
pulses for transmitting and receiving data. The T7504
and T5504 quad codecs require a once-per-frame sync
pulse (FSx) for data transmission and a frame separa-
tion pulse (FSEP) for frame synchron ization. There is
one FSx per channel, and one FSEP per codec or
board. FSEP requires no more than 10 µA current drive
per codec. FSxN and FSEP pulses must be synchro-
nous with MCLK.
Refer to Figures 2 and 3 for the following discussion.
The presence of FSEP signifies the start of a new
frame. FSEP is latched by a negative-going MCLK
pulse. The subsequent rising MCLK pulse defines the
start of frame and byte boundary for time slot 0. Data
will transmit upon the arrival of FSx. FSx determines
the time slot in which data will be transmitted.
With the T7504, FSx is latched by the same negative-
going MCLK edge as FSEP f or time slot 0. With regard
to FSx, the byte boundary (as defined by FSEP) occurs
on the first positive-going MCLK edge after FSx is
detected. FSx must occur at one of the byte bound-
aries; that is, coincident with the FSEP pulse (time slot
0) or multiples of eight clock cycles thereafter (time slot
1, 2, 3, etc.). Data is valid one MCLK cycle after FSx is
detected. This is referred to as delayed timing mode.
The MSB of data is latched on the first negative-going
MCLK edge following the nega tive-going edg e that
latc hes FSx.
With the T5504, FSx occurs one MCLK cycle after
FSEP for time slot 0. FSx is latched by the next nega-
tive-going MCLK edge after FSEP is latched. With
regard to FSx, the byte boundary as defined by FSEP
occurs coincident with the rising edge of FSx. FSx
must occur at one of the byte boundaries; that is, one
clock cycle after FSEP (time slot 0) or multiples of eight
clock cycles thereafter (time slot 1, 2, 3, etc.). Data is
valid coincident with FSx. This is referred to as nonde-
layed timing mode. The MSB of data is latched on the
same negative-going MCLK edge that latches FSx.
The width of FSEP designates when data is received.
For 2.048 MHz MCLK operation, FSEP can be any-
where from 1 clock cycle to 255 clock cycles wide. For
4.096 MHz operation, the width of FSEP will range
from 1 clock cycle to 511 clock cycles. FSEP widths of
256 clock pulses (2 MHz MCLK) or 512 clock pulses
(4 MHz MCLK) are not permitted. FSEP must go low
f or at least one clock cycle during a frame. The width of
FSEP determines the delay in clock cycles between
when data is transmitted and when data is received.
This delay applies to all four channels. The number of
MCLK cycles, minus one, defines the delay. For
instance, in Figure 2, FSEP is one clock cycle long.
This sets data receive coincident with data transmit. If
FSEP were five clock cycles wide, receive data would
execute four clock cycles after the data was transmit-
ted. Like transmit data, receive data is latched by nega-
tive-going MCLK edges.
FSx for a giv en channel can occur only one time per
frame. Unlike FSEP, the falling edge of FSx has no rele-
vance; therefore, the w idth of FSx is not critical. The
digital interface will operate satisfactorily as long as
FSx g oes to l ow a t leas t one cl oc k cycl e prior to it goi ng
high again. FSx is edge triggered and must be glitch
free.
Lucent Technologies Inc. 3
Application Note
November 1999 T7504 and T5504 Quad PCM Codecs with Filters
Digital Interface (continued)
5-3581sF
Figure 2. Digital Interface Timing
Figure 3. User-Supplied Timing Pulses—Definition and Relevance
MCLK MAST ER CLOCK
REQUIRED FOR OVERALL OPERATION.
WITH ONLY MCLK APPLIED, CODEC WILL
ASSUME POWERDOWN MODE.
5-8870F
FSEP FRAM E SE PARATION
DEFINES START OF FRAME.
WIDTH DETERMINES WHEN DATA IS RECEIVED.
WITH MCLK AND FSEP APPLIED, CODEC
ASSUMES STA NDBY MODE.
ABSENCE FOR 4 FRAMES POWERS DOWN
CODEC.
5-8871F
FSxN
(FSx0,
FSx1,
FSx2,
FSx3)
FRAME SY NC
ASSIG N S TI ME SLOT.
REQUIRED FOR PER-CHANNEL OPERATION.
WITH MCLK, FSEP, AND FSx APPLIED, CODEC
ASSU ME S POWERUP MODE.
FSx ONLY NE EDS TO BE PRESENT WHEN DATA
IS TO BE TRANSMITTED AND/OR RECEIVED.
ABSENCE FOR 4 FRAMES POWERS DOWN
CHANNEL. 5-8872F
MCLK
FSXN
123456781
DRBIT BIT
2BIT BIT
4BIT BIT BIT BIT
135
TIME SLOT
678
DXBIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8
FSXN
FSEP
(7504)
(5504)
T7504
T5504
488 ns (2.048 MHz) OR 244 ns (4.096 MHz)
ALLOWABLE DUTY CYCLE
40% TO 60%
DEFINES START OF FRAM E & TIME SLOT 0
WIDTH DETERMINES DELAY
ALLOWABLE WIDTH:
(ON NEXT POSITIVE-GOING MCLK PULSE)
(# OF MCLK PULSES MINUS 1
UNTIL DATA IS RECEIVED)
MCLK = 2.048 MHz, 488 ns TO 124.5 µs (1 MCLK TO 258 MCLK S )
MCLK = 4.096 MHz, 244 ns TO 124.75 µs (1 MCLK TO 511 MCLK S)
ALLOWABLE WIDTH:
DEFINES START OF CHANNEL N TRANSMIT DATA
MUST OCCUR ON BYTE BOUNDARY
(T5504: DATA TRANSMITS IMMEDIATELY)
(T7504: DATA TRANSMITS AFTER 1 MCLK CYCLE)
MCLK = 2.048 MHz, 488 ns TO 124.5 µs (1 MCLK TO 258 MCLK S )
MCLK = 4.096 MHz, 244 ns TO 124.75 µs (1 MCLK TO 511 MCLK S)
44 Lucent Technologies Inc.
Application Note
November 1999
T7504 and T5504 Quad PCM Codecs with Filters
Digital Interface (continued)
Internal Timing and Control
Master Clock
The T7504 and T5504 are configured to operate at
MCLK rates of 2.048 MHz or 4.096 MHz. Internal cir-
cuitry determines the master-clock frequency during a
powerup reset interval. The MCLK is used by various
internal circuits including the filters. For instance, oper-
ating at higher than specified MCLK rates will affect the
device’s filter characteristics by shifting the filter poles
to higher frequencies. Low er than specified MCLK
rates are not recommended because there will be an
inadequate number of pulses to perform normal codec
operations. MCLK duty cycle should be maintained
between 40% to 60%.
A-Law/µ-Law Select
The ASEL pin provides pin-strap programmability of
the companding operation. Logic low selects µ-law
coding, and logic high selects alternate bit inversion A-
law coding. Companding selection can be changed in
real time. ASEL is monitored every 125 µs, so a
change in logic level will change the companding state
on the next frame sync pulse. A pull-down device is
included within the codec, thereby def aulting the part to
µ-law companding.
Powerd own Control
The quad codec exhibits three power dissipation
modes: powerup, standby, and powerdown. Operation
in standby mode or powerdown mode reduces power
consumption and heat dissipation when de vice opera-
tion is not required. The device is at full powerup when
MCLK, FSEP, and all FSx pulses are present. Under
full powerup, the codec typically dissipates 150 mW
(worst case 262.5 mW). Absence of an FSx pulse insti-
tutes a powerdown of that giv en channel. When FSx is
absent for four frames (500 µs), the channel it is asso-
ciated with will power down. As each channel powers
down, each channel reduces overall power dissipation
by 30 mW (worst case 52.5 mW). If all FSx pulses are
absent, the codec will go into standby mode where the
entire part will typically dissipate 30 mW (worst case
52.5 mW). If the MCLK is present but FSEP is absent
for four frames (500 µs), the codec will assume power-
down mode. In this mode, the codec typically dissi-
pates only 1 mW (worst case 5.25 mW). Powerdown
is not guaranteed if MCLK is lost. Powerdown is
achiev ed by removing the FSx pulse for at least 500 µs
with MCLK active, after which MCLK can be removed.
When an absent FSEP or FSx reappears, the codec
immediately powers back up to the appropriate state
without losing a frame. VFRO is held at the voltage ref-
erence potential during powerdown to ensure noise
free transmission upon powerup.
Analog Interface
See Figure 1 for a functional block diagram of this
codec.
Bias Circuit and Reference
The quad codec requires only a +5 V supply to operate.
This eliminates the necessity of a –5 V supply and
bypass capacitor for codec use. It also eliminates the
signal reference of 0 V like codecs that require +5 V
and –5 V supplies use. With a single supply, the analog
input and output signal 0 V reference becomes a dc
+2.4 V ref erence. This +2.4 V is internally generated by
a precision band gap voltage reference. This v oltage
reference requires no additional external components.
A single band gap voltage ref erence is used throughout
the codec circuitry in order to provide very accurate
gains and a wide dynamic range. This voltage refer-
ence is heavily buffered using unity gain op amps. The
reference is used as the input to the noninverting node
of the transmit uncommitted op amp and the reference
output of the receiv e op amp . Each channel is provided
with its own individually buffered transmit and receive
voltage references in order to minimize interchannel
and intrachannel crosstalk. The voltage reference pow-
ers down upon the absence of MCLK.
Transmit Operation (A-D)
The transmit path consists of an input op amp, band-
pass filtering, and an encoder.
5-3786a(F)
Figure 4. Typical Analog Input Section
VFxIN TO
CODEC
FILTERS
2.4 V
GAIN = RF
RI
GSX
RF
CIRI
+
–
Lucent Technologies Inc. 5
Application Note
November 1999 T7504 and T5504 Quad PCM Codecs with Filters
Analog Interface (continued)
The quad codec supplies one uncommitted op amp per
channel. A schematic of an input circuit is shown in Fig-
ure 4. Inverting input (VFxIN) and output leads (GSx)
are user accessible. The input is self-biasing. The band
gap voltage reference is applied to the noninverting
input. External pull-up resistors are not required.
Passband gain is set by simply dividing the op amp’s
feedback resistor (Rf) by the op amp’s input resistor
(RI). For best transmission performance, gain values
should range from 0 dB to +20 dB (gain between 1 to
10).
Feedback resistance values should range from 10 kΩ
to 200 kΩ, and capacitance from GSx to ground should
be kept less than 50 pF. A low-value picofarad capacitor
can be used across the feedback resistor to increase
stability or to reduce the gain of injected high-frequency
noise. Maintaining these values will minimize crosstalk
while still providing acceptable loading on GSx. An
encoder milliwatt is defined as 0.775 Vrms on this part.
This convenient value (1 mW into 600 Ω is 0.775 Vrms)
ref erenced to +2.4 V still allows acceptable headroom
for the maximum signal transmission, which is
+3 dBm0 (3.145 Vp-p max, A-law; 3.169 Vp-p max, µ-
law). The minimum transmission signal level is deter-
mined by the signal-to-noise ratio. The quad codecs
are measured at –50 dBm0 signal le vels in production
test and pass ITU-T quantization distortion plus noise
specifications.
If phase inversion of the analog signal is required for
transhybrid balance considerations, then an external
op amp must be employed. Many SLICs, like Lucent’s
ATTL7551 and ATTL7554 Low-Power SLICs , include a
spare op amp that can be used to supply the neces-
sary phase inversion.
VFxIN must be capacitively coupled to its signal source
since the codec analog inputs are referenced to inter-
nal +2.4 V. Filtering within the codec forms the fre-
quency spectrum shaping, but the input capacitor
selection can impact on the low-frequency pole. The
codec contains fifth-order bandpass filtering. This filter-
ing is required in order to pre vent high frequencies from
folding over and distorting the encoding process. Addi-
tional low-frequency loss contributed by the input net-
work can be calculated using the following equation:
Where fin is the low-frequency pole of interest (e.g.,
300 Hz), and RI and CI are the input resistor and input
capacitor, respectively (see Figure 4). For an input
resistor of 50 kΩ and an input capacitor of 0.1 µF, the
additional loss provided by the input network at 300 Hz
would be –0.05 dB.
For SLIC use, the ac impedance of the transmit and
receive coupling capacitors becomes a factor in the
effective transhybrid balance. Coupling capacitor val-
ues should be selected according to component selec-
tion criteria defined by the SLIC.
The output of the op amp f eeds the bandpass filter net-
work. Transmit filtering consists of an antialiasing filter
followed by a fifth-order elliptic low-pass filter and a
third-order high-pass filter. The filters are all s witched
capacitor filters. The high-pass filter effectively attenu-
ates low-frequency noise like ac and ringing signals,
yet typically provides only –0.5 dB of attenuation at
200 Hz (see Transmit Filter Characteristics in the data
sheet). The passband frequencies adhere to ITU-T
G.712 requirements. Passband frequencies are then
encoded via quantization. The analog signal is sam-
pled and converted to a digital PCM representation
using charge redistribution with successive approxima-
tion. Companding is user selectable as either A-law or
µ-law. The encoded signal is now presented to the
PCM interface block.
If a given transmit channel is not to be used, tie GSx to
VFxIN.
Receive Operati on (D-A)
The decoder converts the digital PCM stream to an
analog signal using charge redistribution and sample
and hold capacitors. The reconstructed analog signal
passes through a fifth-order elliptic low-pass filter com-
pliant with ITU-T G.712 and Lucent PUB43801 D3/D4
requirements. The filtered analog signal is now pro-
vided to the output amplifier.
The output amplifier provides a single-ended output
capable of driving a load of 2000 Ω or greater and a
capacitance of up to 100 pF. The output signal is refer-
enced to its channel’s analog ground. Like the analog
input, common-mode ref erence is a dc +2.4 V. Receive
gain of the codec itself is fixed at unity. A decoder milli-
watt with a PCM input of 0 dBm0 is 0.775 Vrms. Maxi-
mum signal level output is +3 dBm0 (3.145 Vp-p max,
A-law; 3.169 Vp-p max, µ-law). Receive gain can be
attenuated external to the output op amp by simply
employing a resistive voltage divider.
For determining a proper value of capacitive coupling,
follow the same procedure as with the transmit cou-
pling capacitor.
To minimize power dissipation, let unused receive out-
puts float.
loss 20 log10 fin
12p
iRiCi
()÷[]
----------------------------------------
100.5 1fin
12p
iRiCi
()÷[]
----------------------------------------
2
+
----------------------------------------------------------------
=
66 Lucent Technologies Inc.
Application Note
November 1999
T7504 and T5504 Quad PCM Codecs with Filters
Board Layout and Decoupling
Concentrating four sets of analog/digital conversions in
an integrated device places an extra burden on the
board layout. Highly sensitive analog nodes and noisy
digital circuits are placed in close proximity. The high
dynamic range of the codec, which allows low noise
transmission of very small signal levels with minimal
crosstalk, could be jeopardized if proper grounding and
decoupling practices are not followed. Furthermore, the
codec will fail distortion and noise requirements if
proper grounding is not provided.
For best performance, a multilayer board is recom-
mended. One inner layer should be used for a com-
mon, low-impedance ground plane. It is perfectly
acceptable to short SLIC AGND and the codec GNDA
and GNDD pins directly to the inner ground layer. The
codec’s GNDA pins and its GNDD pin must be tied
together at the chip. Use individual vias for each device
ground pin.
If a two-layer board is to be used, a low-impedance
ground plane must be established. A micro-island
(flooded ground plane) and fat ground traces must be
used. To get the lowest-impedance ground plane pos-
sible, tie GNDA and GNDD leads together at the chip.
Provide a dedicated ground plane under the device to
connect these pins together. Fill unused areas around
the device and board with ground. Minimize the use of
vias in ground planes. If the ground plane must transfer
to the other layer, use multiple vias for a better connec-
tion. Give the ground planes routing priority over signal
traces. Keep clock traces short and guard, if possible.
VDD serves both analog and digital circuits. It is impor-
tant to place a 0.1 µF ceramic capacitor on both of
these pins to ground. Keep leads short by placing vias
as close to solder pads as possible. Use individual vias
for each power pin. Use two capacitors, one for each
VDD pin.
VDD is the demarcation point for analog and digital cir-
cuitry. Digital circuits are grouped together in one area
of the package. Runners f or analog and digital circuitry
should diverge from this point. Not following this prac-
tice could result in harmonic frequencies from carrier
modulation or digital transitions coupling into VFXIN
and the passband frequencies. Digital traces require a
continuous adjacent return path to minimize emissions.
Decouple any power or ground discontinuities.
Special consideration is required with regard to layout
of analog input leads to output leads. Interchannel and
intrachannel crosstalk into VFxIN can be significantly
affected by parasitic capacitance feeds from GSx and
VFRO. PWB layouts should be arranged to keep these
parasitics low. The T7504/T5504 Evaluation Board can
be used as a guide for correct layout technique.
The evaluation board achieves interchannel crosstalk
values of < –80 dB.
F or general board lay out, other general rules of digitally
controlled, audio frequency circuits apply. Digital cir-
cuitry should be placed as close to the edge connector
as possible. Clock leads should be kept as short as
possible. And a large bulk storage capacitor (47 µF or
thereabouts) in parallel with the 0.1 µF ceramics should
be placed at distribution points located near the con-
nector.
Specifications
Specifications and typical performance characteristics
are presented in the data sheet. For group delay, enve-
lope delay distortion (Table 8 of data sheet), a range of
values is given. The following discussion allows a user
to determine a specific group delay value for a given
set of conditions.
Group Delay
To deter mi ne abs ol ute round trip delay for FSEP ≥ 1
MCLK pulse wide, use the following formula and
Table 1.
DRTA = DC + DX + DR
For f = 1600 Hz, where:
DRTA = absolute round trip delay in microseconds.
DC = delay of the internal filter circuitry (times 2 for
round trip) in microseconds. F or transmit channels of 0
or 2, use a constant of 327. For transmit channels of 1
or 3, use a constant of 392.
DX = digital delay for transmit path in microseconds.
Obtain appropriate value f or a giv en transmit
channel and time slot from Table 1.
DR = digital delay for receive path in microseconds.
Obtain appropriate value for a given receive
channel and time slot from Tab le 1.
For absolute round trip delays for a single channel and
a single time-slot assignment with FSEP = 1 MCLK
pulse wide, DX = DR, and MCLK = 2.048 MHz, delays
will calc ul ate as follows:
Channels 0, 2 Time Slots 0—3, 16—31 405 µs
Time Slots 4—15 530 µs
Channels 1, 3 Time Slots 0—19 470 µs
Time Slots 20—31 595 µs
Application Note
November 1999
Lucent Technologies Inc. 7
T7504 and T5504 Quad PCM Codecs with Filters
Specifications (continued)
Table 1. Digital Delay Periods
Channel
Time Slot:
MCLK = DX
(Transmit
Digital
Delay)
DR
(Receive
Digital
Delay)
2.048
MHz 4.096
MHz
0, 2 0 0, 1 62.5 15.5
12, 366 12
24, 570 8
36, 774 4
4 8, 9 78 125
5 10, 11 82 121
6 12, 13 86 117
7 14, 15 90 113
8 16, 17 94 109
9 18, 19 98 105
10 20, 21 101.5 101.5
11 22, 23 105.5 97.5
12 24, 25 109 94
13 26, 27 113 90
14 28, 29 117 86
15 30, 31 121 82
16 32, 33 0 78
17 34, 35 4 74
18 36, 37 8 70
19 38, 39 12 66
20 40, 41 15.5 62.5
21 42, 43 19.5 58.5
22 44, 45 23 55
23 46, 47 27 51
24 48, 49 31 47
25 50, 51 35 43
26 52, 53 39 39
27 54, 55 43 35
28 56, 57 47 31
29 58, 59 51 27
30 60, 61 55 23
31 62, 63 58.5 19.5
1, 3 0 0, 1 0 78
12, 3 4 74
24, 5 8 70
36, 712 66
4 8, 9 15.5 62.5
5 10, 11 19.5 58.5
6 12, 13 23 55
7 14, 15 27 51
8 16, 17 31 47
9 18, 19 35 43
10 20, 21 39 39
11 22, 23 43 35
12 24, 25 47 31
13 26, 27 51 27
14 28, 29 55 23
15 30, 31 58.5 19.5
16 32, 33 62.5 15.5
17 34, 35 66 12
18 36, 37 70 8
19 38, 39 74 4
20 40, 41 78 125
21 42, 43 82 121
22 44, 45 86 117
23 46, 47 90 113
24 48, 49 94 109
25 50, 51 98 105
26 52, 53 101.5 101.5
27 54, 55 105 98
28 56, 57 109 94
29 58, 59 113 90
Channel
Time Slot:
MCLK = DX
(Transmit
Digital
Delay)
DR
(Receive
Digital
Delay)
2.048
MHz 4.096
MHz
88 Lucent Technologies Inc.
Application Note
November 1999
T7504 and T5504 Quad PCM Codecs with Filters
Applications
Time-Slot Enable Strobe
Some codecs provide a time-slot enable strobe. This
strobe is useful in enabling e x ternal 3-state buffers that
could be required to driv e heavily loaded b us lines. This
strobe provides an active-low pulse that envelops an
8-bit transmit PCM time slot. The quad codec does not
provide a time-slot enable output. A time-slot enable
pulse can be derived, however, from the T5504 frame
sync pulse. The T5504 operates in nondelayed timing
mode. The rising edge of frame sync envelops the first
bit of the time slot. Frame sync pulses can be set any-
where from one clock pulse wide to 255 or 511 clock
pulses wide (2.048 MHz and 4.096 MHz operation,
respectively). To generate a time-slot enable pulse, the
frame sync pulse should be set eight clock pulses wide.
Inverting the frame sync pulse generates an 8-bit wide
active-low pulse that can be used for time slot enable
(see Figure 5). Please note that for codec operation,
the FSEP pulse still needs to be supplied. For the
T5504, FSEP occurs one clock pulse prior to the time-
slot byte boundary.
To create a time-slot enable for the T7504, insert a D-
type flip-flop clocked by MCLK at node 1C in Figure 5.
5-4713F
5-4714
Figure 5. Time-Slot Enable Strobe Timing Diagram and Circuit
12 456783
MCLK
FSxN
Dx AND SDx
DERIVED TIME-SLOT
ENABLE STRO BE AT 1C
PCM
INTERFACE
T5504
Dx
DR
FSx0
FSx1
FSx2
FSx3
FSEP
1/2 74S260
MCLK
INTERNAL TIMING
1A 1Y
BUFFERED Dx
FROM OTHER CODECS
1C
SDx
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Application Note
November 1999 T7504 and T5504 Quad PCM Codecs with Filters
Applications (continued)
Codec Use Without FSEP Pulse
The T7504 codec can be used without using a separate
frame separation (FSEP) pulse. Operating in this fash-
ion, however, places restraints on operation and com-
plicates the digital interface by requiring a more
intelligent control. F or operation, tie FSEP pin 1 to FSx0
pin 25. FSx0 will now function as the FSEP pulse. (Any
other channel can be selected; for this discussion,
channel 0 was chosen.) FSx0 must occur every 125 µs
as time slot 0. It will therefore become the first channel
on and the last channel off on this codec. If the codec is
idle, the lack of FSx0 will power do wn the codec. When
data is to be transmitted and FSx0 reappears, channel
0 will power up and time slot 0 will become activ e while
the other three channels will go into standby power
mode. Other channels and time slots become active as
their respective FSx pulses are transmitted. If there is
activity on another channel after transmission on chan-
nel 0 is complete, channel 0 must be kept active until
the other channel is no longer in use. The width of
FSx0 determines in what time slot data is received. All
data will be transmitted in delayed timing mode.
SLIC Interface
Interfacing a codec to a SLIC is discussed in detail in
application materials relating to the SLIC. A basic inter-
face circuit for 600 Ω resistive termination and hybrid
balance, with TX and RX gains set at 0 dB, is shown in
Figure 6. RT6 and RX set up the transmit gain of the
codec. The value of RHB1 needs to be appropriately
selected according to loop gains to set up hybrid bal-
ance. RRCV and RGP (with RT3 in parallel) provide
attenuation of the codec receive signal. RT3 (with
RRCV and RGP in parallel) sets up the termination
impedance. CC1 and CC2 provide dc blocking of the
codec reference level and ac signal coupling. RGP2
and CGP are added for SLIC stability.
5-4716F
Figure 6. SLIC Interface (600 Ω
ΩΩ
Ω Resistive)
L8560
RGP
48.7 kΩ
VITR
RX
182 kΩ
–
+
–
+
GSX
VFXIN
VFRO
+2.4 V
T7504
RHB1
182 kΩ
RT6
121 kΩ
RRCV
113 kΩ
RT3
174 kΩ
RGN
RCVP
–
+
48.7 kΩ
CC2
0.1 µF
CC1
0.1 µF
RGP2
1.78 kΩ
CGP
150 pF
RCVN
Application Note
November 1999
T7504 and T5504 Quad PCM Codecs with Filters
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 1999 Lucent Technologies Inc.
All Rights Reserved
November 1999
AP00-004ALC (Replaces AP96-026ALC)
For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET: http://www.lucent.com/micro
E-MAIL: docmaster@micro.lucent.com
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1-800-372-2447, FAX 610-712-4106 ( In CANADA: 1-800-553-2448, FAX 610-712-4106)
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Tel. (65) 778 8833, FAX (65) 777 7495
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200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
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Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
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Applications (continued)
Speaker Driver
The T7504/T5504 quad codecs have single-ended
analog inputs and outputs. The analog output can drive
a minimum of 2000 Ω. The T7502 and T7503 dual
codecs have differential analog inputs and outputs. The
differential output in these devices can drive a minimum
of 300 Ω (600 Ω single ended). The T7502 and T7503
are the preferred choice for direct connection to micro-
phones and transformer drive applications. One can
readily interface the T7504/T5504 to a speaker, how-
ever, by using a generic dual 5 V op amp and a few
resistors and capacitors.
Figure 7 shows the T7504 interfacing a small speaker.
The LM358 op amp (or equivalent) is set up for unity
gain push-pull drive. The output of the codec is capaci-
tively coupled to the op amps with a large value capac-
itor suitable for audio frequencies. This capacitor
removes the output’s dc content. Another midpoint ref-
erence level is provided for the op amps by the R1/R2
voltage divider.
5-4715F
Figure 7. Speaker Driver Circuit
T7504
–
+
–
+
GNDA0
R2
10 kΩ
R1
10 kΩ
+5 V
C2
10 µF
GND
27
6
5
4
R3
10 kΩ
11
2
3
8
C1
10 µF
VFRO0
SMALL
+5 V
LM358
R4
10 kΩ
EFFICIENT
SPEAKER
