VN7010AJ High-side driver with MultiSense analog feedback for automotive applications Datasheet - production data - - - Loss of ground and loss of VCC Reverse battery with external components Electrostatic discharge protection Applications * Features Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 10 m Current limitation (typ) ILIMH 91 A Standby current (max) ISTBY 0.5 A * * * * Automotive qualified General - Single channel smart high-side driver with MultiSense analog feedback - Very low standby current - Compatible with 3 V and 5 V CMOS outputs MultiSense diagnostic functions - Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature - Overload and short to ground (power limitation) indication - Thermal shutdown indication - OFF-state open-load detection - Output short to VCC detection - Sense enable/disable Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin May 2015 * All types of Automotive resistive, inductive and capacitive loads Specially intended for Automotive Headlamps Description The device is a single channel high-side driver manufactured using ST proprietary VIPower(R) M07 technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. DocID027394 Rev 1 This is information on a product in full production. 1/45 www.st.com Contents VN7010AJ Contents 1 Block diagram and pin description ................................................ 5 2 Electrical specification.................................................................... 7 3 4 2.1 Absolute maximum ratings ................................................................ 7 2.2 Thermal data ..................................................................................... 8 2.3 Main electrical characteristics ........................................................... 8 2.4 Waveforms ...................................................................................... 19 2.5 Electrical characteristics curves ...................................................... 21 Protections..................................................................................... 25 3.1 Power limitation ............................................................................... 25 3.2 Thermal shutdown........................................................................... 25 3.3 Current limitation ............................................................................. 25 3.4 Negative voltage clamp ................................................................... 25 Application information ................................................................ 26 4.1 GND protection network against reverse battery............................. 26 4.1.1 Diode (DGND) in the ground line ..................................................... 27 4.2 Immunity against transient electrical disturbances .......................... 27 4.3 MCU I/Os protection........................................................................ 27 4.4 Multisense - analog current sense .................................................. 28 4.4.1 Principle of Multisense signal generation ......................................... 29 4.4.2 TCASE and VCC monitor ................................................................. 31 4.4.3 Short to VCC and OFF-state open-load detection ........................... 32 5 Maximum demagnetization energy (VCC = 16 V) ........................ 34 6 Package and PCB thermal data .................................................... 35 6.1 7 PowerSSO-16 thermal data ............................................................ 35 Package information ..................................................................... 38 7.1 PowerSSO-16 package information ................................................ 38 7.2 PowerSSO-16 packing information ................................................. 40 7.3 PowerSSO-16 marking information ................................................. 42 8 Order codes ................................................................................... 43 9 Revision history ............................................................................ 44 2/45 DocID027394 Rev 1 VN7010AJ List of tables List of tables Table 1: Pin functions ................................................................................................................................. 5 Table 2: Suggested connections for unused and not connected pins ........................................................ 6 Table 3: Absolute maximum ratings ........................................................................................................... 7 Table 4: Thermal data ................................................................................................................................. 8 Table 5: Power section ............................................................................................................................... 8 Table 6: Switching....................................................................................................................................... 9 Table 7: Logic inputs ................................................................................................................................. 10 Table 8: Protections .................................................................................................................................. 11 Table 9: MultiSense .................................................................................................................................. 11 Table 10: Truth table ................................................................................................................................. 18 Table 11: MultiSense multiplexer addressing ........................................................................................... 18 Table 12: ISO 7637-2 - electrical transient conduction along supply line................................................. 27 Table 13: MultiSense pin levels in off-state .............................................................................................. 31 Table 14: PCB properties ......................................................................................................................... 35 Table 15: Thermal parameters ................................................................................................................. 37 Table 16: PowerSSO-16 mechanical data................................................................................................ 38 Table 17: Reel dimensions ....................................................................................................................... 40 Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 41 Table 19: Device summary ....................................................................................................................... 43 Table 20: Document revision history ........................................................................................................ 44 DocID027394 Rev 1 3/45 List of figures VN7010AJ List of figures Figure 1: Block diagram .............................................................................................................................. 5 Figure 2: Configuration diagram (top view)................................................................................................. 6 Figure 3: Current and voltage conventions ................................................................................................. 7 Figure 4: IOUT/ISENSE versus IOUT....................................................................................................... 15 Figure 5: Current sense accuracy versus IOUT ....................................................................................... 15 Figure 6: Switching time and Pulse skew ................................................................................................. 16 Figure 7: MultiSense timings (current sense mode) ................................................................................. 16 Figure 8: Multisense timings (chip temperature and VCC sense mode) .................................................. 17 Figure 9: TDSTKON.................................................................................................................................. 17 Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) ...................... 19 Figure 11: Latch functionality - behavior in hard short circuit condition.................................................... 19 Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) .... 20 Figure 13: Standby mode activation ......................................................................................................... 20 Figure 14: Standby state diagram ............................................................................................................. 21 Figure 15: OFF-state output current ......................................................................................................... 21 Figure 16: Standby current ....................................................................................................................... 21 Figure 17: IGND(ON) vs. Iout ................................................................................................................... 22 Figure 18: Logic Input high level voltage .................................................................................................. 22 Figure 19: Logic Input low level voltage.................................................................................................... 22 Figure 20: High level logic input current ................................................................................................... 22 Figure 21: Low level logic input current .................................................................................................... 22 Figure 22: Logic Input hysteresis voltage ................................................................................................. 22 Figure 23: FaultRST Input clamp voltage ................................................................................................. 23 Figure 24: Undervoltage shutdown ........................................................................................................... 23 Figure 25: On-state resistance vs. Tcase ................................................................................................. 23 Figure 26: On-state resistance vs. VCC ................................................................................................... 23 Figure 27: Turn-on voltage slope .............................................................................................................. 23 Figure 28: Turn-off voltage slope .............................................................................................................. 23 Figure 29: Won vs. Tcase ......................................................................................................................... 24 Figure 30: Woff vs. Tcase ......................................................................................................................... 24 Figure 31: ILIMH vs. Tcase ....................................................................................................................... 24 Figure 32: OFF-state open-load voltage detection threshold ................................................................... 24 Figure 33: Vsense clamp vs. Tcase.......................................................................................................... 24 Figure 34: Vsenseh vs. Tcase .................................................................................................................. 24 Figure 35: Application diagram ................................................................................................................. 26 Figure 36: Simplified internal structure ..................................................................................................... 26 Figure 37: MultiSense and diagnostic - block diagram ............................................................................ 28 Figure 38: MultiSense block diagram ....................................................................................................... 29 Figure 39: Analogue HSD - open-load detection in off-state ................................................................... 30 Figure 40: Open-load / short to VCC condition ......................................................................................... 31 Figure 41: GND voltage shift .................................................................................................................... 32 Figure 42: Maximum turn off current versus inductance .......................................................................... 34 Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 35 Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 35 Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) ..................... 36 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .............. 36 Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16.......................................... 37 Figure 48: PowerSSO-16 package dimensions ........................................................................................ 38 Figure 49: PowerSSO-16 reel 13" ............................................................................................................ 40 Figure 50: PowerSSO-16 carrier tape ...................................................................................................... 41 Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape .................................................. 41 Figure 52: PowerSSO-16 marking information ......................................................................................... 42 4/45 DocID027394 Rev 1 VN7010AJ Block diagram and pin description Figure 1: Block diagram VCC Internal supply VCC - GND Clamp Undervoltage shut-down Con trol & Diagnostic VCC - OUT Clamp FaultRST INPUT Gate Driver SEL1 T VCC VON Limitation SEL0 Current Limitation SEn MultiSense MUX 1 Block diagram and pin description Power Limitation Overtemperature T Short to VCC Open-Load in OFF Current Sense Fault VSENSEH GND OUTPUT GAPGCFT00328 Table 1: Pin functions Name VCC Function Battery connection. OUTPUT Power outputs. All the pins must be connected together. GND INPUT Ground connection. Must be reverse battery protected by an external diode / resistor network. Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. It controls output switch state. MultiSense Multiplexed analog sense output pin; it delivers a current proportional to the selected diagnostic: load current, supply voltage or chip temperature. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. SEL0,1 Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. FaultRST Active low compatible with 3 V and 5 V CMOS outputs pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart. mode DocID027394 Rev 1 5/45 Block diagram and pin description VN7010AJ Figure 2: Configuration diagram (top view) PowerSSO-16 INPUT0 FaultRS T SEn GND SEL0 SEL1 MultiSense N.C. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 OUTPU T OUTPU T OUTPU T OUTPU T OUTPU T OUTPU T OUTPU T OUTPU T TAB = V CC GAPGCFT00329 Pins 9, 10, 11 and 12 are internally connected; Pins 13, 14, 15 and 16 are internally connected; All output pins must be connected together on PCB. Table 2: Suggested connections for unused and not connected pins SEn, SELx, Connection / pin MultiSense N.C. Output Input Floating Not allowed X (1) X X X To ground Through 1 k resistor X Not allowed Through 15 k resistor Through 15 k resistor Notes: (1)X: 6/45 do not care. DocID027394 Rev 1 FaultRST VN7010AJ 2 Electrical specification Electrical specification Figure 3: Current and voltage conventions IS VCC FaultRST I SEn I OUT OUTPUT VSEn I SEL MultiSense SEL 0,1 VSEL VOUT I SENSE SE n VFR VCC VFn I FR VSENSE I IN VIN INPUT I GND GAPGCFT00330 VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 38 -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 ) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT DC output current Internally limited -IOUT Reverse DC output current 35 IIN INPUT DC input current ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current VFR FaultRST DC input voltage DocID027394 Rev 1 V A -1 to 10 mA 7.5 V 7/45 Electrical specification VN7010AJ Symbol Parameter Unit MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 MultiSense pin DC output current in reverse (VCC < 0 V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150 C) 168 mJ VESD Electrostatic discharge (JEDEC 22A-114F) * INPUT * MultiSense * SEn, SEL0,1, FaultRST * OUTPUT * VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V ISENSE Tj Tstg 2.2 Value mA Junction operating temperature -40 to 150 Storage temperature -55 to 150 C Thermal data Table 4: Thermal data Symbol Parameter Typ. value Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) Rthj-amb Rthj-amb (1) Unit 3.9 Thermal resistance junction-ambient (JEDEC JESD 51-5) (2) 55 Thermal resistance junction-ambient (JEDEC JESD 51-7) (1) 21.2 C/W Notes: 2.3 (1)Device mounted on four-layers 2s2p PCB (2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace Main electrical characteristics 7 V < VCC < 18 V; -40C < Tj < 150C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. Table 5: Power section Symbol Parameter VCC Operating supply voltage VUSD Test conditions Typ. 4 13 Max. Unit 28 V Undervoltage shutdown 4 V VUSDReset Undervoltage shutdown reset 5 V VUSDhyst Undervoltage shutdown hysteresis 0.3 IOUT = 5 A; Tj = 25C RON 8/45 Min. On-state resistance V 10 IOUT = 5 A; Tj = 150C 20 IOUT = 5 A; VCC = 4 V; Tj = 25C 15 DocID027394 Rev 1 m VN7010AJ Electrical specification Symbol Vclamp ISTBY Parameter Test conditions Clamp voltage Min. Typ. IS = 20 mA; 25C < Tj < 150C 41 46 IS = 20 mA; Tj = -40C 38 IS(ON) IGND(ON) IL(off) VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 25C 0.5 VCC = 13 V; Supply current in VIN = VOUT = VFR = VSEn = 0 V; standby at VCC = 13 V (1) VSEL0,1 = 0 V; Tj = 85C (2) 0.5 VCC = 13 V; Standby mode blanking VIN = 5 V; VSEn = VFR = VSEL0,1 = 0 V; time IOUT = 0 V Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V; VIN = 5 V; IOUT = 0 A Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN = 5 V; IOUT = 5 A Off-state output current at VCC = 13 V Output - VCC diode voltage VF 52 V V VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 125C tD_STBY Max. Unit A 3 60 VIN = VOUT = 0 V; VCC = 13 V; Tj = 25C 0 VIN = VOUT = 0 V; VCC = 13 V; Tj = 125C 0 300 550 s 3 5 mA 6 mA 0.01 0.5 A 3 IOUT = -5 A; Tj = 150C 0.7 V Notes: (1)PowerMOS (2)Parameter leakage included. specified by design; not subject to production test. Table 6: Switching VCC = 13 V; -40C < Tj < 150C, unless otherwise specified Symbol Parameter td(on)(1) Turn-on delay time at Tj = 25 C td(off)(1) Turn-off delay time at Tj = 25 C (dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25 C (dVOUT/dt)off (1) Turn-off voltage slope at Tj = 25 C Test conditions Min. Typ. Max. Unit RL = 2.6 RL = 2.6 10 70 120 10 40 100 0.1 0.2 0.7 0.1 0.3 0.7 s V/s WON Switching energy losses at turn-on (twon) RL = 2.6 -- 0.9 1.2(2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 2.6 -- 0.6 0.8(2) mJ Differential Pulse skew (tPHL - tPLH) RL = 2.6 -90 -40 tSKEW (1) 10 s Notes: (1)See Figure 6: "Switching time and Pulse skew". (2)Parameter guaranteed by design and characterization; not subject to production test. DocID027394 Rev 1 9/45 Electrical specification VN7010AJ Table 7: Logic inputs 7 V < VCC < 28 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V INPUT characteristics VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN = 0.9 V A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage 1 V 5.3 IIN = -1 mA A 7.2 -0.7 V FaultRST characteristics VFRL Input low level voltage IFRL Low level input current VFRH Input high level voltage IFRH High level input current VFR(hyst) Input hysteresis voltage VFRCL 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage V V 5.3 IIN = -1 mA A 7.5 -0.7 V SEL0,1 characteristics (7 V < VCC < 18 V) VSELL Input low level voltage ISELL Low level input current VSELH Input high level voltage ISELH High level input current VSEL(hyst) Input hysteresis voltage VSELCL 0.9 VIN = 0.9 V A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA Input clamp voltage 1 A V 5.3 IIN = -1 mA V 7.2 -0.7 V SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage ISEnL Low level input current VSEnH Input high level voltage ISEnH High level input current VSEn(hyst) Input hysteresis voltage VSEnCL 10/45 Input clamp voltage 0.9 VIN = 0.9 V 1 A 2.1 V VIN = 2.1 V 10 0.2 IIN = 1 mA IIN = -1 mA DocID027394 Rev 1 V A V 5.3 7.2 -0.7 V VN7010AJ Electrical specification Table 8: Protections 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions ILIMH DC short circuit current ILIML Short circuit current during thermal cycling TTSD Shutdown temperature VCC = 13 V 4 V < VCC < 18 V Reset temperature TRS Thermal reset of fault diagnostic indication VFR = 0 V; VSEn = 5 V Thermal hysteresis (TTSD - TR)(1) TJ_SD Dynamic temperature Tj = -40C; VCC = 13 V Fault reset time for output unlatch(1) VFR = 5 V to 0 V; VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V VDEMAG VON 65 91 Max. Unit 130 A VCC = 13 V; TR < Tj < TTSD THYST tLATCH_RST Typ. (1) (1) TR Min. 30 150 175 200 TRS + 1 TRS + 7 C 135 7 Turn-off output voltage clamp Output voltage drop limitation 60 3 K 10 20 s IOUT = 2 A; L = 6 mH; Tj = -40C VCC - 38 V IOUT = 2 A; L = 6 mH; Tj = 25C to 150C VCC - 41 VCC - 46 VCC - 52 V 20 mV IOUT = 0.2 A Notes: (1)Parameter guaranteed by design and characterization; not subject to production test. Table 9: MultiSense 7 V < VCC < 18 V; -40C < Tj < 150C Symbol VSENSE_CL Parameter MultiSense clamp voltage Test conditions Min. Typ. Max. Unit VSEn = 0 V; ISENSE = 1 mA -17 -12 V VSEn = 0 V; ISENSE = -1 mA 7 CurrentSense characteristics K0 dK0/K0(1)(2) K1 dK1/K1(1)(2) K2 IOUT/ISENSE IOUT = 0.9 A; VSENSE = 0.5 V; VSEn = 5 V Current sense ratio drift IOUT = 0.9 A; VSENSE = 0.5 V; VSEn = 5 V IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V Current sense ratio drift IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE IOUT = 6 A; VSENSE = 4 V; VSEn = 5 V DocID027394 Rev 1 3190 5210 7450 -20 20 % 3530 4950 6560 -15 15 % 3840 4720 5640 11/45 Electrical specification VN7010AJ 7 V < VCC < 18 V; -40C < Tj < 150C Symbol dK2/K2(1)(2) K3 dK3/K3(1)(2) Parameter Test conditions Typ. Max. Unit -10 10 Current sense ratio drift IOUT = 6 A; VSENSE = 4 V; VSEn = 5 V IOUT/ISENSE IOUT = 18 A; VSENSE = 4 V; VSEn = 5 V Current sense ratio drift IOUT = 18 A; VSENSE = 4 V; VSEn = 5 V -5 5 MultiSense disabled: VSEn = 0 V 0 0.5 -0.5 0.5 MultiSense enabled: VSEn = 5 V; Channel ON; IOUT = 0 A; Diagnostic selected; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A 0 2 MultiSense enabled: VSEn = 5 V; Channel OFF; Diagnostic selected: VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V 0 2 MultiSense disabled: -1 V < VSENSE < 5 V(1) ISENSE0 Min. MultiSense leakage current % 4260 4710 5140 % A VOUT_MSD(1) VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; Output Voltage for VSEL1 = 0 V; RSENSE = 2.7 k; MultiSense shutdown IOUT = 5 A VSENSE_SAT VCC = 7 V; RSENSE = 2.7 k; Multisense saturation VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 18 A; voltage Tj = 150C 5 V ISENSE_SAT(1) VCC = 7 V; VSENSE = 4 V; VIN = 5 V; CS saturation current VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 4 mA VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150C 24 A VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V 2 IOUT_SAT(1) Output saturation current 5 V OFF-state diagnostic VOL IL(off2) 12/45 OFF-state open-load voltage detection threshold 3 OFF-state output sink VIN = 0 V; VOUT = VOL; Tj = -40C to -100 125C current tDSTKON OFF-state diagnostic delay time from falling VIN = 5 V to 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; edge of INPUT (see IOUT = 0 A; VOUT = 4 V Figure 9: "TDSTKON") tD_OL_V Settling time for valid OFF-state open load diagnostic indication from rising edge of SEn tD_VOL OFF-state diagnostic VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; delay time from rising VSEL1 = 0 V; VOUT = 0 V to 4 V edge of VOUT 100 350 VIN = 0 V; VFR = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 4 V; VSEn = 0 V to 5 V DocID027394 Rev 1 5 4 V -15 A 700 s 60 s 30 s VN7010AJ Electrical specification 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit Chip temperature analog feedback VSENSE_TC dVSENSE_TC/dT MultiSense output voltage proportional to chip temperature Temperature coefficient VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 k; Tj = -40C 2.325 2.41 2.495 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 k; Tj = 25C 1.985 2.07 2.155 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 k; Tj = 125C 1.435 1.52 1.605 V -5.5 mV/ K Tj = -40C to 150C Transfer function VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) VCC supply voltage analog feedback VSENSE_VCC MultiSense output VCC = 13 V; VSEn = 5 V; voltage proportional VSEL0 = 5 V; VSEL1 = 5 V; VIN = 0 V; to VCC supply voltage RSENSE = 1 k Transfer function (3) 3.16 3.23 3.3 V 6.6 V 30 mA VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10: "Truth table") VSENSEH MultiSense output voltage in fault condition VCC = 13 V; VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V; RSENSE = 1 k; 5 ISENSEH MultiSense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 MultiSense timings (current sense mode - see Figure 7: "MultiSense timings (current sense mode)")(4) tDSENSE1H Current sense settling VIN = 5 V; VSEn = 0 V to 5 V; time from rising edge RSENSE = 1 k; RL = 2.6 of SEn tDSENSE1L Current sense disable VIN = 5 V; VSEn = 5 V to 0 V; delay time from falling RSENSE = 1 k; RL = 2.6 edge of SEn tDSENSE2H Current sense settling VIN = 0 V to 5 V; VSEn = 5 V; time from rising edge RSENSE = 1 k; RL = 2.6 of INPUT tDSENSE2H tDSENSE2L 60 s 5 20 s 100 250 s 100 s 250 s Current sense settling time from rising edge VIN = 5 V; VSEn = 5 V; of IOUT (dynamic RSENSE = 1 k; ISENSE = 90 % of response to a step ISENSEMAX; RL = 2.6 change of IOUT) Current sense turn-off VIN = 5 V to 0 V; VSEn = 5 V; delay time from falling RSENSE = 1 k; RL = 2.6 edge of INPUT DocID027394 Rev 1 50 13/45 Electrical specification VN7010AJ 7 V < VCC < 18 V; -40C < Tj < 150C Symbol Parameter Test conditions Min. Typ. Max. Unit MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode)" )(4) tDSENSE3H VSENSE_TC settling time VSEn = 0 V to 5 V; VSEL0 = 0 V; from rising edge of VSEL1 = 5 V; RSENSE = 1 k SEn 60 s tDSENSE3L VSENSE_TC disable VSEn = 5 V to 0 V; VSEL0 = 0 V; delay time from falling VSEL1 = 5 V; RSENSE = 1 k edge of SEn 20 s MultiSense timings (VCC voltage sense mode - see Figure 8: "Multisense timings (chip temperature and VCC sense mode)")(4) tDSENSE4H VSENSE_VCC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 k 60 s tDSENSE4L VSENSE_VCC disable VSEn = 5 V to 0 V; VSEL0 = 5 V; delay time from falling VSEL1 = 5 V; RSENSE = 1 k edge of SEn 20 s MultiSense timings (Multiplexer transition times)(4) tD_CStoTC MultiSense transition delay from current sense to TC sense VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V to 5 V; IOUT = 2.5 A; RSENSE = 1 k 60 s tD_TCtoCS MultiSense transition delay from TC sense to current sense VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V to 0 V; IOUT = 2.5 A; RSENSE = 1 k 20 s tD_CStoVCC MultiSense transition delay from current sense to VCC sense VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 0 V to 5 V; IOUT = 2.5A; RSENSE = 1 k 60 s tD_VCCtoCS MultiSense transition VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V; delay from VCC sense VSEL1 = 5 V to 0 V; IOUT = 2.5 A; to current sense RSENSE = 1 k 20 s tD_TCtoVCC MultiSense transition delay from TC sense to VCC sense VCC = 13 V; Tj = 125C; VSEn = 5 V; VSEL0 = 0 V to 5 V; VSEL1 = 5 V; RSENSE = 1 k 20 s tD_VCCtoTC MultiSense transition VCC = 13 V; Tj = 125C; VSEn = 5 V; delay from VCC sense VSEL0 = 5 V to 0 V; VSEL1 = 5 V; to TC sense RSENSE = 1 k 20 s Notes: (1)Parameter (2)All (3)V CC sensing and TC are referred to GND potential. (4)Transition 14/45 specified by design; not subject to production test. values refer to VCC = 13 V; Tj = 25C, unless otherwise specified. delay are measured up to +/- 10% of final conditions. DocID027394 Rev 1 VN7010AJ Electrical specification K-factor Figure 4: IOUT/ISENSE versus IOUT 8000 7500 7000 6500 6000 5500 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 Max Min Typ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 IOUT [A] GAPG0508131345CFT Figure 5: Current sense accuracy versus IOUT 65 60 55 50 45 40 35 % 30 25 20 15 10 5 0 Current sense uncalibrated precision Current sense calibrated precision 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 IOUT [A] GAPG0508131350CFT DocID027394 Rev 1 15/45 Electrical specification VN7010AJ Figure 6: Switching time and Pulse skew twon VOUT twoff Vcc 80% Vcc ON OFF dVOUT/dt dVOUT/dt 20% Vcc t INPUT td(off) td(on) tpLH tpHL t GAPG2609141134CFT Figure 7: MultiSense timings (current sense mode) IN1 High SEn Low High SEL0 Low High SEL1 Low IOUT1 CURRENT SENSE tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L GAPGCFT00318 16/45 DocID027394 Rev 1 VN7010AJ Electrical specification Figure 8: Multisense timings (chip temperature and VCC sense mode) High SEn Low High SEL0 Low High SEL1 Low VCC VSENSE = VSENSE_VCC VSENSE = VSENSE_TC SENSE tDSENSE4H tDSENSE3H tDSENSE4L VCC VOLTAGE SENSE MODE tDSENSE3L CHIP TEMPERATURE SENSE MODE GAPGCFT00319 Figure 9: TDSTKON VINPU T VOU T VOU T > VOL MultiSense TDSTKON GAPG2609141140CFT DocID027394 Rev 1 17/45 Electrical specification VN7010AJ Table 10: Truth table Mode Conditions Standby INX FR SEn SELX OUTX MultiSense All logic inputs low Normal L L L X Nominal load H connected; Tj < 150 C L H Overload or short to GND causing: Tj > TTSD or Tj > Tj_SD Overload Hi-Z L See (1) H See (1) Outputs configured for auto-restart H H See (1) Outputs configured for Latch-off L X L See (1) H L H See (1) Output cycles with temperature hysteresis H H L See (1) Output latches-off L L Hi-Z Hi-Z Re-start when VCC > VUSD + VUSDhyst (rising) H See (1) H See (1) <0V See (1) VCC < VUSD (falling) X X OFF-state diagnostics Short to VCC L X Open-load L X Negative output Inductive loads turn-off L voltage X L Low quiescent current consumption L Undervoltage L Comments See (1) See (1) X X See (1) See (1) External pull-up Notes: (1)Refer to Table 11: "MultiSense multiplexer addressing" Table 11: MultiSense multiplexer addressing MultiSense output SEn SEL1 SEL0 MUX channel Normal mode Overload OFF-state diag. (1) L X X H L L H L H Output diagnostic H H L TCHIP Sense VSENSE = VSENSE_TC H H H VCC Sense VSENSE = VSENSE_VCC Negative output Hi-Z ISENSE = 1/K * IOUT VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z Notes: (1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L (latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN = 0; OUT = latched, VOUT > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH 18/45 DocID027394 Rev 1 VN7010AJ 2.4 Electrical specification Waveforms Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD) Figure 11: Latch functionality - behavior in hard short circuit condition DocID027394 Rev 1 19/45 Electrical specification VN7010AJ Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode + latch off) Figure 13: Standby mode activation 20/45 DocID027394 Rev 1 VN7010AJ Electrical specification Figure 14: Standby state diagram 2.5 Electrical characteristics curves Figure 16: Standby current Figure 15: OFF-state output current Iloff [nA] ISTBY [A] 1600 1.8 1400 1.6 Vcc = 13V 1.4 1200 Off State Vcc = 13V Vin = Vout = 0 1000 1.2 1 800 0.8 600 0.6 400 0.4 200 0.2 0 0 -50 -25 0 25 50 75 100 125 150 175 T [C] -50 -25 0 25 50 75 100 125 150 175 T [C] GAPG0805131355CFT DocID027394 Rev 1 GAPG0805131358CFT 21/45 Electrical specification VN7010AJ Figure 17: IGND(ON) vs. Iout Figure 18: Logic Input high level voltage IGND(ON) [mA] ViH, VFRH, VSELH, VSEnH [V] 3.5 2 1.8 3.0 1.6 2.5 1.4 Vcc = 13V Iout = 5A 2.0 1.2 1 1.5 0.8 0.6 1.0 0.4 0.5 0.2 0 0.0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG0805131409CFT GAPG0805131359CFT Figure 20: High level logic input current Figure 19: Logic Input low level voltage VilL VFRL, VSELL, VSEnL [V] IiH, IFRH, ISELH, ISEnH [A] 2 4 1.8 3.5 1.6 3 1.4 2.5 1.2 1 2 0.8 1.5 0.6 1 0.4 0.5 0.2 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG0805131411CFT Figure 21: Low level logic input current GAPG0805131413CFT Figure 22: Logic Input hysteresis voltage IiL, IFRL, ISELL, ISEnL [A] Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V] 4 1 3.5 0.9 0.8 3 0.7 2.5 0.6 2 0.5 0.4 1.5 0.3 1 0.2 0.5 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 GAPG0805131415CFT 22/45 -50 -25 0 25 50 75 100 125 150 175 T [C] T [C] DocID027394 Rev 1 GAPG0805131416CFT VN7010AJ Electrical specification Figure 23: FaultRST Input clamp voltage Figure 24: Undervoltage shutdown VUSD [V] VFRCL [V] 8 8 7 7 Iin = 1mA 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 0 1 0 -1 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG0805131421CFT Figure 25: On-state resistance vs. Tcase Ron [mOhm] GAPG0805131423CFT Figure 26: On-state resistance vs. VCC Ron [mOhm] 50 25 45 40 20 35 T = 150 C Iout = 5A Vcc = 13V 30 15 T = 125 C 25 20 T = 25 C 10 15 T = -40 C 10 5 5 0 0 -50 -25 0 25 50 75 100 125 150 175 0 5 10 15 T [C] 20 25 30 35 40 Vcc [V] GAPG0805131426CFT GAPG0805131425CFT Figure 27: Turn-on voltage slope (dVout/dt)On [V/s] Figure 28: Turn-off voltage slope (dVout/dt)Off [V/s] 1 1 0.9 0.9 0.8 0.8 Vcc = 13V Rl = 2.6 0.7 Vcc = 13V Rl = 2.6 0.7 0.6 0.6 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG0805131428CFT DocID027394 Rev 1 GAPG0805131430CFT 23/45 Electrical specification VN7010AJ Figure 29: Won vs. Tcase Figure 30: Woff vs. Tcase Won [mJ] Woff [mJ] 1 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 T [C] T [C] GAPG0805131431CFT GAPG0805131433CFT Figure 32: OFF-state open-load voltage detection threshold Figure 31: ILIMH vs. Tcase Ilimh [A] VOL [V] 120 4 115 3.5 110 3 105 2.5 100 Vcc = 13V 2 95 1.5 90 1 85 0.5 80 -50 -25 0 25 50 75 100 125 150 175 0 -50 T [C] -25 0 25 GAPG0805131434CFT 50 75 T [C] 100 125 150 175 GAPG0805131435CFT Figure 33: Vsense clamp vs. Tcase VSENSEH [V] VSENSE_CL [V] 10 10 9 9 8 8 7 Iin = 1mA 7 6 6 5 5 4 4 3 3 2 2 1 Iin = -1mA 1 0 0 -1 -50 -25 0 25 50 75 T [C] 100 125 150 175 GAPG0805131447CFT 24/45 Figure 34: Vsenseh vs. Tcase DocID027394 Rev 1 -50 -25 0 25 50 75 T [C] 100 125 150 175 GAPG0805131448CFT VN7010AJ Protections 3 Protections 3.1 Power limitation The basic working principle of this protection consists of an indirect measurement of the junction temperature swing Tj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as Tj exceeds the safety level of Tj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue. 3.2 Thermal shutdown In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High). 3.3 Current limitation The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region. 3.4 Negative voltage clamp In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. DocID027394 Rev 1 25/45 Application information 4 VN7010AJ Application information Figure 35: Application diagram 4.1 GND protection network against reverse battery Figure 36: Simplified internal structure 26/45 DocID027394 Rev 1 VN7010AJ 4.1.1 Application information Diode (DGND) in the ground line A resistor (typ. RGND = 4.7 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. 4.2 Immunity against transient electrical disturbances The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12: "ISO 7637-2 electrical transient conduction along supply line". Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: "The function does not perform as designed during the test but returns automatically to normal operation after the test". Table 12: ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) 1 III -112V 500 pulses 0,5 s 2a III +55V 500 pulses 0,2 s 5s 50s, 2 3a IV -220V 1h 90 ms 100 ms 0.1s, 50 3b IV +150V 1h 90 ms 100 ms 0.1s, 50 IV -7V 1 pulse 4 (2) min max 2ms, 10 100ms, 0.01 Load dump according to ISO 16750-2:2010 Test B (3) 40V 5 pulse 1 min 400ms, 2 Notes: (1)U S 4.3 is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. (2)Test pulse from ISO 7637-2:2004(E). (3)With 40 V external suppressor referred to ground (-40C < Tj < 150C). MCU I/Os protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs. DocID027394 Rev 1 27/45 Application information VN7010AJ The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup 20 mA; VOHC 4.5 V 7.5 k Rprot 140 k. Recommended values: Rprot = 15 k 4.4 Multisense - analog current sense Diagnostic information on device and load status are provided by an analog output pin (MultiSense) delivering the following signals: * * * Current monitor: current mirror of channel output current VCC monitor: voltage propotional to VCC TCASE: voltage propotional to chip temperature Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. Figure 37: MultiSense and diagnostic - block diagram 28/45 DocID027394 Rev 1 VN7010AJ 4.4.1 Application information Principle of Multisense signal generation Figure 38: MultiSense block diagram Current monitor When current mode is selected in the MultiSense, this output is capable to provide: * * Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE * ISENSE = RSENSE * IOUT/K Where: * * VSENSE is voltage measurable on RSENSE resistor ISENSE is current provided from MultiSense pin in current output mode DocID027394 Rev 1 29/45 Application information * * VN7010AJ IOUT is current flowing through output K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin which is switched to a "current limited" voltage source, VSENSEH. In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 39: Analogue HSD - open-load detection in off-state 30/45 DocID027394 Rev 1 VN7010AJ Application information Figure 40: Open-load / short to VCC condition Table 13: MultiSense pin levels in off-state Condition Output VOUT > VOL Open-load VOUT < VOL 4.4.2 Short to VCC VOUT > VOL Nominal VOUT < VOL MultiSense SEn Hi-Z L VSENSEH H Hi-Z L 0 H Hi-Z L VSENSEH H Hi-Z L 0 H TCASE and VCC monitor In this case, MultiSense output operates in voltage mode and output level is referred to device GND. Care must be taken in case a GND network protection is used, because of a voltage shift is generated between device GND and the microcontroller input GND reference. Figure 41: "GND voltage shift" shows link between VMEASURED and real VSENSE signal. DocID027394 Rev 1 31/45 Application information VN7010AJ Figure 41: GND voltage shift VCC monitor Battery monitoring channel provides VSENSE = VCC / 4. Case temperature monitor Case temperature monitor is capable to provide information about the actual device temperature. Since a diode is used for temperature sensing, the following equation describes the link between temperature and output VSENSE level: VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 C to 150 C). 4.4.3 Short to VCC and OFF-state open-load detection Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: 32/45 DocID027394 Rev 1 VN7010AJ Application information Equation RPU < VPU - 4 IL(off2)min @ 4V DocID027394 Rev 1 33/45 Maximum demagnetization energy (VCC = 16 V) 5 VN7010AJ Maximum demagnetization energy (VCC = 16 V) Figure 42: Maximum turn off current versus inductance VN7010AJ - Maximum turn off current versus inductance 100 I (A) 10 1 VN7010AJ - Single Pulse Repetitive pulse Tjstart=100C Repetitive pulse Tjstart=125C 0.1 0.1 1 10 L (mH) 100 1000 VN7010AJ - Maximum turn off Energy versus Tdemag 10000 VN7010AJ - Single Pulse 1000 Repetitive pulse Tjstart=100C E [mJ] Repetitive pulse Tjstart=125C 100 10 1 0.01 0.1 1 Tdemag [ms] 10 100 GAPGCFT01216 Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 34/45 DocID027394 Rev 1 VN7010AJ Package and PCB thermal data 6 Package and PCB thermal data 6.1 PowerSSO-16 thermal data Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14: PCB properties Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) DocID027394 Rev 1 Footprint, 2 cm2 or 8 cm2 35/45 Package and PCB thermal data VN7010AJ Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHjamb 90 RTHjamb 80 70 60 50 40 30 0 2 4 6 8 10 GAPGCFT01055 Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) ZTH (C/W) 100 10 1 Cu=foot print Cu=2 cm2 Cu=8 cm2 4 Layer 0 .1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 GAPGCFT01056 Equation: pulse calculation formula ZTH = RTH * + ZTHtp (1 - ) where = tP/T 36/45 DocID027394 Rev 1 VN7010AJ Package and PCB thermal data Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15: Thermal parameters Area/island (cm2) Footprint R1 (C/W) 0.15 R2 (C/W) 1.7 R3 (C/W) 2 8 4L 7 7 7 5 R4 (C/W) 16 6 6 4 R5 (C/W) 30 20 10 3 R6 (C/W) 26 20 18 7 C1 (W.s/C) 0.0015 C2 (W.s/C) 0.02 C3 (W.s/C) 0.1 C4 (W.s/C) 0.2 0.3 0.3 0.4 C5 (W.s/C) 0.4 1 1 4 C6 (W.s/C) 3 5 7 18 DocID027394 Rev 1 37/45 Package information 7 VN7010AJ Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 PowerSSO-16 package information Figure 48: PowerSSO-16 package dimensions Table 16: PowerSSO-16 mechanical data Millimeters Symbol Min. Max. 0 1 0 2 5 15 3 5 15 A 38/45 Typ. 8 1.70 A1 0.00 0.10 A2 1.10 1.60 DocID027394 Rev 1 VN7010AJ Package information Millimeters Symbol Min. b 0.20 b1 0.20 c 0.19 c1 0.19 D D1 Typ. Max. 0.30 0.25 0.28 0.25 0.20 0.23 4.9 BSC 3.60 4.20 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 1.90 2.50 h 0.25 0.50 L 0.40 0.60 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 0.85 Tolerance of form and position aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15 DocID027394 Rev 1 39/45 Package information 7.2 VN7010AJ PowerSSO-16 packing information Figure 49: PowerSSO-16 reel 13" Table 17: Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 Notes: (1)All 40/45 dimensions are in mm. DocID027394 Rev 1 VN7010AJ Package information Figure 50: PowerSSO-16 carrier tape 0.30 0.05 P2 P0 2.0 0.1 4.0 0.1 X 1.55 0.05 1.75 0.1 B0 W F 1.60.1 R 0.5 Typical K1 Y Y X K0 P1 A0 REF 4.18 REF 0.6 SECTION X - X REF 0.5 SECTION Y - Y GAPG2204151242CFT Table 18: PowerSSO-16 carrier tape dimensions Description Value(1) A0 6.50 0.1 B0 5.25 0.1 K0 2.10 0.1 K1 1.80 0.1 F 5.50 0.1 P1 8.00 0.1 W 12.00 0.3 Notes: (1)All dimensions are in mm. Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape DocID027394 Rev 1 41/45 Package information 7.3 VN7010AJ PowerSSO-16 marking information Figure 52: PowerSSO-16 marking information Marking area 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not in scale) GAPG0401151415CFT Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. 42/45 DocID027394 Rev 1 VN7010AJ 8 Order codes Order codes Table 19: Device summary Order codes Package Tape and reel PowerSSO-16 VN7010AJTR DocID027394 Rev 1 43/45 Revision history 9 VN7010AJ Revision history Table 20: Document revision history 44/45 Date Revision 19-May-2015 1 DocID027394 Rev 1 Changes Initial release. VN7010AJ IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. 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