VN7010AJTR - STMicroelectronics - Datasheet.Directory

VN7010AJ

High-side driver with MultiSense analog feedback for automotive

applications

Datasheet - product ion data

Features

Max transient supply voltage VCC 40 V

Operating voltage range VCC 4 to 28 V

Typ. on-state resistance (per Ch) RON 10 mΩ

Current limitation (typ) ILIMH 91 A

Standby current (max) ISTBY 0.5 µA

• Automotive qualified

• General

− Single channel smart high-side driver

with MultiSense analog feedback

− Very low standby current

− Com patible with 3 V and 5 V CMOS

outputs

• MultiSense diagnostic functions

− Multiplexed analog feedback of: load

current with high precision proportional

current mirror, V CC suppl y voltage and

TCHIP device temperature

− Overload and short to ground (power

limitation) indication

− Thermal shutdown indication

− OFF-state open-load detection

− Output short to VCC detection

− Sense enabl e/d isab le

• Protections

− Undervoltage shutdown

− Overvoltage clamp

− Load current limitation

− Self limiting of fast thermal transients

− Configurable latch-off on

overtemperature or power limitation

with dedicated fault reset pin

− Loss of ground and loss of VCC

− Reverse battery with external

components

− Electrostatic discharge protection

Applications

• All types of Automotive resistive, inductive

and capacitive loads

• Specially intended for Automotive

Headlamps

Description

The device is a single channel high-side driver

manufactured using ST proprietary VIPower® M0-

7 technology and housed in PowerSSO-16

package. The device is designed to drive 12 V

automotive grounded loads through a 3 V and

5 V CMOS-compatible interface, providing

protection and diagnostics.

The device integrates advanced protective

functions such as load current limitation, overload

active management by power limitation and

overtemperature shutdown with configurable

latch-off.

A FaultRST pin unlatches t he outp ut in case of

fault or disables the latch-off functionality.

A dedicated multifunction multiplexed analog

output pin delivers sophisticated diagnostic

functions including high precision proportional

load current sense, supply voltage feedback and

chip temperature sense, in addition to the

detection of overload and short circuit to ground,

short to VCC and OFF-state open-load.

A sense enable pin allows OFF-state diagnosis to

be disabled during the module low-power mode

as well as external sense resistor sharing among

similar devices.

May 2015 DocID027394 Rev 1 1/45

This is information on a product in full production. www.st.com

Contents

VN7010AJ

Contents

1 Block diagram and pin des cr iption ................................................ 5

2 Electrical specification .................................................................... 7

2.1 Absolute maxi mu m ratings ................................................................ 7

2.2 Thermal dat a ..................................................................................... 8

2.3 Main electrical characteristics ........................................................... 8

2.4 Waveforms ...................................................................................... 19

2.5 Electrical characteristics curves ...................................................... 21

3 Protections..................................................................................... 25

3.1 Power limitation ............................................................................... 25

3.2 Thermal shutdown ........................................................................... 25

3.3 Current limitation ............................................................................. 25

3.4 Negative voltage clamp ................................................................... 25

4 Application information ................................................................ 26

4.1 GND protection network against reverse battery ............................. 26

4.1.1 Diode (DGND) in the ground line ..................................................... 27

4.2 Immunity against transient electrical disturbances .......................... 27

4.3 MCU I/Os protection ........................................................................ 27

4.4 Multisense - analog current sense .................................................. 28

4.4.1 Principle of Multisense signal generation ......................................... 29

4.4.2 TCASE and VCC monitor ................................................................. 31

4.4.3 Short to VCC and OFF-state open-l oad det ec tio n ........................... 32

5 Maxim um demagne t izati on ener gy (VCC = 16 V) ........................ 34

6 Package and PCB thermal data .................................................... 35

6.1 PowerSSO-16 thermal data ............................................................ 35

7 Package information ..................................................................... 38

7.1 PowerSSO-16 package information ................................................ 38

7.2 PowerSSO-16 packing information ................................................. 40

7.3 PowerSSO-16 marki ng in format ion ................................................. 42

8 Order c ode s ................................................................................... 43

9 Revision history ............................................................................ 44

2/45 DocID027394 Rev 1

VN7010AJ

List of tables

Table 1: Pin functions ................................................................................................................................. 5

Table 2: Suggested connections for unused and not connected pins ........................................................ 6

Table 3: Absolute maximum ratings ........................................................................................................... 7

Table 4: Thermal data ................................................................................................................................. 8

Table 5: Power section ............................................................................................................................... 8

Table 6: Switching ....................................................................................................................................... 9

Table 7: Logic inputs ................................................................................................................................. 10

Table 8: Protec t io ns .................................................................................................................................. 11

Table 9: MultiSense .................................................................................................................................. 11

Table 10: Truth table ................................................................................................................................. 18

Table 11: MultiSense multiplexer addressing ........................................................................................... 18

Table 12: ISO 7637-2 - electrical transient conduction along supply line ................................................. 27

Table 13: MultiSense pin levels in off-state .............................................................................................. 31

Table 14: PCB properties ......................................................................................................................... 35

Table 15: Thermal parameters ................................................................................................................. 37

Table 16: PowerSSO-16 mechanical data................................................................................................ 38

Table 17: Reel dimensions ....................................................................................................................... 40

Table 18: PowerSSO-16 carrier tape dimensions .................................................................................... 41

Table 19: Device summary ....................................................................................................................... 43

Table 20: Document revision history ........................................................................................................ 44

DocID027394 Rev 1 3/45

List of figur es

VN7010AJ

List of figures

Figure 1: Block diagram .............................................................................................................................. 5

Figure 2: Configuration diagram (top view)................................................................................................. 6

Figure 3: Current and voltage conventions ................................................................................................. 7

Figure 4: IOUT/ISENSE versus IOUT ....................................................................................................... 15

Figure 5: Current sense accuracy versus IOUT ....................................................................................... 15

Figure 6: Switching time and Pulse skew ................................................................................................. 16

Figure 7: MultiSense timings (current sense mode) ................................................................................. 16

Figure 8: Multisense timings (chip temperature and VCC sense mode) .................................................. 17

Figure 9: TDSTKON .................................................................................................................................. 17

Figure 10: Latch func t ion al ity - behavior in hard short circuit condition (TAMB << TTSD) ...................... 19

Figure 11: Latch func t ion al ity - behavior in hard short circuit condition .................................................... 19

Figure 12: Latch func t ion al ity - behavior in hard short circuit condition (autorestart mode + latch off) .... 20

Figure 13: Standby mode activation ......................................................................................................... 20

Figure 14: Stand b y state di agram ............................................................................................................. 21

Figure 15: OFF-state output current ......................................................................................................... 21

Figure 16: Stand b y curre nt ....................................................................................................................... 21

Figure 17: IGND(ON) vs. Iout ................................................................................................................... 22

Figure 18: Logic Input hi gh le vel volt age .................................................................................................. 22

Figure 19: Logic Input lo w level vo ltag e .................................................................................................... 22

Figure 20: High lev el logic input curre nt ................................................................................................... 22

Figure 21: Low level logic input current .................................................................................................... 22

Figure 22: Logic Input h yster es is volt age ................................................................................................. 22

Figure 23: FaultRST Input clamp voltage ................................................................................................. 23

Figure 24: Under vo lta ge shut do wn ........................................................................................................... 23

Figure 25: On-state resistance vs. Tcase ................................................................................................. 23

Figure 26: On-state resistance vs. VCC ................................................................................................... 23

Figure 27: Turn-on volta ge s lope .............................................................................................................. 23

Figure 28: Turn-off voltage slope .............................................................................................................. 23

Figure 29: Won vs. Tcase ......................................................................................................................... 24

Figure 30: Woff vs. Tcase ......................................................................................................................... 24

Figure 31: ILIMH vs. Tcase ....................................................................................................................... 24

Figure 32: OFF-state open-load voltage detection threshold ................................................................... 24

Figure 33: Vsense clamp vs. Tcase .......................................................................................................... 24

Figure 34: Vsense h vs . Tc ase .................................................................................................................. 24

Figure 35: Appl icati on dia gram ................................................................................................................. 26

Figure 36: Simplified internal structure ..................................................................................................... 26

Figure 37: Multi Se nse a nd diagnos t ic – block diagram ............................................................................ 28

Figure 38: MultiSense block diagram ....................................................................................................... 29

Figure 39: Anal ogu e HSD – open-load detect ion in of f -state ................................................................... 30

Figure 40: Open-load / short to VCC condition ......................................................................................... 31

Figure 41: GND voltage shift .................................................................................................................... 32

Figure 42: Maximum turn off current versus inductance .......................................................................... 34

Figure 43: Power S SO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ............................................ 35

Figure 44: Power S SO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ........................................... 35

Figure 45: Rthj-amb vs PCB copper area in open box free air condition (one channel on) ..................... 36

Figure 46: Power S SO-16 thermal impedance junction ambient single pulse (one channel on) .............. 36

Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16.......................................... 37

Figure 48: Power S SO-16 package dimensions ........................................................................................ 38

Figure 49: Power S SO-16 reel 13" ............................................................................................................ 40

Figure 50: Power S SO-16 carrier tape ...................................................................................................... 41

Figure 51: Power S SO-16 schematic drawing of leader and trailer tape .................................................. 41

Figure 52: Power S SO-16 marking information ......................................................................................... 42

4/45 DocID027394 Rev 1

VN7010AJ

Block diagram and pin description

1 Block diagram and pin description

Figure 1: Block diagra m

Table 1: Pin functions

Name Function

VCC Battery connection.

OUTPUT Power outputs. All the pins must be connected together.

GND Ground connection. Must be reverse battery protected by an external diode / resistor

network.

INPUT Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs.

It controls output switch state.

MultiSense

Multiplexed analog sense output pin; it delivers a current proportional to the selected

diagnostic: load current, supply voltage or chip temperature.

SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense

diagnostic pin.

SEL0,1 Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense

multiplexer.

FaultRST Active low compatible with 3 V and 5

V CMOS outputs pin; it unlatches the output in case

of fault; If kept low, sets the outputs in auto-rest ar t. mod e

Con tr o l &Diagnostic

Limitation

Current

Limitation

– OUT

Clamp

Internal supply

OUTPUT

MUX

Current

Sense

GND

Undervoltage

shut-down

– GND

Clamp

Fault

Short to V

Open-Loadin OFF

Overtemperature

Power Limitation

SENSEH

INPUT

SEL

SEn

MultiSense

FaultRST

Gate Driver

GAPGCFT00328

DocID027394 Rev 1 5/45

Block diagram and pin description

VN7010AJ

Figure 2: Configuration diagram (top view)

Pins 9, 10, 11 and 12 are internally connected; Pins 13, 14, 15 and 16 are

internally connected; All output pins must be connected together on PCB.

Table 2: Suggested connections for unused and not connected pins

Connection /

pin MultiSense N.C.

Output Input SEn, SELx,

FaultRST

Floating Not allowed X (1)

X X X

To ground Through 1 kΩ

resistor X Not

allowed Through 15 kΩ

resistor Through 15 kΩ

resistor

Notes:

(1)X: do not care.

MultiSense

FaultRSTOUTPUT

SEn

N.C.

11OUTPU T

OUTPUT

SEL1

GND

INPUT0

TAB = VCC

PowerSSO-16

GAPGCFT00329

SEL0

6/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

2 Electrical specification

Figure 3: Current and voltage conventions

= V

OUTn

- V

during reverse battery condition.

2.1 Absolute m a xi m um rat ings

Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to the conditions in table below for extended

periods may affect device reliability.

Table 3: A bsolut e maximum rat ings

Symbol

Parameter Value Unit

VCC DC supply voltage 38 V

-VCC Reverse DC supply voltage 0.3

VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B

clamped to 40 V; RL = 4 Ω) 40 V

VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V

-IGND DC reverse ground pin current 200 mA

IOUT OUTPUT DC output current Internally limited

-IOUT Reverse DC output current 35

IIN INPUT DC input current

-1 to 10 mA

ISEn SEn DC input current

ISEL SEL0,1 DC input curre nt

IFR FaultRST DC input current

VFR FaultRST DC input voltage 7.5 V

OUTPUT

MultiSense

FaultRST

SEL

0,1

INPUT

SEL

SEn

GND

SENSE

OUT

SENSE

SEL

SEn

GAPGCFT00330

DocID027394 Rev 1 7/45

Electrical specification

VN7010AJ

Symbol

Parameter Value Unit

ISENSE MultiSense pin DC output current (VGND = VCC and VSENSE < 0 V) 10 mA

MultiSense pin DC output current in reverse (VCC < 0 V) -20

EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms;

Tjstart = 150 °C) 168 mJ

VESD

Electrostatic discharge (JEDEC 22A-114F)

• INPUT

• MultiSense

• SEn, SEL0,1, FaultRST

• OUTPUT

• VCC

4000

2000

4000

VESD Charge device model (CDM-AEC-Q100-011) 750 V

Tj Junction operating temperature -40 to 150 °C

Tstg Storage temperat ure -55 to 150

2.2 Thermal da t a

Table 4: Thermal data

Symbol Parameter Typ. value Unit

Rthj-board T hermal resi stan ce jun cti on-board (JEDEC JESD 51-5 / 51-8) (1) 3.9

°C/W

Rthj-amb Thermal resistan ce jun cti on-ambient (JEDEC JESD 51-5)(2) 55

Rthj-amb Thermal resistan ce jun cti on-ambient (JEDEC JESD 51-7)(1) 21.2

Notes:

(1)Device mounted on four-layers 2s2p PCB

(2)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace

2.3 Main electrical characteristics

7 V < VCC < 18 V; -40°C < Tj < 150°C, unless otherwise specified.

All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.

Table 5: Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply

voltage

4 13 28 V

VUSD Undervoltage shut dow n

4 V

VUSDReset

Undervolta ge shut down

reset

5 V

VUSDhyst Undervolta ge shut down

hysteresis

0.3

RON On-state resistance

IOUT = 5 A; Tj = 25°C

mΩ IOUT = 5 A; Tj = 150°C

IOUT = 5 A; VCC = 4 V; Tj = 25°C

8/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

Symbol Parameter Test conditions Min. Typ. Max. Unit

Vclamp Clamp voltage IS = 20 mA; 25°C < Tj < 150°C 41 46 52 V

IS = 20 mA; Tj = -40°C 38

ISTBY Supply current in

standby at VCC = 13 V (1)

VCC = 13 V;

VIN = VOUT = VFR = VSEn = 0 V;

VSEL0,1 = 0 V; Tj = 25°C 0.5

µA

VCC = 13 V;

VIN = VOUT = VFR = VSEn = 0 V;

VSEL0,1 = 0 V; Tj = 85°C (2) 0.5

VCC = 13 V;

VIN = VOUT = VFR = VSEn = 0 V;

VSEL0,1 = 0 V; Tj = 125°C 3

tD_STBY Standby mode blanking

time

VCC = 13 V;

VIN = 5 V; VSEn = VFR = VSEL0,1 = 0 V;

IOUT = 0 V 60 300 550 µs

IS(ON) Supply current VCC = 13 V;

VSEn = VFR = VSEL0,1 = 0 V; VIN = 5 V;

IOUT = 0 A 3 5 mA

IGND(ON)

Control stage curr en t

consumption in ON

state. All c hannels

active.

VCC = 13 V; VSEn = 5 V;

VFR = VSEL0,1 = 0 V; VIN = 5 V;

IOUT = 5 A 6 mA

IL(off) Off-state output curre nt

at VCC = 13 V

VIN = VOUT = 0 V; VCC = 13 V;

Tj = 25°C 0 0.01 0.5 µA

VIN = VOUT = 0 V; VCC = 13 V;

Tj = 125°C 0

VF Output - VCC diode

voltage IOUT = -5 A; Tj = 150°C

0.7 V

Notes:

(1)PowerMOS leakage included.

(2)Parameter specified by design; not subject to production t est.

Table 6: Switchin g

VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified

Symbol Parameter Test conditions Min. Typ.

Max. Unit

td(on)(1) Turn-on delay time at Tj = 25 °C RL = 2.6 Ω 10 70 120 µs

td(off)(1) Turn-off delay time at Tj = 25 °C 10 40 100

(dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25 °C RL = 2.6 Ω 0.1 0.2 0.7 V/µs

(dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25 °C 0.1 0.3 0.7

WON Switching energy losses at turn-on (twon) RL = 2.6 Ω — 0.9 1.2(2) mJ

WOFF Switching energy losses at turn-off (twoff) RL = 2.6 Ω — 0.6 0.8(2) mJ

tSKEW(1) Differential Pulse skew (tPHL - tPLH) RL = 2.6 Ω -90 -40 10 µs

Notes:

(1)See Figure 6: "Switching time and Pulse skew".

(2)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.

DocID027394 Rev 1 9/45

Electrical specification

VN7010AJ

Table 7: Logic inputs

7 V < VCC < 28 V; -40°C < Tj < 150°C

Symbol Parameter Test conditions Min. Typ. Max. Unit

INPUT characteristics

VIL Input low level voltage

0.9 V

IIL Low level input current VIN = 0.9 V 1

µA

VIH Input high level voltage

2.1

IIH High level input current VIN = 2.1 V

10 µA

VI(hyst) Input hystere si s voltage

0.2

VICL Input clamp voltag e IIN = 1 mA 5.3

7.2 V

IIN = -1 mA

-0.7

FaultRST characteristics

VFRL Input low level voltage

0.9 V

IFRL Low level input current VIN = 0.9 V 1

µA

VFRH Input high level voltage

2.1

IFRH High level input current VIN = 2.1 V

10 µA

VFR(hyst) Input hysteresi s volta ge

0.2

VFRCL Input clamp voltage IIN = 1 mA 5.3

7.5 V

IIN = -1 mA

-0.7

SEL0,1 characteristics (7 V < VCC < 18 V)

VSELL Input low level voltage

0.9 V

ISELL Low level input current VIN = 0.9 V 1

µA

VSELH Input high level voltage

2.1

ISELH High level input current VIN = 2.1 V

10 µA

VSEL(hyst) Input hysteresi s voltage

0.2

VSELCL Input clamp voltage IIN = 1 mA 5.3

7.2 V

IIN = -1 mA

-0.7

SEn characteristics (7 V < VCC < 18 V)

VSEnL Input low level voltage

0.9 V

ISEnL Low level input current VIN = 0.9 V 1

µA

VSEnH Input high level voltage

2.1

ISEnH High level input current VIN = 2.1 V

10 µA

VSEn(hyst) Input hysteresis voltage

0.2

VSEnCL Input clamp voltage IIN = 1 mA 5.3

7.2 V

IIN = -1 mA

-0.7

10/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

Table 8: Protections

7 V < VCC < 18 V; -40°C < Tj < 150°C

Symbol Parameter Test conditions Min. Typ. Max. Unit

ILIMH DC short circuit current VCC = 13 V 65 91 130 A

4 V < VCC < 18 V (1)

ILIML Short circuit current

during thermal cycling VCC = 13 V;

TR < Tj < TTSD

TTSD Shutdown temperature

150 175 200

°C

TR Reset temperature(1)

TRS + 1 TRS + 7

TRS Thermal reset of fault

diagnostic ind ica tio n VFR = 0 V; VSEn = 5 V 135

THYST Thermal hysteresis

(TTSD - TR)(1)

ΔTJ_SD Dynamic temperature Tj = -40°C; VCC = 13 V

tLATCH_RST

Fault reset time for

output unlatch(1)

VFR = 5 V to 0 V; VSEn = 5 V;

VIN = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V 3 10 20 µs

VDEMAG Turn-off output voltage

clamp

IOUT = 2 A; L = 6 mH;

Tj = -40°C VCC - 38

IOUT = 2 A; L = 6 mH;

Tj = 25°C to 150°C VCC - 41 VCC - 46

VCC - 52 V

VON Output volt age drop

limitation IOUT = 0.2 A

Notes:

(1)Parameter guaranteed by design and characterizati on; not subj ect to product i on test.

Table 9: MultiSen se

7 V < VCC < 18 V; -40°C < Tj < 150°C

Symbol Parameter Test conditions Min. Typ. Max.

Unit

VSENSE_CL MultiS ense clamp

voltage

SEn

= 0 V; I

SENSE

= 1 mA

-17

-12 V

VSEn = 0 V; ISENSE = -1 mA

CurrentS ense char act er istics

K0 IOUT/ISENSE IOUT = 0.9 A; VSENSE = 0.5 V;

VSEn = 5 V 3190 5210 7450

dK0/K0(1)(2) Current sense ratio

drift IOUT = 0.9 A; VSENSE = 0.5 V;

VSEn = 5 V -20

20 %

K1 IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V;

VSEn = 5 V 3530 4950 6560

dK1/K1(1)(2) Current sense ratio

drift IOUT = 1.5 A; VSENSE = 4 V;

VSEn = 5 V -15

15 %

K2 IOUT/ISENSE IOUT = 6 A; VSENSE = 4 V;

VSEn = 5 V 3840 4720 5640

DocID027394 Rev 1 11/45

Electrical specification

VN7010AJ

7 V < VCC < 18 V; -40°C < Tj < 150°C

Symbol Parameter Test conditions Min. Typ. Max.

Unit

dK2/K2(1)(2) Current sense ratio

drift IOUT = 6 A; VSENSE = 4 V;

VSEn = 5 V -10

10 %

K3 IOUT/ISENSE IOUT = 18 A; VSENSE = 4 V;

VSEn = 5 V 4260 4710 5140

dK3/K3(1)(2) Current sense ratio

drift IOUT = 18 A; VSENSE = 4 V;

VSEn = 5 V -5

5 %

ISENSE0 MultiSense leakage

current

MultiSense disabled: VSEn = 0 V 0

0.5

µA

MultiSense disabled:

-1 V < VSENSE < 5 V(1) -0.5

0.5

MultiSense enabled: VSEn = 5 V;

Channel ON; IOUT = 0 A;

Diagnostic selected; VIN = 5 V;

VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A 0 2

MultiSense enabled: VSEn = 5 V;

Channel OFF; Diagnostic

selected:

VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V 0 2

VOUT_MSD(1) Output Voltage for

MultiS ense shut dow n

VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V; RSENSE = 2.7 kΩ;

IOUT = 5 A 5 V

VSENSE_SAT Multisense saturation

voltage

VCC = 7 V; RSENSE = 2.7 kΩ;

VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V; IOUT = 18 A;

Tj = 150°C

5 V

ISENSE_SAT(1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V;

VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V; Tj = 150°C 4 mA

IOUT_SAT(1) Output saturation

current

VCC = 7 V; VSENSE = 4 V; VIN = 5 V;

VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V; Tj = 150°C 24 A

OFF-state diagnostic

VOL OFF-state open-load

voltage detection

threshold

VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V 2 3 4 V

IL(off2) OFF-state output sin k

current VIN = 0 V; VOUT = VOL; Tj = -40°C to

125°C -100

-15 µA

tDSTKON

OFF-state diagnostic

delay time from falling

edge of INPUT (see

Figure 9:

"TDSTKON")

VIN = 5 V to 0 V; VSEn = 5 V;

VSEL0 = 0 V; VSEL1 = 0 V;

IOUT = 0 A; VOUT = 4 V 100 350 700 µs

tD_OL_V

Settling time for valid

OFF-state open load

diagnostic ind ica tio n

from rising edge of

SEn

VIN = 0 V; VFR = 0 V; VSEL0 = 0 V;

VSEL1 = 0 V; VOUT = 4 V; VSEn = 0 V

to 5 V 60 µs

tD_VOL OFF-state diagnostic

delay time from rising

edge of VOUT

VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V; VOUT = 0 V to 4 V 5 30 µs

12/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

7 V < VCC < 18 V; -40°C < Tj < 150°C

Symbol Parameter Test conditions Min. Typ. Max.

Unit

Chip temperature analog feedback

VSENSE_TC MultiSense output

voltage propor tio nal

to chip temperature

VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 5 V; VIN = 0 V;

RSENSE = 1 kΩ; Tj = -40°C 2.325

2.41 2.495

VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 5 V; VIN = 0 V;

RSENSE = 1 kΩ; Tj = 25°C 1.985

2.07 2.155

VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 5 V; VIN = 0 V;

RSENSE = 1 kΩ; Tj = 125°C 1.435

1.52 1.605

dVSENSE_TC/dT

Temperature

coefficient Tj = -40°C to 150°C

-5.5

mV/

Transfer function VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)

VCC supply voltage analog feedback

VSENSE_VCC MultiSense output

voltage propor tio nal

to VCC supply voltage

VCC = 13 V; VSEn = 5 V;

VSEL0 = 5 V; VSEL1 = 5 V; VIN = 0 V;

RSENSE = 1 kΩ 3.16 3.23 3.3 V

Transfer function (3) VSENSE_VCC = VCC / 4

Fault diagnostic feedback (see Table 10: "Truth table")

VSENSEH MultiSense output

voltage in fault

condition

VCC = 13 V; VIN = 0 V; VSEn = 5 V;

VSEL0 = 0 V; VSEL1 = 0 V;

IOUT = 0 A; VOUT = 4 V;

RSENSE = 1 kΩ;

5 6.6 V

ISENSEH MultiSense output

cu rrent in fault

condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA

MultiSense ti mings (current sense mode - see Figure 7: "MultiSense timings (current sense

mode)")(4)

tDSENSE1H

Current sense sett ling

time from rising edge

of SEn

VIN = 5 V; VSEn = 0 V to 5 V;

RSENSE = 1 kΩ; RL = 2.6 Ω 60 µs

tDSENSE1L

Current sense disa ble

delay time from falling

edge of SEn

VIN = 5 V; VSEn = 5 V to 0 V;

RSENSE = 1 kΩ; RL = 2.6 Ω 5 20 µs

tDSENSE2H

Current sense sett ling

time from rising edge

of INPUT

VIN = 0 V to 5 V; VSEn = 5 V;

RSENSE = 1 kΩ; RL = 2.6 Ω 100 250 µs

ΔtDSENSE2H

Current sense sett ling

time from rising edge

of IOUT (dynamic

response to a step

change of IOUT)

VIN = 5 V; VSEn = 5 V;

RSENSE = 1 kΩ; ISENSE = 90 % of

ISENSEMAX; RL = 2.6 Ω 100 µs

tDSENSE2L Current sense tur n-off

delay time from falling

edge of INPUT

VIN = 5 V to 0 V; VSEn = 5 V;

RSENSE = 1 kΩ; RL = 2.6 Ω 50 250 µs

DocID027394 Rev 1 13/45

Electrical specification

VN7010AJ

7 V < VCC < 18 V; -40°C < Tj < 150°C

Symbol Parameter Test conditions Min. Typ. Max.

Unit

MultiSense timings (chip temperature sense mode - see Figure 8: "Multisense timings (chip

temperature and VCC sens e mode)" )(4)

tDSENSE3H VSENSE_TC

settling time

from rising edge of

SEn

VSEn = 0 V to 5 V; VSEL0 = 0 V;

VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs

tDSENSE3L VSENSE_TC disable

delay time from falling

edge of SEn

VSEn = 5 V to 0 V; VSEL0 = 0 V;

VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs

MultiSense timings (VCC vo ltage sense mo de - see Figure 8: "Multisense timings (chip

temperature and VCC sens e mode)")(4)

tDSENSE4H VSENSE_VCC settling

time from rising edge

of SEn

VSEn = 0 V to 5 V; VSEL0 = 5 V;

VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs

tDSENSE4L VSENSE_VCC disable

delay time from falling

edge of SEn

VSEn = 5 V to 0 V; VSEL0 = 5 V;

VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs

MultiSense timings (Multiplexer transition times)(4)

tD_CStoTC MultiSense transition

delay from current

se nse to TC sense

VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 0 V to 5 V; IOUT = 2.5 A;

RSENSE = 1 kΩ 60 µs

tD_TCtoCS MultiSense transition

delay from TC sense

to current sense

VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V;

VSEL1 = 5 V to 0 V; IOUT = 2.5 A;

RSENSE = 1 kΩ 20 µs

tD_CStoVCC MultiSense transition

delay from current

se nse to VCC sense

VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V;

VSEL1 = 0 V to 5 V; IOUT = 2.5A;

RSENSE = 1 kΩ 60 µs

tD_VCCtoCS MultiSense transition

delay from VCC sense

to current sense

VIN = 5 V; VSEn = 5 V; VSEL0 = 5 V;

VSEL1 = 5 V to 0 V; IOUT = 2.5 A;

RSENSE = 1 kΩ 20 µs

tD_TCtoVCC MultiSense transition

delay from TC sense

to VCC sense

VCC = 13 V; Tj = 125°C; VSEn = 5

VSEL0 = 0 V to 5 V; VSEL1 = 5 V;

RSENSE = 1 kΩ 20 µs

tD_VCCtoTC MultiSense transition

delay from VCC sense

to TC sense

VCC = 13 V; Tj = 125°C; VSEn = 5

VSEL0 = 5 V to 0 V; VSEL1 = 5 V;

RSENSE = 1 kΩ 20 µs

Notes:

(1)Parameter specified by design; not subject to production t est.

(2)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.

(3)VCC sensing and TC are referred to GND potential.

(4)Transition delay are measured up to +/- 10% of final conditions.

14/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

Figure 4: IOUT/ISENSE versus IOUT

Figure 5: Current sense accuracy versus IOUT

500

1000

1500

2000

2500

3000

3500

4000

4500

5000

5500

6000

6500

7000

7500

8000

01 2 34 5 6 7 89 10 11 12 13 14 15 16 17 18 19

K-factor

OUT

[A]

Max

Min

Typ

GAPG0508131345CFT

GAPG0508131350CFT

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

IOUT [A]

Current sense uncalibrated precision

Current sense calibrated precision

DocID027394 Rev 1 15/45

Electrical specification

VN7010AJ

Figure 6: Switching time and Pulse skew

Figure 7: MultiSense timings (current sense mode)

VOUT

Vcc

twon

80% Vcc

20% Vcc

twoff

INPUT

td(on)

tpLH tpHL

td(off)

OUT

/dt

ON OFF

OUT

/dt

GAPG2609141134CFT

CURRENT SENSE

IN1

SEn

IOUT1

tDSENSE2H tDSENSE1L tDSENSE2L

tDSENSE1H

SEL0

SEL1

Low

High

Low

High

Low

High

GAPGCFT00318

16/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

Figure 8: Multisense timings (chip temperature and VCC sense mode)

Figure 9: TDSTKON

SENSE

SEn

DSENSE4H

DSENSE4L

DSENSE3L

DSENSE3H

SEL0

SEL1

Low

High

Low

High

Low

High

SENSE

= V

SENSE_VCC

SENSE

= V

SENSE_TC

VCC VOLTAGE SENSE MODE CHIP TEMPERATURESENSE MODE

GAPGCFT00319

DSTKON

INPU T

OUT

MultiSense

OUT

> V

GAPG2609141140CFT

DocID027394 Rev 1 17/45

Electrical specification

VN7010AJ

Table 10: Truth table

Mode Conditions INX

SEn

SELX

OUTX

MultiSense

Comments

Standby All logic inputs low L L L L L Hi-Z Low quiescent

current

consumption

Normal Nominal load

connected; Tj < 150 °C

L X

See (1)

L See (1)

H L H See (1) Outputs config ur ed

for auto-restart

H H H See (1) Outputs config ur ed

for Latch-off

Overload

Overload or short to

GND causing:

Tj > TTSD or

ΔTj > ΔTj_SD

L X

See (1)

L See (1)

H L H See (1) Output cycles with

temperature

hysteresis

H H L See (1) Output latches-off

Undervoltage VCC < VUSD (falling) X X X X L

L Hi-Z

Hi-Z

Re-start when

VCC > VUSD +

VUSDhyst (rising)

OFF-state

diagnostics Short to VCC L X See (1) H See (1)

Open-load L X H See (1) External pull-up

Negative output

voltage Inductive loads turn-off

L X See (1) < 0 V

See (1)

Notes:

(1)Refer to Table 11: "MultiSense multiplexer addressing"

Table 11: MultiSe nse mult iplexer addressi n g

SEn

SEL1

SEL0

MUX channel MultiSense output

Normal mode Overload OFF-

state diag.

(1) Negative

output

L X X

Hi-Z

H L L Output

diagnostic ISENSE =

1/K * IOUT VSENSE =

VSENSEH VSENSE =

VSENSEH Hi-Z

H L H

H H L TCHIP Sense VSENSE = VSENSE_TC

H H H VCC Sense VSENSE = VSENSE_VCC

Notes:

(1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant i nput is

low, Multisens e pin deli vers feedback accordi ng to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L

(latched); MUX channel = channel 0 diagnost ic; Mutisense = 0. Example 2: FR = 1; IN = 0; OUT = latched,

VOUT > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH

18/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

2.4 Waveforms

Figure 10: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)

Figure 11: Latch functionality - behavior in hard short circuit condition

DocID027394 Rev 1 19/45

Electrical specification

VN7010AJ

Figure 12: Latch functionality - behavior in hard short circuit condition (autorestart mode +

latch off)

Figure 13: Standby mode activation

20/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

Figure 14: Standby state diagram

2.5 Electrical characteristics curves

Figure 15: OFF-state output current

Figure 16: Standby current

200

400

600

800

1000

1200

1400

1600

-50 -25 0 25 50 75 100125150175

T [°C]

Iloff [nA]

GAPG0805131355CFT

Off State

Vcc =13V

Vin = Vout = 0

GAPG0805131358CFT

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100125150175

T [°C]

ISTBY [µA]

Vcc =13V

DocID027394 Rev 1 21/45

Electrical specification

VN7010AJ

Figure 17: IGND(ON) vs. Iou t

Figure 18: Logic Input high level voltage

Figure 19: Logic Input low level voltage

Figure 20: High level logic input current

Figure 21: Low level logic input current

Figure 22: Logic Input hysteresis voltage

GAPG0805131359CFT

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-50 -25 0 25 5075 100125150175

T[°C]

IGND(ON) [mA]

Vcc =13V

Iout = 5A

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100125150175

T [°C]

ViH, VFRH, VSELH, VSEnH[V]

GAPG0805131409CFT

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-50 -25 0 25 50 75 100125150175

T [°C]

VilL VFRL, VSELL, VSEnL [V]

GAPG0805131411CFT

GAPG0805131413CFT

0.5

1.5

2.5

3.5

-50 -25 0 25 50 75 100125150175

T [°C]

IiH, IFRH, ISELH, ISEnH[µA]

GAPG0805131415CFT

0.5

1.5

2.5

3.5

-50 -25 0 25 50 75 100125150175

T [°C]

IiL, IFRL, ISELL, ISEnL [µA]

GAPG0805131416CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100125150175

T [°C]

Vi(hyst), VFR(hyst), VSEL(hyst), VSEn(hyst) [V]

22/45 DocID027394 Rev 1

VN7010AJ

Electrical specification

Figure 23: FaultRST Input clamp voltage

Figure 24: Undervoltage shutdown

Figure 25: On-state resistance vs. Tcase

Figure 26: On-state resistance vs. VCC

Figure 27: Turn-on voltage slope

Figure 28: Turn-off voltage slope

GAPG0805131421CFT

-1

-50 -25 0 25 50 75 100125150175

T [°C]

VFRCL [V]

Iin = 1mA

Iin = -1mA

GAPG0805131423CFT

-50 -25 0 25 50 75 100125150175

T [°C]

VUSD [V]

GAPG0805131425CFT

-50 -25 0 25 50 75 100125150175

T [°C]

Ron[mOhm]

Iout = 5A

Vcc =13V

GAPG0805131426CFT

0 5 10 15 20 25 30 35 40

Vcc [V]

Ron[mOhm]

T = -40 °C

T = 25 °C

T = 125°C

T = 150°C

GAPG0805131428CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100125150175

T [°C]

(dVout/dt)On [V/µs]

Vcc =13V

Rl = 2.6Ω

GAPG0805131430CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100125150175

T [°C]

(dVout/dt)Off[V/µs]

Vcc =13V

Rl = 2.6Ω

DocID027394 Rev 1 23/45

Electrical specification

VN7010AJ

Figure 29: Won vs. Tcase

Figure 30: Woff vs. Tcase

Figure 31: ILIMH vs. Tcase

Figure 32: OFF-state open-load voltage

detection threshold

Figure 33: Vsense clamp vs. Tcase

Figure 34: Vsenseh vs. Tcase

GAPG0805131431CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

-50 -25 0 25 50 75 100125150175

T [°C]

Won[mJ]

GAPG0805131433CFT

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

-50 -25 0 25 50 75 100125150175

T [°C]

Woff[mJ]

GAPG0805131434CFT

100

105

110

115

120

-50 -25 0 25 50 75 100125150175

T [°C]

Ilimh[A]

Vcc =13V

GAPG0805131435CFT

0.5

1.5

2.5

3.5

-50 -25 0 25 50 75 100125150175

T [°C]

VOL [V]

GAPG0805131447CFT

-1

-50 -25 0 25 50 75 100125150175

T [°C]

VSENSE_CL[V]

Iin = 1mA

Iin = -1mA

GAPG0805131448CFT

-50 -25 0 25 50 75 100125150175

T [°C]

VSENSEH[V]

24/45 DocID027394 Rev 1

VN7010AJ

Protections

3 Protections

3.1 Power limitation

The basic working principle of this protection consists of an indirect measurement of the

junction temperature swing ΔTj through the direct measurement of the spatial temperature

gradient on the device surface in order to automatically shut off the output MOSFET as

soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the

FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis

according to the maximum instantaneous power which can be handled (FaultRST = Low)

or remains off (FaultRST = High). The protection prevents fast thermal transient effects

and, consequently, reduces thermo-mechanical fatigue.

3.2 Thermal s hut dow n

In case the junction temperature of the device exceeds the maximum allowed threshold

(typically 175°C), it automatically switches off and the diagnostic indication is triggered.

According to the voltage level on the FaultRST pin, the device switches on again as soon

as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).

3.3 Current limitation

The device is equipped with an output current limiter in order to protect the silicon as well

as the other components of the system (e.g. bonding wires, wiring harness, connectors,

loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or

during load power-up, the output current is clamped to a safety level, ILIMH, by operating the

output power MOSFET in the active region.

3.4 Negative voltage clamp

In case the device drives inductive load, the output voltage reaches a negative value during

turn off. A negative voltage clamp structure limits the maximum negative voltage to a

certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the

device.

DocID027394 Rev 1 25/45

Application information

VN7010AJ

4 Application information

Figure 35: Application diagram

4.1 GND protection network against reverse battery

Figure 36: Simplified internal structure

26/45 DocID027394 Rev 1

VN7010AJ

Application information

4.1.1 Diode (DGND) in the ground line

A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an

inducti ve load.

This small signal diode can be safely shared amongst several different HSDs. Also in this

case, the presence of the ground network produces a shift (≈600 mV) in the input threshold

and in the status output values if the microprocessor ground is not common to the device

ground. This shift does not vary if more than one HSD shares the same diode/resistor

network.

4.2 Immuni ty against t ransie nt electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the

supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E)

and ISO 16750-2:2010.

The related function performance status classification is shown in Table 12: "ISO 7637-2 -

electrical transient conduction along supply line".

Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and

in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present

device only, without components and accessed through VCC and GND terminals.

Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as

follows: “The function does not perform as designed during the test but returns

automatically to normal operation after the test”.

Table 12: ISO 7637-2 - electrical transient conduction along supply line

Test

Pulse

2011(E)

Test pulse severity

level with Status II

functional performance

status

Minimum

number of

pulses or test

time

Burst cycle / pulse

repetition time P ulse durati on and

pulse generator

internal impedance

Level US(1) min max

1 III -112V 500 pulses 0,5 s

2ms, 10Ω

2a III +55V 500 pulses 0,2 s 5 s 50µs, 2Ω

3a IV -220V 1h 90 ms 100 ms 0.1µs, 50Ω

3b IV +150V 1h 90 ms 100 ms 0.1µs, 50Ω

4 (2) IV -7V 1 pulse

100ms, 0.01Ω

Load dump according to ISO 16750-2:2010

Test B (3)

40V 5 pulse 1 min

400ms, 2Ω

Notes:

(1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.

(2)Test pulse from ISO 7637-2:2004(E).

(3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).

4.3 MCU I/O s prot e ction

If a ground protection network is used and negative transients are present on the VCC line,

the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to

prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.

DocID027394 Rev 1 27/45

Application information

VN7010AJ

The value of these resistors is a compromise between the leakage current of

microcontroller and the current required by the HSD I/Os (Input levels compatibility) with

the latch-up limit of microcontroller I/Os.

Equation

VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax

Calculat ion example:

For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V

7.5 kΩ ≤ Rprot ≤ 140 kΩ.

Recommended values: Rprot = 15 kΩ

4.4 Multisense - analog curr ent sense

Diagnostic information on device and load status are provided by an analog output pin

(MultiSense) delivering the following signals:

• Current monitor: current mirror of channel output current

• VCC monitor: voltage propotional to VCC

• TCASE: voltage propotional to chip temperature

Those signals are routed through an analog multiplexer which is configured and controlled

by means of SELx and SEn pins, according to the address map in MultiSense multiplexer

addressing Table.

Figure 37: MultiSense and diagnostic – block diagra m

28/45 DocID027394 Rev 1

VN7010AJ

Application information

4.4.1 Principle of Multisense signal generation

Figure 38: MultiSense block diagram

Current monitor

When current mode is selected in the MultiSense, this output is capable to provide:

• Current mirror proportional to the load current in normal operation, delivering current

proportional to the load according to known ratio named K

• Diagnostics flag in fault conditions delivering fixed voltage VSENSEH

The current delivered by the current sense circuit, ISENSE, can be easily converted to a

voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load

monitoring and abnormal condition detection.

Normal operation (channel ON, no fault, SEn active)

While device is operating in normal conditions (no fault intervention), VSENSE calculation can

be done using simple equations

Current provided by MultiSense output: ISENSE = IOUT/K

Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K

Where:

• VSENSE is voltage measurable on RSENSE resistor

• ISENSE is current provided from MultiSense pin in current output mode

DocID027394 Rev 1 29/45

Application information

VN7010AJ

• IOUT is current flowing through output

• K factor represents the ratio between PowerMOS cells and SenseMOS cells; its

spread includes geometric factor spread, current sense amplifier offset and process

parameters spread of overall circuitry specifying ratio between IOUT and ISENSE.

Failure flag indication

In case of power limitation/overtemperature, the fault is indicated by the MultiSense pin

which is switched to a “current limited” voltage source, VSENSEH.

In any case, the current sourced by the MultiSense in this condition is limited to ISENSEH.

The typical behavior in case of overload or hard short circuit is shown in Waveforms

section.

Figure 39: Analogue HSD – open-load detection in off-state

30/45 DocID027394 Rev 1

VN7010AJ

Application information

Figure 40: Open -load / short to VCC condition

Table 13: MultiSense pin levels in off-state

Condition Output MultiSense SEn

Open-load

VOUT > VOL Hi-Z L

VSENSEH H

VOUT < VOL Hi-Z L

0 H

Short to VCC VOUT > VOL Hi-Z L

VSENSEH H

Nominal VOUT < VOL Hi-Z L

0 H

4.4.2 TCASE and VCC monitor

In this case, MultiSense output operates in voltage mode and output level is referred to

device GND. Care must be taken in case a GND network protection is used, because of a

voltage shift is generated between device GND and the microcontroller input GND

reference.

Figure 41: "GND voltage shift" shows link between VMEASURED and real VSENSE signal.

DocID027394 Rev 1 31/45

Application information

VN7010AJ

Figure 41: GND voltage shift

VCC monitor

Battery monitoring channel provides VSENSE = VCC / 4.

Case temperature monitor

Case temperature monitor is capable to provide information about the actual device

temperature. Since a diode is used for temperature sensing, the following equation

describes the link between temperature and output VSENSE level:

VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0)

where dVSENSE_TC / dT ~ typically -5.5 mV/K (for temperature range (-40 °C to 150 °C).

4.4.3 Short to VCC and OFF-state open-load detection

Short to VCC

A short circuit between VCC and output is indicated by the relevant current sense pin set to

VSENSEH during the de vice off-state. Small or no current is delivered by the current sense

during the on-state depending on the nature of the short circuit.

OFF-state open-load with external circuitry

Detection of an open-load in off mode requires an external pull-up resistor RPU connecting

the output to a positive supply voltage VPU.

It is preferable VPU to be switched off during the module standby mode in order to avo id the

overall standby current consumption to increase in normal conditions, i.e. when load is

connected.

RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following

equation:

32/45 DocID027394 Rev 1

VN7010AJ

Application information

Equation

< V

- 4

L(off2)min @ 4V

DocID027394 Rev 1 33/45

Maximum demagnetization energy (VCC = 16 V)

VN7010AJ

5 Maximu m demagnetization energy (VCC = 16 V)

Figure 42: Maximum turn off current versus inductance

Values are generated with R

= 0 Ω.

In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of

every pulse must not exceed the temperature specified above for curves A and B.

GAPGCFT01216

0.1

100

0.11 10100 1000

I (A)

L(mH)

VN7010AJ- Maximum turn offcurrent versusinductance

VN7010AJ - Single Pulse

RepetitivepulseTjstart=100°C

Repetitive pulse Tjstart=125°C

100

1000

10000

0.01 0.1 1 10 100

E [mJ]

Tdemag [ms]

VN7010AJ - Maximumturn off Energyversus Tdemag

VN7010AJ - Single Pulse

Repetitive pulse Tjstart=100°C

Repetitive pulse Tjstart=125°C

34/45 DocID027394 Rev 1

VN7010AJ

Package and PCB thermal data

6 Package and PCB thermal data

6.1 PowerSSO-16 thermal data

Figure 43: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5)

Figure 44: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)

Table 14: PCB properties

Dimension Value

Board finish thickness 1.6 mm +/- 10%

Board dimension 77 mm x 86 mm

Board Material FR4

Copper thickness (top and bottom layers) 0. 070 m m

Copper thickness (inner layers) 0.035 mm

Thermal vias separation 1.2 mm

Thermal via diamet er 0.3 mm +/- 0.08 mm

Copper thickness on vias 0.025 mm

Footprint dimension (top layer ) 2.2 mm x 3.9 mm

Heatsink copper area dimension (bottom layer) Footprint, 2 cm2 or 8 cm2

DocID027394 Rev 1 35/45

Package and PCB thermal data

VN7010AJ

Figure 45: Rthj-a m b vs PCB copper area in open box free air condition (one channel on)

Figure 46: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)

Equation: pulse calculation formula

ZTHδ = RTH · δ + ZTHtp (1 - δ)

where δ = tP/T

0 2 4 6 8 10

RTHjamb

GAPGCFT01055

0.1

100

0.0001 0.001 0.01 0.1 1 10 100 1000

(°C/W)

Time (s)

Cu=foot print

Cu=2 cm2

Cu=8 cm2

4 Layer

GAPGCFT01056

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Package and PCB thermal data

Figure 47: Thermal fitting model of a double-channel HSD in PowerSSO-16

The fitting model is a simplified thermal tool and is valid for transient evolutions

where the embedded protections (power limitation or thermal cycling during

thermal shutdown) are not triggered.

Table 15: Thermal par am eters

Area/island (cm2) Footprint 2 8 4L

R1 (°C/W) 0.15

R2 (°C/W) 1.7

R3 (°C/W) 7 7 7 5

R4 (°C/W) 16 6 6 4

R5 (°C/W) 30 20 10 3

R6 (°C/W) 26 20 18 7

C1 (W.s/ ° C) 0.0015

C2 (W.s/ ° C) 0.02

C3 (W.s/ ° C) 0.1

C4 (W.s/ ° C) 0.2 0.3 0.3 0.4

C5 (W.s/ ° C) 0.4 1 1 4

C6 (W.s/°C) 3 5 7 18

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Package information

VN7010AJ

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

7.1 PowerSSO-16 package information

Figure 48: PowerSSO-16 package dimensions

Table 16: Po werSSO-16 mec h anica l data

Symbol Millimeters

Min. Typ. Max.

Θ 0°

8°

Θ1 0°

Θ2 5°

15°

Θ3 5°

15°

1.70

A1 0.00

0.10

A2 1.10

1.60

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Package information

Symbol Millimeters

Min. Typ. Max.

b 0.20

0.30

b1 0.20 0.25 0.28

c 0.19

0.25

c1 0.19 0.20 0.23

D 4.9 BSC

D1 3.60

4.20

e 0.50 BSC

E 6.00 BSC

E1 3.90 BSC

E2 1.90

2.50

h 0.25

0.50

L 0.40 0.60 0.85

L1 1.00 REF

N 16

R 0.07

R1 0.07

S 0.20

Tolerance of form and position

aaa 0.10

bbb 0.10

ccc 0.08

ddd 0.08

eee 0.10

fff 0.10

ggg 0.15

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Package information

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7.2 PowerSSO-16 packing inf orm a ti on

Figure 49: PowerSSO-16 reel 13"

Table 17: Reel dimensions

Description Value(1)

Base quantity 2500

Bulk quantity 2500

A (max) 330

B (min) 1.5

C (+0.5, -0.2) 13

D (min) 20.2

N 100

W1 (+2 /-0) 12.4

W2 (max) 18.4

Notes:

(1)All dimensions are in mm.

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Package information

Figure 50: PowerSSO-16 carrier tape

Table 18: Po werSSO-16 carrier tape dimensions

Description Value(1)

A0 6.50 ± 0.1

B0 5.25 ± 0.1

K0 2.10 ± 0.1

K1 1.80 ± 0.1

F 5.50 ± 0.1

P1 8.00 ± 0.1

W 12.00 ± 0.3

Notes:

(1)All dimensions are in mm.

Figure 51: PowerSSO-16 schematic drawing of leader and trailer tape

0.30 ±0.05 1.55 ±0.05

1.6±0.1

R 0.5

Typical

2.0 ±0.1

4.0 ±0.1

1.75 ±0.1

SECTION X - X

SECTION Y - Y

REF 4.18

REF 0.6

REF 0.5

Y Y

GAPG2204151242CFT

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Package information

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7.3 PowerSSO-16 marking information

Figure 52: PowerSSO-16 marking information

Engineering Samples: these samples can be clearly identified by a dedicated

special symbol in the marking of each unit. These samples are intended to be

used for electrical compatibility evaluation only; usage for any other purpose may

be agreed only upon written authorization by ST. ST is not liable for any customer

usage in product ion and/or in reliability qualification trials.

Commercial Samples: fully qualified parts from ST standard production with no

usage restrictions.

GAPG0401151415CFT

1234567 8

Special function digit

&: Engineering sample

<blank>: Commercial sample

PowerSSO-16 TOP VIEW

(not in scale)

Marking area

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Order codes

8 Order codes

Table 19: Device summary

Package Order codes

Tape and reel

PowerSSO-16 VN7010AJTR

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Revision history

VN7010AJ

9 Revision history

Table 20: Document revision history

Date Revision Changes

19-May-2015 1 Initial release.

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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST

produc ts befor e placin g orders . ST produc ts are sold pursuant to ST’s terms and c onditions of sa le in pla ce at the ti me of order acknowledgement.

Purchasers are solely responsible for the choic e, selection, and use of S T produc ts and ST as sumes no li abili ty for appli catio n assistance or th e

design of Purchasers’ pr oduc ts.

No license, express or im pl ied, t o any int ellect ual prop erty right is granted by ST herein.

Resale of ST products wit h provisions dif ferent from the informa tion set forth herein shall void any warranty granted by ST for such product.

ST and the S T logo are tr ademarks of ST. Al l other product or s ervice n ames are the proper ty of their respective owners.

Info rm atio n i n th is docum e nt sup erse de s an d r e places information previously supplied in any prior versions of this docu ment.

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