1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PWPPACKAGE
(TOPVIEW)
NC
VIN1
VIN1
MR
EN1
EN2
RESET
GND
VIN2
VIN2
NC
VOUT1
VOUT1
VSENSE1/FB1
PG1
PG2
VSENSE2/FB2
VOUT2
VOUT2
NC
NC=Nointernalconnection
1.8 V
VIN1
VIN2
EN1
EN2
VOUT1
VSENSE1
PG1
MR
RESET
PG2
VSENSE2
VOUT2
TPS70251PWP
5V
3.3V I/O
PG2
Core
0.1 mF
RESET
10 mF
10 mF
0.1 mF
MR
PG1
EN1
250kW
>2V
<0.7V
250kW
>2V
<0.7V
>2V
<0.7V
EN2
250kW
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS
1FEATURES DESCRIPTION
23• Dual Output Voltages for Split-Supply The TPS702xx is a low dropout voltage regulator with
Applications integrated SVS (RESET, POR, or power on reset)
and power good (PG) functions. These devices are
• Independent Enable Functions (See Part capable of supplying 500mA and 250mA by regulator
Number TPS701xx for Sequenced Outputs) 1 and regulator 2 respectively. Quiescent current is
• Output Current Range of 500mA on Regulator typically 190μA at full load. Differentiated features,
1 and 250mA on Regulator 2 such as accuracy, fast transient response, SVS
• Fast Transient Response supervisory circuit (power on reset), manual reset
input, and independent enable functions provide a
• Voltage Options: 3.3V/2.5V, 3.3V/1.8V, complete system solution.
3.3V/1.5V, 3.3V/1.2V, and Dual Adjustable
Outputs
• Open Drain Power-On Reset with 120ms Delay
• Open Drain Power Good for Regulator 1 and
Regulator 2
• Ultralow 190μA (typ) Quiescent Current
• 1μA Input Current During Standby
• Low Noise: 65μVRMS Without Bypass Capacitor
• Quick Output Capacitor Discharge Feature
• One Manual Reset Input
• 2% Accuracy Over Load and Temperature
• Undervoltage Lockout (UVLO) Feature
• 20-Pin PowerPAD™ TSSOP Package
• Thermal Shutdown Protection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
The TPS702xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have
extremely low noise output performance without using any added filter bypass capacitors and are designed to
have a fast transient response and be stable with 10μF low ESR capacitors.
These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable voltage options. Regulator
1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the
designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on
regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a
voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230μA
over the full range of output current and full range of temperature). This LDO family also features a sleep mode;
applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high
signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to
2μA at TJ= +25°C.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off (disabled).
The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET,
POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at
VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.
The TPS702xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of
an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the
logic high state, RESET goes to a high impedance state after a 120ms delay. To monitor VOUT1, the PG1 output
pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR.
The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until
VIN1 reaches 2.5V.
2Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
VOLTAGE (V)(2) PACKAGE- SPECIFIED
LEAD TEMPERATURE ORDERING TRANSPORT
PRODUCT VOUT1 VOUT2 (DESIGNATOR) RANGE (TJ) NUMBER MEDIA, QUANTITY
TPS70202PWP Tube, 70
TPS70202 Adjustable Adjustable HTSSOP-20 (PWP) -40°C to +125°C TPS70202PWPR Tape and Reel, 2000
TPS70245PWP Tube, 70
TPS70245 3.3V 1.2V HTSSOP-20 (PWP) -40°C to +125°C TPS70245PWPR Tape and Reel, 2000
TPS70248PWP Tube, 70
TPS70248 3.3V 1.5V HTSSOP-20 (PWP) -40°C to +125°C TPS70248PWPR Tape and Reel, 2000
TPS70251PWP Tube, 70
TPS70251 3.3V 1.8V HTSSOP-20 (PWP) -40°C to +125°C TPS70251PWPR Tape and Reel, 2000
TPS70258PWP Tube, 70
TPS70258 3.3V 2.5V HTSSOP-20 (PWP) -40°C to +125°C TPS70258PWPR Tape and Reel, 2000
(1) For the most current package and ordering information see the Package Option Addendum located at the end of this document, or see
the TI web site at www.ti.com.
(2) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted). TPS702xx UNIT
Input voltage range: VIN1, VIN2 (2) –0.3 to +7 V
Voltage range at EN1, EN2 –0.3 to +7 V
Output voltage range (VOUT1, VSENSE1) 5.5 V
Output voltage range (VOUT2, VSENSE2) 5.5 V
Maximum RESET, PG1, PG2 voltage 7 V
Maximum MR voltage VIN1 V
Peak output current Internally limited —
Continuous total power dissipation See Dissipation Ratings Table —
Operating virtual junction temperature range, TJ–40 to +150 °C
Storage temperature range, Tstg –65 to +150 °C
ESD rating, HBM 2 kV
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are tied to network ground.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
DISSIPATION RATINGS DERATING
PACKAGE AIR FLOW (CFM) TA≤+25°C TA= +70°C TA= +85°C
FACTOR
0 3.067W 30.67mW/°C 1.687W 1.227W
PWP(1) 250 4.115W 41.15mW/°C 2.265W 1.646W
(1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground
layer. For more information, refer to TI technical brief SLMA002.
RECOMMENDED OPERATING CONDITIONS
Over operating temperature range (unless otherwise noted). MIN MAX UNIT
Input voltage, VI(1)(regulator 1 and 2) 2.7 6 V
Output current, IO(regulator 1) 0 500 mA
Output current, IO(regulator 2) 0 250 mA
Output voltage range (for adjustable option) 1.22 5.5 V
Operating virtual junction temperature, TJ–40 +125 °C
(1) To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
4Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
Lineregulation(mV)=(%/V)x Vox1000
(V 2.7)
100
-
Imax
x1000
[ V (V +1) ]
100
-
Imax o
Lineregulation(mV)=(%/V)x Vo
(3) If VO< 1.8V then VImax = 6V, VImin = 2.7V:
If VO> 2.5V then VImax = 6V, VImin = VO+ 1V:
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS
Over recommended operating junction temperature range (TJ= –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1V, IO= 1mA,
EN1 = 0V, EN2 = 0V, and CO= 33μF (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
2.7V < VIN < 6V, FB connected to VO1.22
Reference TJ= +25°C
voltage 2.7V < VIN < 6V, FB connected to VO1.196 1.244
2.7V < VIN < 6V, TJ= +25°C 1.2
1.2V Output 2.7V < VIN < 6V, 1.176 1.224
2.7V < VIN < 6V, TJ= +25°C 1.5
Output 1.5V Output 2.7V < VIN < 6V, 1.47 1.53
VOvoltage (1) , V
(2) 2.8V < VIN < 6V, TJ= +25°C 1.8
1.8V Output 2.8V < VIN < 6V, 1.764 1.836
3.5V < VIN < 6V, TJ= +25°C 2.5
2.5V Output 3.5V < VIN < 6V, 2.45 2.55
4.3V < VIN < 6V, TJ= +25°C 3.3
3.3V Output 4.3V < VIN < 6V, 3.234 3.366
Quiescent current (GND current) for See (2) TJ= +25°C 190
regulator 1 and regulator 2, EN1 = EN2 μA
See (2) 230
= 0V(1)
Output voltage line regulation (∆VO/VO) VO+ 1V < VIN ≤6V, TJ= +25°C(1) 0.01 %V
for regulator 1 and regulator 2 (3) VO+ 1V < VIN ≤6V (1) 0.1
Load regulation for VOUT 1 and VOUT2 TJ= +25°C 1 mV
Output noise Regulator 1 65
VnBW = 300Hz to 50kHz, CO= 33μF, TJ= +25°C μVRMS
voltage Regulator 2 65
Regulator 1 1.6 1.9
Output current limit VOUT = 0V A
Regulator 2 0.750 1
Thermal shutdown junction temperature +150 °C
Regulator 1 EN1 = VIN, EN2 = VITJ= +25°C 2
IIStandby μA
(standby) current Regulator 2 EN1 = VIN, EN2 = VI6
f = 1kHz, CO= 33μF,
Regulator 1 TJ= +25°C(1) 60
Power- IOUT1 = 500mA
PSRR supply ripple dB
f = 1kHz, CO= 33μF,
rejection Regulator 2 TJ= +25°C(1) 50
IOUT2 = 250mA
UVLO threshold 2.4 2.65 V
RESET Terminal
Minimum input voltage for valid RESET IRESET = 300μA, V(RESET) ≤0.8V 1.0 1.3 V
t(RESET) RESET pulse duration 80 120 160 ms
Output low voltage VIN = 3.5V, I(RESET) = 1mA 0.15 0.4 V
Leakage current V(RESET) = 6V 1 μA
(1) Minimum input operating voltage is 2.7V or VO(typ) + 1V, whichever is greater. Maximum input voltage = 6V, minimum output
current = 1mA.
(2) IO= 1mA to 500mA for Regulator 1 and 1mA to 250mA for Regulator 2.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating junction temperature range (TJ= –40°C to +125°C), VIN1 or VIN2 = VOUT(nom) + 1V, IO= 1mA,
EN1 = 0V, EN2 = 0V, and CO= 33μF (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PG1/PG2 Terminal
Minimum input voltage for valid PGx I(PGx) = 300μA, V(PGx) ≤0.8V 1.0 1.3 V
Trip threshold voltage VOdecreasing 92 95 98 %VOUT
Hysteresis voltage Measured at VO0.5 %VOUT
tr(PGx) Rising edge deglitch 30 μs
Output low voltage VIN = 2.7V, I(PGx) = 1mA 0.15 0.4 V
Leakage current V(PGx) = 6V 1 μA
EN1/EN2 Terminal
High-level ENx input voltage 2 V
Low-level ENx input voltage 0.7 V
Input current (ENx) –1 1 μA
MR Terminal
High-level input voltage 2 V
Low-level input voltage 0.7 V
Pull-up current source 6 μA
VOUT1 Terminal
IO= 500mA, VIN1 = 3.2V TJ= +25°C 170
Dropout voltage(4) mV
IO= 500mA, VIN1 = 3.2V 275
Peak output current 2ms pulse width 750 mA
Discharge transistor current VOUT1 = 1.5V 7.5 mA
VOUT2 Terminal
Peak output current 2ms pulse width 375 mA
Discharge transistor current VOUT2 = 1.5V 7.5 mA
FB Terminal
Input current: TPS70202 FB = 1.8V 1 μA
(4) Input voltage (VIN1 or VIN2) = VO(typ) – 100mV. For 1.5V, 1.8V and 2.5V regulators, the dropout voltage is limited by input voltage range.
The 3.3V regulator input is set to 3.2V to perform this test.
6Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
UVLO
Comp
+
-
+
-
Thermal
Shutdown
2.5V
+-
Current
Sense
Reference Vref
Vref
ENA_1
FB1
ENA_1
120ms
Delay
0.95xVref
VSENSE1
0.95xVref
VSENSE2
RisingEdge
Deglitch
ENA_1
ENA_2
Current
Sense
+-
ENA_2
ENA_2
FB2
Vref
V (2Pins)
IN1
GND
EN1
EN2
VIN2 (2Pins)
PG1
MR
RESET
VIN1
PG1
Comp
RisingEdge
Deglitch
PG2
PG2
Comp
VOUT2 (2Pins)
+
-
10kW
VSENSE1
(seeNoteA)
V (2Pins)
OUT1
VSENSE2
(seeNoteA)
10kW
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
DEVICE INFORMATION
Fixed Voltage Version
A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT1 and VOUT2, respectively, as
close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the
Application Information section.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 7
UVLO
Comp
+
-
+
-
Thermal
Shutdown
2.5V
+-
Current
Sense
Reference Vref
Vref
ENA_1
ENA_1
120ms
Delay
0.95xVref
FB1
0.95xVref
FB2
RisingEdge
Deglitch
ENA_1
ENA_2
Current
Sense
+-
ENA_2
ENA_2
FB2
Vref
V (2Pins)
IN1
GND
EN1
EN2
VIN2 (2Pins)
FB1
(seeNoteA)
PG1
MR
RESET
FB2
(seeNoteA)
VIN1
PG1
Comp
RisingEdge
Deglitch
PG2
PG2
Comp
VOUT1 (2Pins)
VOUT2 (2Pins)
+
-
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
Adjustable Voltage Version
A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the
device. For other implementations, refer to FB terminals connection discussion in the Application Information
section.
8Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
VIN1
VUVLO VUVLO
t
t
t
MR Input
RESET Output
120ms
Delay
120ms
Delay
NOTEA: V .ThesymbolV
RES RES
RESETistheminimuminputvoltageforavalid isnotcurrentlylistedwithinEIAorJEDECstandardsfor
semiconductorsymbology.
VRES
(seeNoteA)
Output
Undefined
Output
Undefined
VRES (seeNoteA)
VPG
t
t
t
PG1 Output
VIT+
(seeNoteB)
VIN1
VOUT1
VPG1
(seeNoteA)
V
(seeNoteB)
VUVLO VUVLO
PG1
NOTES: A. V istheminimuminputvoltageforavalidPG1.ThesymbolV isnotcurrentlylistedwithinEIAorJEDEC
PG1 PG1
standards forsemiconductorsymbology.
B. V tripvoltageistypically5%lowerthantheoutputvoltage(95%V ). toV i
O IT+ sthehysteresisvoltage.
IT-VIT-
Threshold
Voltage
Output
Undefined
Output
Undefined
IT-
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
RESET Timing Diagram
PG1 Timing Diagram
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 9
NOTE A: V trip V to
IT IT- -
voltageistypically5%lowerthantheoutputvoltage(95%V ).
O IT+
V isthehysteresisvoltage.
t
t
t
PG2
Output
VIT+
(seeNoteA)
VIN2
VOUT2
V
(seeNoteA)
Threshold
Voltage IT-
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
PG2 Timing Diagram (assuming VIN1 already powered up)
TERMINAL FUNCTIONS
TERMINAL I/O DESCRIPTION
NAME NO.
EN1 5 I Active low enable for VOUT1
EN2 6 I Active low enable for VOUT2
GND 8 — Ground
MR 4 I Manual reset input, active low, pulled up internally
NC 1, 11, 20 — No connection
PG1 16 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage
PG2 15 O Open drain output, low when VOUT2 voltage is less than 95% of the nominal regulated voltage
RESET 7 I Open drain output, SVS (power-on reset) signal, active low
VIN1 2, 3 I Input voltage of regulator 1
VIN2 9, 10 I Input voltage of regulator 2
VOUT1 18, 19 O Output voltage of regulator 1
VOUT2 12, 13 O Output voltage of regulator 2
VSENSE2/FB2 14 I Regulator 2 output voltage sense/regulator 2 feedback for adjustable
VSENSE1/FB1 17 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable
10 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
Detailed Description
The TPS702xx low dropout regulator family provides dual regulated output voltages with independent enable
functions. These devices provide fast transient response and high accuracy with small output capacitors, while
drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good
(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features
provide a complete power solution.
The TPS702xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even
with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly
proportional to the load current through the regulator (IB= IC/β). The TPS702xx uses a PMOS transistor to pass
current; the gate of the PMOS is voltage-driven, so operating current is low and stable over the full load range.
Pin Functions
Enable (EN1, EN2)
The EN terminals are inputs that enable or shut down each respective regulator. If EN is at a voltage high signal,
the respective regulator is in shutdown mode. When EN goes to voltage low, the respective regulator is enabled.
Power-Good (PG1, PG2)
The PG terminals are open drain, active high output terminals that indicate the status of each respective
regulator. When VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When VOUT2
reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance
state when its respective output voltage is pulled below 95% (that is, goes to an overload condition) of its
regulated voltage. The open drain outputs of the PG terminals require a pull-up resistor.
Manual Reset Pin
MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR
(RESET) occurs. The terminal has a 6μA pull-up current to VIN1.
Sense (VSENSE1, VSENSE2)
The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection
should be as short as possible. Internally, the sense terminal connects to high-impedance, wide-bandwidth
amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential
to route the sense connection in such a way as to minimize or avoid noise pickup. Adding RC networks between
sense terminals and VOUT terminals to filter noise is not recommended because these networks can cause the
regulators to oscillate.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize or avoid noise pickup. Adding RC networks between FB terminals and VOUT
terminals to filter noise is not recommended because these networks can cause the regulators to oscillate.
RESET Indicator
The TPS702xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power on reset
circuitry or a low-battery indicator. RESET is an active low, open drain output that indicates the status of the
manual reset pin (MR). When MR is in a high impedance state, RESET goes to a high impedance state after a
120 ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output
pin can be connected to MR. The open drain output of the RESET terminal requires a pull-up resistor. If RESET
is not used, it can be left floating.
VIN1 and VIN2
VIN1 and VIN2 are inputs to each regulator. Internal bias voltages are powered by VIN1.
VOUT1 and VOUT2
VOUT1 and VOUT2 are output terminals of each regulator.
12 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
O
I OutputCurrent (A)- -
3.299
3.298
3.296
3.295
0 0.1 0.2 0.3
3.301
3.302
3.303
0.4 0.5
3.300
3.297
V OutputVoltage (V)- -
O
VIN1 =4.3V
TJ=+25°C
VOUT1
I OutputCurrent (A)- -
V OutputVoltage (V)
O--
1.799
1.797
1.796
1.795
0 0.05 0.1 0.15
1.800
1.801
1.802
0.2 0.25
1.798
VIN2 =2.8V
VOUT2
O
TJ=+25°C
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS
Table of Graphs FIGURE
vs Output current Figure 1 to Figure 3
VOOutput voltage vs Junction temperature Figure 4 to Figure 5
Ground current vs Junction temperature Figure 6
PSRR Power-supply rejection ratio vs Frequency Figure 7 to Figure 10
Output spectral noise density vs Frequency Figure 11 to Figure 14
ZOOutput impedance vs Frequency Figure 15 to Figure 18
vs Temperature Figure 19 and Figure 20
Dropout voltage vs Input voltage Figure 21 and Figure 22
Load transient response Figure 23 and Figure 24
Line transient response (VOUT1)Figure 25
Line transient response (VOUT2)Figure 26
VOOutput voltage vs Time (start-up) Figure 27 and Figure 28
Equivalent series resistance (ESR) vs Output current Figure 30 to Figure 33
TPS70251 TPS70251
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 1. Figure 2.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
1.198
1.197
1.196
1.195
0 0.05 0.1 0.15
1.199
1.200
1.201
0.2 0.25
VIN2 =2.7V
TJ=+25°C
VOUT2
O
I OutputCurrent (A)- -
V OutputVoltage (V)- -
O
TJJunctionT-emperature - °C
TJ°C
3.23
3.25
3.27
3.29
3.31
3.33
3.35
-40 -25 -10 5 20 35 50 65 80 95 110 125
VIN1 =4.3V
VOUT1
IO=500mA
IO=1mA
V OutputVoltage (V)- -
O
1.73
1.75
1.77
1.79
1.81
1.83
-40 -25 -10 5 20 35 50 65 80 95 110 125
VIN2 =2.8V
VOUT2
1.85
IO=1mA
IO=250mA
TJJunctionT-emperature C- °
V OutputVoltage (V)- -
O
TJJunctionT-emperature C- °
150
160
170
180
-40 -25 -10 5 20 35 50 65 80 95 110 125
190
200
210
IOUT1 =1mA
IOUT2 =1mA
Regulator1andRegulator2
IOUT1 =500mA
IOUT2 =250mA
°
GroundCurrent A- m
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TPS70245 TPS70251
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE
Figure 3. Figure 4.
TPS70251
OUTPUT VOLTAGE GROUND CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 5. Figure 6.
14 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
IO=10mA
CO=22 mF
VOUT1
-60
-80
-90 10 100 1k 10k
-40
-20
-10
100k 1 M
-30
-50
-70
PSRR -PowerSupplyRejectionRatio -dB
f-Frequency -Hz
-40
-60
-70
-90
10 100 1k 10k
-20
0
10
100k 1 M
-10
-30
-50
-80
IO=500mA
CO=22 mF
VOUT1
PSRR PowerSupplyRejectionRatio- - dB
f Frequency- - Hz
-60
-80
-90 10 100 1k 10k
-40
-20
-10
100k 1 M
-30
-50
-70
IO=10mA
CO=22 mF
VOUT2
PSRR PowerSupplyRejectionRatio- - dB
f Frequency- - Hz
-40
-60
-70 10 100 1k 10k
-20
0
10
100k 1 M
-10
-30
-50
IO=250mA
CO=22 mF
VOUT2
PSRR -PowerSupplyRejectionRatio -dB
f-Frequency -Hz
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
TPS70251 TPS70251
POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 7. Figure 8.
TPS70251 TPS70251
POWER-SUPPLY REJECTION RATIO POWER-SUPPLY REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 9. Figure 10.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 15
0.01
0.1
1
10
100 1k 10k 100k
f-Frequency -Hz
VIN1 =4.3V
VOUT1 =3.3V
IO=10mA
OutputSpectralNoiseDensity V/- m ÖHz
0.01
0.1
1
10
100 1k 10k 100k
VIN1 =4.3V
VOUT1 =3.3V
IO=500mA
f-Frequency -Hz
OutputSpectralNoiseDensity V/- m ÖHz
0.01
0.1
1
10
100 1k 10k 100k
VIN2 =2.8V
VOUT2 =1.8V
IO=250mA
f-Frequency -Hz
OutputSpectralNoiseDensity V/- m ÖHz
0.01
0.1
1
10
100 1k 10k 100k
VIN2 =2.8V
VOUT2 =1.8V
IO=10mA
f-Frequency -Hz
OutputSpectralNoiseDensity V/- m ÖHz
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY
vs vs
FREQUENCY FREQUENCY
Figure 11. Figure 12.
OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY
vs vs
FREQUENCY FREQUENCY
Figure 13. Figure 14.
16 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
CO=33 mF
IO=500mA
VOUT1 =3.3V
TJ=+25°C
10 100 1k 10k
10
100
100k 1 M 10M
1
0.1
0.01
f-Frequency -Hz
Z-
OOutputImpednace - W
CO=33 mF
IO=10mA
VOUT1 =3.3V
10 100 1k 10k
10
100
100k 1 M 10M
1
0.1
0.01
TJ=+25°C
f-Frequency -Hz
Z-
OOutputImpednace - W
CO=33 mF
IO=250mA
VOUT2 =1.8V
10 100 1k 10k
10
100
100k 1 M 10M
1
0.1
0.01
TJ=+25°C
f-Frequency -Hz
Z-
OOutputImpednace - W
CO=33 mF
IO=10mA
VOUT2 =1.8V
10 100 1k 10k
10
100
100k 1 M 10M
1
0.1
0.01
TJ=+25°C
f-Frequency -Hz
Z-
OOutputImpednace - W
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
OUTPUT IMPEDANCE OUTPUT IMPEDANCE
vs vs
FREQUENCY FREQUENCY
Figure 15. Figure 16.
OUTPUT IMPEDANCE OUTPUT IMPEDANCE
vs vs
FREQUENCY FREQUENCY
Figure 17. Figure 18.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 17
0
50
100
150
200
250
40 25 10 5 20 35 50 65 80
CO=33 mF
VIN1 =3.2V
95 110 125
IO=500mA
T Temperature- - °C
DropoutVoltage mV-
0
1
2
3
4
5
6
-40 -25 -10 5 20 35 50 65 80 95 110 125
CO=33 mF
VIN1 =3.2V
IO=10mA
IO=0mA
T Temperature- - °C
DropoutVoltage mV-
0
50
100
150
200
250
2.5 3 3.5 4 4.5 5 5.5
IO=500mA
VOUT1
300
TJ=+125°C
TJ=+25°C
TJ=-40°C
V InputVoltage
I- - V
DropoutVoltage mV-
0
100
200
300
400
500
2.5 3 3.5 4 4.5 5 5.5
IO=250mA
VOUT2
TJ=+125°C
TJ=+25°C
TJ=-40°C
V InputVoltage
I- - V
DropoutVoltage mV-
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs
TEMPERATURE TEMPERATURE
Figure 19. Figure 20.
TPS70202 TPS70202
DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 21. Figure 22.
18 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
20
250
CO=33 mF
TJ=+25°C
VOUT1 =3.3V
0
0
-20
500
t Time- - ms
I OutputCurrent
O- - mA
DVO
OutputVoltage mV
-
-
Changein
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
20
0
250
0
-20
CO=33 mF
TJ=+25°C
VOUT2 =1.8V
t Time- - ms
I OutputCurrent
O- - mA
DVO
OutputVoltage mV
-
-
Changein
0 20 40 60 80 100 120
5.3
4.3
140 160 180 200
TJ=+25°C
IO=500mA
CO=33 mF
VOUT1
0
50
-50
t Time- - ms
V InputVoltage
I- - V
DVO
OutputVoltage mV
-
-
Changein
0 20 40 60 80 100 120
2.8
140 160 180 200
TJ=+25°C
IO=250mA
CO=33 mF
VOUT2
0
10
10
3.8
t Time- - ms
V InputVoltage
I- - V
DVO
OutputVoltage mV
-
-
Changein
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
Figure 23. Figure 24.
LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 25. Figure 26.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 19
VO=3.3V
CO=33 mF
IO=500mA
VOUT2 =Standby
0 2.0
0
2
3
1
0
5
0.2 1.81.61.41.21.00.4 0.6 0.8
t Time- - ms
V OutputVoltage
OUT1 -
EnableVoltage(EN1) V-
VO=1.5V
CO=33 mF
IO=250mA
VOUT1 =Standby
0 2.0
0
2
3
1
0
5
0.2 1.81.61.41.21.00.4 0.6 0.8
t Time- - ms
V OutputVoltage
OUT2 -
EnableVoltage(EN2) V-
IN
EN
OUT
GND
ESR
VIN
COUT
ToLoad
RL
+
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
TYPICAL CHARACTERISTICS (continued)
OUTPUT VOLTAGE AND ENABLE VOLTAGE OUTPUT VOLTAGE AND ENABLE VOLTAGE
vs vs
TIME (START-UP) TIME (START-UP)
Figure 27. Figure 28.
Figure 29. Test Circuit for Typical Regions of Stability
20 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
0 50 100 150 200 250
REGIONOFINSTABILITY
0.1
10
1
250mW
VO=3.3V
CO=6.8 mF
TJ=25°C
REGIONOFINSTABILITY
I OutputCurrent
O- - mA
ESR EquivalentSeriesResistance- - W
0.1
0.010 50 100 150 200 250
10
1
VO=3.3V
CO=10 mF
TJ=25°C
REGIONOFINSTABILITY
REGIONOFINSTABILITY
50mW
I OutputCurrent
O- - mA
ESR EquivalentSeriesResistance- - W
0.1
0.010 25 50 75 100 125
10
1
REGIONOFINSTABILITY
50mW
REGIONOFINSTABILITY
VO=1.8V
CO=10 mF
TJ=25°C
I OutputCurrent
O- - mA
ESR EquivalentSeriesResistance- - W
0 25 50 75 100 125
REGIONOFINSTABILITY
0.1
1
VO=1.8V
CO=6.8 mF
TJ=25°C
10
REGIONOFINSTABILITY
250mW
I OutputCurrent
O- - mA
ESR EquivalentSeriesResistance- - W
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
TYPICAL CHARACTERISTICS (continued)
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1) EQUIVALENT SERIES RESISTANCE(1)
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 30. Figure 31.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1) EQUIVALENT SERIES RESISTANCE(1)
vs vs
OUTPUT CURRENT OUTPUT CURRENT
Figure 32. Figure 33.
(1) Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any
series resistance added externally, and PWB trace resistance to CO.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 21
VOUT2
VIN1
VIN2
EN1
EN2
VOUT1
VSENSE1
PG1
MR
RESET
PG2
VSENSE2
VOUT2
TPS702xxPWP
(FixedOutputOption)
VIN VOUT1
PG2
0.1 Fm
RESET
10 Fm
10 Fm
0.1 Fm
MR
EN1
>2V
<0.7V
EN2
250kW
250kW
>2V
<0.7V
95%
95%
EN2
VOUT2
VOUT1
PG2
PG1
EN1
MR
(PG1tiedto )MR
120ms
t1
RESET
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO MR
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
APPLICATION INFORMATION
Sequencing Timing Diagrams
This section provides a number of timing diagrams
showing how this device functions in different
configurations.
Application condition: VIN1 and VIN2 are tied to the
same fixed input voltage greater than VUVLO. PG2 is
tied to MR.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 (tied to MR) are
at logic low. Since MR is at logic low, RESET is also
at logic low. When EN1 is taken to logic low, VOUT1
turns on. Later, when EN2 is taken to logic low, VOUT2
turns on. When VOUT1 reaches 95% of its regulated
output voltage, PG1 goes to logic high. When VOUT2
reaches 95% of its regulated output voltage, PG2
(tied to MR) goes to logic high. When VIN1 is greater
than VUVLO and M R (tied to PG2) is at logic high,
RESET is pulled to logic high after a 120ms delay.
When EN1 and EN2 are returned to logic high, both
devices power down and both PG1, PG2 (tied to
MR2), and RESET return to logic low.
Figure 34. Timing When VOUT1 Is Enabled Before VOUT2
22 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
MR
VOUT2
VIN1
VIN2
EN1
EN2
VOUT1
VSENSE1
PG1
RESET
PG2
MR
VSENSE2
VOUT2
VIN VOUT1
PG2
0.1 Fm
RESET
10 mF
10 mF
0.1 mF
EN1
2V
0.7V
TPS702xxPWP
(FixedOutputOption)
>2V
<0.7V
EN2
250kW
250kW
250kW
>2V
<0.7V
95%
95%
EN2
VOUT2
VOUT1
PG2
PG1
EN1
MR
RESET
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO MR
120ms
t1
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
Application condition: VIN1 and VIN2 are tied to the
same fixed input voltage greater than VUVLO. MR is
initially logic high but is eventually toggled.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 and PG2 are at logic low.
Since VIN1 is greater than VUVLO and MR is at logic
high, RESET is also at logic high. When EN2 is taken
to logic low, VOUT2 turns on. Later, when EN1 is taken
to logic low, VOUT1 turns on. When VOUT2 reaches
95% of its regulated output voltage, PG2 goes to
logic high. When VOUT1 reaches 95% of its regulated
output voltage, PG1 goes to logic high. When MR is
taken to logic low, RESET is taken low. When MR
returns to logic high, RESET returns to logic high
after a 120ms delay.
Figure 35. Timing When MR is Toggled
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 23
RESET
VOUT2
VIN1
VIN2
EN1
EN2
VOUT1
VSENSE1
PG1
MR
RESET
PG2
VSENSE2
VOUT2
VIN VOUT1
PG2
0.1 Fm10 Fm
10 Fm
0.1 Fm
EN1
TPS702xxPWP
(FixedOutputOption)
>2V
<0.7V
EN2
250kW
250kW
>2V
<0.7V
EN2
VOUT2
VOUT1
PG2
PG1
RESET
EN1
95%
95%
MR
(PG1tiedto )MR
FAULTONVOUT1
120ms
t1
NOTES:A.t :TimeatwhichV isgreaterthanV and islogichigh.
B.Thetimingdiagramisnotdrawntoscale.
1 IN UVLO MR
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
Application condition: VIN1 and VIN2 are tied to
same fixed input voltage greater than VUVLO. PG1 is
tied to MR.
EN1 and EN2 are initially high; therefore, both
regulators are off, and PG1 (tied to MR) and PG2 are
at logic low. Since MR is at logic low, RESET is also
at logic low. When EN2 is taken to logic low, VOUT2
turns on. Later, when EN1 is taken to logic low, VOUT1
turns on. When VOUT2 reaches 95% of its regulated
output voltage, PG2 goes to logic high. When VOUT1
reaches 95% of its regulated output voltage, PG1
goes to logic high. When VIN1 is greater than VUVLO
and MR (tied to PG2) is at logic high, RESET is
pulled to logic high after a 120ms delay. When a fault
on VOUT1 causes it to fall below 95% of its regulated
output voltage, PG1 (tied to MR) goes to logic low.
Since MR is logic low, RESET goes to logic low.
VOUT2 is unaffected.
Figure 36. Timing When VOUT1 Faults Out
24 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
RESR LESL C
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
APPLICATION INFORMATION
Input Capacitor
For a typical application, an input bypass capacitor (0.1μF to 1μF) is recommended. This capacitor filters any
high-frequency noise generated in the line. For fast transient conditions where droop at the input of the LDO may
occur because of high inrush current, it is recommended to place a larger capacitor at the input as well. The size
of this capacitor depends on the output current and response time of the main power supply, as well as the
distance to the VIpins of the LDO.
Output Capacitor
As with most LDO regulators, the TPS702xx requires an output capacitor connected between OUT and GND to
stabilize the internal control loop. The minimum recommended capacitance values are 10μF ceramic capacitors
with an ESR (equivalent series resistance) between 50mΩand 2.5Ωor 6.8μF tantalum capacitors with ESR
between 250mΩand 4Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors with
capacitance values greater than 10μF are all suitable, provided they meet the requirements described above.
Larger capacitors provide a wider range of stability and better load transient response. Table 1 gives a partial
listing of surface-mount capacitors suitable for use with the TPS702xx for fast transient response applications.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for user
applications. When necessary to achieve low height requirements along with high output current and/or high load
capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
Table 1. Partial Listing of TPS702xx-Compatible Surface-Mount Capacitors
VALUE MANUFACTURER MAXIMUM ESR MFR PART NO.
22μF Kemet 345mΩ7495C226K0010AS
33μF Sanyo 100mΩ10TPA33M
47μF Sanyo 100mΩ6TPA47M
68μF Sanyo 45mΩ10TPC68M
ESR and Transient Response
LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors
are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is
used to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are
resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the
inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any
capacitor can therefore be drawn as shown in Figure 37.
Figure 37. ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application
focuses mainly on the parasitic resistance ESR.
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 25
LDO
Vin
VESR
Iout
RESR
Cout
RLOAD Vout
+
−
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
Figure 38 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
Figure 38. LDO Output Stage with Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V(CO) = VOUT). This condition means no current is flowing into the
COUT branch. If IOUT suddenly increases (a transient condition), the following results occur:
• The LDO is not able to supply the sudden current need because of its response time (t1in Figure 39).
Therefore, capacitor COUT provides the current for the new load condition (dashed arrow). COUT now acts like
a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop
occurs at RESR. This voltage is shown as VESR in Figure 38.
• When COUT is conducting current to the load, initial voltage at the load will be VOUT = V(CO) – VESR. As a result
of the discharge of COUT, the output voltage VOUT drops continuously until the response time t1of the LDO is
reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until
it reaches the regulated voltage. This period is shown as t2in Figure 39.
26 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
ESR1
ESR2
ESR3
3
1
2
IOUT
VOUT
t1t2
R1= V
V
OUT
REF
-1´R2
(
(
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
Figure 39. Correlation of Different ESRs and Their Influence on the Regulation of VOat a Load Step from
Low-to-High Output Current
Figure 39 also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
• The higher the ESR, the larger the droop at the beginning of the load transient.
• The smaller the output capacitor, the faster the discharge time and the greater the voltage droop during the
LDO response period.
Conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
Programming the TPS70202 Adjustable LDO Regulator
The output voltage of the TPS70202 adjustable regulators is programmed using external resistor dividers as
shown in Figure 40.
Resistors R1 and R2 should be chosen for approximately a 50μA divider current. Lower value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at the sense terminal increase the output voltage error. The recommended design procedure is to
choose R2 = 30.1kΩto set the divider current at approximately 50μA, and then calculate R1 using Equation 1:
(1)
where:
• VREF = 1.224V typ (the internal reference voltage)
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 27
OUTPUTVOLTAGE
PROGRAMMINGGUIDE
VO
VI
OUT
FB
R1
R2
GND
EN
IN
<0.7V
>2.0 V
TPS70202
0.1 mF
+
OUTPUT
VOLTAGE R1 R2
2.5V
3.3V
3.6V
UNIT
31.6
51.1
59.0
30.1
30.1
30.1
kW
kW
kW
PD(max) +TJmax*TA
RqJA
PD+ǒVI*VOǓ IO
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
www.ti.com
Figure 40. TPS70202 Adjustable LDO Regulator Programming
Regulator Protection
Both TPS702xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (for example, during power-down). Current is conducted from the output
to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS702xx also features internal current limiting and thermal protection. During normal operation, the
TPS702xx regulator 1 limits output current to approximately 1.6A (typ) and regulator 2 limits output current to
approximately 750mA (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
+150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below +130°C (typ),
regulator operation resumes.
Power Dissipation and Junction Temperature
Specified regulator operation is assured to a junction temperature of +125°C; the maximum junction temperature
should be restricted to +125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max).
The maximum-power-dissipation limit is determined using Equation 2:
(2)
where:
• TJmax is the maximum allowable junction temperature
• RθJA is the thermal resistance junction-to-ambient for the package; that is, 32.6°C/W for the 20-terminal PWP
with no airflow
• TAis the ambient temperature
The regulator dissipation is calculated using Equation 3:
(3)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
28 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated
TPS70245, TPS70248
TPS70251, TPS70258
TPS70202
www.ti.com
SLVS286E –JUNE 2000–REVISED DECEMBER 2009
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December, 2007) to Revision E Page
• Corrected typo in output current limit specification units ...................................................................................................... 5
• Deleted falling edge delay specification ................................................................................................................................ 6
• Updated Fixed Voltage Version block diagram .................................................................................................................... 7
• Updated Adjustable Voltage Version block diagram ............................................................................................................ 8
Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 29
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS70202PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70202PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70202PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70202PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70245PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70245PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70245PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70245PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70248PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70248PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70248PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70248PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70251PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70251PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70251PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70251PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70258PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70258PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70258PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS70258PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 3-Dec-2009
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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PACKAGE OPTION ADDENDUM
www.ti.com 3-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS70202PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS70245PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS70248PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS70251PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS70258PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS70202PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS70245PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS70248PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS70251PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS70258PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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