TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS FEATURES DESCRIPTION * The TPS702xx is a low dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 500mA and 250mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190A at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. 1 23 * * * * * * * * * * * * * * * Dual Output Voltages for Split-Supply Applications Independent Enable Functions (See Part Number TPS701xx for Sequenced Outputs) Output Current Range of 500mA on Regulator 1 and 250mA on Regulator 2 Fast Transient Response Voltage Options: 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and Dual Adjustable Outputs Open Drain Power-On Reset with 120ms Delay Open Drain Power Good for Regulator 1 and Regulator 2 Ultralow 190A (typ) Quiescent Current 1A Input Current During Standby Low Noise: 65VRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature One Manual Reset Input 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 20-Pin PowerPADTM TSSOP Package Thermal Shutdown Protection PWP PACKAGE (TOP VIEW) NC VIN1 VIN1 MR EN1 EN2 RESET GND VIN2 VIN2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC VOUT1 VOUT1 VSENSE1/FB1 PG1 PG2 VSENSE2/FB2 VOUT2 VOUT2 NC NC = No internal connection TPS70251 PWP 5V VIN1 0.1 mF 10 mF VSENSE1 250 kW PG1 PG1 VIN2 MR MR >2 V EN1 <0.7 V EN2 >2 V 250 kW >2 V <0.7 V 0.1 mF 250 kW RESET RESET EN1 PG2 EN2 VSENSE2 I/O 3.3 V VOUT1 PG2 <0.7 V 1.8 V VOUT2 Core 10 mF 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com The TPS702xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10F low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230A over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2A at TJ = +25C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS702xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the logic high state, RESET goes to a high impedance state after a 120ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V. 2 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) VOLTAGE (V) (1) (2) (2) PRODUCT VOUT1 VOUT2 PACKAGELEAD (DESIGNATOR) SPECIFIED TEMPERATURE RANGE (TJ) TPS70202 Adjustable Adjustable HTSSOP-20 (PWP) -40C to +125C TPS70245 3.3V 1.2V HTSSOP-20 (PWP) -40C to +125C TPS70248 3.3V 1.5V HTSSOP-20 (PWP) -40C to +125C TPS70251 3.3V 1.8V HTSSOP-20 (PWP) -40C to +125C TPS70258 3.3V 2.5V HTSSOP-20 (PWP) -40C to +125C ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TPS70202PWP Tube, 70 TPS70202PWPR Tape and Reel, 2000 TPS70245PWP Tube, 70 TPS70245PWPR Tape and Reel, 2000 TPS70248PWP Tube, 70 TPS70248PWPR Tape and Reel, 2000 TPS70251PWP Tube, 70 TPS70251PWPR Tape and Reel, 2000 TPS70258PWP Tube, 70 TPS70258PWPR Tape and Reel, 2000 For the most current package and ordering information see the Package Option Addendum located at the end of this document, or see the TI web site at www.ti.com. For fixed 1.20V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). Input voltage range: VIN1, VIN2 (2) Voltage range at EN1, EN2 TPS702xx UNIT -0.3 to +7 V -0.3 to +7 V Output voltage range (VOUT1, VSENSE1) 5.5 V Output voltage range (VOUT2, VSENSE2) 5.5 V Maximum RESET, PG1, PG2 voltage 7 V Maximum MR voltage VIN1 V Internally limited -- See Dissipation Ratings Table -- Operating virtual junction temperature range, TJ -40 to +150 C Storage temperature range, Tstg -65 to +150 C 2 kV Peak output current Continuous total power dissipation ESD rating, HBM (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are tied to network ground. Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 3 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com DISSIPATION RATINGS PACKAGE AIR FLOW (CFM) TA +25C DERATING FACTOR TA = +70C TA = +85C 0 3.067W 30.67mW/C 1.687W 1.227W 250 4.115W 41.15mW/C 2.265W 1.646W PWP (1) (1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground layer. For more information, refer to TI technical brief SLMA002. RECOMMENDED OPERATING CONDITIONS Over operating temperature range (unless otherwise noted). Input voltage, VI (1) (regulator 1 and 2) Output current, IO (regulator 1) Output current, IO (regulator 2) MIN MAX 2.7 6 UNIT 0 500 mA mA V 0 250 Output voltage range (for adjustable option) 1.22 5.5 V Operating virtual junction temperature, TJ -40 +125 C (1) 4 To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 ELECTRICAL CHARACTERISTICS Over recommended operating junction temperature range (TJ = -40C to +125C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN1 = 0V, EN2 = 0V, and CO = 33F (unless otherwise noted). PARAMETER Reference voltage 1.2V Output Output voltage VO (1) , 1.5V Output (2) 1.8V Output 2.5V Output 3.3V Output TEST CONDITIONS 2.7V < VIN < 6V, TJ = +25C FB connected to VO 2.7V < VIN < 6V, FB connected to VO 2.7V < VIN < 6V, TJ = +25C 2.7V < VIN < 6V, 2.7V < VIN < 6V, Output voltage line regulation (VO/VO) for regulator 1 and regulator 2 (3) VO + 1V < VIN 6V, TJ = +25C (1) VO + 1V < VIN 6V (1) Load regulation for VOUT 1 and VOUT2 TJ = +25C Output current limit Regulator 2 Regulator 1 Regulator 2 BW = 300Hz to 50kHz, TJ = +25C PSRR Powersupply ripple rejection 3.366 190 230 0.01 0.1 1 CO = 33F, TJ = +25C 1.6 1.9 0.750 1 +150 Regulator 1 EN1 = VIN, EN2 = VI Regulator 2 EN1 = VIN, EN2 = VI Regulator 1 f = 1kHz, CO = 33F, IOUT1 = 500mA TJ = +25C (1) 60 Regulator 2 f = 1kHz, CO = 33F, IOUT2 = 250mA TJ = +25C (1) 50 %V VRMS 65 VOUT = 0V A mV 65 Thermal shutdown junction temperature II Standby (standby) current 2.55 3.3 3.234 (2) V 1.836 2.45 See Vn 1.53 2.5 TJ = +25C (2) Regulator 1 1.224 1.764 See Output noise voltage 1.244 1.8 TJ = +25C 4.3V < VIN < 6V, UNIT 1.5 TJ = +25C Quiescent current (GND current) for regulator 1 and regulator 2, EN1 = EN2 = 0V (1) MAX 1.2 1.47 3.5V < VIN < 6V, 4.3V < VIN < 6V, 1.196 1.176 2.8V < VIN < 6V, 3.5V < VIN < 6V, TYP 1.22 TJ = +25C 2.7V < VIN < 6V, 2.8V < VIN < 6V, MIN A C TJ = +25C 2 6 A dB UVLO threshold 2.4 2.65 V RESET Terminal Minimum input voltage for valid RESET IRESET = 300A, t (RESET) RESET pulse duration Output low voltage VIN = 3.5V, Leakage current V(RESET) = 6V (1) (2) (3) V(RESET) 0.8V 80 I(RESET) = 1mA 1.0 1.3 V 120 160 ms 0.15 0.4 V 1 A Minimum input operating voltage is 2.7V or VO(typ) + 1V, whichever is greater. Maximum input voltage = 6V, minimum output current = 1mA. IO = 1mA to 500mA for Regulator 1 and 1mA to 250mA for Regulator 2. (VImax - 2.7) x 1000 Line regulation (mV) = (%/V) x Vo 100 If VO < 1.8V then VImax = 6V, VImin = 2.7V: [V - (Vo + 1) ] x 1000 Line regulation (mV) = (%/V) x Vo Imax 100 If VO > 2.5V then VImax = 6V, VImin = VO + 1V: Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 5 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating junction temperature range (TJ = -40C to +125C), VIN1 or VIN2 = VOUT(nom) + 1V, IO = 1mA, EN1 = 0V, EN2 = 0V, and CO = 33F (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.0 1.3 95 98 %VOUT PG1/PG2 Terminal V(PGx) 0.8V Minimum input voltage for valid PGx I(PGx) = 300A, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO 0.5 %VOUT tr(PGx) Rising edge deglitch 30 s Output low voltage VIN = 2.7V, Leakage current V(PGx) = 6V 92 I(PGx) = 1mA 0.15 V 0.4 V 1 A EN1/EN2 Terminal High-level ENx input voltage 2 V Low-level ENx input voltage Input current (ENx) -1 0.7 V 1 A MR Terminal High-level input voltage 2 V Low-level input voltage 0.7 Pull-up current source V A 6 VOUT1 Terminal Dropout voltage (4) IO = 500mA, VIN1 = 3.2V TJ = +25C 170 IO = 500mA, VIN1 = 3.2V 275 mV Peak output current 2ms pulse width 750 mA Discharge transistor current VOUT1 = 1.5V 7.5 mA Peak output current 2ms pulse width 375 mA Discharge transistor current VOUT2 = 1.5V 7.5 mA 1 A VOUT2 Terminal FB Terminal Input current: TPS70202 (4) 6 FB = 1.8V Input voltage (VIN1 or VIN2) = VO(typ) - 100mV. For 1.5V, 1.8V and 2.5V regulators, the dropout voltage is limited by input voltage range. The 3.3V regulator input is set to 3.2V to perform this test. Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 DEVICE INFORMATION Fixed Voltage Version VIN1 (2 Pins) VOUT1 (2 Pins) 2.5 V UVLO Comp 10 kW Current Sense + + GND VSENSE1 ENA_1 Thermal Shutdown Reference (see Note A) ENA_1 Vref FB1 Vref PG1 VSENSE1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG1 Comp MR RESET 120 ms Delay ENA_1 EN1 VSENSE2 - 0.95 x Vref + ENA_2 PG2 Comp PG2 Rising Edge Deglitch Vref FB2 EN2 - + ENA_2 VSENSE2 Current Sense ENA_2 (see Note A) 10 kW VOUT2 (2 Pins) VIN2 (2 Pins) A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT1 and VOUT2, respectively, as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the Application Information section. Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 7 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com Adjustable Voltage Version VIN1 (2 Pins) VOUT1 (2 Pins) UVLO Comp Current Sense 2.5 V (see Note A) + GND FB1 ENA_1 + Thermal Shutdown Reference ENA_1 Vref Vref PG1 FB1 - 0.95 x Vref + Rising Edge Deglitch VIN1 PG1 Comp MR RESET 120 ms Delay ENA_1 EN1 PG2 Comp FB2 - 0.95 x Vref + ENA_2 PG2 Rising Edge Deglitch Vref FB2 EN2 - + ENA_2 FB2 Current Sense 8 (see Note A) VOUT2 (2 Pins) VIN2 (2 Pins) A. ENA_2 For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other implementations, refer to FB terminals connection discussion in the Application Information section. Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 RESET Timing Diagram VIN1 VUVLO VUVLO VRES (see Note A) t VRES (see Note A) MR Input t RESET Output Output Undefined 120 ms Delay 120 ms Delay Output Undefined t NOTE A: VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. PG1 Timing Diagram VIN1 VUVLO VUVLO VPG VPG1 (see Note A) t VOUT1 VIT+ (see Note B) Threshold Voltage VIT(see Note B) t PG1 Output PG1 Output Undefined Output Undefined t NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT- trip voltage is typically 5% lower than the output voltage (95%VO). VIT- to VIT+ is the hysteresis voltage. Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 9 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com PG2 Timing Diagram (assuming VIN1 already powered up) VIN2 t VOUT2 VIT+ (see Note A) Threshold Voltage VIT(see Note A) t PG2 Output t NOTE A: VIT- trip voltage is typically 5% lower than the output voltage (95%VO). VIT- to VIT+ is the hysteresis voltage. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION EN1 5 I Active low enable for VOUT1 EN2 6 I Active low enable for VOUT2 GND 8 -- MR 4 I NC 1, 11, 20 -- No connection PG1 16 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage PG2 15 O Open drain output, low when VOUT2 voltage is less than 95% of the nominal regulated voltage RESET 7 I Open drain output, SVS (power-on reset) signal, active low VIN1 2, 3 I Input voltage of regulator 1 VIN2 9, 10 I Input voltage of regulator 2 VOUT1 18, 19 O Output voltage of regulator 1 VOUT2 12, 13 O Output voltage of regulator 2 VSENSE2/FB2 14 I Regulator 2 output voltage sense/regulator 2 feedback for adjustable VSENSE1/FB1 17 I Regulator 1 output voltage sense/regulator 1 feedback for adjustable 10 Submit Documentation Feedback Ground Manual reset input, active low, pulled up internally Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 Detailed Description The TPS702xx low dropout regulator family provides dual regulated output voltages with independent enable functions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good (PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete power solution. The TPS702xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/). The TPS702xx uses a PMOS transistor to pass current; the gate of the PMOS is voltage-driven, so operating current is low and stable over the full load range. Pin Functions Enable (EN1, EN2) The EN terminals are inputs that enable or shut down each respective regulator. If EN is at a voltage high signal, the respective regulator is in shutdown mode. When EN goes to voltage low, the respective regulator is enabled. Power-Good (PG1, PG2) The PG terminals are open drain, active high output terminals that indicate the status of each respective regulator. When VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When VOUT2 reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance state when its respective output voltage is pulled below 95% (that is, goes to an overload condition) of its regulated voltage. The open drain outputs of the PG terminals require a pull-up resistor. Manual Reset Pin MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR (RESET) occurs. The terminal has a 6A pull-up current to VIN1. Sense (VSENSE1, VSENSE2) The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection should be as short as possible. Internally, the sense terminal connects to high-impedance, wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way as to minimize or avoid noise pickup. Adding RC networks between sense terminals and VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 11 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize or avoid noise pickup. Adding RC networks between FB terminals and VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. RESET Indicator The TPS702xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power on reset circuitry or a low-battery indicator. RESET is an active low, open drain output that indicates the status of the manual reset pin (MR). When MR is in a high impedance state, RESET goes to a high impedance state after a 120 ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. The open drain output of the RESET terminal requires a pull-up resistor. If RESET is not used, it can be left floating. VIN1 and VIN2 VIN1 and VIN2 are inputs to each regulator. Internal bias voltages are powered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 are output terminals of each regulator. 12 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO vs Output current Figure 1 to Figure 3 vs Junction temperature Figure 4 to Figure 5 Ground current vs Junction temperature Figure 6 Power-supply rejection ratio vs Frequency Figure 7 to Figure 10 Output spectral noise density vs Frequency Figure 11 to Figure 14 Output impedance vs Frequency Output voltage PSRR ZO Dropout voltage Figure 15 to Figure 18 vs Temperature Figure 19 and Figure 20 vs Input voltage Figure 21 and Figure 22 Load transient response Figure 23 and Figure 24 Line transient response (VOUT1) Figure 25 Line transient response (VOUT2) VO Figure 26 Output voltage vs Time (start-up) Figure 27 and Figure 28 Equivalent series resistance (ESR) vs Output current Figure 30 to Figure 33 TPS70251 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70251 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.303 1.802 VIN1 = 4.3 V TJ = +25C VOUT1 VIN2 = 2.8 V TJ = +25C VOUT2 1.801 3.301 VO - Output Voltage - (V) VO - Output Voltage - (V) 3.302 3.300 3.299 3.298 3.297 1.800 1.799 1.798 1.797 1.796 3.296 3.295 1.795 0 0.1 0.2 0.3 I O - Output Current - (A) Figure 1. Copyright (c) 2000-2009, Texas Instruments Incorporated 0.4 0.5 0 0.05 0.2 0.1 0.15 I O - Output Current - (A) 0.25 Figure 2. Submit Documentation Feedback 13 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) TPS70245 OUTPUT VOLTAGE vs OUTPUT CURRENT TPS70251 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE 3.35 1.201 3.33 VO - Output Voltage - (V) 1.200 VO - Output Voltage - (V) VIN1 = 4.3 V VOUT1 VIN2 = 2.7 V TJ = +25C VOUT2 1.199 1.198 1.197 1.196 IO = 500 mA 3.31 3.29 IO = 1 mA 3.27 3.25 1.195 0 0.05 0.2 0.1 0.15 I O - Output Current - (A) 3.23 -40 -25 -10 0.25 50 65 TPS70251 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE GROUND CURRENT vs JUNCTION TEMPERATURE 80 95 110 125 210 Regulator 1 and Regulator 2 200 IO = 1 mA 1.79 IO = 250 mA 1.77 Ground Current - mA 1.83 VO - Output Voltage - (V) 35 Figure 4. VIN2 = 2.8 V VOUT2 190 IOUT1 = 1 mA IOUT2 = 1 mA 180 IOUT1 = 500 mA IOUT2 = 250 mA 170 1.75 160 1.73 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - C 150 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ - Junction Temperature - C Figure 5. 14 20 Figure 3. 1.85 1.81 5 TJ - Junction Temperature - C Submit Documentation Feedback Figure 6. Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) TPS70251 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70251 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 10 IO = 10 mA CO = 22 mF VOUT1 -20 PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB -10 -30 -40 -50 -60 -70 -80 -90 100 1k 10 k 100 k -20 -30 -40 -50 -60 -70 -80 1M 10 100 1k 10 k 100 k f - Frequency - Hz f - Frequency - Hz Figure 7. Figure 8. TPS70251 POWER-SUPPLY REJECTION RATIO vs FREQUENCY TPS70251 POWER-SUPPLY REJECTION RATIO vs FREQUENCY 1M 10 IO = 10 mA CO = 22 mF VOUT2 -20 PSRR - Power Supply Rejection Ratio - dB PSRR - Power Supply Rejection Ratio - dB -10 -90 10 -10 -30 -40 -50 -60 -70 -80 -90 IO = 500 mA CO = 22 mF VOUT1 0 10 100 1k 10 k f - Frequency - Hz Figure 9. Copyright (c) 2000-2009, Texas Instruments Incorporated 100 k 1M IO = 250 mA CO = 22 mF VOUT2 0 -10 -20 -30 -40 -50 -60 -70 10 100 1k 10 k 100 k 1M f - Frequency - Hz Figure 10. Submit Documentation Feedback 15 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN1 = 4.3 V VOUT1 = 3.3 V IO = 10 mA Output Spectral Noise Density - mV/OHz Output Spectral Noise Density - mV/OHz 10 1 0.1 0.01 100 1k 10 k f - Frequency - Hz 1k 10 k f - Frequency - Hz Figure 12. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 100 k 10 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA Output Spectral Noise Density - mV/OHz Output Spectral Noise Density - mV/OHz 0.1 Figure 11. 1 0.1 1k 10 k f - Frequency - Hz Figure 13. 16 1 0.01 100 100 k 10 0.01 100 VIN1 = 4.3 V VOUT1 = 3.3 V IO = 500 mA Submit Documentation Feedback 100 k VIN2 = 2.8 V VOUT2 = 1.8 V IO = 250 mA 1 0.1 0.01 100 1k 10 k f - Frequency - Hz 100 k Figure 14. Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 100 CO = 33 mF IO = 500 mA VOUT1 = 3.3 V TJ = +25C 10 ZO - Output Impednace - W ZO - Output Impednace - W 100 1 0.1 0.01 10 100 100 k 1k 10 k f - Frequency - Hz 1M 0.1 10 100 1k 10 k 100 k Figure 15. Figure 16. OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 1M 10 M 1M 10 M 100 CO = 33 mF IO = 250 mA VOUT2 = 1.8 V TJ = +25C 10 ZO - Output Impednace - W ZO - Output Impednace - W 1 f - Frequency - Hz 100 1 0.1 0.01 10 0.01 10 M CO = 33 mF IO = 10 mA VOUT1 = 3.3 V TJ = +25C 10 100 1k 10 k 100 k f - Frequency - Hz Figure 17. Copyright (c) 2000-2009, Texas Instruments Incorporated 1M 10 M CO = 33 mF IO = 10 mA VOUT2 = 1.8 V TJ = +25C 10 1 0.1 0.01 10 100 1k 10 k 100 k f - Frequency - Hz Figure 18. Submit Documentation Feedback 17 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) DROPOUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs TEMPERATURE 6 250 CO = 33 mF VIN1 = 3.2 V CO = 33 mF VIN1 = 3.2 V 5 200 Dropout Voltage - mV Dropout Voltage - mV IO = 500 mA 150 100 50 IO = 10 mA 4 3 2 1 IO = 0 mA 0 40 25 10 5 20 35 50 65 80 0 -40 -25 -10 95 110 125 T - Temperature - C Figure 20. TPS70202 DROPOUT VOLTAGE vs INPUT VOLTAGE TPS70202 DROPOUT VOLTAGE vs INPUT VOLTAGE IO = 250 mA VOUT2 400 TJ = +125C Dropout Voltage - mV Dropout Voltage - mV 95 110 125 500 IO = 500 mA VOUT1 250 200 TJ = +25C 150 100 TJ= - 40C TJ = +125C 300 TJ = +25C 200 TJ = -40C 100 50 3 3.5 4 4.5 VI - Input Voltage - V Figure 21. 18 20 35 50 65 80 T - Temperature - C Figure 19. 300 0 2.5 5 Submit Documentation Feedback 5 5.5 0 2.5 3 3.5 4 4.5 5 5.5 VI - Input Voltage - V Figure 22. Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) IO - Output Current - mA LOAD TRANSIENT RESPONSE CO = 33 mF TJ = +25C VOUT1 = 3.3 V 500 250 0 20 0 -20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 DVO - Change in Output Voltage - mV Output Voltage - mV DVO - Change in IO - Output Current - mA LOAD TRANSIENT RESPONSE CO = 33 mF TJ = +25C VOUT2 = 1.8 V 250 0 20 0 -20 0 0.2 0.4 0.6 0.8 LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE VI - Input Voltage - V Figure 24. 4.3 50 0 -50 20 40 60 80 100 120 140 160 180 200 t - Time - ms Figure 25. Copyright (c) 2000-2009, Texas Instruments Incorporated DVO - Change in Output Voltage - mV VI - Input Voltage - V DVO - Change in Output Voltage - mV 1.4 1.6 Figure 23. TJ = +25C IO = 500 mA CO = 33 mF VOUT1 0 1.2 1.8 2 t - Time - ms t - Time - ms 5.3 1 TJ = +25C IO = 250 mA CO = 33 mF VOUT2 3.8 2.8 10 0 10 0 20 40 60 80 100 120 140 160 180 200 t - Time - ms Figure 26. Submit Documentation Feedback 19 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) Enable Voltage (EN2) - V VOUT2 - Output Voltage Enable Voltage (EN1) - V VOUT1 - Output Voltage OUTPUT VOLTAGE AND ENABLE VOLTAGE vs TIME (START-UP) 3 2 VO = 3.3 V CO = 33 mF IO = 500 mA VOUT2 = Standby 1 0 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VO = 1.5 V CO = 33 mF IO = 250 mA VOUT1 = Standby 3 2 1 0 5 0 0 0.2 0.4 0.6 t - Time - ms Figure 27. VIN 0.8 1.0 1.2 1.4 t - Time - ms 1.6 1.8 2.0 Figure 28. To Load IN OUT + COUT EN RL GND ESR Figure 29. Test Circuit for Typical Regions of Stability 20 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 10 REGION OF INSTABILITY ESR - Equivalent Series Resistance - W ESR - Equivalent Series Resistance - W 10 TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT VO = 3.3 V CO = 10 mF TJ = 25C 1 0.1 50 mW REGION OF INSTABILITY 0.01 REGION OF INSTABILITY VO = 3.3 V CO = 6.8 mF TJ = 25C 1 250 mW REGION OF INSTABILITY 0.1 0 50 100 150 200 0 250 50 Figure 31. TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE(1) vs OUTPUT CURRENT 250 10 REGION OF INSTABILITY ESR - Equivalent Series Resistance - W ESR - Equivalent Series Resistance - W 200 Figure 30. 10 VO = 1.8 V CO = 10 mF TJ = 25C 0.1 50 mW REGION OF INSTABILITY 0.01 150 IO - Output Current - mA IO - Output Current - mA 1 100 REGION OF INSTABILITY VO = 1.8 V CO = 6.8 mF TJ = 25C 1 250 mW REGION OF INSTABILITY 0.1 0 25 50 75 IO - Output Current - mA Figure 32. 100 125 0 25 50 75 100 125 IO - Output Current - mA Figure 33. (1) Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 21 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com APPLICATION INFORMATION TPS702xxPWP (Fixed Output Option) Sequencing Timing Diagrams This section provides a number of timing diagrams showing how this device functions in different configurations. VIN VIN1 0.1 mF VSENSE1 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO. PG2 is tied to MR. V OUT1 VOUT1 10 mF 250 kW PG1 MR VIN2 EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 and PG2 (tied to MR) are at logic low. Since MR is at logic low, RESET is also at logic low. When EN1 is taken to logic low, VOUT1 turns on. Later, when EN2 is taken to logic low, VOUT2 turns on. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When VOUT2 reaches 95% of its regulated output voltage, PG2 (tied to MR) goes to logic high. When VIN1 is greater than VUVLO and M R (tied to PG2) is at logic high, RESET is pulled to logic high after a 120ms delay. When EN1 and EN2 are returned to logic high, both devices power down and both PG1, PG2 (tied to MR2), and RESET return to logic low. 0.1 mF >2 V RESET EN1 <0.7 V 250 kW RESET PG2 VSENSE2 EN2 >2 V PG2 EN1 MR EN2 VOUT2 VOUT2 <0.7 V 10 mF EN2 EN1 95% VOUT2 95% VOUT1 PG2 PG1 MR (PG1 tied to MR) RESET t1 120 ms NOTES: A. t1: Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagram is not drawn to scale. Figure 34. Timing When VOUT1 Is Enabled Before VOUT2 22 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 Application condition: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO. MR is initially logic high but is eventually toggled. EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 and PG2 are at logic low. Since VIN1 is greater than VUVLO and MR is at logic high, RESET is also at logic high. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on. When VOUT2 reaches 95% of its regulated output voltage, PG2 goes to logic high. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When MR is taken to logic low, RESET is taken low. When MR returns to logic high, RESET returns to logic high after a 120ms delay. TPS702xxPWP (Fixed Output Option) VIN VIN1 0.1 mF VOUT1 VOUT1 VSENSE1 10 mF 250 kW 250 kW PG1 VIN2 0.1 mF RESET EN1 EN1 PG2 <0.7 V EN2 EN2 VSENSE2 MR >2 V >2 V 250 kW VOUT2 <0.7 V RESET PG2 MR 2V 0.7 V VOUT2 10 mF EN2 EN1 95% VOUT2 95% VOUT1 PG2 PG1 MR RESET t1 120 ms NOTES: A. t1: Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagram is not drawn to scale. Figure 35. Timing When MR is Toggled Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 23 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com Application condition: VIN1 and VIN2 are tied to same fixed input voltage greater than VUVLO. PG1 is tied to MR. EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 (tied to MR) and PG2 are at logic low. Since MR is at logic low, RESET is also at logic low. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on. When VOUT2 reaches 95% of its regulated output voltage, PG2 goes to logic high. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When VIN1 is greater than VUVLO and MR (tied to PG2) is at logic high, RESET is pulled to logic high after a 120ms delay. When a fault on VOUT1 causes it to fall below 95% of its regulated output voltage, PG1 (tied to MR) goes to logic low. Since MR is logic low, RESET goes to logic low. VOUT2 is unaffected. TPS702xxPWP (Fixed Output Option) VIN VIN1 0.1 mF VOUT1 VOUT1 VSENSE1 10 mF 250 kW PG1 VIN2 0.1 mF EN1 MR RESET EN1 PG2 250 kW RESET PG2 >2 V VSENSE2 <0.7 V EN2 >2 V EN2 VOUT2 VOUT2 <0.7 V 10 mF EN2 EN1 95% VOUT2 95% VOUT1 FAULT ON VOUT1 PG2 PG1 MR (PG1 tied to MR) RESET t1 120 ms NOTES: A. t1: Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagram is not drawn to scale. Figure 36. Timing When VOUT1 Faults Out 24 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 APPLICATION INFORMATION Input Capacitor For a typical application, an input bypass capacitor (0.1F to 1F) is recommended. This capacitor filters any high-frequency noise generated in the line. For fast transient conditions where droop at the input of the LDO may occur because of high inrush current, it is recommended to place a larger capacitor at the input as well. The size of this capacitor depends on the output current and response time of the main power supply, as well as the distance to the VI pins of the LDO. Output Capacitor As with most LDO regulators, the TPS702xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance values are 10F ceramic capacitors with an ESR (equivalent series resistance) between 50m and 2.5 or 6.8F tantalum capacitors with ESR between 250m and 4. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors with capacitance values greater than 10F are all suitable, provided they meet the requirements described above. Larger capacitors provide a wider range of stability and better load transient response. Table 1 gives a partial listing of surface-mount capacitors suitable for use with the TPS702xx for fast transient response applications. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for user applications. When necessary to achieve low height requirements along with high output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. Table 1. Partial Listing of TPS702xx-Compatible Surface-Mount Capacitors VALUE MANUFACTURER MAXIMUM ESR MFR PART NO. 22F Kemet 345m 7495C226K0010AS 33F Sanyo 100m 10TPA33M 47F Sanyo 100m 6TPA47M 68F Sanyo 45m 10TPC68M ESR and Transient Response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor can therefore be drawn as shown in Figure 37. RESR LESL C Figure 37. ESR and ESL In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application focuses mainly on the parasitic resistance ESR. Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 25 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com Figure 38 shows the output capacitor and its parasitic impedances in a typical LDO output stage. Iout LDO + VESR RESR - Vin RLOAD Vout Cout Figure 38. LDO Output Stage with Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(CO) = VOUT). This condition means no current is flowing into the COUT branch. If IOUT suddenly increases (a transient condition), the following results occur: * The LDO is not able to supply the sudden current need because of its response time (t1 in Figure 39). Therefore, capacitor COUT provides the current for the new load condition (dashed arrow). COUT now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop occurs at RESR. This voltage is shown as VESR in Figure 38. * When COUT is conducting current to the load, initial voltage at the load will be VOUT = V(CO) - VESR. As a result of the discharge of COUT, the output voltage VOUT drops continuously until the response time t1 of the LDO is reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 39. 26 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 IOUT VOUT 1 2 3 ESR 1 ESR 2 ESR 3 t1 t2 Figure 39. Correlation of Different ESRs and Their Influence on the Regulation of VO at a Load Step from Low-to-High Output Current Figure 39 also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: * The higher the ESR, the larger the droop at the beginning of the load transient. * The smaller the output capacitor, the faster the discharge time and the greater the voltage droop during the LDO response period. Conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. Programming the TPS70202 Adjustable LDO Regulator The output voltage of the TPS70202 adjustable regulators is programmed using external resistor dividers as shown in Figure 40. Resistors R1 and R2 should be chosen for approximately a 50A divider current. Lower value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at the sense terminal increase the output voltage error. The recommended design procedure is to choose R2 = 30.1k to set the divider current at approximately 50A, and then calculate R1 using Equation 1: VOUT - 1 R2 R1 = VREF (1) ( ( where: * VREF = 1.224V typ (the internal reference voltage) Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 27 TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 www.ti.com OUTPUT VOLTAGE PROGRAMMING GUIDE TPS70202 VI IN OUTPUT VOLTAGE R1 R2 UNIT 2.5 V 31.6 30.1 kW 3.3 V 51.1 30.1 kW 3.6 V 59.0 30.1 kW 0.1 mF >2.0 V OUT EN VO <0.7 V + R1 FB GND R2 Figure 40. TPS70202 Adjustable LDO Regulator Programming Regulator Protection Both TPS702xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input voltage drops below the output voltage (for example, during power-down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS702xx also features internal current limiting and thermal protection. During normal operation, the TPS702xx regulator 1 limits output current to approximately 1.6A (typ) and regulator 2 limits output current to approximately 750mA (typ). When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds +150C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below +130C (typ), regulator operation resumes. Power Dissipation and Junction Temperature Specified regulator operation is assured to a junction temperature of +125C; the maximum junction temperature should be restricted to +125C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using Equation 2: T max *T A P D(max) + J R qJA (2) where: * TJmax is the maximum allowable junction temperature * RJA is the thermal resistance junction-to-ambient for the package; that is, 32.6C/W for the 20-terminal PWP with no airflow * TA is the ambient temperature The regulator dissipation is calculated using Equation 3: P D + VI*V O I O (3) Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. 28 Submit Documentation Feedback Copyright (c) 2000-2009, Texas Instruments Incorporated TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 www.ti.com SLVS286E - JUNE 2000 - REVISED DECEMBER 2009 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (December, 2007) to Revision E Page * Corrected typo in output current limit specification units ...................................................................................................... 5 * Deleted falling edge delay specification ................................................................................................................................ 6 * Updated Fixed Voltage Version block diagram .................................................................................................................... 7 * Updated Adjustable Voltage Version block diagram ............................................................................................................ 8 Copyright (c) 2000-2009, Texas Instruments Incorporated Submit Documentation Feedback 29 PACKAGE OPTION ADDENDUM www.ti.com 3-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS70202PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70202PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70202PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70202PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70245PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70245PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70245PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70245PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70248PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70248PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70248PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70248PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70251PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70251PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70251PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70251PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70258PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70258PWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70258PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS70258PWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 3-Dec-2009 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS70202PWPR HTSSOP PWP 20 2000 330.0 16.4 TPS70245PWPR HTSSOP PWP 20 2000 330.0 TPS70248PWPR HTSSOP PWP 20 2000 330.0 TPS70251PWPR HTSSOP PWP 20 2000 TPS70258PWPR HTSSOP PWP 20 2000 6.95 7.1 1.6 8.0 16.0 Q1 16.4 6.95 7.1 1.6 8.0 16.0 Q1 16.4 6.95 7.1 1.6 8.0 16.0 Q1 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS70202PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70245PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70248PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70251PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS70258PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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