74ABT2244D,112 - NXP Semiconductors

May 1992

Revised November 1999

74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs

74ABT244

Octal Buf f e r/L ine Driv e r wit h 3- S TATE Ou tputs

General Description

The ABT244 is an octal buffer and line driver with 3-STATE

outputs designed to be employed as a memory and

address driver, clock driver, or bus-oriented transmitter/

receiver.

Features

■Non-inverting buffers

■Output sink capability of 64 mA, source capability of

32 mA

■Guaranteed output skew

■Guaranteed multiple output switching specifications

■Output switching specified for both 50 pF and 250 pF

loads

■Guaranteed simultaneous switching, noise level and

dynamic thresh ol d per for man ce

■Guaranteed latchup protection

■High impedance glitch free bus loading during entire

power up and power down cycle

■Nondestructive hot insertion capability

■Disable time less than ena ble time to av oid bus cont en-

tion

Ordering Code:

Device a ls o av ailable in Tape and Reel. Specify by append ing suffix lette r “X” to the or dering co de.

Connection Diagram Pin Descriptions

Truth Table

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Order Number Package Number Package Description

74ABT244CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

74ABT244CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ABT244CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

74ABT244CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ABT244CPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Nam es Descri ption

OE1, OE2Output Enable Input

(Active LOW)

I0–I7Inputs

O0–O7Outputs

OE1I0–3 O0–3 OE2I4–7 O4–7

HXZHXZ

LHHLHH

LLLLLL

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74ABT244

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under th es e conditi ons is not im plied.

Note 2: Eith er v oltage lim it or c urrent limit is sufficien t to prot ect inputs .

DC Electrical Characteristics

Note 3: For 8 bits toggling, ICCD < 0.8 mA / M H z .

Note 4: Guaranteed, but not tested.

Storage Temperat ure −65°C to +150°C

Ambient Temperature under Bias −55°C to +125°C

Junction Temperature under Bias −55°C to +150°C

VCC Pin Potential to Ground Pin −0.5V to +7.0V

Input Voltage (Note 2) −0.5V to +7.0V

Input Current (N ote 2) −30 mA to +5.0 mA

Voltage Applied to Any Output

in the Disabled or

Power-Off State −0.5V to 5.5V

in the HIGH State −0.5V to VCC

Current Applied to Output

in LOW St ate (Max) twice the r ated IOL (mA)

DC Latchup Source Current −500 mA

Over Voltage Latchup (I/O) 10V

Free Air Ambient Temperature −40°C to +85°C

Supply Voltage +4.5V to +5.5V

Minimum Input Edge Rate (∆V/∆t)

Data Input 50 mV/ns

Enable Input 20 mV/ns

Symbol Parameter Min Typ Max Units VCC Conditions

VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal

VIL Input LOW Voltage 0.8 V Recognized LOW Signal

VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA

VOH Output HIGH Voltage 2.5 V Min IOH = −3 mA

2.0 V Min IOH = −32 mA

VOL Output LOW Voltage 0.55 IOL = 64 mA

IIH Input HIGH Current 1 µAMaxV

IN = 2.7V (Note 4)

IN = VCC

IBVI Input HIGH Current Breakdown Test 7 µAMaxV

IN = 7.0V

IIL Input LOW Current −1µAMax

VIN = 0.5V (Note 4)

−1V

IN = 0.0V

VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA

All Other Pins Grounded

IOZH Output Leakage Current 10 µA0 − 5.5V VOUT = 2.7V; OEn = 2.0V

IOZL Output Leakage Current −10 µA0 − 5.5V VOUT = 0.5V; OEn = 2.0V

IOS Output Short-Circuit Current −100 −275 mA Max VOUT = 0.0V

ICEX Output High Leakage Current 50 µAMaxV

OUT = VCC

IZZ Bus Drainage Test 10 0 µA0.0V

OUT = 5.5V; All Others GND

ICCH Power Supply Current 50 µA Max All Outputs HIGH

ICCL Power Supply Current 30 mA Max All Outputs LOW

ICCZ Power Supply Current 50 µAMax

OEn = VCC,

All Others at VCC or Ground

ICCT Additional ICC/Input Outputs Enabled 2.5 mA Max VI = VCC − 2.1V

Outputs 3-STATE 2.5 mA Enable Input VI = VCC − 2.1V

Outputs 3-STATE 50 µA Data Input VI = VCC − 2.1V

All Others at VCC or Ground

ICCD Dynamic ICC No Load mA/ Max Outputs OPEN

(Note 4) 0.1 MHz OEn = GND, (Note 3)

One Bit Toggling, 50% Duty Cycle

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74ABT244

DC Electrical Characteristics

(SOIC package)

Note 5: Ma x num ber of outpu t s defined as (n). n − 1 data inp ut s are drive n 0V to 3V. One output at LOW. Guarante ed, but no t tes t ed.

Note 6: Max number of da ta inp uts (n) swit chi ng. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD).

Guaranteed, but not tested.

Note 7: Ma x num ber of outpu t s defined as (n). n − 1 data inp ut s are drive n 0V to 3V. One output H I GH . Guaranteed, bu t not te s t ed.

AC Electrical Characteristics

(SOIC and SSOP package)

Extended AC Electrical Characteristics

(SOIC package)

Note 8: This specification is gu aranteed but not tes t ed. The limits apply t o propaga t ion delays fo r all paths describe d s w it c hing in phase

(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).

Note 9: This speci fication is gu aranteed but not tes t ed. The lim it s represent propaga t ion delay with 250 pF load capac it ors in plac e of t he 50 pF load

capacitors in the standard AC load. This specification pertains to single output switching only.

Note 10: T his spec if ic at ion is guaranteed but not tes te d. T he limits represen t propagation delays f or all paths d es c ribed swit c hing in phase

(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.

Note 11: The 3-STATE delays are d om inated by th e R C network (500Ω, 250 pF) on the output and have been excluded from the datasheet.

Conditions

Symbol Parameter Min Typ Max Units VCC CL = 50 pF,

RL = 500Ω

VOLP Quiet Output Maximum Dynamic VOL 0.5 0.8 V 5.0 TA = 25°C (Note 5)

VOLV Quiet Output Minimum Dynamic VOL −1.3 −0.8 V 5.0 TA = 25°C (Note 5)

VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.1 V 5.0 TA = 25°C (Note 7)

VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.5 V 5.0 TA = 25°C (Note 6)

VILD Maximum LOW Level Dynamic Input Voltage 1.1 0.8 V 5.0 TA = 25°C (Note 6)

TA = +25°CT

A = −55°C to +125°CT

A = −40°C to +85°C

Symbol Parameter VCC = +5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V Units

CL = 50 pF CL = 50 pF CL = 50 pF

Min Typ Max Min Max Min Max

tPLH Propagation Delay 1.0 2.5 3.6 1.0 5.3 1.0 3.6 ns

tPHL Data to Outputs 1.0 2.3 3.6 1.0 5.0 1.0 3.6

tPZH Output Enable 1.5 3.5 6.0 0.8 6.5 1.5 6.0 ns

tPZL Time 1.5 3.6 6.0 1.2 7.9 1.5 6.0

tPHZ Output Disable 1.7 3.5 5.6 1.2 7.6 1.7 5.6 ns

tPLZ Time 1.7 3.3 5.6 1.0 7.9 1.7 5.6

TA−40°C to +85°CT

A = −40°C to +85°CT

A = −40°C to +85°C

VCC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V

Symbol Parameter CL = 50 pF CL = 250 pF CL = 250 pF Units

8 Outputs Switching 1 Output Switching 8 Outputs Switching

(Note 8) (Note 9) (Note 10)

Min Typ Max Min Max Min Max

fTOGGLE Max Toggle Frequency 100 MHz

tPLH Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.5 ns

tPHL Data to Outputs 1.5 5.0 1.5 6.0 2.5 8.5

tPZH Output Enable Time 1.5 6.5 2.5 7.5 2.5 10.0 ns

tPZL 1.5 6.5 2.5 7.5 2.5 12.0

tPHZ Output Disable Time 1.0 5.6 (Note 11) (Note 11) ns

tPLZ 1.0 5.6

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74ABT244

Skew

Note 12: Skew is de fined as the ab solute va lue of the difference betwe en the a ctual prop agation delays for any t wo separ ate out puts of the same device.

The specific at ion applie s to any outputs s w it ch ing HIGH-t o-LOW (t OSHL), LOW-to-HIGH (tOSLH), or any combinat ion s witching LOW -to-HIGH and/o r

HIGH -t o-LOW (tOST). The specification is guaranteed but not tested.

Note 13: Propag at ion delay varia ti on f or a given set of c onditio ns (i. e. , t em perature and VCC) from device to device. This specification is guaranteed but not

tested.

Note 14: This spec if ic at ion is gua ranteed but not tested. The limits appl y to propagation delays for all paths de s c ribed swit c hing in phase

(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)

Note 15: T hese spec ifications g uaranteed but not tested. Th e limits re present pro pagation delays wit h 250 pF load capa citors in p lace of the 50 pF load

capacitors in the standard AC load.

Not e 16: This de sc ribes the differe nce be tween th e d elay of the LOW-to -HI GH and the HIG H-to- LO W tra nsit ion o n the same p in. It is mea sure d across all

the ou tp ut s (drivers) on the sa m e c hip, the wors t (largest d elt a) number is the guaranteed speci fication. This spec if ic at ion is guar ante ed but not t es ted.

Capacitance

Note 17: COUT is mea s ured at frequency f = 1 MH z , per MIL-STD-88 3, M et hod 3012 .

TA = −40°C to +85°CT

A = −40°C to +85°C

VCC = 4.5V–5.5V VCC = 4.5V–5.5V

Symbol Parameter CL = 50 pF CL = 250 pF Units

8 Outputs Switching 8 Outputs Switching

(Note 14) (Note 15)

Max Max

tOSHL Pin to Pin Skew 0.8 1.8 ns

(Note 12) HL Transitions

tOSLH Pin to Pin Skew 0.8 1.8 ns

(Note 12) LH Transitions

tPS Duty Cycle 1.0 2.5 ns

(Note 16) LH–HL Skew

tOST Pin to Pin Skew 1.0 2.5 ns

(Note 12) LH/HL Transitions

tPV Device to Device Skew 1.5 3.0 ns

(Note 13) LH/HL Transitions

Symbol Parameter Typ Units Conditions

TA = 25°C

CIN Input Capacitance 5.0 pF VCC = 0V

COUT (Note 17) Output Capacitance 9.0 pF VCC = 5.0V

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74ABT244

AC Loading

*Includes jig and probe capacitance FIGURE 1. Standard AC Test Load

AC Waveforms

FIGURE 2. Test Input Signal Levels

FIGURE 3. Test Input Signal Requirements

FIGURE 4. Propa gation Delay,

Pulse Width Waveforms

FIGURE 5. 3-STATE Output HIGH

and LOW Enable and Disable Times

FIGURE 6. Propagation Delay Waveforms for

Inverting and Non-Inverting Functions

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

Amplitude Rep. Rate tWtrtf

3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

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74ABT244

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integr ated Cir cuit (SOIC ), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74ABT244

Physical Dimensions in ches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74ABT244

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Packag e Num b er MSA2 0

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74ABT244

Physical Dimensions in ches (millimeters) unless otherwise noted (Continued)

20-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC20

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74ABT244 Octal Buffer/Line Driver with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syste ms are devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a lif e supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.