MR256A08B FEATURES * * * * * * * * 32K x 8 MRAM 3.3 Volt power supply Fast 35 ns read/write cycle SRAM compatible timing Native non-volatility Unlimited read & write endurance Data always non-volatile for >20-years at temperature Commercial and industrial temperatures RoHS-Compliant TSOP2, BGA and SOIC packages BENEFITS * One memory replaces FLASH, SRAM, EEPROM and BBSRAM in system for simpler, more efficient design * Improves reliability by replacing battery-backed SRAM RoHS INTRODUCTION The MR256A08B is a 262,144-bit magnetoresistive random access memory (MRAM) device organized as 32,768 words of 8 bits. The MR256A08B offers SRAM compatible 35ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR256A08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR256A08B is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type-2 package, an 8 mm x 8 mm, 48-pin ball grid array (BGA) package or a 32-lead SOIC package. All package footprints are compatible with similar low-power SRAM products and other non-volatile RAM products. The MR256A08B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 C) and industrial temperature (-40 to +85 C) range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 11 5. MECHANICAL DRAWING.......................................................................... 12 6. REVISION HISTORY...................................................................................... 15 How to Reach Us.......................................................................................... 15 Everspin Technologies (c) 2011 1 MR256A08B Rev 4, 12/2011 MR256A08B 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT ENABLE BUFFER G A[14:0] 15 OUTPUT ENABLE 7 ADDRESS BUFFER 8 ROW DECODER COLUMN DECODER CHIP ENABLE BUFFER E 8 8 OUTPUT BUFFER 8 32K x 8 BIT MEMORY ARRAY WRITE ENABLE BUFFER W SENSE AMPS 8 FINAL WRITE DRIVERS 8 WRITE DRIVER 8 DQ[7:0] WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection - Pin 2, 40, 41,43 (TSOPII); Ball D3, G2, H1, H6, (BGA) Reserved For Future Expansion Everspin Technologies (c) 2011 2 MR256A08B Rev 4, 12/2011 MR256A08B DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View) DC NC A A A A A E VDD VSS W A A A A A DC DC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DC 1 32 VDD A14 2 31 NC A12 3 30 W A7 4 29 A13 A6 5 28 A8 A5 6 27 A9 A4 7 26 A11 VSS A3 8 25 G VDD NC 9 24 NC A2 10 23 A10 A1 11 22 E DC NC DC NC NC A 14 A13 G DC VSS VDD A A A DC DC A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3 44 Pin TSOP2 1 2 3 4 5 6 DC G A A A DC A NC DC A A E DC B DQ NC A A NC DQ C VSS DQ NC A DQ VDD D VDD DQ DC A 14 DQ VSS E DQ3 NC VSS A13 NC DQ F NC NC A VDD W NC G NC A A A A NC H 32 Pin SOIC 48 Pin FBGA Table 1.2 Operating Modes 1 E1 G1 W1 Mode VDD Current DQ[7:0]2 H X X Not selected ISB1, ISB2 Hi-Z L H H Output disabled IDDR Hi-Z L L H Byte Read IDDR DOut L X L Byte Write IDDW Din H = high, L = low, X = don't care Hi-Z = high impedance 2 Everspin Technologies (c) 2009-2010 3 MR256A08B Rev 4, 12/2011 MR256A08B 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Table 2.1 Absolute Maximum Ratings1 Parameter Symbol Value Unit Supply voltage2 VDD -0.5 to 4.0 V Voltage on an pin2 VIN -0.5 to VDD + 0.5 V Output current per pin IOUT 20 mA Package power dissipation 3 PD 0.600 W Temperature under bias MR256A08B (Commercial) MR256A08BC (Industrial) TBIAS -10 to 85 -45 to 95 C Storage Temperature Tstg -55 to 150 C Lead temperature during solder (3 minute max) TLead 260 C Maximum magnetic field during write MR256A08B (All Temperatures) Hmax_write 2000 A/m Maximum magnetic field during read or standby Hmax_read 8000 A/m 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. 3 Power dissipation capability depends on package characteristics and use environment. Everspin Technologies (c) 2011 4 MR256A08B Rev 4, 12/2011 MR256A08B Electrical Specifications Table 2.2 Operating Conditions 1 2 3 Parameter Symbol Min Typical Max Unit Power supply voltage VDD 3.0 1 3.3 3.6 V Write inhibit voltage VWI 2.5 2.7 3.0 1 V Input high voltage VIH 2.2 - VDD + 0.3 2 V Input low voltage VIL -0.5 3 - 0.8 V Temperature under bias MR256A08B (Commercial) MR256A08BC (Industrial) TA 0 -40 70 85 C There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width 10 ns) for I 20.0 mA. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width 10 ns) for I 20.0 mA. Power Up and Power Down Sequencing The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 2.1 Power Up and Power Down Diagram VWIDD VDD STARTUP 2 ms READ/WRITE INHIBITED BROWNOUT or POWER LOSS NORMAL OPERATION READ/WRITE INHIBITED 2 ms RECOVER NORMAL OPERATION VIH VIH E W Everspin Technologies (c) 2011 5 MR256A08B Rev 4, 12/2011 MR256A08B Electrical Specifications Table 2.3 DC Characteristics Parameter Symbol Min Typical Max Unit Input leakage current Ilkg(I) - - 1 A Output leakage current Ilkg(O) - - 1 A Output low voltage (IOL = +4 mA) (IOL = +100 A) VOL - - 0.4 VSS + 0.2 V Output high voltage (IOL = -4 mA) (IOL = -100 A) VOH 2.4 VDD - 0.2 - - V Table 2.4 Power Supply Characteristics Parameter Symbol Typical Max Unit AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) IDDR 25 30 mA IDDW 55 65 mA AC standby current (VDD= max, E = VIH) no other restrictions on other inputs ISB1 6 7 mA CMOS standby current (E VDD - 0.2 V and VIn VSS + 0.2 V or VDD - 0.2 V) (VDD = max, f = 0 MHz) ISB2 5 6 mA AC active supply current - write modes1 (VDD= max) 1 All active current measurements are measured with one address transition per cycle and at minimum cycle time. Everspin Technologies (c) 2011 6 MR256A08B Rev 4, 12/2011 MR256A08B 3. TIMING SPECIFICATIONS Table 3.1 Capacitance1 1 Parameter Symbol Typical Max Unit Address input capacitance CIn - 6 pF Control input capacitance CIn - 6 pF Input/Output capacitance CI/O - 8 pF Parameter Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3.1 Output load for all other timing parameters See Figure 3.2 f = 1.0 MHz, dV = 3.0 V, TA = 25 C, periodically sampled rather than 100% tested. Table 3.2 AC Measurement Conditions Figure 3.1 Output Load Test Low and High ZD= 50 Output RL = 50 VL = 1.5 V Figure 3.2 Output Load Test All Others 3.3 V 590 Output 5 pF 435 Everspin Technologies (c) 2011 7 MR256A08B Rev 4, 12/2011 MR256A08B Timing Specifications Read Mode Table 3.3 Read Cycle Timing1 Parameter Symbol Min Max Unit Read cycle time tAVAV 35 - ns Address access time tAVQV - 35 ns Enable access time2 tELQV - 35 ns Output enable access time tGLQV - 15 ns Output hold from address change tAXQX 3 - ns Enable low to output active tELQX 3 - ns Output enable low to output active3 tGLQX 0 - ns Enable high to output Hi-Z tEHQZ 0 15 ns tGHQZ 0 10 ns 3 3 Output enable high to output Hi-Z3 1 2 3 W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. Figure 3.3A Read Cycle 1 t AVAV A (ADDRESS) t AXQX Q (DATA OUT) Previous Data Valid Data Valid t AVQV Figure 3.3B Read Cycle 2 t AVAV A (ADDRESS) t AVQV E (CHIP ENABLE) t ELQV t EHQZ t ELQX G (OUTPUT ENABLE) Q (DATA OUT) Everspin Technologies (c) 2011 t GHQZ t GLQV t GLQX Data Valid 8 MR256A08B Rev 4, 12/2011 MR256A08B Timing Specifications Table 3.4 Write Cycle Timing 1 (W Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 18 - ns Address valid to end of write (G low) tAVWH 20 - ns 15 - ns 15 - ns tWLWH tWLEH tWLWH tWLEH Write pulse width (G high) Write pulse width (G low) Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns tWLQZ 0 12 ns tWHQX 3 - ns tWHAX 12 - ns Write low to data Hi-Z3 Write high to output active 3 Write recovery time 1 2 3 All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given voltage or temperature, tWLQZ(max) < tWHQX(min) Figure 3.4 Write Cycle Timing 1 (W Controlled) t AVAV A (ADDRESS) t WHAX t AVWH E (CHIP ENABLE) t WLEH t WLWH W (WRITE ENABLE) t AVWL t DVWH D (DATA IN) t WHDX Data Valid t WLQZ Q (DATA OUT) Hi-Z Hi-Z t WHQX Everspin Technologies (c) 2011 9 MR256A08B Rev 4, 12/2011 MR256A08B Timing Specifications Table 3.5 Write Cycle Timing 2 (E Controlled)1 1 2 3 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 18 - ns Address valid to end of write (G low) tAVEH 20 - ns Enable to end of write (G high) tELEH tELWH 15 - ns Enable to end of write (G low)3 tELEH tELWH 15 - ns Data valid to end of write tDVEH 10 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 3.5 Write Cycle Timing 2 (E Controlled) t AVAV A (ADDRESS) t EHAX t AVEH t ELEH E (CHIP ENABLE) t AVEL t ELWH W (WRITE ENABLE) t DVEH D (DATA IN) Data Valid Hi-Z Q (DATA OUT) Everspin Technologies (c) 2011 t EHDX 10 MR256A08B Rev 4, 12/2011 MR256A08B 4. ORDERING INFORMATION Figure 4.1 Part Numbering System MR 256 A 08 B C YS 35 R Carrier Blank = Tray, R = Tape & Reel Speed 35 ns Package YS = TSOP2, SO = SOIC, MA = FBGA Temperature Range Blank = Commercial 0 to + 70 C, C = Industrial -40 to + 85 C Revision Data Width 08 = 8-Bit Type A = Asynchronous Density 256 = 256 Kb Magnetoresistive RAM MR Table 4.1 Available Parts Part Number Description Package Ship Pack Temp Rating MR256A08BYS35 MR256A08BCYS35 MR256A08BYS35R MR256A08BCYS35R MR256A08BMA35 MR256A08BCMA35 MR256A08BMA35R MR256A08BCMA35R MR256A08BSO35 MR256A08BCSO35 1 3.3 V 32Kx8 MRAM Commercial 3.3 V 32Kx8 MRAM Industrial 3.3 V 32Kx8 MRAM Commercial 3.3 V 32Kx8 MRAM Industrial 3.3 V 32Kx8 MRAM Commercial 3.3 V 32Kx8 MRAM Industrial 3.3 V 32Kx8 MRAM Commercial 3.3 V 32Kx8 MRAM Industrial 3.3 V 32Kx8 MRAM Commercial 3.3 V 32Kx8 MRAM Industrial 44-TSOP 44-TSOP 44-TSOP 44-TSOP 48-BGA 48-BGA 48-BGA 48-BGA 32-SOIC 32-SOIC Tray Tray Tape and Reel Tape and Reel Tray Tray Tape and Reel Tape and Reel Tray Tray 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C 0 to +70 C -40 to +85 C Preliminary Product: This product is classified as Preliminary until the completion of all qualification tests. The specifications in this data sheet are intended to be final but are subject to change. Please check the Everspin web site www.everspin.com for the latest information on product status. 1 Everspin Technologies (c) 2011 11 MR256A08B Rev 4, 12/2011 MR256A08B 5. MECHANICAL DRAWING Figure 5.1 TSOP2 1. 2. 3. 4. Print Version Not To Scale Dimensions and tolerances per ASME Y14.5M - 1994. Dimensions in Millimeters. Dimensions do not include mold protrusion. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58. Everspin Technologies (c) 2011 12 MR256A08B Rev 4, 12/2011 MR256A08B Mechanical Drawings Figure 5.2 FBGA TOP VIEW 0.41 0.31 SIDE VIEW BOTTOM VIEW 1. 2. 3. 4. 5. 0.32 0.22 Print Version Not To Scale Dimensions in Millimeters. Dimensions and tolerances per ASME Y14.5M - 1994. Maximum solder ball diameter measured parallel to DATUM A DATUM A, the seating plane is determined by the spherical crowns of the solder balls. Parallelism measurement shall exclude any effect of mark on top surface of package. Everspin Technologies (c) 2011 13 MR256A08B Rev 4, 12/2011 MR256A08B Mechanical Drawings Figure 5.3 SOIC PIN 1 ID 32 17 J Reference JEDEC MO-119 K 1 16 A I G D B Unit mm - Min - Max inch - Min - Max E C A 20.574 20.878 0.810 0.822 B 1.00 1.50 0.04 0.06 C 0.355 0.508 0.14 0.02 Everspin Technologies (c) 2011 D 0.66 0.81 0.026 0.032 E 0.101 0.254 0.004 0.010 14 H F F 2.286 2.540 0.09 0.10 G Radius 0.101 Radius 0.0040 H 0.533 1.041 0.021 0.041 I 0.152 0.304 0.006 0.012 J 7.416 7.594 0.292 0.299 K 10.287 10.642 0.405 0.419 MR256A08B Rev 4, 12/2011 MR256A08B 6. REVISION HISTORY Revision Date Description of Change 0 1 Sept 12, 2008 Mar 25, 2009 August 16, 2011 Initial Advance Information Release Add Industrial and Automotive Temperature Options Removed Automotive temperature options. Included SOIC package. Revised formatting Changed TSOP-II to TSOP2. Changed logo to new EST Logo. Revisions to Available Parts, Table 4.1: Added Industrial Temp Grade option in SOIC package. Deleted Tape & Reel pack option for all SOIC packaged parts. 2 3 October 28, 2011 4 Dec 16, 2011 Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing revised for package ball size. How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA/Asia/Pacific Everspin Technologies 1347 N. Alma School Road, Suite 220 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa support.europe@everspin.com Asia Pacific support.asia@everspin.com Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters, which may be provided in Everspin Technologies data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including "Typicals" must be validated for each customer application by customer's technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. EverspinTM and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. (c)Everspin Technologies, Inc. 2011 Japan support.japan@everspin.com File Name: MR256A08B_Datasheet_EST355_Rev4.pdf Everspin Technologies (c) 2011 15 MR256A08B Rev 4, 12/2011