LP3907TL-JSXS/NOPB - Texas Instruments

LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

LP3907 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I2C-

Compatible Interface

Check for Samples: LP3907

1FEATURES KEY SPECIFICATIONS

2• Compatible with Advanced Applications • Step-Down DC/DC Converter (Buck)

Processors and FPGAs – Programmable VOUT from:

• 2 LDOs for Powering Internal Processor – Buck1 : 0.8V - 2.0V @ 1A

Functions and I/Os – Buck2 : 1.0V - 3.5V @ 600mA

• High-Speed Serial Interface for Independent – Up to 96% Efficiency

Control of Device Functions and Settings – 2.1MHz PWM Switching Frequency

• Precision Internal Reference – PWM - PFM Automatic Mode Change

• Thermal Overload Protection Under Low Loads

• Current Overload Protection – ±3% Output Voltage Accuracy

• 24-Lead 4 × 4 × 0.8mm WQFN or 25-Bump 2.5 – Automatic Soft Start

x 2.5mm DSBGA Package • Linear Regulators (LDO)

• Software Programmable Regulators – Programmable VOUT of 1.0V–3.5V

• External Power-On-Reset Function for Buck1 (except “JJ11” and “FX6W” options)

and Buck2 (i.e., Power Good with Delay – ±3% Output Voltage Accuracy

Function) – 300mA Output Current

• Undervoltage Lock Out Detector to Monitor – 30mV (Typ) Dropout

Input Supply Voltage

• LP3907-Q1 is an Automotive Grade Product DESCRIPTION

that is AECQ-100 Grade 1 Qualified The LP3907 is a multi-function, programmable Power

Management Unit, optimized for low power FPGAs,

APPLICATIONS microprocessors and DSPs. This device integrates

• FPGA, DSP Core Power two highly efficient 1A/600mA step-down DC/DC

converters with dynamic voltage management (DVM),

• Applications Processors two 300mA linear regulators and a 400kHz I2C

• Peripheral I/O Power compatible interface to allow a host controller access

to the internal control registers of the LP3907. The

LP3907 additionally features programmable power-on

sequencing. Package options include a tiny 4 x 4 x

0.8mm WQFN 24-pin package and an even smaller

2.5 x 2.5mm DSBGA 25-bump package.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP3907

VINLDO1

SDA

GND_L

LDO1

ENLDO1

SCL

VIN1

LDO2

SW2

FB2

VIN2

GND_SW2

ENSW1

ENSW2

VINLDO2

EN_T

ENLDO2

GND_C AVDD

VINLDO12

DAP

0.47 PF

1 PF

0.47 PF 2.2 PH

10 PF

1 PF

10 PF

GND_SW1

SW1

FB1 10 PF

2.2 PH

nPOR

VDD

100k

LP3907

SNVS511O –JUNE 2007–REVISED MAY 2013

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Typical Application Circuit

Application Circuit

Product Folder Links: LP3907

OSC

Logic Control

and

Registers

I2C

SW2

VFB2

Cvdd

4.7PF

nPOR

BUCK1

BUCK2

Lsw1

SW1

VFB1

LDO2

RESET

LDO2

GND_C

BIAS

Thermal

Shutdown

Power On

Reset

Lsw1

VINLDO1

124

1319

4 9 18

AVDD

VBUCK2

LDO1 LDO1

20 Cldo1

VinLDO12

Cldo2

Power

ON-OFF

Logic

LP3907 PMIC

VBUCK1

EN_T 2

ENLDO1 21

ENLDO2 22

ENSW 1

ENSW2 12

VINLDO2

AVDD

1 uF

VDD

RDY1 RDY2

ULVO

Vin OK

100k

10 PF

F1P

Li-ion/polymer cell 3.3V - 4.2V

DC SOURCE

4.5V - 5.5V

GND_LGND_SW2GND_SW1

I2C_SDA

I2C_SCL 1.8V

0.47 PF

3.3V

10 PF

3.3V

10 PF

1.2V

2.2 PH

10 PF

VINLDO12

VINLDO2

VINLDO1

VIN1

VIN2

LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

Application Circuit

Product Folder Links: LP3907

A B C D E

SW1

VIN

LDO12

GND_C

SCL

VIN1

VIN

LDO2

AVDD

FB2

LDO1

GND_S

FB1

EN_S

EN_T

VIN

LDO12

nPOR

EN_

LDO1

SDA

VIN2SW2

GND_

SW2

VIN

LDO1

EN_

LDO2

EN_

SW2

GND_

E D C B A

EN_

LDO2

EN_

SW2

VIN1 SW1 VIN

LDO12 VIN

LDO2

GND_S

FB1 EN_S

W1 EN_T VIN

LDO12 LDO2

AVDD GND_C nPOR EN_

LDO1

FB2 SDA SCL LDO1

VIN2 SW2 GND_

SW2 GND_

LVIN

LDO1

7 8 9 10 11 12

212019 242322

1 2 3 4 5 6

131418 17 16 15

LP3907

SNVS511O –JUNE 2007–REVISED MAY 2013

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Connection Diagrams

24-Lead WQFN Package (top view)

25-Bump Thin DSBGA Package, Large Bump

Package Number YZR0025

Figure 1. Top View Figure 2. Bottom View

Package Type Default I2C Address

24-lead WQFN 60

25-bump DSBGA 61

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SNVS511O –JUNE 2007–REVISED MAY 2013

Table 1. Pin Descriptions(1)

WQFN DSBGA pin Name I/O Type Description

Pin No. no.

1 B4, B5 VINLDO12 I PWR Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)

2 C4 EN_T I D Enable for preset power on sequence. (See POWER UP

SEQUENCING USING THE EN_T FUNCTION.)

3 C3 nPOR O D nPOR Power on reset pin for both Buck1 and Buck 2. Open drain

logic output 100K pullup resistor. nPOR is pulled to ground when

the voltages on these supplies are not good. See nPOR section

for more info.

4 C5 GND_SW1 G G Buck1 NMOS Power Ground

5 D5 SW1 O PWR Buck1 switcher output pin

6 E5 VIN1 I PWR Power in from either DC source or Battery to Buck1

7 D4 ENSW1 I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1

8 E4 FB1 I A Buck1 input feedback terminal

9 D3 GND_C G G Non switching core ground pin

10 E3 AVDD I PWR Analog Power for Buck converters

11 E2 FB2 I A Buck2 input feedback terminal

12 D2 ENSW2 I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2

13 E1 VIN2 I PWR Power in from either DC source or Battery to Buck2

14 D1 SW2 O PWR Buck2 switcher output pin

15 C1 GND_SW2 G G Buck2 NMOS Power ground

16 C2 SDA I/O D I2C Data (bidirectional)

17 B2 SCL I D I2C Clock

18 B1 GND_L G G LDO ground

19 A1 VINLDO1 I PWR Power in from either DC source or battery to input terminal to

LDO1

20 A2 LDO1 O PWR LDO1 Output

21 B3 ENLDO1 I D LDO1 enable pin, a logic HIGH enables the LDO1

22 A3 ENLDO2 I D LDO2 enable pin, a logic HIGH enables the LDO2

23 A4 LDO2 O PWR LDO2 Output

24 A5 VINLDO2 I PWR Power in from either DC source or battery to input terminal to

LDO2.

DAP DAP GND GND Connection isn't necessary for electrical performance, but it is

recommended for better thermal dissipation.

(1) A: Analog Pin D: Digital Pin G: Ground Pin PWR: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin.

Power Block Operation Note

Power Block Input Enabled Disabled

VINLDO12 VIN+(1) VIN+ Always Powered

AVDD VIN+ VIN+ Always Powered

VIN1 VIN+ VIN+ or 0V

VIN2 VIN+ VIN+ or 0V

LDO 1 ≤VIN+ ≤VIN+ If Enabled, Min Vin is 1.74V

LDO 2 ≤VIN+ ≤VIN+ If Enabled, Min Vin is 1.74V

(1) VIN+ is the largest potential voltage on the device.

Product Folder Links: LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Default Voltage Options(1)(2)

Part Number Buck1 Buck2 LDO1 LDO2

LP3907SQ-PXPP/NOPB 1.5V 3.3V 2.5V 2.5V

LP3907SQX-PXPP/NOPB 1.5V 3.3V 2.5V 2.5V

LP3907SQ-TJXIP/NOPB 1.2V 3.3V 1.8V 2.5V

LP3907SQX-TJXIP/NOPB 1.2V 3.3V 1.8V 2.5V

LP3907QSQ-JXIP/NOPB 1.2V 3.3V 1.8V 2.5V

LP3907QSQX-JXIP/NOPB 1.2V 3.3V 1.8V 2.5V

LP3907QSQ-JXI7/NOPB 1.2V 3.3V 1.8V 2.5V

LP3907QSQX-JXI7/NOPB 1.2V 3.3V 1.8V 2.5V

LP3907SQ-JXQX/NOPB 1.2V 3.3V 2.6V 3.3V

LP3907SQX-JXQX/NOPB 1.2V 3.3V 2.6V 3.3V

LP3907SQ-JYQX/NOPB 1.2V 3.4V 2.6V 3.3V

LP3907SQX-JYQX/NOPB 1.2V 3.4V 2.6V 3.3V

LP3907SQ-PJXIX/NOPB 1.2V 3.3V 1.8V 3.3V

LP3907SQX-PJXIX/NOPB 1.2V 3.3V 1.8V 3.3V

LP3907SQ-PFX6W/NOPB 1.0V 3.3V 1.8V 3.3V

LP3907SQX-PFX6W/NOPB 1.0V 3.3V 1.8V 3.3V

LP3907SQ-BJX6X/NOPB 1.2V 3.3V 2.65V(3) 3.3V

LP3907SQX-BJX6X/NOPB 1.2V 3.3V 2.65V(3) 3.3V

LP3907SQ-BJXQX/NOPB 1.2V 3.3V 2.6V 3.3V

LP3907SQX-BJXQX/NOPB 1.2V 3.3V 2.6V 3.3V

LP3907SQ-BJYQX/NOPB 1.2V 3.4V 2.6V 3.3V

LP3907SQX-BJYQX/NOPB 1.2V 3.4V 2.6V 3.3V

LP3907SQ-BJXIX/NOPB 1.2V 3.3V 1.8V 3.3V

LP3907SQX-BJXIX/NOPB 1.2V 3.3V 1.8V 3.3V

LP3907SQ-BFX6W/NOPB 1.0V 3.3V 1.8V 3.3V

LP3907SQX-BFX6W/NOPB 1.0V 3.3V 1.8V 3.3V

LP3907SQ-JJXP/NOPB 1.2V 1.8V 3.3V 2.5V

LP3907SQX-JJXP/NOPB 1.2V 1.8V 3.3V 2.5V

LP3907SQ-VRZX/NOPB 1.8V 2.7V 3.5V 3.3V

LP3907SQX-VRZX/NOPB 1.8V 2.7V 3.5V 3.3V

LP3907TL-JJ11/NOPB 1.2V 1.8V 2.85V(3) 2.85V(3)

LP3907TLX-JJ11/NOPB 1.2V 1.8V 2.85V(3) 2.85V(3)

LP3907TL-JSXS/NOPB 1.2V 2.8V 3.3V 2.8V

LP3907TLX-JSXS/NOPB 1.2V 2.8V 3.3V 2.8V

LP3907TL-JJCP/NOPB 1.2V 1.8V 1.2V 2.5V

LP3907TLX-JJCP/NOPB 1.2V 1.8V 1.2V 2.5V

LP390QTL-VXSS/NOPB 1.8V 3.3V 2.8V 2.8V

LP3907QTLX-VXSS/NOPB 1.8V 3.3V 2.8V 2.8V

LP3907TL-PLNTO/NOPB 1.3V 2.2V 2.9V 2.4V

LP3907TLX-PLNTO/NOPB 1.3V 2.2V 2.9V 2.4V

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Voltage is fixed and not programmable.

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SNVS511O –JUNE 2007–REVISED MAY 2013

Absolute Maximum Ratings(1)(2)

VIN, SDA, SCL −0.3V to +6V

GND to GND SLUG ±0.3V

Power Dissipation (PD_MAX)

(TA=85°C, TMAX=125°C, )(3) 1.43W

Junction Temperature (TJ-MAX) 150°C

Storage Temperature Range −65°C to +150°C

Maximum Lead Temperature (Soldering) 260°C

ESD Ratings

Human Body Model

(4) 2kV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP −(θJA × PD-MAX). See Application Notes.

(4) The Human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin. (MILSTD - 883 3015.7)

Operating Ratings: Bucks(1)(2)(3)(4)

VIN 2.8V to 5.5V

VEN 0 to (VIN + 0.3V)

Junction Temperature (TJ) Range −40°C to +125°C

Ambient Temperature (TA) Range (5) −40°C to +85°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(4) Buck VIN ≥VOUT + 1V.

(5) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

Thermal Properties(1)(2)(3)

Junction-to-Ambient Thermal Resistance (θJA) RTW0024A 28°C/W

Junction-to-Ambient Thermal Resistance (θJA) YZR0025 51°C/W

(1) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 160°C (typ.) and

disengages at TJ= 140°C (typ.)

(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP −(θJA × PD-MAX). See Application Notes.

(3) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

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SNVS511O –JUNE 2007–REVISED MAY 2013

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General Electrical Characteristics(1)(2)(3)(4)(5)

Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C.

Symbol Parameter Conditions Min Typ Max Units

IQVINLDO12 Shutdown Current VIN = 3.6V 3 µA

VPOR Power-On Reset Threshold VDD Falling Edge(5) 1.9 V

TSD Thermal Shutdown Threshold 160 °C

TSDH Themal Shutdown Hysteresis 20 °C

UVLO Under Voltage Lock Out Rising 2.9 V

Falling 2.7

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics.

(2) All voltages are with respect to the potential at the GND pin.

(3) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(4) This specification is ensured by design.

(5) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the

regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range.

I2C Compatible Interface Electrical Specifications (1)

Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing

in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C

Symbol Parameter Conditions Min Typ Max Units

FCLK Clock Frequency 400 kHz

tBF Bus-Free Time Between Start and Stop (1) 1.3 µs

tHOLD Hold Time Repeated Start Condition (1) 0.6 µs

tCLKLP CLK Low Period (1) 1.3 µs

tCLKHP CLK High Period (1) 0.6 µs

tSU Set Up Time Repeated Start Condition (1) 0.6 µs

tDATAHLD Data Hold time (1) 0 µs

tDATASU Data Set Up Time (1) 100 ns

TSU Set Up Time for Start Condition (1) 0.6 µs

TTRANS Maximum Pulse Width of Spikes that (1)

Must be Suppressed by the Input Filter of 50 ns

Both DATA & CLK Signals.

(1) This specification is ensured by design.

Low Drop Out Regulators, LDO1 and LDO2

Unless otherwise noted, VIN = 3.6V, CIN = 1.0µF, COUT = 0.47µF. Typical values and limits appearing in normal type apply for

TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to

+125°C. (1)(2)(3)(4)(5)(6)(7)

Symbol Parameter Conditions Min Typ Max Units

VIN Operational Voltage Range VINLDO1 and VINLDO2 PMOS 1.74 5.5 V

pins (8)

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100mV below its nominal

value.

(6) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(7) VIN minimum for line regulation values is 1.8V.

(8) Pins 24, 19 can operate from VIN min of 1.74 to a VIN max of 5.5V. This rating is only for the series pass PMOS power FET. It allows the

system design to use a lower voltage rating if the input voltage comes from a buck output.

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SNVS511O –JUNE 2007–REVISED MAY 2013

Low Drop Out Regulators, LDO1 and LDO2 (continued)

Unless otherwise noted, VIN = 3.6V, CIN = 1.0µF, COUT = 0.47µF. Typical values and limits appearing in normal type apply for

TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to

+125°C. (1)(2)(3)(4)(5)(6)(7)

Symbol Parameter Conditions Min Typ Max Units

VOUT Accuracy Output Voltage Accuracy (Default VOUT) Load current = 1 mA −3 3 %

ΔVOUT Line Regulation VIN = (VOUT + 0.3V) to 5.0V, 0.15 %/V

(7), Load Current = mA

Load Regulation VIN = 3.6V, 0.011 %/mA

Load Current = 1mA to IMAX

ISC Short Circuit Current Limit LDO1-2, VOUT = 0V 500 mA

VIN – VOUT Dropout Voltage Load Current = 50mA 30 200 mV

(5)

PSRR Power Supply Ripple Rejection F = 10kHz, Load Current = IMAX 45 dB

θn Supply Output Noise 10Hz < F < 100KHz 80 µVrms

IQ(6) (9) Quiescent Current “On” IOUT = 0mA 40 µA

Quiescent Current “On” IOUT = IMAX 60 µA

Quiescent Current “Off” EN is de-asserted(10) 0.03 µA

TON Turn On Time Start up from shut-down 300 µs

COUT Output Capacitor Capacitance for stability 0°C ≤TJ0.33 0.47 µF

≤125°C

−40°C ≤TJ≤125°C 0.68 1.0 µF

ESR 5 500 mΩ

(9) The IQcan be defined as the standing current of the LP3907 when the I2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3907 is powered using a battery.

(10) The IQexhibits a higher current draw when the EN pin is de-asserted because the I22 buffer pins draw an additional 2µA.

Buck Converters SW1, SW2

Unless otherwise noted, VIN = 3.6V, CIN = 10µF, COUT = 10µF, LOUT = 2.2µH ceramic. Typical values and limits appearing in

normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for

operation, −40°C to +125°C. (1)(2)(3)(4)(5)(6)

Symbol Parameter Conditions Min Typ Max Units

VFB Feedback Voltage −3 +3 %

VOUT Line Regulation 2.8< VIN < 5.5 0.089 %/V

IO=10mA

Load Regulation 100mA < IO< IMAX 0.0013 %/mA

Eff Efficiency Load Current = 250mA 96 %

ISHDN Shutdown Supply Current EN is de-asserted 0.01 µA

fOSC Internal Oscillator Frequency 1.7 2.1 MHz

IPEAK Buck1 Peak Switching Current Limit 1.5 A

Buck2 Peak Switching Current Limit 1.0

IQ(7) Quiescent Current “On” No load PFM Mode 33 µA

RDSON (P) Pin-Pin Resistance PFET 200 mΩ

RDSON (N) Pin-Pin Resistance NFET 180 mΩ

(1) All voltages are with respect to the potential at the GND pin.

(2) Min and Max limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely

norm.

(3) CIN, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) The device maintains a stable, regulated output voltage without a load.

(5) Quiescent current is defined here as the difference in current between the input voltage source and the load at VOUT.

(6) Buck VIN ≥VOUT + 1V.

(7) The IQcan be defined as the standing current of the LP3907 when the I2C bus is active and all other power blocks have been disabled

via the I2C bus, or it can be defined as the I2C bus active, and the other power blocks are active under no load condition. These two

values can be used by the system designer when the LP3907 is powered using a battery.

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SNVS511O –JUNE 2007–REVISED MAY 2013

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Buck Converters SW1, SW2 (continued)

Unless otherwise noted, VIN = 3.6V, CIN = 10µF, COUT = 10µF, LOUT = 2.2µH ceramic. Typical values and limits appearing in

normal type apply for TJ= 25°C. Limits appearing in boldface type apply over the entire junction temperature range for

operation, −40°C to +125°C. (1)(2)(3)(4)(5)(6)

Symbol Parameter Conditions Min Typ Max Units

TON Turn On Time Start up from shut-down 500 µs

CIN Input Capacitor Capacitance for stability 10 µF

COOutput Capacitor Capacitance for stability 10 µF

I/O Electrical Characteristics

Unless otherwise noted: Typical values and limits appearing in normal type apply for TJ= 25°C. Limits appearing in boldface

type apply over the entire junction temperature range for operation, TJ=−40°C to +125°C. (1)

Limit

Symbol Parameter Conditions Units

Min Max

VIL Input Low Level 0.4 V

VIH Input High Level 1.2 V

(1) This specification is ensured by design.

Power On Reset Threshold/Function (POR)

Symbol Parameter Conditions Min Typ Max Units

nPOR nPOR = Power on reset forBuck1 and Default 50 ms

Buck2

nPOR Percentage of Target voltage Buck1 or VBUCK1 AND VBUCK2 rising 94 %

threshold Buck2 VBUCK1 OR VBUCK2 falling 85

VOL Output Level Low Load = IoL = 500mA 0.23 0.5 V

Product Folder Links: LP3907

TEMPERATURE (°C)

VOUT CHANGE (%)

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

TEMPERATURE (°C)

VOUT CHANGE (%)

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS — LDO

TA= 25°C unless otherwise noted

Output Voltage Change Output Voltage Change

vs vs

Temperature (LDO1) Temperature (LDO2)

VIN = 3.6V, VOUT = 2.6V, 100mA load VIN = 3.6V, VOUT = 3.3V, 100mA load

Figure 3. Figure 4.

Load Transient (LDO1) Load Transient (LDO2)

3.6 VIN, 2.6VOUT, 0 – 150mA load 3.6 VIN, 3.3 VOUT, 0 – 150mA load

Figure 5. Figure 6.

Line Transient (LDO1) Line Transient (LDO2)

3.6 - 4.2 VIN, 2.6 VOUT, 300mA load 3.6 – 4.2 VIN, 3.3VOUT, 300mA load

Figure 7. Figure 8.

Product Folder Links: LP3907

VOUT (V)

MAXIMUM LOAD (mA)

300

250

200

150

100

1.00 1.10 1.20 1.30 1.40 1.50 1.60

VIN = 1.74V

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TYPICAL PERFORMANCE CHARACTERISTICS — LDO (continued)

TA= 25°C unless otherwise noted

Enable Start-up time (LDO1) ) Enable Start-up time (LDO2)

0-3.6 VIN, 2.6 VOUT, 1mA load 0 – 3.6 VIN, 3.3 VOUT, 1 mA load

Figure 9. Figure 10.

LDO Maximum Load

VIN = 1.74V

Figure 11.

Product Folder Links: LP3907

SUPPLY VOLTAGE (V)

VOUT (V)

1.85

1.83

1.81

1.79

1.77

1.75

2.7 3.3 3.8 4.4 4.9

IOUT = 20 mA

IOUT = 750 mA

IOUT = 1.0A

SUPPLY VOLTAGE (V)

VOUT (V)

3.35

3.33

3.31

3.29

3.27

3.25

4.0 4.5 5.0 5.5

IOUT = 20 mA

IOUT = 300 mA

IOUT = 600 mA

TEMPERATURE (°C)

SHUTDOWN CURRENT (éA)

0.15

0.12

0.09

0.06

0.03

0.00

-40 -20 0 20 40 60 80

VIN = 2.7V

VIN = 3.6V

VIN = 5.5V

SUPPLY VOLTAGE (V)

VOUT (V)

1.05

1.03

1.01

0.99

0.97

0.95

2.5 3.0 3.5 4.0 4.5 5.0 5.5

IOUT = 20 mA

IOUT = 750 mA

IOUT = 1.0A

LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS — BUCKS

VIN= 2.8V to 5.5V, TA= 25°C

Output Voltage

Shutdown Current vs.

vs. Supply Voltage

Temp (VOUT = 1.0V)

Figure 12. Figure 13.

Output Voltage Output Voltage

vs. vs.

Supply Voltage Supply Voltage

(VOUT = 1.8V) (VOUT = 3.5V)

Figure 14. Figure 15.

Product Folder Links: LP3907

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 2.8V

VIN = 3.6V

VIN = 5.5V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 2.8V

VIN = 3.6V

VIN = 5.5V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 2.8V

VIN = 3.6V

VIN = 5.5V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 2.8V

VIN = 3.6V

VIN = 5.5V

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SNVS511O –JUNE 2007–REVISED MAY 2013

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCK1

VIN= 2.8V to 5.5V, TA= 25°C, VOUT = 1.2V, 2.0V

Efficiency Efficiency

vs vs

Output Current Output Current

(VOUT =1.2V, L= 2.2µH —(Forced PWM mode) (VOUT =2.0V, L= 2.2µH — Forced PWM mode)

Figure 16. Figure 17.

Efficiency Efficiency

vs vs

Output Current Output Current

(VOUT =1.2V, L= 2.2µH — PWM mode to PFM mode) (VOUT =2.0V, L= 2.2µH — PWM mode to PFM mode)

Figure 18. Figure 19.

Product Folder Links: LP3907

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 4.5V

VIN = 5.5V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 4.5V

VIN = 5.5V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 4.5V

VIN = 5.5V

OUTPUT CURRENT (mA)

EFFICIENCY (%)

100

0.1 1 10 100 1000

VIN = 4.5V

VIN = 5.5V

LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS — BUCK2

VIN= 4.5V to 5.5V, TA= 25°C, VOUT = 1.8V, 3.3V

Efficiency Efficiency

vs vs

Output Current Output Current

( VOUT =1.8V, L= 2.2µH —Forced PWM mode) (VOUT =3.3V, L= 2.2µH — Forced PWM mode)

Figure 20. Figure 21.

TYPICAL PERFORMANCE CHARACTERISTICS — BUCK2

VIN= 4.3V to 5.5V, TA= 25°C, VOUT = 1.8V, 3.3V

Efficiency Efficiency

vs vs

Output Current Output Current

(VOUT =1.2V, L= 2.2µH — PWM mode to PFM mode) (VOUT =2.0V, L= 2.2µH — PWM mode to PFM mode)

Figure 22. Figure 23.

Product Folder Links: LP3907

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TYPICAL PERFORMANCE CHARACTERISTICS — BUCKS

VIN= 3.6V, TA= 25°C, VOUT = 1.2V unless otherwise noted

Load Transient Response Mode Change by Load Transient

VOUT = 1.2V, ILOAD = 300–500mA (PWM Mode) VOUT = 1.2V, ILOAD = 50–150mA (PFM to PWM Mode)

Figure 24. Figure 25.

Line Transient Response Line Transient Response

VIN = 3.6 – 4.2V, VOUT = 1.2V, 250mA load VIN = 3.6 – 4.2V, VOUT = 3.3V, 250 mA load

Figure 26. Figure 27.

Start up into PWM Mode Start up into PWM Mode

VOUT = 1.2V, 1.0A load VOUT = 3.3 V, 600mA load

Figure 28. Figure 29.

Product Folder Links: LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

TYPICAL PERFORMANCE CHARACTERISTICS — BUCKS (continued)

VIN= 3.6V, TA= 25°C, VOUT = 1.2V unless otherwise noted

Start up into PFM Mode Start up into PFM Mode

VOUT = 1.2V, 30mA load VOUT = 3.3V, 30mA load

Figure 30. Figure 31.

Product Folder Links: LP3907

VIN

ENLDO

VLDO

GND

Vref

LDO

controlled

LP3907

SNVS511O –JUNE 2007–REVISED MAY 2013

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DC/DC CONVERTERS

OVERVIEW

The LP3907 supplies the various power needs of the application by means of two Linear Low Drop Regulators

(LDO1 and LDO2) and two Buck converters (SW1 and SW2). The following table lists the output characteristics

of the various regulators.

Table 2. Supply Specification

Output

Supply Load IMAX

VOUT Range(V) Resolution (mV) Maximum Output Current (mA)

LDO1 analog 1.0 to 3.5 100 300

LDO2 analog 1.0 to 3.5 100 300

SW1 digital 0.8 to 2.0 50 1000

SW2 digital 1.0 to 3.5 100 600

LINEAR LOW DROPOUT REGULATORS (LDOS)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control

programmed during Final Test, which can be tailored to the specific needs of the system designer.

NO-LOAD STABILITY

The LDOs will remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example, CMOS RAM keep-alive applications.

LDO1 AND LDO2 CONTROL REGISTERS

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is

programmable in steps of 100mV from 1.0V to 3.5V by programming bits D4-0 in the LDO Control registers. Both

LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control is

also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in the

SW1, SW2: Synchronous Step-Down Magnetic DC/DC Converters

FUNCTIONAL DESCRIPTION

The LP3907 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that deliver

a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode

architecture with synchronous rectification, both bucks have the ability to deliver up to 1000mA and 600mA,

respectively, depending on the input voltage and output voltage (voltage head room), and the inductor chosen

(maximum current capability).

Product Folder Links: LP3907

-VOUT

VIN - VOUT

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There are three modes of operation depending on the current required - PWM, PFM, and shutdown. PWM mode

handles current loads of approximately 70mA or higher, delivering voltage precision of ±3% with 90% efficiency

or better. Lighter output current loads cause the device to automatically switch into PFM for reduced current

consumption (IQ= 15µA typ.) and a longer battery life. The Standby operating mode turns off the device, offering

the lowest current consumption. PWM or PFM mode is selected automatically or PWM mode can be forced

through the setting of the buck control register.

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low drop out control of

the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

Additional features include soft-start, under-voltage lock-out, current overload protection, and thermal overload

protection.

CIRCUIT OPERATION DESCRIPTION

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous

rectifying NFET connected between the output and ground (BCKGND pin) and a feedback path. During the first

portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow

from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of

(1)

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET

switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor

draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor

current down with a slope of

(2)

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load.

PWM OPERATION

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional

to the input voltage. To eliminate this dependence, feed forward voltage inversely proportional to the input

voltage is introduced.

INTERNAL SYNCHRONOUS RECTIFICATION

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

CURRENT LIMITING

A current limit feature allows the converter to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 1.5A for Buck1 and at 1.0A for

Buck2 (typ). If the output is shorted to ground the device enters a timed current limit mode where the NFET is

turned on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has

more time to decay, thereby preventing runaway.

PFM OPERATION

At very light loads, the converter enters PFM mode and operates with reduced switching frequency and supply

current to maintain high efficiency.

The part will automatically transition into PFM mode when either of two conditions occurs for a duration of 32 or

more clock cycles:

1. The inductor current becomes discontinuous

Product Folder Links: LP3907

VIN

80:

IPFM = 66 mA +

VIN

160:

IMODE < 66 mA )

(Typically +

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SNVS511O –JUNE 2007–REVISED MAY 2013

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2. The peak PMOS switch current drops below the IMODE level

(3)

During PFM operation, the converter positions the output voltage slightly higher than the nominal output voltage

during PWM operation, allowing additional headroom for voltage drop during a load transient from light to heavy

load. The PFM comparators sense the output voltage via the feedback pin and control the switching of the output

FETs such that the output voltage ramps between 0.8% and 1.6% (typical) above the nominal PWM output

voltage. If the output voltage is below the ‘low’ PFM comparator threshold, the PMOS power switch is turned on.

It remains on until the output voltage exceeds the ‘high’ PFM threshold or the peak current exceeds the IPFM level

set for PFM mode. The typical peak current in PFM mode is:

(4)

Once the PMOS power switch is turned off, the NMOS power switch is turned on until the inductor current ramps

to zero. When the NMOS zero-current condition is detected, the NMOS power switch is turned off. If the output

voltage is below the ‘high’ PFM comparator threshold (see Figure 32), the PMOS switch is again turned on and

the cycle is repeated until the output reaches the desired level. Once the output reaches the ‘high’ PFM

threshold, the NMOS switch is turned on briefly to ramp the inductor current to zero and then both output

switches are turned off and the part enters an extremely low power mode. Quiescent supply current during this

‘sleep’ mode is less than 30µA, which allows the part to achieve high efficiencies under extremely light load

conditions. When the output drops below the ‘low’ PFM threshold, the cycle repeats to restore the output voltage

to ~1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode (see Figure 32) causing the output voltage to fall below the

‘low2’ PFM threshold, the part will automatically transition into fixed-frequency PWM mode.

SW1, SW2 OPERATION

SW1 and SW2 have selectable output voltages ranging from 0.8V to 3.5V (typ.). Both SW1 and SW2 in the

LP3907 are I2C register controlled and are enabled by default through the internal state machine of the LP3907

following a Power-On event that moves the operating mode to the Active state. (See FLEXIBLE POWER

SEQUENCING OF MULTIPLE POWER SUPPLIES.) The SW1 and SW2 output voltages revert to default values

when the power on sequence has been completed. The default output voltage for each buck converter is factory

programmable. (See Application Notes).

SW1, SW2 CONTROL REGISTERS

SW1, SW2 can be enabled/disabled through the corresponding control register.

The Modulation mode PWM/PFM is by default automatic and depends on the load as described above in the

functional description. The modulation mode can be overridden by setting I2C bit to a logic 1 in the corresponding

buck control register, forcing the buck to operate in PWM mode regardless of the load condition.

Product Folder Links: LP3907

High PFM Threshold

~1.016 * Vout

Low1 PFM Threshold

~1.008 * Vout

PFM Mode at Light Load

PWM Mode at

Moderate to Heavy

Loads

Pfet on

until

Ipfm limit

reached

Nfet on

drains

inductor

current

until

I inductor = 0

High PFM

Voltage

Threshold

reached,

go into

sleep mode

Low PFM

Threshold,

turn on

PFET

Current load

increases,

draws Vout

towards

Low2 PFM

Threshold

Low2 PFM Threshold,

switch back to PWMmode

Load current

increases

Low2 PFM Threshold

Vout

Z-

Axis

LP3907

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SNVS511O –JUNE 2007–REVISED MAY 2013

Figure 32.

SHUTDOWN MODE

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The

NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is

activated. It is recommended to disable the converter during the system power up and under voltage conditions

when the supply is less than 2.8V.

SOFT START

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus

reducing startup stresses and surges. The two LP3907 buck converters have a soft-start circuit that limits in-rush

current during startup. During startup the switch current limit is increased in steps. Soft start is activated only if

EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch

current limit in steps of 180mA, 300mA, and 720mA for Buck1; 161mA, 300mA and 536mA for Buck2 (typ.

Switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at

start-up.

LOW DROPOUT OPERATION

The LP3907 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low drop out support

of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

When the device operates near 100% duty cycle, output voltage ripple is approximately 25mV. The minimum

input voltage needed to support the output voltage is

VIN, MIN = ILOAD * (RDSON, PFET + RINDUCTOR)+VOUT

Load current

• ILOAD Drain to source resistance of

• RDSON, PFET PFET switch in the triode region

Inductor resistance

• RINDUCTOR

FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES

The LP3907 provides several options for power on sequencing. The two bucks can be individually controlled with

ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.

If the user desires a set power on sequence, he can program the chip through I2C and raise EN_T from LOW to

HIGH to activate the power on sequencing.

Product Folder Links: LP3907

EN_T

Vout Buck1

Vout Buck2

Vout LDO1

Vout LDO2

I2C

Ext_Enable

Pins

Regulator ON

Start Programmed

Timing Sequence

EN_T

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POWER UP SEQUENCING USING THE EN_T FUNCTION

EN_T assertion causes the LP3907 to emerge from Standby mode to Full Operation mode at a preset timing

sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are

500K internally pulled down, which causes the part to stay OFF until enabled. If the user wishes to use the

preset timing sequence to power on the regulators, transition the EN_T pin from Low to High. Otherwise, simply

tie the enables of each specific regulator HIGH to turn on automatically.

EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched and the

default is set at 1ms. As shown in the next 2 diagrams, a rising EN_T edge will start a power-on sequence, while

a falling EN_T edge will start a shutdown sequence. If EN_T is high, toggling the external enables of the

regulators will have no effect on the chip.

The regulators can also be programmed through I2C to turn on and off. By default, I2C enables for the regulators

on ON.

The regulators are on following the pattern below:

Regulators on = (I2C enable) AND (External pin enable OR EN_T high).

Note: The EN_T power-up sequencing may also be employed immediately after VIN is applied to the device.

However, VIN must be stable for approximately 8ms minimum before EN_T be asserted high to ensure internal

bias, reference, and the Flexible POR timing are stabilized. This initial EN_T delay is necessary only upon first

time device power on for power sequencing function to operate properly.

Figure 33.

LP3907 Default Power-Up Sequence

Figure 34.

Table 3. Power-On Timing Specification

Symbol Description Min Typ Max Units

t1Programmable Delay from EN_T assertion to VCC_Buck1 On 1.5 ms

t2Programmable Delay from EN_T assertion to VCC_Buck2 On 2 ms

t3Programmable Delay from EN_T assertion to VCC_LDO1 On 3 ms

Product Folder Links: LP3907

EN_T

Vout Buck1

Vout Buck2

Vout LDO1

Vout LDO2

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SNVS511O –JUNE 2007–REVISED MAY 2013

Table 3. Power-On Timing Specification (continued)

Symbol Description Min Typ Max Units

t4Programmable Delay from EN_T assertion to VCC_LDO2 On 6 ms

NOTE

The LP3907 default Power on delays can be reprogrammed at final test or I2C to 1, 1.5, 2,

3, 6, or 11ms.

LP3907 Default Power-Off Sequence

Figure 35.

Symbol Description Min Typ Max Units

t1Programmable Delay from EN_T deassertion to VCC_Buck1 Off 1.5 ms

t2Programmable Delay from EN_T deassertion to VCC_Buck2 Off 2 ms

t3Programmable Delay from EN_T deassertion to VCC_LDO1 Off 3 ms

t4Programmable Delay from EN_T deassertion to VCC_LDO2 Off 6 ms

NOTE

The LP3907 default Power on delays can be reprogrammed at final test to 0, .5, 1, 2, 5, or

10ms. Default setting is the same as the on sequence.

Flexible Power-On Reset (i.e., Power Good with delay)

The LP3907 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage

levels on bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck

outputs are below 91% of the rising value , or when one or both outputs fall below 82% of the desired value. The

time delay between output voltage level and nPOR is enabled is (50µs, 50ms, 100ms, 200ms) 50ms by default.

The system designer can choose the external pull-up resistor (i.e. 100kΩ) for the nPOR pin.

Product Folder Links: LP3907

EN1

nPOR

RDY1

EN2

RDY2

EN1

nPOR

RDY1

EN2

RDY2

Case1

Case2

EN1

nPOR

RDY1

EN2

RDY2

Case3

Counter

delay

t1 t2

Counter

delay

t1 t2

Counter

delay

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Figure 36. NPOR With Counter Delay

Figure 37.

The above diagram shows the simplest application of the Power On Reset, where both switcher enables are tied

together. In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power

supply for Buck2 does not come on within that period, nPOR will stay LOW, indicating a power fail mode. Case 2

indicates the vice versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW.

Case 3 shows a typical application of the Power On Reset, where both switcher enables are tied together. Even

if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal will trigger a programmable delay

before going HIGH, as explained below.

Product Folder Links: LP3907

EN1

nPOR

RDY1

t1 t2 t3 t4

EN2

RDY2

Counter

delay Counter

delay

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Figure 38. Faults Occurring in Counter Delay After Startup

Figure 39.

The above timing diagram details the Power good with delay with respect to the enable signals EN1, and EN2.

The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has been

trimmed as follows:

Comparator Level Buck Supply Level

HIGH Greater than 94%

LOW Less than 85%

The circuits for EN1 and RDY1 is symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 will also

work for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are High at time t1, then the RDY1 signal rising edge triggers the programmable delay

counter (50μs, 50ms, 100ms, 200ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is

then pulled high after the programmable delay is completed. Now if EN2 and RDY2 are initiated during this

interval the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

Product Folder Links: LP3907

RDY1

t1 t2 t3 t4

RDY2

Counter

delay

EN1

EN2

nPOR

Counter

delay

nPOR

Mask Time

Counter

delay

Case 2:

Case 1:

Mask

Window

Mask

Window

RDY2

EN2

nPOR

Mask Time

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Figure 40. NPOR Mask Window

Figure 41.

If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted as explained

above.

In Case 1, we see that case where EN2 and RDY2 are initiated after triggered programmable delay. To prevent

the nPOR being asserted again, a masked window ( 5ms ) counter delay is triggered off the EN2 rising edge.

nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards will depend on the

status of both RDY1 and RDY2 lines.

In Case 2, we see the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2

never goes HIGH (Buck2 never turns on). Normal operation operation of nPOR occurs wilth respect to EN1 and

RDY1, and the nPOR signal is held HIGH for the duration of the mask window. We see that nPOR goes LOW

after the masking window has timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

Product Folder Links: LP3907

Delay Mask Counter

Delay nPOR

EN1

RDY1

EN2

RDY2

POR

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Figure 42. Design Implementation of the Flexible Power-On Reset

Figure 43.

An internal Power-on reset of the IC is used with EN1, and EN2 to produce a reset signal (LOW) to the delay

timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer.

S=R=1 never occurs. The mask timers are triggered off EN1 and EN2 which are gated with RDY1, and RDY2 to

generate outputs to the final AND gate to generate the nPOR.

Under Voltage Lock Out

The LP3907 features an “under voltage lock out circuit”. The function of this circuit is to continuously monitor the

raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply

voltage is less than 2.8VDC.

The circuit incorporates a bandgap based circuit that establishes the reference used to determine the 2.8VDC

trip point for a VIN OK – Not OK detector. This VIN OK signal is then used to gate the enable signals to the four

regulators of the LP3907. When VINLDO12 is greater than 2.8VDC the four enables control the four regulators,

when VINLDO12 is less than 2.8VDC the four regulators are disabled by the VIN detector being in the “Not OK”

state. The circuit has built in hysteresis to prevent chattering occurring.

I2C Compatible Serial Interface

I2C SIGNALS

The LP3907 features an I2C compatible serial interface, using two dedicated pins: SCL and SDA for I2C clock

and data respectively. Both signals need a pull-up resistor according to the I2C specification. The LP3907

interface is an I2C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I2C bus specification. The maximum bit rate is 400kbit/s. See I2C

specification from Philips for further details.

I2C DATA VALIDITY

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), e.g.- the state of the

data line can only be changed when CLK is LOW.

Product Folder Links: LP3907

ADR6

bit7

MSB

ADR5

bit6 ADR4

bit5 ADR3

I2C SLAVE address (chip address)

ADR2

bit3 ADR1

bit2 ADR0

bit1 R/W

bit0

LSB

1 1 0 0 0 0 0

bit4

I2C_SDA

I2C_SCL S P

START condition STOP condition

I2C_SCL

I2C_SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid data

valid

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Figure 44. I2C Signals: Data Validity

I2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while the SCL is HIGH. The 2C master always generates START and STOP

bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I2C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

Figure 45. START and STOP Conditions

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been

addressed must generate an acknowledgment (“ACK”) after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W).

NOTE

Please note that according to industry I2C standards for 7-bit addresses, the MSB of an 8-

bit address is removed, and communication actually starts with the 7th most significant bit.

For the eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second

byte selects the register to which the data will be written. The third byte contains data to

write to the selected register.

The LP3907 has factory-programmed I2C addresses. The WQFN chip has a chip address of 60'h, while the

DSBGA chip has a chip address of 61'h.

Figure 46. I2C Chip Address (see note above)

Product Folder Links: LP3907

ack from slave

w ackstart msb Chip Address lsb msb Register Add lsb msb DATA lsback ack stop

ack from slave ack from slave

SCL

start id = K¶60 w ack register addr = K¶10 GDWDDGGUK¶6Aack ack stop

SDA

rs msb Chip Address lsb r ack

repeated start data from slave ack from master

rid = K¶60ack rs

SCL

SDA

start id = K¶60 w ack addr = K¶02 DGGUHVVK¶$$GDWDack ack stop

ack from slave

w ackstart msb Chip Address lsb msb Register Add lsb msb DATA lsback ack stop

ack from slave ack from slave

123 4 5 6 7 8 9 1 2 3 ...

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SNVS511O –JUNE 2007–REVISED MAY 2013

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = LP3907 WQFN chip address: 0x60; DSBGA chip address: 0x61

Figure 47. I2C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

Figure 48. I2C Read Cycle

LP3907 Control Registers

Address Name

0x02 ICRA R Interrupt Status Register A

0x07 SCR1 R/W System Control 1 Register

0x10 BKLDOEN R/W Buck and LDO Output Voltage Enable Register

0x11 BKLDOSR R Buck and LDO Output Voltage Status Register

0x20 VCCR R/W Voltage Change Control Register 1

0x23 B1TV1 R/W Buck1 Target Voltage 1 Register

0x24 B1TV2 R/W Buck1 Target Voltage 2 Register

0x25 B1RC R/W Buck1 Ramp Control

0x29 B2TV1 R/W Buck2 Target Voltage 1 Register

0x2A B2TV2 R/W Buck2 Target Voltage 2 Register

0x2B B2RC R/W Buck2 Ramp Control

0x38 BFCR R/W Buck Function Register

0x39 LDO1VCR R/W LDO1 Voltage control Registers

0x3A LDO2VCR R/W LDO2 Voltage control Registers

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INTERRUPT STATUS REGISTER (ISRA) 0X02

This register informs the System Engineer of the temperature status of the chip.

D7-2 D1 D0

Name — Temp 125°C —

Access — R —

Data Reserved Status bit for thermal warning Reserved

PMIC T>125°C

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reset 0 0 0

CONTROL 1 REGISTER (SCR1) 0X07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM

and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.

D7 D6-4 D3 D2 D1 D0

Name — EN_DLY — FPWM2 FPWM1 ECEN

Access — R/W — R/W R/W R/W

Data Reserved Selects the preset Reserved Buck2 PWM /PFM Mode Buck 1 PWM /PFM Reserved

delay sequence from select Mode select

EN_T assertion 0 – Auto Switch PFM - 0 – Auto Switch PFM -

(shown below) PWM operation PWM operation

1 – PWM Mode Only 1 – PWM Mode Only

Reset 0 Factory-Programmed 1 Factory-Programmed Factory-Programmed 0

Default Default Default

EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION

Delay (ms)

EN_DLY<2:0> Buck1 Buck2 LDO1 LDO2

000 1111

001 1 1.5 2 2

010 1.5 2 3 6

011 1.5 2 1 1

100 1.5 2 3 6

101 1.5 1.5 2 2

110 3 2 1 1.5

111 2 3 6 11

BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10

This register controls the enables for the Bucks and LDOs.

D7 D6 D5 D4 D3 D2 D1 D0

Name — LDO2EN — LDO1EN — BK2EN — BK1EN

Access — R/W — R/W — R/W — R/W

Data Reserved 0 – Disable Reserved 0 – Disable Reserved 0 – Disable Reserved 0 – Disable

1 – Enable 1 – Enable 1 – Enable 1 – Enable

Reset01110101

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BUCK AND LDO STATUS REGISTER (BKLDOSR) – 0X11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

D7 D6 D5 D4 D3 D2 D1 D0

Name BKS_OK LDOS_OK LDO2_OK LDO1_OK — BK2_OK — BK1_OK

Access R R R R — R — R

Data 0 – Buck 1-2 0 – LDO 1-2 0 – LDO2 Not 0 – LDO1 Not Reserve 0 – Buck2 Not Reserve 0 – Buck1 Not

Not Valid Not Valid Valid Valid d Valid d Valid

1 – Bucks Valid 1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid 1 – Buck2 Valid 1 – Buck1 Valid

Reset 0 0 0 0 0 0 0 0

BUCK VOLTAGE CHANGE CONTROL REGISTER 1 (VCCR) – 0X20

This register selects and controls the output target voltages for the buck regulators.

D7-6 D5 D4 D3-2 D1 D0

Name — B2VS B2GO — B1VS B1GO

Access — R/W R/W — R/W R/W

Data Reserved Buck2 Target Voltage Buck2 Voltage Ramp Reserved Buck1 Target Voltage Buck1 Voltage Ramp

Select CTRL Select CTRL

0 – B2VT1 0 – Hold 0 – B1VT1 0 – Hold

1 – B2VT2 1 – Ramp to B2VS 1 – B1VT2 1 – Ramp to B1VS

selection selection

Reset 00 0 0 00 0 0

BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23

This register allows the user to program the output target voltage of Buck1.

D7-5 D4-0

Name — BK1_VOUT1

Access — R/W

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D7-5 D4-0

Data Reserved Buck1 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 0.80

5’h02 0.85

5’h03 0.90

5’h04 0.95

5’h05 1.00

5’h06 1.05

5’h07 1.10

5’h08 1.15

5’h09 1.20

5’h0A 1.25

5’h0B 1.30

5’h0C 1.35

5’h0D 1.40

5’h0E 1.45

5’h0F 1.50

5’h10 1.55

5’h11 1.60

5’h12 1.65

5’h13 1.70

5’h14 1.75

5’h15 1.80

5’h16 1.85

5’h17 1.90

5’h18 1.95

5’h19 2.00

5’h1A–5’h1F 2.00

Reset 000 Factory-Programmed Default

BUCK1 TARGET VOLTAGE 2 REGISTER (B1TV2) – 0X24

This register allows the user to program the output target voltage of Buck1.

D7-5 D4-0

Name — BK1_VOUT2

Access — R/W

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D7-5 D4-0

Data Reserved Buck1 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 0.80

5’h02 0.85

5’h03 0.90

5’h04 0.95

5’h05 1.00

5’h06 1.05

5’h07 1.10

5’h08 1.15

5’h09 1.20

5’h0A 1.25

5’h0B 1.30

5’h0C 1.35

5’h0D 1.40

5’h0E 1.45

5’h0F 1.50

5’h10 1.55

5’h11 1.60

5’h12 1.65

5’h13 1.70

5’h14 1.75

5’h15 1.80

5’h16 1.85

5’h17 1.90

5’h18 1.95

5’h19 2.00

5’h1A–5’h1F 2.00

Reset 000 Factory-Programmed Default

* If using Ext Ctrl, contact TI Sales for support.

BUCK1 RAMP CONTROL REGISTER (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck1.

D7 D6-4 D3-0

Name - - - - - - - - B1RS

Access - - - - - - - - R/W

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Data Reserved Reserved Data Code Ramp Rate mV/us

4h'0 Instant

4h'1 1

4h'2 2

4h'3 3

4h'4 4

4h'5 5

4h'6 6

4h'7 7

4h'8 8

4h'9 9

4h'A 10

4h'B - 4h'F 10

Reset 0 010 1000

BUCK2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29

This register allows the user to program the output target voltage of Buck2.

D7-5 D4-0

Name — BK2_VOUT1

Access — R/W

Data Reserved Buck2 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 1.0

5’h02 1.1

5’h03 1.2

5’h04 1.3

5’h05 1.4

5’h06 1.5

5’h07 1.6

5’h08 1.7

5’h09 1.8

5’h0A 1.9

5’h0B 2.0

5’h0C 2.1

5’h0D 2.2

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory-Programmed Default

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BUCK2 TARGET VOLTAGE 2 REGISTER (B2TV2) – 0X2A

This register allows the user to program the output target voltage of Buck2.

D7-5 D4-0

Name — BK2_VOUT2

Access — R/W

Data Reserved Buck2 Output Voltage (V)

5’h00 Ext Ctrl

5’h01 1.0

5’h02 1.1

5’h03 1.2

5’h04 1.3

5’h05 1.4

5’h06 1.5

5’h07 1.6

5’h08 1.7

5’h09 1.8

5’h0A 1.9

5’h0B 2.0

5’h0C 2.1

5’h0D 2.2

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory-Programmed Default

*If using Ext Ctrl, contact TI Sales for support.

BUCK2 RAMP CONTROL REGISTER (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck2.

D7 D6-4 D3-0

Name - - - - - - - - B2RS

Access - - - - - - - - R/W

Product Folder Links: LP3907

2 MHz

Clock Frequency

Time

Spread Spectrum

frequency

10 kHz triangle

wave

Peak frequency deviation

2 kHz triangle

wave

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Data Reserved Reserved Data Code Ramp Rate mV/us

4h'0 Instant

4h'1 1

4h'2 2

4h'3 3

4h'4 4

4h'5 5

4h'6 6

4h'7 7

4h'8 8

4h'9 9

4h'A 10

4h'B - 4h'F 10

Reset 0 010 1000

BUCK FUNCTION REGISTER (BFCR) – 0x38

This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less

Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the

frequency ramps up and down, centered at 2MHz.

This register also allows dynamic scaling of the nPOR Delay Timing. The LP3907 is equipped with an internal

Power-On-Reset (“POR”) circuit which monitors the output voltage levels on the buck regulators, allowing the

user to more actively monitor the power status of the chip.

The Under Voltage Lock-Out feature continuously monitor the raw input supply voltage (VINLDO12) and

automatically disables the four voltage regulators whenever this supply voltage is less than 2.8VDC. This

prevents the user from damaging the power source (i.e. battery), but can be disabled if the user wishes.

Note that if the supply to VDD_M is close to 2.8V with a heavy load current on the regulators, the chip is in

danger of powering down due to UVLO. If the user wishes to keep the chip active under those conditions, enable

the “Bypass UVLO” feature.

D7-2 D4 D3 D1 D0

Name — BP_UVLO TPOR BK_SLOMOD BK_SSEN

Access — R/W R/w R/W R/W

Data Reserved Bypass UVLO nPOR Delay Timing Buck Spread Spectrum Spread Spectrum

monitoring 00 - 50µs Modulation Function Output

0 - Allow UVLO 01 - 50ms 0 – 10 kHz triangular wave 0 – Disabled

1 - Disable UVLO 10 - 100ms 1 – 2 kHz triangular wave 1 – Enabled

11 - 200ms

Reset 000 Factory-Programmed 01 1 0

Default

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LDO1 CONTROL REGISTER (LDO1VCR) – 0X39

This register allows the user to program the output target voltage of LDO 1.

For “JJ11” voltage options LDO1 has a fixed output voltage of 2.85V.

D7-5 D4-0

Name — LDO1_OUT

Access — R/W

Data Reserved LDO1 Output voltage (V)

5’h00 1.0

5’h01 1.1

5’h02 1.2

5’h03 1.3

5’h04 1.4

5’h05 1.5

5’h06 1.6

5’h07 1.7

5’h08 1.8

5’h09 1.9

5’h0A 2.0

5’h0B 2.1

5’h0C 2.2

5’h0D 2.3

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory-Programmed Default

LDO2 CONTROL REGISTER (LDO2VCR) – 0X3A

This register allows the user to program the output target voltage of LDO 2.

For “JJ11” voltage options LDO2 has a fixed output voltage of 2.85V.

D7-5 D4-0

Name — LDO2_OUT

Access — R/W

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D7-5 D4-0

Data Reserved LDO2 Output voltage (V)

5’h00 1.0

5’h01 1.1

5’h02 1.2

5’h03 1.3

5’h04 1.4

5’h05 1.5

5’h06 1.6

5’h07 1.7

5’h08 1.8

5’h09 1.9

5’h0A 2.0

5’h0B 2.1

5’h0C 2.2

5’h0D 2.3

5’h0E 2.4

5’h0F 2.5

5’h10 2.6

5’h11 2.7

5’h12 2.8

5’h13 2.9

5’h14 3.0

5’h15 3.1

5’h16 3.2

5’h17 3.3

5’h18 3.4

5’h19 3.5

5’h1A–5’h1F 3.5

Reset 000 Factory-Programmed Default

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L tVIN - VOUT

IPP xx VOUT

VIN ¹

§f

§¹

where Iripple = VIN - VOUT

x x VOUT

VIN ¹

§¹

·©

§¹

Isat > Ioutmax + Iripple

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SNVS511O –JUNE 2007–REVISED MAY 2013

APPLICATION NOTES

ANALOG POWER SIGNAL ROUTING

All power inputs should be tied to the main VDD source (i.e. battery), unless the user wishes to power it from

another source. (i.e. external LDO output).

The analog VDD inputs power the internal bias and error amplifiers, so they should be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.8 and 5.5V, as specified in the Electrical

Characteristics Section in the front of the datasheet.

The other VINs (VINLDO1, VINLDO2, VIN1, VIN2) can actually have inputs lower than 2.8V, as long as it's higher

than the programmed output (+0.3V, to be safe).

The analog and digital grounds should be tied together outside of the chip to reduce noise coupling.

COMPONENT SELECTION

Inductors for SW1 and SW2

There are two main considerations when choosing an inductor; the inductor should not saturate and the inductor

current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing

the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are

typically specified at 25ºC, so ratings at maximum ambient temperature of the application should be requested

from the manufacturer.

There are two methods to choose the inductor saturation current rating:

Method 1:

The saturation current is greater than the sum of the maximum load current and the worst case average to peak

inductor current. This can be written as follows:

(5)

IRIPPLE:Average to peak inductor current

IOUTMAX:Maximum load current

VIN:Maximum input voltage to the buck

L: Min inductor value including worse case tolerances (30% drop can be considered for method 1)

f: Minimum switching frequency (1.6 MHz)

VOUT:Buck Output voltage

Method 2:

A more conservative and recommended approach is to choose an inductor that has saturation current rating

greater than the maximum current limit of 1250mA for Buck1 and 1750mA for Buck2.

Given a peak-to-peak current ripple (IPP) the inductor needs to be at least

(6)

Inductor Value Unit Description Notes

LSW1,2 2.2 µH SW1,2 inductor D.C.R. 70mΩ

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External Capacitors

The regulators on the LP3907 require external capacitors for regulator stability. These are specifically designed

for portable applications requiring minimum board space and smallest components. These capacitors must be

correctly selected for good performance.

LDO CAPACITOR SELECTION

Input Capacitor

An input capacitor is required for stability. It is recommended that a 1.0μF capacitor be connected between the

LDO input pin and ground (this capacitance value may be increased without limit).

This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

Important: Tantalum capacitors can suffer catastrophic failures due to surge currents when connected to a low

impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,

it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain

approximately 1.0μF over the entire operating temperature range.

Output Capacitor

The LDOs on the LP3907 are designed specifically to work with very small ceramic output capacitors. A 0.47µF

ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩto 500mΩ, is suitable in the

application circuit.

It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as

attractive for reasons of size and cost.

The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR

value that is within the range 5 mΩto 500 mΩfor stability.

Capacitor Characteristics

The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they

offer. For capacitance values in the range of 0.47µF to 4.7µF, ceramic capacitors are the smallest, least

expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The

ESR of a typical 1.0µF ceramic capacitor is in the range of 20mΩto 40mΩ, which easily meets the ESR

requirement for stability for the LDOs.

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly, depending on the operating conditions and

capacitor type.

In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.

The capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer

performance figures in general. As an example, below is typical graph comparing different capacitor case sizes in

a Capacitance vs. DC Bias plot.

Product Folder Links: LP3907

Irms = Ioutmax VOUT

VIN 1

§12

+¹

(Vin ± Vout) x Vout

L x f x Ioutmax x Vin

where r =

0402, 6.3V, X5R

0603, 10V, X5R

0 1.0 2.0 3.0 4.0 5.0

DC BIAS (V)

20%

40%

60%

80%

100%

CAP VALUE (% of NOMINAL 1 PF)

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Figure 49. Graph Showing a Typical Variation in Capacitance vs. DC Bias

As shown in the graph, increasing the DC Bias condition can result in the capacitance value that falls below the

minimum value given in the recommended capacitor specifications table. Note that the graph shows the

capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended

that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions,

as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.

The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a

temperature range of −55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R

has a similar tolerance over a reduced temperature range of −55°C to +85°C. Many large value ceramic

capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance

can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over

Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more

expensive when comparing equivalent capacitance and voltage ratings in the 0.47µF to 4.7µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about

2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.

Input Capacitor Selection for SW1 and SW2

A ceramic input capacitor of 10µF, 6.3V is sufficient for the magnetic dc/dc converters. Place the input capacitor

as close as possible to the input of the device. A large value may be used for improved input voltage filtering.

The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias

characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The

input filter capacitor supplies current to the PFET switch of the dc/dc converter in the first half of each cycle and

reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low ESR (Equivalent Series

Resistance) provides the best noise filtering of the input voltage spikes due to fast current transients. A capacitor

with sufficient ripple current rating should be selected. The Input current ripple can be calculated as:

(7)

The worse case is when VIN = 2VOUT.

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Vpp-rms = Vpp-c2 + Vpp-esr2

Iripple

4 x f x C

Vpp-c =

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Output Capacitor Selection for SW1, SW2

A 10μF, 6.3V ceramic capacitor should be used on the output of the sw1 and sw2 magnetic dc/dc converters.

The output capacitor needs to be mounted as close as possible to the output of the device. A large value may be

used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V type

capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when selecting

case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC bias

curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic dc/dc converter smooths out current flow from the inductor to the load,

helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These

capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

ESR and can be calculated as follows:

(8)

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

VPP–ESR = 2 × IRIPPLE × RESR (9)

Because the VPP-C and VPP-ESR are out of phase, the rms value can be used to get an approximate value of the

peak-to-peak ripple:

(10)

Note that the output voltage ripple is dependent on the inductor current ripple and the equivalent series

resistance of the output capacitor (RESR). The RESR is frequency dependent as well as temperature dependent.

The RESR should be calculated with the applicable switching frequency and ambient temperature.

Capacitor Min Value Unit Description Recommended Type

CLDO1 0.47 µF LDO1 output capacitor Ceramic, 6.3V, X5R

CLDO2 0.47 µF LDO2 output capacitor Ceramic, 6.3V, X5R

CSW1 10.0 µF SW1 output capacitor Ceramic, 6.3V, X5R

CSW2 10.0 µF SW2 output capacitor Ceramic, 6.3V, X5R

I2C Pullup Resistor

Both SDA and SCL terminals need to have pullup resistors connected to VINLDO12 or to the power supply of the

I2C master. The values of the pull-up resistors (typ. ∼1.8kΩ) are determined by the capacitance of the bus. Too

large of a resistor combined with a given bus capacitance will result in a rise time that would violate the max. rise

time specification. A too small resistor will result in a contention with the pull-down transistor on either slave(s) or

master.

Operation without I2C Interface

Operation of the LP3907 without the I2C interface is possible if the system can operate with default values for the

LDO and Buck regulators. (Read below: Factory programmable options). The I2C-less system must rely on the

correct default output values of the LDO and Buck converters.

Factory Programmable Options

The following options are EPROM programmed during final test of the LP3907. The system designer that needs

specific options is advised to contact the TI sales office.

Factory programmable options Current value

Enable delay for power on code 010 (see CONTROL 1 REGISTER (SCR1) 0X07)

SW1 ramp speed 8 mV/µs

SW2 ramp speed 8 mV/µs

Product Folder Links: LP3907

LP3907

www.ti.com

SNVS511O –JUNE 2007–REVISED MAY 2013

The I2C Chip ID address is offered as a metal mask option. The current address for the WQFN chip equals 0x60,

while the address for the DSBGA chip is 0x61.

HIGH VIN HIGH-LOAD OPERATION

Additional information is provided when the IC is operated at extremes of VIN and regulator loads. These are

described in terms of the Junction temperature and, Buck output ripple management.

JUNCTION TEMPERATURE

The maximum junction temperature TJ-MAX-OP of 125°C of the IC package.

The following equations demonstrate junction temperature determination, ambient temperature TA-MAX and Total

chip power must be controlled to keep TJbelow this maximum:

TJ-MAX-OP = TA-MAX + (θJA) [°C/ Watt] * (PD-MAX) [Watts]

Total IC power dissipation PD-MAX is the sum of the individual power dissipation of the four regulators plus a minor

amount for chip overhead. Chip overhead is Bias, TSD & LDO analog.

PD-MAX = PLDO1 + PLD02 + PBUCK1 + PBUCK2 + (0.0001A * VIN) [Watts].

Power dissipation of LDO1

PLDO1 = (VINLDO1- VOUTLDO1) * IoutLDO1 [V*A]

Power dissipation of LDO2

PLDO2 = (VINLDO2 - VoutLDO2) * IoutLDO2 [V*A]

Power dissipation of Buck1

PBuck1 = PIN – POUT =

VoutBuck1* IoutBuck1 * (1 -η1) / η1[V*A]

η1= efficiency of buck 1

Power dissipation of Buck2

PBuck2 = PIN – POUT =

VoutBuck2 * IoutBuck2 * (1 - η2) / η2[V*A]

η2= efficiency of Buck2

Where ηis the efficiency for the specific condition taken from efficiency graphs.

Thermal Performance of the WQFN Package

The LP3907 is a monolithic device with integrated power FETs. For that reason, it is important to pay special

attention to the thermal impedance of the WQFN package and to the PCB layout rules in order to maximize

power dissipation of the WQFN package.

The WQFN package is designed for enhanced thermal performance and features an exposed die attach pad at

the bottom center of the package that creates a direct path to the PCB for maximum power dissipation.

Compared to the traditional leaded packages where the die attach pad is embedded inside the molding

compound, the WQFN reduces one layer in the thermal path.

The thermal advantage of the WQFN package is fully realized only when the exposed die attach pad is soldered

down to a thermal land on the PCB board with thermal vias planted underneath the thermal land. Based on

thermal analysis of the WQFN package, the junction-to-ambient thermal resistance (θJA) can be improved by a

factor of two when the die attach pad of the WQFN package is soldered directly onto the PCB with thermal land

and thermal vias, as opposed to an alternative with no direct soldering to a thermal land. Typical pitch and outer

diameter for thermal vias are 1.27mm and 0.33mm respectively. Typical copper via barrel plating is 1oz, although

thicker copper may be used to further improve thermal performance. The LP3907 die attach pad is connected to

the substrate of the IC and therefore, the thermal land and vias on the PCB board need to be connected to

ground (GND pin).

Product Folder Links: LP3907

LP3907

SNVS511O –JUNE 2007–REVISED MAY 2013

www.ti.com

For more information on board layout techniques, refer to Application Note AN–1187 “Leadless Lead frame

Package (LLP)” SNOA401 on http://www.ti.com This application note also discusses package handling, solder

stencil and the assembly process.

Product Folder Links: LP3907

LP3907

www.ti.com

SNVS511O –JUNE 2007–REVISED MAY 2013

REVISION HISTORY

Changes from Revision N (May 2013) to Revision O Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 44

Product Folder Links: LP3907

PACKAGE OPTION ADDENDUM

www.ti.com 3-May-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

LP3907QSQ-JJXP/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJJXP

LP3907QSQ-JXI7/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXI7

LP3907QSQ-JXIP/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXIP

LP3907QSQX-JJXP/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJJXP

LP3907QSQX-JXI7/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXI7

LP3907QSQX-JXIP/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 07QJXIP

LP3907QTL-VXSS/NOPB ACTIVE DSBGA YZR 25 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 V025

LP3907QTLX-VXSS/NOPB ACTIVE DSBGA YZR 25 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 V025

LP3907SQ-BFX6W/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 7BFX6W

LP3907SQ-BJX6X/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJX6X

LP3907SQ-BJXIX/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJXIX

LP3907SQ-BJXQX/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJXQX

LP3907SQ-BJYQX/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJYQX

LP3907SQ-JXQX/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 07-JXQX

LP3907SQ-PFX6W/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 7PFX6W

LP3907SQ-PJXIX/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07PJXIX

LP3907SQ-PXPP/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 07-PXPP

PACKAGE OPTION ADDENDUM

www.ti.com 3-May-2013

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

LP3907SQ-VRZX/NOPB ACTIVE WQFN RTW 24 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07-VRZX

LP3907SQX-BFX6W/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 7BFX6W

LP3907SQX-BJX6X/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJX6X

LP3907SQX-BJXIX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJXIX

LP3907SQX-BJXQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJXQX

LP3907SQX-BJYQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07BJYQX

LP3907SQX-JXQX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07-JXQX

LP3907SQX-PFX6W/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 7PFX6W

LP3907SQX-PJXIX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07PJXIX

LP3907SQX-PXPP/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07-PXPP

LP3907SQX-VRZX/NOPB ACTIVE WQFN RTW 24 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 07-VRZX

LP3907TL-JJ11/NOPB ACTIVE DSBGA YZR 25 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V013

LP3907TL-JJCP/NOPB ACTIVE DSBGA YZR 25 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V016

LP3907TL-JSXS/NOPB ACTIVE DSBGA YZR 25 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V012

LP3907TL-PLNTO/NOPB ACTIVE DSBGA YZR 25 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V027

LP3907TLX-JJ11/NOPB ACTIVE DSBGA YZR 25 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V013

LP3907TLX-JJCP/NOPB ACTIVE DSBGA YZR 25 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V016

LP3907TLX-JSXS/NOPB ACTIVE DSBGA YZR 25 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V012

PACKAGE OPTION ADDENDUM

www.ti.com 3-May-2013

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

LP3907TLX-PLNTO/NOPB ACTIVE DSBGA YZR 25 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM V027

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LP3907, LP3907-Q1 :

•Catalog: LP3907

•Automotive: LP3907-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 3-May-2013

Addendum-Page 4

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3907QSQ-JJXP/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907QSQ-JXI7/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907QSQ-JXIP/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907QSQX-JJXP/NOP

BWQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907QSQX-JXI7/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907QSQX-JXIP/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907QTL-VXSS/NOPB DSBGA YZR 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907QTLX-VXSS/NOP

BDSBGA YZR 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907SQ-BFX6W/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-BJX6X/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-BJXIX/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-BJXQX/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-BJYQX/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-JXQX/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-PFX6W/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-PJXIX/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQ-PXPP/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 1

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LP3907SQ-VRZX/NOPB WQFN RTW 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-BFX6W/NOP

BWQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-BJX6X/NOP

BWQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-BJXIX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-BJXQX/NOP

BWQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-BJYQX/NOP

BWQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-JXQX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-PFX6W/NOP

BWQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-PJXIX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-PXPP/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907SQX-VRZX/NOPB WQFN RTW 24 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1

LP3907TL-JJ11/NOPB DSBGA YZR 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907TL-JJCP/NOPB DSBGA YZR 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907TL-JSXS/NOPB DSBGA YZR 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907TL-PLNTO/NOPB DSBGA YZR 25 250 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907TLX-JJ11/NOPB DSBGA YZR 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907TLX-JJCP/NOPB DSBGA YZR 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907TLX-JSXS/NOPB DSBGA YZR 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

LP3907TLX-PLNTO/NOP

BDSBGA YZR 25 3000 178.0 8.4 2.69 2.69 0.76 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 2

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3907QSQ-JJXP/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907QSQ-JXI7/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907QSQ-JXIP/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907QSQX-JJXP/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907QSQX-JXI7/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907QSQX-JXIP/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907QTL-VXSS/NOPB DSBGA YZR 25 250 210.0 185.0 35.0

LP3907QTLX-VXSS/NOPB DSBGA YZR 25 3000 210.0 185.0 35.0

LP3907SQ-BFX6W/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-BJX6X/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-BJXIX/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-BJXQX/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-BJYQX/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-JXQX/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-PFX6W/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-PJXIX/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-PXPP/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQ-VRZX/NOPB WQFN RTW 24 1000 210.0 185.0 35.0

LP3907SQX-BFX6W/NOP

BWQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-BJX6X/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 3

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP3907SQX-BJXIX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-BJXQX/NOP

BWQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-BJYQX/NOP

BWQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-JXQX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-PFX6W/NOP

BWQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-PJXIX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-PXPP/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907SQX-VRZX/NOPB WQFN RTW 24 4500 367.0 367.0 35.0

LP3907TL-JJ11/NOPB DSBGA YZR 25 250 210.0 185.0 35.0

LP3907TL-JJCP/NOPB DSBGA YZR 25 250 210.0 185.0 35.0

LP3907TL-JSXS/NOPB DSBGA YZR 25 250 210.0 185.0 35.0

LP3907TL-PLNTO/NOPB DSBGA YZR 25 250 210.0 185.0 35.0

LP3907TLX-JJ11/NOPB DSBGA YZR 25 3000 210.0 185.0 35.0

LP3907TLX-JJCP/NOPB DSBGA YZR 25 3000 210.0 185.0 35.0

LP3907TLX-JSXS/NOPB DSBGA YZR 25 3000 210.0 185.0 35.0

LP3907TLX-PLNTO/NOPB DSBGA YZR 25 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 4

MECHANICAL DATA

RTW0024A

www.ti.com

SQA24A (Rev B)

MECHANICAL DATA

YZR0025xxx

www.ti.com

TLA25XXX (Rev D)

0.600±0.075 D

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

4215055/A 12/12

D: Max =

E: Max =

2.521 mm, Min =

2.46 mm

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