SSRAM A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A AS5SP512K36DQ Plastic Encapsulated Microcircuit Symbol tCYC tCD tOE 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 Units ns ns ns 81 84 82 83 85 87 86 89 88 91 4 77 5 76 DQc DQc 6 75 7 74 DQc DQc 8 73 9 72 71 DQPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VSSQ VDDQ 10 11 70 DQc 12 69 DQc NC VDD 13 68 NC VSS DQd 16 65 17 64 18 63 DQd 19 62 VDDQ VSSQ 20 61 VDD ZZ DQa DQa VDDQ 21 60 VSSQ DQd 22 59 DQd DQd 23 58 24 57 DQa DQa DQa DQd 25 56 DQa VSSQ VDDQ 26 55 27 54 DQd DQd DQPd 28 53 29 52 VSSQ VDDQ DQa DQa 30 51 DQP 14 67 VSS NC 50 49 48 47 66 46 45 44 43 42 41 40 39 38 37 35 34 36 SSRAM [SPB] 15 VDDQ DQb DQb GENERAL DESCRIPTION The AS5SP512K36DQ is a 18Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 512K x 36. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. Block Diagram OE\ ZZ CLK CE1\ CE2 90 92 93 95 96 94 97 78 VDD A A A A A A A A A Fast Access Times Parameter Cycle Time Clock Access Time Output Enable Access Time 79 3 33 * * * * * * * 80 2 MODE A A A A A1 A0 NC NC VSS Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support Global Write support On-Chip low power mode [powerdown] via ZZ pin Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention. Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP\, ADSC\, ADV\) 3.3V Core Power Supply 3.3V/2.5V IO Power Supply JEDEC Standard 100 pin TQFP Package, MS026-D/BHA Available in Industrial, Enhanced, and MilTemperature Operating Ranges 1 DQc DQc VDDQ VSSQ 32 * * * * * * * * * * DQPc 31 FEATURES 98 100 Pipeline Burst, Single Cycle Deselect 99 18Mb, 512K x 36, Synchronous SRAM I/O Gating and Control CE3\ BWE\ BWx\ CONTROL BLOCK GW\ ADV ADSC\ ADSP\ MODE A0-Ax AS5SP512K36DQ Rev. 2.6 01/10 BURST CNTL. Address Registers Row Decode Column Decode Memory Array x36 SBP Synchronous Pipeline Burst Two (2) cycle load One (1) cycle de-select One (1) cycle latency on Mode change Output Register Input Register Output Driver The AS5SP512K36DQ includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are handled by three (3) input pins, ADV, ADSP\ and ADSC\. DQx, DQPx Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status Cache controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system's burst sequence control block and are controlled by Address Advance (ADV) control input. Micross Components reserves the right to change products or specifications without notice. 1 SSRAM AS5SP512K36DQ Fast Access Times Signal Name Clock Symbol CLK Type Input Pin Address A0, A1 Input Address A Input(s) Chip Enable Chip Enable Global Write Enable Byte Enables Input Input Input Input Byte Write Enable Output Enable Address Strobe Controller CE1\, CE3\ CE2 GW\ BWa\, BWb\, BWc\, BWd\ BWE\ OE\ ADSC\ 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 42 98, 92 97 88 93, 94, 95, 96 Input Input Input 87 86 85 Address Strobe from Processor ADSP\ Input 84 Address Advance ADV Input 83 Power-Down ZZ Input 64 Data Parity Input/Outputs DQPa, DQPb DQPc, DQPd Input/ Output Data Input/Outputs DQa, DQb, DQc Input/ DQd Output Burst Mode Power Supply [Core] Ground [Core] Power Supply I/O MODE VDD VSS VDDQ Input Supply Supply Supply I/O Ground VSSQ Supply No Connection(s) NC NA 89 37, 36 Description This input registers the address, data, enables, Global and Byte writes as well as the burst control functions Low order, Synchronous Address Inputs and Burst counter address inputs Synchronous Address Inputs Active Low True Chip Enables Active High True Chip Enable Active Low True Global Write enable. Write to all bits Active Low True Byte Write enables. Write to byte segments Active Low True Byte Write Function enable Active Low True Asynchronous Output enable Address Strobe from Controller. When asserted LOW, Address is captured in the address registers and A0-A1 are loaded into the Bur When ADSP\ and ADSC are both asserted, only ADSP is recognized Synchronous Address Strobe from Processor. When asserted LOW, Address is captured in the Address registers, A0-A1 is registered in the burst counter. When both ADSP\ and ADSC\ or both asserted, only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH Advance input Address. When asserted HIGH, address in burst counter is incremented. Asynchronous, non-time critical Power-down Input control. Places the chip into an ultra low power mode, with data preserved. Bidirectional I/O Parity lines. As inputs they reach the memory array via an input register, the address stored in the register on the rising edge of clock. As and output, the line delivers the valid data stored in the array via an output register and output driver. The data delieverd is from the previous clock period of the READ cycle. Bidirectional I/O Data lines. As inputs they reach the memo array via an input register, the address stored in the register on the rising edge of clock. As and output, the line delivers the valid data stored in the array via an output register and output driver. The data delieverd is from the previous clock period of the READ cycle. Interleaved or Linear Burst mode control Core Power Supply Core Power Supply Ground Isolated Input/Output Buffer Supply 51, 80, 1, 30 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 31 91, 15, 41, 65 90, 17, 40, 67 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, Isolated Input/Output Buffer Ground 71, 76 14, 16, 38, 39, 66 No connections to internal silicon Logic Block Diagram A0, A1, Ax ADDRESS REGISTER MODE 2 A0, A1 ADV\ CLK Burst Counter Q1 and CLR Logic Q0 ADSC\ ADSP\ BWd\ BWc\ BWb\ BWa\ BWE\ GW\ CE1\ CE2 CE3\ OE\ Byte Write Register DQd, DQPd Byte Write Driver DQd, DQPd Byte Write Register DQc, DQPc Byte Write Driver DQc, DQPc Byte Write Register DQb, DQPb Byte Write Driver DQb, DQPb Byte Write Register DQa, DQPa Byte Write Driver DQa, DQPa Enable Register Sense Amps Output Registers Output Buffers DQx, DQPx Input Registers Pipeline Enable Sleep Control ZZ AS5SP512K36DQ Rev. 2.6 01/10 Memory Array Micross Components reserves the right to change products or specifications without notice. 2 SSRAM AS5SP512K36DQ Functional Description cycle. Consecutive single cycle READS are supported. Once the READ operation has been completed and deselected by use of the Chip Enable(s) and either ADSP\ or ADSC\, its outputs will tri-state immediately. Micross Components AS5SP512K36DQ Synchronous SRAM is manufactured to support today's High Performance platforms utilizing the Industries leading Processor elements including those of Intel and Motorola. The AS5SP512K36DQ supports Synchronous SRAM READ and WRITE operations as well as Synchronous Burst READ/WRITE operations. All inputs with the exception of OE\, MODE and ZZ are synchronous in nature and sampled and registered on the rising edge of the devices input clock (CLK). The type, start and the duration of Burst Mode operations is controlled by MODE, ADSC\, ADSP\ and ADV as well as the Chip Enable pins CE1\, CE2, and CE3\. All synchronous accesses including the Burst accesses are enabled via the use of the multiple enable pins and wait state insertion is supported and controlled via the use of the Advance control (ADV). A Single ADSP\ controlled WRITE operation is initiated when both of the following conditions are satisfied at the time of Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip Enable(s) are asserted ACTIVE. The address presented to the address bus is registered and loaded on CLK HIGH, then presented to the core array. The WRITE controls Global Write, and Byte Write Enable (GW\, BWE\) as well as the individual Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are ignored on the first machine cycle. ADSP\ triggered WRITE accesses require two (2) machine cycles to complete. If Global Write is asserted LOW on the second Clock (CLK) rise, the data presented to the array via the Data bus will be written into the array at the corresponding address location specified by the Address bus. If GW\ is HIGH (inactive) then BWE\ and one or more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\) controls the write operation. All WRITES that are initiated in this device are internally self timed. The AS5SP512K36DQ supports both Interleaved as well as Linear Burst modes therefore making it an architectural fit for either the Intel or Motorola CISC processor elements available on the Market today. The AS5SP512K36DQ supports Byte WRITE operations and enters this functional mode with the Byte Write Enable (BWE\) and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). Global Writes are supported via the Global Write Enable (GW\) and Global Write Enable will override the Byte Write inputs and will perform a Write to all Data I/Os. A Single ADSC\ controlled WRITE operation is initiated when the following conditions are satisfied: [1] ADSC\ is asserted LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are asserted (TRUE or Active), and [4] the appropriate combination of the WRITE inputs (GW\, BWE\, BWx\) are asserted (ACTIVE). Thus completing the WRITE to the desired Byte(s) or the complete data-path. ADSC\ triggered WRITE accesses require a single clock (CLK) machine cycle to complete. The address presented to the input Address bus pins at time of clock HIGH will be the location that the WRITE occurs. The ADV pin is ignored during this cycle, and the data WRITTEN to the array will either be a BYTE WRITE or a GLOBAL WRITE depending on the use of the WRITE control functions GW\ and BWE\ as well as the individual BYTE CONTOLS (BWx\). The AS5SP512K36DQ provides ease of producing very dense arrays via the multiple Chip Enable input pins and Tri-state outputs. Single Cycle Access Operations A Single READ operation is initiated when all of the following conditions are satisfied at the time of Clock (CLK) HIGH: [1] ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all asserted active, and [3] the WRITE signals (GW\, BWE\) are in their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. The address presented to the Address inputs is stored within the Address Registers and Address Counter/Advancement Logic and then passed or presented to the array core. The corresponding data of the addressed location is propagated to the Output Registers and passed to the data bus on the next rising clock via the Output Buffers. The time at which the data is presented to the Data bus is as specified by either the Clock to Data valid specification or the Output Enable to Data Valid spec for the device speed grade chosen. The only exception occurs when the device is recovering from a deselected to select state where its outputs are tristated in the first machine cycle and controlled by its Output Enable (OE\) on following AS5SP512K36DQ Rev. 2.6 01/10 Deep Power-Down Mode (SLEEP) The AS5SP512K36DQ has a Deep Power-Down mode and is controlled by the ZZ pin. The ZZ pin is an Asynchronous input and asserting this pin places the SSRAM in a deep powerdown mode (SLEEP). White in this mode, Data integrity is guaranteed. For the device to be placed successfully into this operational mode the device must be deselected and the Chip Enables, ADSP\ and ADSC\ remain inactive for the duration of tZZREC after the ZZ input returns LOW. Use of this deep power-down mode conserves power and is very useful in multiple memory page designs where the mode recovery time can be hidden. Micross Components reserves the right to change products or specifications without notice. 3 SSRAM AS5SP512K36DQ Synchronous Truth Table CE1\ H L L L L L L L X H X H X H X H CE2 X L X L X H H H X X X X X X X X CE3\ X X H X H L L L X X X X X X X X ADSP\ X L L X X L H H H X H X H X H X ADSC\ L X X L L X L L H H H H H H H H ADV\ X X X X X X X X L L L L H H H H WT / RD X X X X X X WT RD RD RD WT WT RD RD WT WT CLK Address Accessed NA NA NA NA NA External Address External Address External Address Next Address Next Address Next Address Next Address Current Address Current Address Current Address Current Address Operation Not Selected Not Selected Not Selected Not Selected Not Selected Begin Burst, READ Begin Burst, WRITE Begin Burst, READ Continue Burst, READ Continue Burst, READ Continue Burst, WRITE Continue Burst, WRITE Suspend Burst, READ Suspend Burst, READ Suspend Burst, WRITE Suspend Burst, WRITE Notes: 1. X = Don't Care 2. WT= WRITE operation in WRITE TABLE, RD= READ operation in WRITE TABLE Burst Sequence Tables Burst Control Pin [MODE] First Address State HIGH Case 1 A1 A0 0 0 1 1 Fourth Address Burst Control Pin [MODE] First Address Capacitance State LOW Case 1 A0 A1 0 0 1 1 Fourth Address Interleaved Burst Case 2 A1 A0 0 0 1 0 0 1 1 1 0 1 0 1 Linear Burst Case 2 A1 A0 0 1 1 0 Case 3 A1 1 0 1 0 Case 4 A0 1 1 0 0 A1 0 1 0 1 1 1 0 0 Case 3 A1 1 0 1 0 BW\ H L L L L L X Max. 5.0 5.0 5.0 Units pF pF pF 1 1 0 0 A1 0 1 0 1 1 0 0 1 Asynchronous Truth Table BWa\ X H L H H L X BWb\ X H H L H L X BWc\ X H H H L L X BWd\ X H H H L L X Operation READ READ WRITE Byte [A] WRITE Byte [B] WRITE Byte [C], [D] WRITE ALL Bytes WRITE ALL Bytes Parameter Voltage on VDD Pin Voltage on VDDQ Pins Voltage on Input Pins Voltage on I/O Pins Power Dissipation Storage Temperature Operating Temperatures [Screening Levels] Symbol VDD VDDQ VIN VIO PD tSTG /IT /ET /XT Operation Power-Down (SLEEP) READ WRITE De-Selected ZZ H L L L L OE\ X L H X X I/O Status High-Z DQ High-Z Din, High-Z High-Z AC Test Loads Absolute Maximum Ratings* Min. Max. -0.3 4.6 VDD Units Output V V -0.3 VDD+0.3 -0.3 VDDQ+0.3 V 1.6 W R C -65 150 -40 85 -40 105 -55 125 Rt = 50 ohm Zo=50 ohm V Diagram [A] Vt= Termination Voltage Rt= Termination Resistor R C R C 30 pF Vt= 1.50v for 3.3v VDDQ Vt= 1.25v for 2.5v VDDQ R C R= 317 ohm@3.3v R= 1667 ohm@2.5v *Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. AS5SP512K36DQ Rev. 2.6 01/10 Symbol CI CIO CCLK Case 4 A0 Write Table GW\ H H H H H H L Parameter Input Capacitance Input/Output Capacitance Clock Input Capacitance Output 3.3/2.5v 5 pF R= 351 ohm@3.3v R= 1538 ohm@2.5v Diagram [B] Micross Components reserves the right to change products or specifications without notice. 4 SSRAM AS5SP512K36DQ DC Electrical Characteristics (VDD=3.3v-5%/+10%, TA=Min. and Max temperatures of Screening level chosen Symbol VDD VDDQ VoH Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage Test Conditions 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA VoL Output Low Voltage VDD=Min., IOL=8mA VDD=Min., IOL=1mA VIH Input High Voltage VIL Input Low Voltage IIL IZZL IOL IDD Input Leakage (except ZZ) Input Leakage, ZZ pin Output Leakage Operating Current VDD=Max., VIN=VSS to VDD Output Disabled, VOUT=VSSQ to VDDQ Automatic CE, Power Down Current - TTL inputs CMOS Standby Max 3.630 VDD 0.4 0.4 VDD+0.3 VDD+0.3 0.8 0.7 5 30 5 350 300 275 Units V V V V V V V V V V uA uA uA mA mA mA 160 150 140 70 mA 80 mA 135 130 125 mA mA mA Typical Units Notes 1 1,5 1,4 1,4 1,4 1,4 1,2 1,2 1,2 1,2 3 3 Max VDD, De-Selected, 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz VIN>=VIH or VIN</=VIL f=fMAX=1/tCYC ISB2 2 1.7 -0.3 -0.3 -5 -30 -5 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz VDD=Max., f=Max., IOH=0mA ISB1 Min 3.135 2.375 2.4 2 Max. VDD, Device deselected, VIN </=0.3V or VIN>/=VDDQ-0.3V f=fMAX=1/tCYC ISB3 TTL Standby Device deselected; VDD=Max.; All Inputs </= VIL or VIH; All inputs static; CLK frequency = 0 ISB4 Clock Running Device deselected; 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz VDD=Max.; All inputs < VSS+0.2v or VDD-0.2v; Cycle time (tKC)= Min. Thermal Resistance Symbol Description Thermal Resistance (Junction to Ambient) TJA TJC Conditions Test Conditions follow standard test methods and Thermal Resistance procedures for measuring thermal impedance, as (Junction to Top of Case, Top) per EIA/JESD51 Notes 31 0 6 9 0 6 C/W 1-Layer C/W Notes: [1] [2] [3] [4] [5] [6] AS5SP512K36DQ Rev. 2.6 01/10 All Voltages referenced to VSS (Logic Ground) Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA Power-up: VIH <+3.6V and VDD<3.135V for t<200ms MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies. AC load current is higher than stated values, AC I/O curves can be made available upon request VDDQ should never exceed VDD, VDD and VDDQ can be connected together This parameter is sampled Micross Components reserves the right to change products or specifications without notice. 5 SSRAM AS5SP512K36DQ AC Switching Characteristics (VDD=3.3v-5%/+10%, TA=Min. and Max temperatures of Screening level chosen Parameter Clock (CLK) Cycle Time Clock (CLK) High Time Clock (CLK) Low Time Clock Access Time Clock (CLK) High to Output Low-Z Clock High to Output High-Z Output Enable to Data Valid Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Address Set-up to CLK High Address Hold from CLK High Address Status Set-up to CLK High Address Status Hold from CLK High Address Advance Set-up to CLK High Address Advance Hold from CLK High Chip Enable Set-up to CLK High (CEx\, CE2) Chip Enable Hold from CLK High (CEx\, CE2) Data Set-up to CLK High Data Hold from CLK High Write Set-up to CLK High (GW\, BWE\, BWx\) Write Hold from CLK High (GW\, BWE\, BWX\) ZZ High to Power Down ZZ Low to Power Up Symbol tCYC tCH tCL tCD tCLZ tCHZ tOE tOH tOELZ tOEHZ tAS tAH tASS tASH tADVS tADVH tCES tCEH tDS tDH tWES tWEH tPD tPU -30 [200Mhz] Max. Min. 5.00 2.00 2.00 3.00 1.25 1.25 3.00 3.00 1.55 0.00 3.00 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 1.40 0.40 2 2 -35 [166Mhz] Min. Max. 6.00 2.20 2.20 3.50 1.25 1.25 3.50 3.50 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 -40 [133Mhz] Min. Max. 7.50 2.50 2.50 4.00 1.25 1.25 3.50 4.00 1.25 0.00 3.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 1.50 0.50 2 2 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles cycles Notes 1 1 2 2,3,4,5 2,3,4,5 6 2,3,4,5 2,3,4,5 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 7,8 Notes to Switching Specifications: 1. 2. 3. 4. 5. 6. 7. 8. AS5SP512K36DQ Rev. 2.6 01/10 Measured as HIGH when above VIH and Low when below VIL This parameter is measured with the output loading shown in AC Test Loads This parameter is sampled Transition is measured +500mV from steady state voltage Critical specification(s) when Design Considerations are being reviewed/analyized for Bus Contentention OE\ is a Don't Care when a Byte or Global Write is sampled LOW A READ cycle is defined by Byte or Global Writes sampled LOW and ADSP\ is sampled HIGH for the required SET-UP and HOLD times This is a Synchronous device. All addresses must meet the specified SET-UP and HOLD times for all rising edges of CLK when either ADSP\ or ADSC\ is sampled LOW while the device is enabled. All other synchronous inputs must meet the SET-UP and HOLD times with stable logic levels for all rising edges of clock (CLK) during device operation (enabled). Chip Enable (Cex\, CE2) must be valid at each rising edge of clock (CLK) when either ADSP\ or ADSC\ is LOW to remain enabled. Micross Components reserves the right to change products or specifications without notice. 6 SSRAM AS5SP512K36DQ AC SWITCHING WAVEFORMS Write Cycle Timing Single Write Burst Write tCYC Pipelined Write tCH CLK tASS tASH tCL ADSP\ ADSP\ Ignored with CE1\ inactive ADSC\ tASS tASH ADV\ tADVS tADVH A1 Ax ADV\ Must be Inactive for ADSP\ Write A3 A2 tAS tAH GW\ tWES tWEH tWEH tWES BWE\, BWx\ tCES tCEH CE1\ Masks ADSP\ CE1\ CE2 CE3\ OE\ tDS tDH DQx,DQPx W1 W2a W2b W2c W2d W3 DON'T CARE UNDEFINED AS5SP512K36DQ Rev. 2.6 01/10 Micross Components reserves the right to change products or specifications without notice. 7 SSRAM AS5SP512K36DQ AC SWITCHING WAVEFORMS Read Cycle Timing Single Read Burst Read tCYC tCH Pipelined Read tCL CLK tASS tASH ADSP\ Ignored with CE1\ Inactive ADSP\ ADSC\ Initiated Read ADSC\ Suspend Burst ADV\ tADVS tADVH Ax A2 A1 tAS A3 tAH GW\ tWES tWEH BWE\, BWx\ tCES CE1\ Masks ADSP\ tCEH CE1\ Unselected with CE2 CE2 CE3\ OE\ tOEHZ tOE tCD DQx,DQPx R1 tOH R2a R2b R2c R2d R3a DON'T CARE UNDEFINED AS5SP512K36DQ Rev. 2.6 01/10 Micross Components reserves the right to change products or specifications without notice. 8 SSRAM AS5SP512K36DQ AC SWITCHING WAVEFORMS Read/Write Cycle Timing Pipelined Read Burst Read tCYC tCH tCL CLK tASS tASH ADSP\ ADSC\ ADV\ tADVS tADVH tAS Ax A1R A2W A3W A4R A5R tAH GW\ tWES tWEH BWE\, BWx\ tCES tCEH tCES tCEH CE1\ CE2 CE3\ OE\ tOEHZ tOE DQx,DQPx DON'T CARE A1O tOH A2I A4O [a] A3I A4O [b] A4O [c] A4O [d] tOELZ tCD UNDEFINED AS5SP512K36DQ Rev. 2.6 01/10 Micross Components reserves the right to change products or specifications without notice. 9 SSRAM AS5SP512K36DQ POWER DOWN (SNOOZE MODE) ORDERING INFORMATION Power Down or Snooze is a Power conservation mode which when building large/very dense arrays, using multiple devices in a multi-banked or paged array, can greatly reduce the Operating current requirements of your total memory array solution. Micross Part Number Configuration tCD (ns) Clock (Mhz) 3.0 3.5 4.0 200 166 133 3.0 3.5 4.0 200 166 133 3.5 4.0 166 133 Industrial Operating Range (-400C to +850C) AS5SP512K36DQ-30IT AS5SP512K36DQ-35IT AS5SP512K36DQ-40IT 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 0 0 Enhanced Operating Range (-40 C to +105 C) The device is placed in this mode via the use of the ZZ pin, an asynchronous control pin which when asserted, places the array into the lower power or Power Down mode. Awakening the array or leaving the Power Down (SNOOZE) mode is done so by deasserting the ZZ pin . AS5SP512K36DQ-30ET AS5SP512K36DQ-35ET AS5SP512K36DQ-40ET 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO 0 0 Extended Operating Range (-55 C to +125 C) AS5SP512K36DQ-35XT AS5SP512K36DQ-40XT 512Kx36, 3.3vCore/3.3,2.5vIO 512Kx36, 3.3vCore/3.3,2.5vIO While in the Power Down or Snooze mode, Data integrity is guaranteed. Accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. The device must be de-selected prior to entering the Power Down mode, all Chip Enables, ADSP\ and ADSC\ must remain inactive for the duration of ZZ recovery time (tZZREC). ZZ MODE ELECTRICAL CHARACTERISTICS ZZ MODE TIMING DIAGRAM MECHANICAL DIAGRAM 16.00 +/- 0.20mm 1.40 +/- 0.05mm 14.00 +/- 0.10mm 1.60mm Max. 20.00 +/- 0.10mm 22.00 +/- 0.20mm 0.30 +/- 0.08 100 Pin TQFP 14mm x 20mm JEDEC MS026-D/BHA 0.65mm TYP. See Detail A 1.00mm TYP. 0.10 +0.10/-0.05mm Detail A 0.10 Standoff 0.15 MAX 0.05 MIN AS5SP512K36DQ Rev. 2.6 01/10 Seating Plane 12 +/- 1 0.60 +/- 0.15mm Micross Components reserves the right to change products or specifications without notice. 10 SSRAM AS5SP512K36DQ DOCUMENT TITLE Plastic Encapsulated Microcircuit , 18Mb, 512K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect REVISION HISTORY Rev # 2.5 2.6 AS5SP512K36DQ Rev. 2.6 01/10 History Release Date Updated pinout on page one, updated September 2008 max ratings & DC Electrical Characteristics Updated Micross Information January 2010 Status Release Release Micross Components reserves the right to change products or specifications without notice. 11