LM5068
LM5068 Negative Voltage Hot Swap Controller
Literature Number: SNVS254B
LM5068
Negative Voltage Hot Swap Controller
General Description
The LM5068 hot-swap controller provides intelligent control
of power supply connections during the insertion and re-
moval of circuit cards powered by live system backplanes.
The LM5068 provides both in-rush current control and short-
circuit protection functions, and limits power supply tran-
sients in the backplane caused by the insertion of additional
circuit cards. The LM5068 controls the external N-Channel
MOSFET to provide programmable load current limiting and
circuit breaker functions using a single external current
sense resistor. The LM5068 issues a power good (PWRGD)
signal at the conclusion of a successful power-on sequence.
Input over-voltage or under -voltage fault conditions will can-
cel the PWRGD indication.
The LM5068-1 and -2 indicate power-good as an open-drain
active HIGH PWRGD state. The LM5068-3 and -4 indicate
power-good as an open-drain active LOW PWRGD state.
The LM5068-1 and -3 latch off after a fault condition is
detected while the LM5068-2 and -4 continuously re-try at
intervals set by a programmable timer.
The LM5068 is available in a MSOP-8 package.
Features
nSafe module insertion and removal from live backplanes
nIn-rush current limiting for safe board insertion into live
backplanes
nFast response to over-current fault conditions with active
current limiting
n-10V to -90V input range
nProgrammable under-voltage/over-voltage shutdown
protection with adjustable hysteresis
nProgrammable multi-function timer for board insertion
de-bounce delay
nFault timer avoids nuisance trips caused by short
duration load transients
nActive gate clamping during initial power application
nAvailable in both latched fault and automatic re-try
versions
nAvailable with either active HIGH or active LOW power
good flag
Applications
n- 48V Power Modules
nCentral Office Switching
nDistributed Power Systems
nElectronic Circuit Breaker
nPBX Systems
nNegative Power Supply Control
Typical Application
20078601
Negative Power Supply Control
December 2004
LM5068 Negative Voltage Hot Swap Controller
© 2004 National Semiconductor Corporation DS200786 www.national.com
Connection Diagram
20078602
Pin Description
PIN NAME DESCRIPTION APPLICATION INFORMATION
1 PWRGD Open Drain Power Good indicator Following a successful power-up sequence the PWRGD
signal will be active. The LM5068-1 and -2 are
configured for an active power-good state as HIGH,
while the LM5068-3 and –4 are configured for an active
power-good state as LOW.
2 OV Line Over-Voltage Shutdown An external resistor divider from the power source sets
the over-voltage shutdown level. Hysteresis is
generated by an internal current source which sources
20 µA into the external divider when the OV pin
exceeds 2.5V.
3 UV Line Under-Voltage Shutdown An external resistor divider from the power source sets
the under-voltage shutdown level. Hysteresis is set by
an internal current source which sinks 20 µA from the
external divider when the UV pin falls below 2.5V.
4V
EE
Negative Supply Voltage Input
5 SENSE Current Sense Input Load current is monitored via an external current sense
resistor (R
s
). If the voltage across R
s
exceeds 50mV the
fault timer is initiated. Load current is actively limited to
100mV/R
s
. If the sense voltage exceeds 200mV due to
a catastrophic fault, the fast gate pull down circuit will
reduce the MOSFET gate voltage and initiate active
current limiting.
6 GATE N-Channel MOSFET Gate Drive Output This output is pulled high by a 60 µA current source to
turn on the MOSFET.
7 TIMER Timer Input An external capacitor connected to this pin sets the
initial start-up delay and the delay to shutdown in the
event of an over-current condition. This pin is also used
for the automatic re-try timing sequence, following fault
shutdown (-2 and –4 versions).
8V
DD
Positive Supply Voltage Input
LM5068
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Configuration Table
Part Number Latch Off /Successive Re-try Power Good Polarity Package
LM5068MM-1/MMX-1 Latch Off Active HIGH MSOP- 8
LM5068MM-2/MMX-2 Auto Re-try Active HIGH
LM5068MM-3/MMX-3 Latch Off Active LOW
LM5068MM-4/MMX-4 Auto Re-try Active LOW
Ordering Information
Order Number Package Marking NSC Package Drawing Supplied As
LM5068MM-1 S66B
MUA08A
Available Soon
LM5068MMX-1 S66B Available Soon
LM5068MM-2 S67B 1000 Units on Tape and Reel
LM5068MMX-2 S67B 3500 Units on Tape and Reel
LM5068MM-3 S68B 1000 Units on Tape and Reel
LM5068MMX-3 S68B 3500 Units on Tape and Reel
LM5068MM-4 S69B 1000 Units on Tape and Reel
LM5068MMX-4 S69B 3500 Units on Tape and Reel
LM5068
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
DD
(V
DD
to V
EE
) 100V
PWRGD (PWRGD to V
EE
) 100V
SENSE (SENSE to V
EE
)8V
UV/OV (Clamped) (UV/OV to V
EE
)8V
All Other Inputs to V
EE
16V
Junction Temperature (T
J
) +150˚C
Storage Temperature (T
S
) -55˚C to +150˚C
Soldering Information
ESD Rating (Note 2) 2kV
Operating Ratings
Supply Voltage Range (V
DD
) 10V to 90V
Junction Temp. Range −40˚C to +105˚C
Electrical Characteristics
Specifications in standard typeface are for T
J
= +25˚C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise noted V
DD
−V
EE
= 48V.
Symbol Parameter Conditions Min Typ Max Units
V
DD
Supply
I
IN
Supply Current 0.82 1.3 mA
I
SD
Shutdown Current UV/OV = 0V 580 1000 µA
V
DD
−V
EE
Operating Supply Range 10 90 V
UV/OV Shutdown
V
UVS
V
DD
Under-voltage Shutdown 8.5 V
V
UVSH
V
DD
Under-voltage Shutdown
Hysteresis
0.6 V
V
UV
Under-voltage Comparator
Threshold
2.45 2.5 2.55 V
I
UVHCS
Under-voltage Hysteresis
Current Source
18 20 22 µA
V
OV
Over-voltage Comparator
Threshold
2.45 2.5 2.55 V
I
OVHCS
Over-voltage Hysteresis Current
Sink
18 20 22 µA
t
UVCD
UV Comparator Delay UV Low to Gate Low 1100 ns
t
OVCD
OV Comparator Delay OV High to Gate Low 500 ns
Current Limit Voltage
V
CB
Circuit Breaker Current Limit
Voltage
40 50 60 mV
V
AC
Analog Current Limit Voltage 80 100 120 mV
V
FDC
Fast Discharge Current Limit
Voltage (Fast Gate Pull Down
Threshold)
150 200 250 mV
Sense Input
I
SENSE
Sense Input Current V
SENSE
= 50mV -30 -15 µA
Timer
V
THVT
Timer High Voltage Threshold 4 V
V
TLVT
Timer Low Voltage Threshold 1V
I
TIMER
Timer On (Initial Cycle,
Sourcing)
V
TIMER
=2V 468µA
Timer Off (Initial Cycle, Sinking) V
TIMER
=2V 27 mA
Timer On (Circuit Breaker,
Sourcing)
V
TIMER
=2V 200 240 280 µA
Timer Off (Cooling Cycle,
Sinking)
V
TIMER
=2V 468µA
LM5068
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Electrical Characteristics (Continued)
Specifications in standard typeface are for T
J
= +25˚C, and those in boldface type apply over the full operating junction tem-
perature range. Unless otherwise noted V
DD
−V
EE
= 48V.
Symbol Parameter Conditions Min Typ Max Units
Gate Drive
V
G
Saturation Gate Drive Voltage V
DD
-V
EE
= 48V 910.6 12 V
V
DD
-V
EE
= 10V 7.8 V
V
GLT
Gate Low Threshold Before Gate ramp-up 0.5 V
I
GATE
Gate Pin Current (Sourcing) V
SENSE
=0V 40 60 80 µA
Gate Pin Current (Sinking) V
SENSE
= 150mV
V
GATE
=3V
2.7 mA
Gate Pin Current (Sinking) V
SENSE
= 300mV
V
GATE
=1V
300 mA
PWRGD
V
PGLV
PWRGD Low Voltage I
SINK
= 1mA 0.2 0.6 V
I
PGLC
PWRGD High Leakage Current V
PWRGD
= 90V 1 µA
V
PGV
GATE Voltage at onset of
PWRGD
8V
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The ESD rating of Pin 7 is 1.5kV. It is recommended that proper ESD precautions are taken to avoid performance degradation or loss of functionality.
LM5068
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Block Diagram
20078603
LM5068
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Typical Performance Characteristics
I
IN
vs Temperature I
IN
vs V
DD
20078632 20078633
V
DD
Under-Voltage Shutdown (V
UVS
) vs Temperature
V
DD
Under-Voltage Shutdown Hysteresis (V
UVSH
)vs
Temperature
20078634 20078635
Under-Voltage Comparator Threshold (V
UV
) and
Over-Voltage Comparator Threshold (V
OV
)vs
Temperature
Under-Voltage Comparator Threshold Hysteresis Current
Source (I
UVHCS
) vs Temperature
20078636 20078637
LM5068
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Typical Performance Characteristics (Continued)
Over-Voltage Comparator Threshold Hysteresis Current
Sink (I
OVHCS
) vs Temperature
UV Comparator Delay (t
UVCD
) and OV Comparator Delay
(t
OVCD
) vs Temperature
20078638 20078639
Circuit Breaker Current Limit Voltage (V
CB
)vs
Temperature Analog Current Limit Voltage (V
AC
) vs Temperature
20078640 20078641
Fast Discharge Current Limit Voltage (V
FDC
)vs
Temperature Timer High Voltage Threshold (V
THVT
) vs Temperature
20078642 20078643
LM5068
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Typical Performance Characteristics (Continued)
Timer Low Voltage Threshold (V
TLVT
) vs Temperature Timer On (Initial Cycle, Sourcing) vs Temperature
20078644 20078645
Timer On (Circuit Breaker, Sourcing) vs Temperature Timer Off (Cooling Cycle, Sinking) vs Temperature
20078647 20078648
Saturation Gate Drive Voltage (V
G
) vs Temperature (48V) Saturation Gate Drive Voltage (V
G
) vs Temperature
20078649
20078650
LM5068
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Typical Performance Characteristics (Continued)
Gate Pin Current (Sourcing) (I
GATE
) vs Temperature PWRGD Low Voltage (V
PGLV
) vs Temperature
20078652 20078655
Gate Voltage at onset of PWRGD (V
PGV
) vs Temperature
20078656
LM5068
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Function Description
The LM5068 is designed to facilitate the insertion and re-
moval of circuit cards into live backplanes in a controlled
manner. Because the supply bypass capacitors on the circuit
card can draw large transient currents, it is critical to control
the supply current during insertion to limit system power
glitches and connector damage. Controlling in-rush current
prevents other boards in the system from resetting during
board insertion. Load short-circuit protection is accom-
plished by active current limiting of the load current. The
topology of the LM5068 is illustrated in the simplified appli-
cation circuit shown in Figure 1.
Start-Up Operation
The LM5068 resides on a removable circuit card. Power is
applied to the load or power conversion circuitry through an
external N-Channel MOSFET switch and current sense re-
sistor.
When power is initially applied to the card, the gate of the
external MOSFET is held low. When certain interlock condi-
tions are met, a turn-on sequence begins and an internal 60
µA current source charges the gate of the MOSFET. To
initiate the start-up sequence, all of the following interlock
conditions must be satisfied:
•The input voltage V
DD
-V
EE
exceeds 9V(V
UVS
)
•The voltage at UV is above 2.5V (V
UV
)
•The voltage at OV falls below 2.5V (V
OV
)
•The voltage on the Timer capacitor (C
T
) is less than 1V
(V
TLVT
)
•The GATE pin is below 0.5V (V
GLT
)
When all of the interlock conditions are met,a6µATIMER
current source is enabled to charge the timer capacitor C
T
.
During this initial timer sequence the GATE output is held
low. When the C
T
capacitor successfully charges up to 4V,
the TIMER circuit resets the timer capacitor to 1V and acti-
vates a 60 µA current source (I
GATE
) into the MOSFET gate.
Over and Under-Voltage Lockout
The line Under-voltage lockout (UVLO) circuitry of the
LM5068 monitors V
DD
for under-voltage conditions, where
V
UVS
is the negative going threshold and the hysteresis is
V
UVSH
(see Electrical Characteristics). A V
DD
-V
EE
voltage
less than 8.5V (V
UVS
) keeps the controller in a disabled
mode. Raising the V
DD
voltage above 9.1V (V
UVS
+V
UVSH
)
releases the V
DD
UVLO and enables the controller.
In addition to the internal UVLO circuit, the UV and OV
comparators monitor the input line voltage through an exter-
nal resistor divider. Programmable UV and OV comparator
hysteresis is implemented with switched 20µA current
sources that raise or lower the OV and UV pins when the
comparators reach their threshold. Either UV or OV fault
conditions will switch the GATE pin low and disconnect the
power to the load. To restart the GATE pin, the supply
voltage must return to a level which is greater than the UV
fault and less than the OV fault threshold and all of the
interlock conditions (with the exception of the TIMER) must
be met.
Removal of the circuit card from the backplane initiates an
under-voltage condition. The series MOSFET is then dis-
abled to disconnect the source of power to the load. The
under-voltage threshold and hysteresis are programmed by
the external resistor divider connected to the UV pin.
Timer
The value of the C
T
capacitor sets the duration of the
LM5068’s timer delay and filter functions. There are four
charging and discharging modes:
1. 6µA slow charge for initial timing delay and post-fault
re-try timer (LM5068-2 and -4)
2. 240µA fast charge for circuit breaker delay.
3. 6µA slow discharge for circuit breaker "cool-off".
4. Low impedance switch to reset capacitor after initial
timing delay, input under-voltage lockout, and during
over-voltage and under-voltage initial timing.
Current Control
The LM5068 has three current sense thresholds which pro-
tect the backplane supply and circuit card from overload
20078604
FIGURE 1. LM5068 Topology
20078605
FIGURE 2. Hot Swap Controller
LM5068
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Current Control (Continued)
conditions. The voltage drop across the sense resistor (R
S
)
is monitored at the SENSE pin. The over-current protection
functions are determined through the following three distinct
thresholds at the SENSE pin:
1. Circuit Breaker (CB) threshold (typically 50mV)
2. Analog Current Limit (ACL) loop threshold (typically
100mV)
3. Fast Discharge Current (FDC) threshold (typically
200mV)
When the voltage drop across R
S
exceeds 50mV the Circuit
Breaker comparator indicates an over-load condition. The
TIMER sources 240µA into C
T
when SENSE exceeds 50mV
and sinks 6µA from C
T
when SENSE falls below 50mV. If the
C
T
capacitor ramps to a 4V threshold, a fault condition is
declared and the gate of the MOSFET is forced low, discon-
necting the power to the load.
Active Current Limiting (ACL) is activated when the voltage
across sense resistor R
S
reaches 100mV. The LM5068 con-
trols the gate of the MOSFET and maintains a constant
output load current equal to 100mV/ R
S
. In the ACL mode the
SENSE pin is greater than 50mV and the TIMER charges C
T
with 240µA. A fault will be declared if the LM5068 remains in
the ACL mode longer than the circuit breaker timer period.
Fast Discharge Current (FDC) responds to fast rising over-
loads such as short circuit faults. During a short circuit event
the fast rising current may overshoot past the ACL threshold
due to the finite response time of the ACL loop. If the SENSE
voltage reaches 200mV a fast discharge comparator quickly
pulls GATE pin low. The rapid response of the FDC circuit
assures a fast and safe transition to the ACL mode.
The LM5068 circuit breaker action filters low duty cycle
over-load conditions to avoid declaring a fault during short
duration load transients. The timer charges capacitor C
T
with
240µA when the SENSE voltage is greater than 50mV. When
the SENSE pin voltage falls below 50mV, a 6µA current
discharges the TIMER capacitor. Repetitive over-current
faults with duty cycle greater than 2.5% will eventually
charge C
T
and trip the fault timer. This feature protects the
pass MOSFET which has a fast heating and slow cooling
characteristic.
Latch-Off and Auto-Retry
If the fault conditions persist long enough for TIMER to
charge C
T
to 4V, the LM5068 latches off (LM5068-1, -3) or
switches off and initiates the re-try timer (LM5068-2, -4).
At the fault condition, after reaching the 4V, the TIMER pin
will continue to ramp-up with 6µA current source until it
reaches the internal regulated voltage, which is equivalent to
the saturation GATE drive voltage. The LM5068-1 and
LM5068-3 remains off until the controller is reset by either
temporarily pulling the UV pin low, pulling the TIMER pin
below 1 volt, or decreasing the input voltage below the
internal V
DD
under-voltage lockout (UVLO) threshold.
The LM5068-2 and LM5068-4 respond to a fault condition by
pulling the GATE and TIMER pins low and then initiating a
timer sequence for automatic re-try. The re-try timer se-
quence begins with C
T
capacitor being charged slowly to 4V
with a 6µA current source and then discharged quickly to 1V
with a 30mA discharge current. After 8 charge/discharge
cycles the GATE pin is released and charged with a 60µA
current source. If the fault condition persists, the LM5068 will
again turn off the MOSFET and another 8-cycle fault timer
sequence will begin.
Power Good Flag
The power good flag (PWRGD) is activated when the MOS-
FET GATE is fully enhanced (>8V) and the voltage input UV
and OV comparators are satisfied. The power good output is
a 90V capable open drain N-Channel MOSFET. The
LM5068-1 and LM5068-2 provide an active HIGH power-
good state, while the LM5068-3 and LM5068–4 are config-
ured for an active LOW power-good state. The UV compara-
tor, OV comparator, V
DD
UVLO, or a circuit breaker time-out
will reset the power good flag.
Internal Soft-Start
An internal soft-start feature ramps the (positive) input of the
analog current limit amplifier during initial start-up. The ramp
duration is approximately 200µs. This feature reduces the
load current slew rate (di/dt) at start-up.
Design Information
The LM5068 contains an internal regulator enabling the V
DD
pin to be connected directly to the line voltage from 10 to
90V. A local RC filter (0.1µF ceramic capacitor and 499Ω
resistor) connected between V
DD
and V
EE
is recommended
to filter supply transients that exceed the 100V Absolute
Maximum Rating.
UV and OV Thresholds and
Voltage Divider Selection for R1,
R2, and R3
Two comparators detect under-voltage and over-voltage
conditions at the UV and OV pins. The threshold voltages
(V
UV
,V
OV
) of the UV and OV comparators are nominally
2.5V. Hysteresis is accomplished by 20µA current sources
(I
UVHCS
), into the external resistor divider connected to the
UV and OV pins as shown in Figure 3
20078606
FIGURE 3. UV/OV Setting
LM5068
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UV and OV Thresholds and
Voltage Divider Selection for R1,
R2, and R3 (Continued)
Hysteresis is necessary to prevent a possible “chattering”
condition when the controller enables or disables the exter-
nal MOSFET. The change in line current interacts with the
line impedance. This interaction can cause several rapid
on/off cycles on the MOSFET. A hysteresis window larger
than the line impedance voltage drop prevents this condition.
The impedance seen looking into the resistor divider from
the UV and OV pin determines the hysteresis level. UV/OV
ON and OFF thresholds are calculated as follow:
The independent UV and OV pins provide complete flexibility
for the user to select the operational voltage range of the
system. However, due to the UV Abs Max rating, the UV and
OV thresholds can’t be simultaneously set to extremes in
one resistor string. For the wide ranges of input voltages (i.e.
UV threshold to12V and OV threshold to 90V) it is recom-
mended to use two separate voltage dividers to set the UV
and OV thresholds independently.
The typical operating ranges of under-voltage and over-
voltage thresholds are calculated from the above equations
with known resistors. For example, for resistor values:
R1=130KΩ, R2=5.5KΩ, and R3=4.5KΩ, the computed
thresholds are:
•UV turn-on = 37.60V
•UV turn-off = 35.0V
•OV turn-off = 77.78V
•OV turn-on = 75.07V
To maintain the threshold’s accuracy, a resistor tolerance of
1% or better is recommended.
Calculation of Normal, Circuit
Breaker, and Retry Timing
The C
T
capacitor at the TIMER pin controls the timing func-
tions of the LM5068. When the interlock conditions are met
the timer capacitor is charged to 4V in a slow initial delay
time period t
IDT
calculated from:
(1)
If the SENSE pin detects more than 50mV across R
S
, the
TIMER pin charges C
T
with 240µA. The Circuit Breaker
timeout period t
CBT
is calculated from:
(2)
When the LM5068-2 or LM5068-4 is latched, it pulls down
the GATE pin and initiates eight, 6µA charging cycles be-
tween 1V and 4V on C
T
. The total re-try time period t
RT
is
given by:
(3)
Sense Resistor (R
s
), Timer
Capacitor (C
T
) and N-Channel
Mosfet (Q1) Selection
To select the proper MOSFET, the following safe operating
area (SOA) parameters are needed: maximum input voltage,
maximum current and the maximum current conduction time.
First, R
S
is calculated for the maximum operating load cur-
rent (I
L(MAX)
) and the minimum circuit breaker trip point
(V
CB(MIN)
):
(4)
During the initial charging process, the LM5068 may operate
the MOSFET in current limit, forcing V
AC(MIN)
(80mV) to
VAC(MAX) (120mV) across R
S
.
The minimum in-rush current and maximum short-circuit limit
are calculated from:
(5)
(6)
The value of TIMER capacitor (C
T
) is calculated in order to
prevent C
T
from timing out before the load capacitor is fully
charged using the slowest expected charging rate of the load
capacitor. Assuming there is no initial resistive loading, the
time necessary to charge the load capacitor C
L
is calculated
from:
(7)
LM5068
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Sense Resistor (R
s
), Timer
Capacitor (C
T
) and N-Channel
Mosfet (Q1) Selection (Continued)
Applying Equation (5) and Equation (7) to Equation (2) gives
the TIMER capacitor value of:
(8)
Finally, the SOA curves of a prospective MOSFET are
checked using V
IN (MAX)
, and I
SHORT-CIRCUIT (MAX)
calculated
from equation Equation (6) and time of the current flow from
Equation (2).
Example: For: I
L
=1A, V
DD
= 48V, V
DD (MAX)
= 100V and
C
L
=100µF,
To account for tolerances of R
S
,C
L
, TIMER current and
TIMER threshold voltage, the computed C
T
value should be
increased, for this example 50% was selected, therefore:
C
T
= 300nF •1.5 = 450nF
The maximum active current limiting value and duration are:
(9)
(10)
The N-channel MOSFET selection for use with the LM5068
controller in this example must be capable of sustaining
V
DD
=100V and I
(MAX)
=3A for 7.5ms in the worst case fault
condition. A device that meets the established criteria is the
Vishay - 5UB85N10-10.
External Sense Resistor
Precise current measurement depends on the accuracy of
the sense resistor (R
S
). For the optimal results, Kelvin con-
nection and close location of R
S
to the LM5068 should be
considered. Figure 4 demonstrates PCB layout for the Kelvin
sensing.
The R
S
power rating should be greater than I
2L*
R, where I
L
is the normal maximum operating load.
20078623
FIGURE 4. Sense Resistor Connections
LM5068
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Timing Diagrams
Assuming all of the initial conditions are met, the power-up
sequence starts with Timer capacitor (C
T
) getting charged.
C
T
is charged with 6µA current source up to V
THVT
(4V) then
quickly discharge to V
TLVT
(1V). At time point (2) the 60µA
GATE current source is enabled. The GATE voltage in-
creases until the MOSFET starts conducting causing the
SENSE voltage to increase until Active Current Limiting is
activated (3). During the current limiting period (3-4), C
T
is
charged again, but there is not enough time to reach the 4V
threshold before the load capacitor is fully charged and the
SENSE voltage falls below V
CB
. The GATE continues to fully
enhance the MOSFET and activating the PWRGD when the
GATE voltage exceeds 8V.
20078625
FIGURE 5. System Power-Up Timing Behavior
LM5068
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Timing Diagrams (Continued)
UV drops below UV HIGH (time point 1) puts the controller
into a disabled mode. Later, UV increases over the UV LOW
threshold (time point 3), which initiates a system power-up
sequence.
20078626
FIGURE 6. Under-Voltage Timing Behavior
LM5068
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Timing Diagrams (Continued)
During normal operation, if the OV pin exceeds OV HIGH, as
shown at time point 1 in the above diagram, the TIMER
status is unaffected. The GATE and PWRGD ( for LM5068-1
& -2) pins are pulled low and the load is disconnected. At
time point 2, OV recovers and drops below the OV LOW
threshold, the GATE start-up cycle begins. If the load capaci-
tor is completely depleted during OV conditions, a full
start-up cycle is initiated.
20078627
FIGURE 7. Over-Voltage Timing Behavior
LM5068
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Timing Diagrams (Continued)
The above timing waveform shows the circuit breaker cur-
rent limit fault behavior. The timer capacitor is charged with
240µA when the SENSE pin exceeds V
CB
. If the SENSE pin
drops below V
CB
before the TIMER reaches V
THVT
, the timer
capacitor will be discharged with 6µA. In the above figure
when TIMER exceeds V
THVT
, GATE is pulled low immedi-
ately to disconnect power to the load.
20078628
FIGURE 8. Circuit Breaker Current Limit Fault
LM5068
www.national.com 18
Timing Diagrams (Continued)
The above diagram shows analog current limit behavior
when the SENSE pin voltage exceeds V
AC
for a period of
time, which activates the Analog Current Limit but never
reaches the fault timer threshold. At that time the GATE is
regulated by the analog current limit amplifier loop. When the
SENSE voltage falls below V
AC
, GATE is allowed to charge
with a 60µA current source. A compensation circuit consist-
ing of a resistor and a capacitor in series, connected be-
tween GATE and V
EE
stabilizes the current limit loop.
20078629
FIGURE 9. Analog Current Limit Fault
LM5068
www.national.com19
Timing Diagrams (Continued)
In case of a severe fault (for example sudden short-circuit of
the output load) the SENSE pin exceeds the V
FDC
threshold
and GATE immediately pulls down until the Active Current
Limit loop establishes control of the current in the MOSFET.
Careful selection of TIMER capacitor and MOSFET with
adequate current and voltage ratings will prevent damage to
MOSFET low impedance faults.
20078630
FIGURE 10. Fast Current Limit Fault
LM5068
www.national.com 20
Timing Diagrams (Continued)
Figure 11 shows the timer behavior for LM5068-2, -4 during
fault re-try time. During normal operation, whenever the
SENSE pin exceeds the 50mV, circuit breaker fault limit, the
timer capacitor begins to charge. If the TIMER pin voltage
exceeds 4V, the GATE is pulled down immediately, and
LM5068-2, -4 disconnects power to the load. The TIMER
starts the fault re-try cycle by discharging C
T
with 30mA to
the V
TLVT
threshold. The TIMER then charges C
T
with 6µA to
the V
THVT
threshold. After eight charging phases and nine
discharging phases, LM5068-2, -4 initiates an automatic
retry start-up cycle.
20078631
FIGURE 11. Shutdown Cooling Timing Behavior
LM5068
www.national.com21
Evaluation Board Schematic
20078657
PART VALUE PACKAGE DESCRIPTION PART NUMBER
C1 NOT USED
C2 NOT USED
C3 0.022uF/ 50V C0805 CAPACITOR, CERAMIC,KEMET C0805C223K5RAC
C4 0.33uF / 50V C0805 CAPACITOR,CERAMIC,KEMET C0805C334K5RAC
C5 100uF / 100V CAPACITOR, ALUMINIUM
ELECTROLYTIC, SURFACE
MOUNT,PANASONIC
EEV-FK2A101M
C6 0.1uF / 100V C1206 CAPACITOR, CERAMIC, TDK C3216X7R2A104KT
F1 10A FUSE SMD_FUSE COOPER BUSSMAN FAST
ACTING FUSE TRON
TR/SFT-10
(Digikey # 283-2439-2-ND)
J1 PCB terminal Blocks/ 10A MOUSER TERMINAL BLOCKS 651-1727010
J2 PCB terminal Blocks/ 10A MOUSER TERMINAL BLOCKS 651-1727010
Q1 100V / 60A N-Channel Power
MOSFET,TO263
VISHAY SUB85N10-10
R1 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F
R2 100K R1206 SMD RESISTOR, 1% TOL CRCW12061003F
R3 4.02K R0805 SMD RESISTOR, 1% TOL CRCW08053401F
R4 3.04K R0805 SMD RESISTOR, 1% TOL CRCW08053040F
R5 100K R0805 SMD RESISTOR, 1% TOL CRCW08051003F
R6 0 R0805 SMD RESISTOR, 1% TOL CRCW08050000F
R7 50m R2512 SMD RESISTOR, 1% TOL WSL-2512 .050F
R8 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F
R9 0 R1206 SMD RESISTOR, 1% TOL CRCW12060000F
R10 499 R1206 SMD RESISTOR, 1% TOL CRCW1206499RF
LM5068
www.national.com 22
Evaluation Board Schematic (Continued)
PART VALUE PACKAGE DESCRIPTION PART NUMBER
U1 LM5068 MSOP-8 National Semiconductor LM5068
20078660
20078661
LM5068
www.national.com23
20078662
20078673
LM5068
www.national.com 24
20078674
LM5068
www.national.com25
Physical Dimensions inches (millimeters) unless otherwise noted
Package Number MU08A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
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which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
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Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned
Substances’’ as defined in CSP-9-111S2.
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Email: new.feedback@nsc.com
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www.national.com
LM5068 Negative Voltage Hot Swap Controller
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