A3979SLPTR-T - Allegro Microsystems

AGND and PGND must be

connected together externally

Description

The A3979 is a complete microstepping motor driver with

built-in translator, designed as a pin-compatible replacement for

the successful A3977, with enhanced microstepping (1/16 step)

precision. It is designed to operate bipolar stepper motors in

full-, half-, quarter-, and sixteenth-step modes, with an output

drive capacity of up to 35 V and ±2.5 A. The A3979 includes a

fixed off-time current regulator that has the ability to operate in

Slow, Fast, or Mixed decay modes. This current-decay control

scheme results in reduced audible motor noise, increased step

accuracy, and reduced power dissipation.

The translator is the key to the easy implementation of the

A3979. It allows the simple input of one pulse on the STEP

pin to drive the motor one microstep, which can be either a full

step, half, quarter, or sixteenth, depending on the setting of the

MS1 and MS2 logic inputs. There are no phase-sequence tables,

high-frequency control lines, or complex interfaces to program.

The A3979 interface is an ideal fit for applications where a

complex microprocessor is unavailable or is overburdened.

Internal synchronous-rectification control circuitry is provided

to improve power dissipation during PWM operation. Internal

circuit protection includes: thermal shutdown with hysteresis,

UVLO (undervoltage lockout), and crossover-current

protection. Special power-on sequencing is not required.

The A3979 is supplied in a low-profile (height 1.20 mm),

28-pin TSSOP with exposed thermal pad. The package is lead

(Pb) free, with 100% matte tin leadframe plating.

26184.23E

Features and Benefits

 ±2.5 A, 35 V output rating

 Low RDS(On) outputs: 0.28  source, 0.22  sink, typical

 Automatic current decay mode detection/selection

 3.0 to 5.5 V logic supply voltage range

 Slow, Fast or Mixed current decay modes

 Home output

 Synchronous rectification for low power dissipation

 Internal UVLO and thermal shutdown circuitry

 Crossover-current protection

Microstepping DMOS Driver with Translator

Package: 28 lead TSSOP (suffix LP) with

exposed thermal pad

Pin-out Diagram

A3979

VCP

PGND

VREG

STEP

OUT2B

RESET

VBB2

PFD

RC1

AGND

REF

RC2

VDD

OUT2A

MS2

MS1

SENSE2

SENSE1

HOME

DIR

OUT1A

ENABLE

OUT1B

CP2

CP1

SLEEP

VBB1

Translator

and

Control

Logic

÷8

Reg

Charge

Pump

PWM

Timer

Not to scale

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Selection Guide

Part Number Packing

A3979SLPTR-T 4000 pieces per reel

Absolute Maximum Ratings

Load Supply Voltage VBB 35 V

Output Current IOUT

Output current rating may be limited by duty cycle,

ambient temperature, and heat sinking. Under any set of

conditions, do not exceed the specified current rating or a

junction temperature of 150°C.

±2.5 A

Logic Supply Voltage VDD 7.0 V

Logic Input Voltage Range VIN

tW > 30 ns –0.3 to VDD + 0.3 V

tW < 30 ns –1 to VDD + 1 V

Sense Voltage VSENSE 0.5 V

Reference Voltage VREF VDD V

Operating Ambient Temperature TARange S –20 to 85 °C

Junction Temperature TJ(max) 150 °C

Storage Temperature Tstg

–55 to 150 °C

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Functional Block Diagram

SENSE1

SENSE2

VREG

VCP

CP1

DAC

VDD

PWM Timer:

PWM Latch

Blanking

Mixed Decay

DAC

STEP

DIR

MS1

PWM Timer:

PWM Latch

Blanking

Mixed Decay

CP2

Charge

Pump

VBB1

OUT1A

OUT1B

VBB2

OUT2A

OUT2B

Translator

Gate

Drive

DMOS Full Bridge

0.22 µF

MS2

REF

RS2 CS2

RS1 CS1

0.22 µF

UVLO and

Fault

Logic

Supply

Reference

Supply

RESET

SLEEP

ENABLE

PFD

RC2

RC1

HOME

2 V

0.22 µF

Control

Logic

>47 µF

Load

Supply

RT2 CT2

RT1 CT1

VPFD

0.1 µF

Regulator

Bandgap

Exposed Thermal Pad

AGND PGND

(Required)

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 35 V, VDD = 3.0 to 5.5 V (unless otherwise noted)

Characteristics Symbol Test Conditions Min. Typ.1Max. Units

Output Drivers

Load Supply Voltage Range VBB

Operating 8 – 35 V

During Sleep mode 0 – 35 V

Output Leakage Current2IDSS

VOUT = VBB – <1.0 20 A

VOUT = 0 V – <1.0 –20 A

Output On Resistance RDS(On)

Source driver, IOUT = –2.5 A – 0.28 0.335 

Sink driver, IOUT = 2.5 A – 0.22 0.265 

Body Diode Forward Voltage VF

Source diode, IF = –2.5 A – – 1.4 V

Sink diode, IF = 2.5 A – – 1.4 V

Motor Supply Current IBB

fPWM < 50 kHz – – 8.0 mA

Operating, outputs disabled – – 6.0 mA

Sleep mode – – 20 A

Control Logic

Logic Supply Voltage Range VDD Operating 3.0 5.0 5.5 V

Logic Supply Current IDD

fPWM < 50 kHz – – 12 mA

Outputs off – – 10 mA

Sleep mode – – 20 A

Logic Input Voltage VIN(1) 0.7× V DD ––V

VIN(0) ––

0.3

×VDD V

Logic Input Current2IIN(1) VIN = 0.7 × VDD –20 <1.0 20 A

IIN(0) VIN = 0.3 × VDD –20 <1.0 20 A

Reference Input Voltage Range VREF Operating 0 – VDD V

Reference Input Current IREF –0±3A

HOME Output Voltage VHOME(1) IHOME(1) = –200 A0.7× V DD ––V

VHOME(0) IHOME(0) = 200 A––

0.3× V DD V

Mixed Decay Mode Trip Point VPFDH –0.6

×VDD –V

VPFDL –0.21×VDD –V

Gain (Gm) Error3EG

VREF = 2 V, Phase Current = 38.27% – – ±10 %

VREF = 2 V, Phase Current = 70.71% – – ±5.0 %

VREF = 2 V, Phase Current = 100.00% – – ±5.0 %

STEP Pulse Width tW1––s

Blank Time tBLANK RT = 56 k, CT = 680 pF 700 950 1200 ns

Fixed Off-Time tOFF RT = 56 k, CT = 680 pF 30 38 46 s

Crossover Dead Time tDT Synchronous rectification enabled 100 475 800 ns

Continued on the next page...

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

1Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for

individual units, within the specified maximum and minimum limits.

2Negative current is defined as coming out of (sourcing from) the specified device pin.

3EG = ( [ VREF

/ 8] – VSENSE ) / ( VREF

/ 8 ).

ELECTRICAL CHARACTERISTICS, continued at TA = 25°C, VBB = 35 V, VDD = 3.0 to 5.5 V (unless otherwise noted)

Thermal Shutdown Temperature TJSD – 165 – °C

Thermal Shutdown Hysteresis TJSDHYS –15–°C

UVLO Enable Threshold VUVLO Increasing VDD 2.45 2.7 2.95 V

UVLO Hysteresis VUVLOHYS 0.05 0.10 – V

Characteristics Symbol Test Conditions Min. Typ.1Max. Units

Characteristic Symbol Test Conditions* Value Units

Package Thermal Resistance RJA

Two-layer PCB with 3.8 in.2 of copper area on each side

connected with thermal vias and to device exposed pad 32 ºC/W

High-K PCB (multilayer with significant copper areas,

based on JEDEC standard) 28 ºC/W

*Additional thermal information available on Allegro Web site.

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Temperature (°C)

Power Dissipation, P

(W)

0.0

0.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

1.0

1.5

20 40 60 80 100 120 140 160

Maximum Power Dissipation, PD(max)

(RθJA = 32 ºC/W)

θJA

= 28 ºC/W)

High-K PCB

2-Layer PCB with 3.8 in2 copper per side

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Figure 1. Logic Interface Timing Diagram

Table 1. Microstep Resolution Truth Table

MS1 MS2 Microstep Resolution Excitation Mode

L L Full Step 2 Phase

H L Half Step 1-2 Phase

L H Quarter Step W1-2 Phase

H H Sixteenth Step 4W1-2 Phase

Timing Requirements

(TA = +25°C, VDD = 5 V, Logic Levels are VDD and Ground)

C D

50%

STEP

MS1/MS2/

DIR/RESET

Dwg. WP-042

SLEEP

A. Minimum Command Active Time

Before Step Pulse (Data Set-Up Time) ..... 200 ns

B. Minimum Command Active Time

After Step Pulse (Data Hold Time)............ 200 ns

C. Minimum STEP Pulse Width ...................... 1.0 μs

D. Minimum STEP Low Time ......................... 1.0 μs

E. Maximum Wake-Up Time ......................... 1.0 ms

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Functional Description

Device Operation. The A3979 is a complete micro-

stepping motor driver with a built-in translator for easy

operation with minimal control lines. It is designed to

operate bipolar stepper motors in full-, half-, quarter-, and

sixteenth-step modes. The currents in each of the two output

full-bridges (all of the N-channel MOSFETs) are regulated

with fixed off-time PMW (pulse width modulated) control

circuitry. At each step, the current for each full-bridge is

set by the value of its external current-sense resistor (RS1

or RS2), a reference voltage (VREF), and the output voltage

of its DAC (which in turn is controlled by the output of the

translator).

At power-on or reset, the translator sets the DACs and the

phase current polarity to the initial Home state (shown in

figures 2 through 5), and the current regulator to Mixed

decay mode for both phases. When a step command signal

occurs on the STEP input, the translator automatically

sequences the DACs to the next level and current polarity.

(See table 2 for the current-level sequence.) The microstep

resolution is set by the combined effect of inputs MS1 and

MS2, as shown in table 1.

While stepping is occurring, if the next output level of the

DACs is lower than the immediately preceeding output

level, then the decay mode (Fast, Slow, or Mixed) for the

active full bridge is set by the PFD input. If the next DAC

output level is higher than or equal to the preceeding level,

then the decay mode for that full bridge will be Slow decay.

This automatic current-decay selection improves microstep-

ping performance by reducing the distortion of the current

waveform due to back EMF of the motor.

RESET Input ( ¯R¯ ¯E¯ ¯S¯ ¯E¯ ¯T¯ ). The ¯R¯ ¯E¯ ¯S¯ ¯E¯ ¯T¯ input (active

low) sets the translator to a predefined Home state (shown

in figures 2 through 5), and turns off all of the DMOS out-

puts. The HOME output goes low and all STEP inputs are

ignored until the ¯R¯ ¯E¯ ¯S¯ ¯E¯ ¯T¯ input is set to high.

Home Output (HOME). The HOME output is a logic

output indicator of the initial state of the translator. At

power-on, the translator is reset to the Home state (shown in

figures 2 through 5).

Step Input (STEP). A low-to-high transition on the

STEP input sequences the translator and advances the motor

one increment. The translator controls the input to the DACs

and the direction of current flow in each winding. The size

of the increment is determined by the combined state of

inputs MS1 and MS2 (see table 1).

Microstep Select (MS1 and MS2). The input on

terminals MS1 and MS2 selects the microstepping format,

as shown in table 1. Any changes made to these inputs do not

take effect until the next rising edge of a step command signal

on the STEP input.

Direction Input (DIR). The state of the DIR input deter-

mines the direction of rotation of the motor. Any changes

made to this input does not take effect until the next rising

edge of a step command signal on the STEP input.

Internal PWM Current Control. Each full bridge is

controlled by a fixed–off-time PWM current-control circuit

that limits the load current to a desired value, ITRIP

. Initially,

a diagonal pair of source and sink MOS outputs are enabled

and current flows through the motor winding and the current

sense resistor, RSx. When the voltage across RSx equals the

DAC output voltage, the current-sense comparator resets the

PWM latch. The latch then turns off either the source MOS-

FETs (when in Slow decay mode) or the sink and source

MOSFETs (when in Fast or Mixed decay mode).

The maximum value of current limiting is set by the selec-

tion of RS and the voltage at the VREF input with a transcon-

ductance function approximated by:

ITRIPmax = VREF/8RS

The DAC output reduces the VREF output to the cur-

rent-sense comparator in precise steps (see table 2 for

% ITRIPmax at each step).

ITRIP = (% ITRIPmax/100) ITRIPmax

It is critical that the maximum rating (0.5 V) on either the

SENSE1 and SENSE2 pins is not exceeded. For full step-

ping, VREF can be applied up to the maximum rating of VDD

because the peak sense value is 0.707 × VREF / 8. In all other

modes, VREF should not exceed 4 V.

Functional Description

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Fixed Off-Time. The internal PWM current-control cir-

cuitry uses a one-shot timer to control the duration of time

that the MOSFETs remain off. The one shot off-time, tOFF,

is determined by the selection of external resistors, RTx , and

capacitors, CTx , connected from each RCx timing terminal to

ground. The off-time, over a range of values of CT = 470 pF

to 1500 pF and RT = 12 k to 100 k is approximated by:

tOFF = RTCT

RC Blanking. In addition to the fixed off-time of the

PWM control circuit, the CTx component sets the compara-

tor blanking time. This function blanks the output of the

current-sense comparators when the outputs are switched

by the internal current-control circuitry. The comparator

outputs are blanked to prevent false overcurrent detection

due to reverse recovery currents of the clamp diodes, or to

switching transients related to the capacitance of the load.

The blank time tBLANK can be approximated by:

tBLANK = 1400CT

Charge Pump (CP1 and CP2). The charge pump is

used to generate a gate supply greater than that of VBB for

driving the source-side DMOS gates. A 0.22 F ceramic

capacitor should be connected between CP1 and CP2 for

pumping purposes. In addition, a 0.22 F ceramic capacitor

is required between VCP and VBB, to act as a reservoir for

operating the high-side DMOS gates.

VREG (VREG). This internally-generated voltage is used to

operate the sink-side DMOS outputs. The VREG pin must

be decoupled with a 0.22 F capacitor to ground. VREG is

internally monitored, and in the case of a fault condition, the

DMOS outputs of the device are disabled.

Enable Input (¯E¯ ¯N¯ ¯A¯ ¯B¯ ¯L¯ ¯E¯ ). This active-low input

enables all of the DMOS outputs. When set to a logic high,

the outputs are disabled. The inputs to the translator (STEP,

DIR, MS1, and MS2), all remain active, independent of the

¯E¯ ¯N¯ ¯A¯ ¯B¯ ¯L¯ ¯E¯ input state.

Shutdown. During normal operation, in the event of a

fault, such as overtemperature (excess TJ) or an undervolt-

age on VCP, the outputs of the device are disabled until the

fault condition is removed.

At power up, and in the event of low VDD, the undervoltage

lockout (UVLO) circuit disables the drivers and resets the

translator to the Home state.

Sleep Mode ( ¯S¯ ¯L¯ ¯E¯ ¯E¯ ¯P¯ ). This active-low control input

is used to minimize power consumption when the motor is

not in use. It disables much of the internal circuitry includ-

ing the output DMOS FETs, current regulator, and charge

pump. Setting this to a logic high allows normal operation,

as well as start-up (at which time the A3979 drives the

motor to the Home microstep position). When bringing the

device out of Sleep mode, in order to allow the charge pump

(gate drive) to stabilize, provide a delay of 1 ms before issu-

ing a step command signal on the STEP input.

Percent Fast Decay Input (PFD). When a STEP

input signal commands a lower output current than the

previous step, it switches the output current decay to either

Slow, Fast, or Mixed decay mode, depending on the voltage

level at the PFD input. If the voltage at the PFD input is

greater than 0.6 × VDD , then Slow decay mode is selected.

If the voltage on the PFD input is less than 0.21 × VDD , then

Fast decay mode is selected. Mixed decay mode is selected

when VPFD is between these two levels, as described in

the next section. This terminal should be decoupled with a

0.1 F capacitor.

Mixed Decay Operation. If the voltage on the PFD input

is between 0.6 × VDD and 0.21 × VDD , the bridge operates

in Mixed decay mode, as determined by the step sequence

(shown in figures 2 through 5). As the trip point is reached,

the device goes into Fast decay mode until the voltage

on the RCx terminal decays to the same level as voltage

applied to the PFD terminal. The time that the device oper-

ates in fast decay is approximated by:

tFD = RTCTln (0.6VDD/VPFD)

After this Fast decay portion, the device switches to Slow

decay mode for the remainder of the fixed off-time period.

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Synchronous Rectification. When a PWM off-

cycle is triggered by an internal fixed–off-time cycle, load

current recirculates according to the decay mode selected

by the control logic. The A3979 synchronous rectification

feature turns on the appropriate MOSFETs during the decay

of the current, and effectively shorts out the body diodes

with the low RDS(On) driver. This reduces power dissipation

significantly and eliminates the need for external Schottky

diodes for most applications. The synchronous rectification

can be set to either Active mode or Disabled mode:

• Active Mode. When the SR input is logic low, Active

mode is enabled and synchronous rectification can occur.

This mode prevents reversal of the load current by turning

off synchronous rectification when a zero current level is

detected. This prevents the motor winding from conduct-

ing in the reverse direction.

• Disabled Mode. When the SR input is logic high, syn-

chronous rectification is disabled. This mode is typi-

cally used when external diodes are required to transfer

power dissipation from the A3979 package to the external

diodes.

Layout. The printed circuit board on which the device is

mounted should have a heavy ground plane. For optimum

electrical and thermal performance, the A3979 should be

soldered directly onto the board.

The load supply terminals, VBBx, should be decoupled with

an electrolytic capacitor (>47 F is recommended), placed

as close to the device as possible.

To avoid problems due to capacitive coupling of the high

dv / dt switching transients, route the bridge-output traces

away from the sensitive logic-input traces.

Always drive the logic inputs with a low source impedance

to increase noise immunity.

Grounding. The AGND (analog ground) terminal and the

PGND (power ground) terminal must be connected together

externally.

All ground lines should be connected together and be as

short as possible. A star ground system, centered under the

device, is an optimum design.

The copper ground plane located under the exposed thermal

pad is typically used as the star ground.

Current Sensing. To minimize inaccuracies caused by

ground-trace IR drops in sensing the output current level,

the current-sense resistors, RSx, should have an independent

ground return to the star ground of the device. This path

should be as short as possible.

For low-value sense resistors, the IR drops in the printed cir-

cuit board sense resistor traces can be significant and should

be taken into account.

The use of sockets should be avoided as they can introduce

variation in RSx due to their contact resistance.

Allegro MicroSystems recommends a value of RS given by

RS = 0.5/ITRIPmax

Thermal Protection. This internal circuitry turns off

all drivers when the junction temperature reaches 165°C,

typical. It is intended only to protect the device from failures

due to excessive junction temperatures and should not imply

that output short circuits are permitted. Thermal shutdown

has a hysteresis of approximately 15°C.

Applications Information

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

0.00

100.00

92.39

70.71

38.27

–38.27

–70.71

–92.39

–100.00

0.00

100.00

92.39

70.71

38.27

–38.27

–70.71

–92.39

–100.00

Phase 2

IOUT2B

Direction = H

(%)

Phase 1

IOUT1A

Direction = H

(%)

Home Microstep Position

Slow Mixed Slow

Slow Mixed

Slow Mixed Slow MixedMixed

Slow

STEP Input

HOME Output

Home Microstep Position

100.00

70.71

–70.71

0.00

–100.00

100.00

70.71

–70.71

0.00

–100.00

Phase 2

IOUT2B

Direction = H

(%)

Phase 1

IOUT1A

Direction = H

(%)

Slow

Mixed

Slow

Mixed

Slow

Mixed

Slow

Mixed

Slow

Mixed

Slow

STEP Input

HOME Output

Phase 2

IOUT2A

Direction = H

(%)

Phase 1

IOUT1A

Direction = H

(%)

STEP Input

Home Microstep Position

100.00

70.71

–70.71

0.00

–100.00

100.00

70.71

–70.71

0.00

–100.00

Slow

HOME Output

Figure 4. Decay Modes for Quarter-Step Increments

Figure 3. Decay Modes for Half-Step IncrementsFigure 2. Decay Mode for Full-Step Increments

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Figure 5. Decay Modes for Sixteenth-Step Increments

MixedSlow MixedSlow

MixedSlow Slow

Slow

100.00

95.69

88.19

83.15

–83.15

77.30

70.71

63.44

55.56

47.14

38.27

29.03

19.51

9.8

0.00

–100.00

–95.69

–88.19

–77.30

–70.71

–63.44

–55.56

–47.14

–38.27

–29.03

–19.51

–9.8

100.00

95.69

88.19

83.15

–83.15

77.30

70.71

63.44

55.56

47.14

38.27

29.03

19.51

9.8

0.00

–100.00

–95.69

–88.19

–77.30

–70.71

–63.44

–55.56

–47.14

–38.27

–29.03

–19.51

–9.8

Phase 2

IOUT2B

Direction = H

(%)

Phase 1

IOUT1A

Direction = H

(%)

Home Microstep Position

Mixed

STEP Input

HOME Output

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Table 2. Step Sequencing Settings

Home microstep position at Step Angle 45º; DIR = H; 360° = 4 full steps

Full

Step

Half

Step

1/4

Step

1/16

Step

Phase 1

Current

[% ItripMax]

(%)

Phase 2

Current

[% ItripMax]

(%)

Step

Angle

(º)

Full

Step

Half

Step

1/4

Step

1/16

Step

Phase 1

Current

[% ItripMax]

(%)

Phase 2

Current

[% ItripMax]

(%)

Step

Angle

(º)

1 1 1 100.00 0.00 0.0 5 9 33 –100.00 0.00 180.0

2 99.52 9.80 5.6 34 –99.52 –9.80 185.6

3 98.08 19.51 11.3 35 –98.08 –19.51 191.3

4 95.69 29.03 16.9 36 –95.69 –29.03 196.9

2 5 92.39 38.27 22.5 10 37 –92.39 –38.27 202.5

6 88.19 47.14 28.1 38 –88.19 –47.14 208.1

7 83.15 55.56 33.8 39 –83.15 –55.56 213.8

8 77.30 63.44 39.4 40 –77.30 –63.44 219.4

1 2 3 9 70.71 70.71 45.0 3 6 11 41 –70.71 –70.71 225.0

10 63.44 77.30 50.6 42 –63.44 –77.30 230.6

11 55.56 83.15 56.3 43 –55.56 –83.15 236.3

12 47.14 88.19 61.9 44 –47.14 –88.19 241.9

4 13 38.27 92.39 67.5 12 45 –38.27 –92.39 247.5

14 29.03 95.69 73.1 46 –29.03 –95.69 253.1

15 19.51 98.08 78.8 47 –19.51 –98.08 258.8

16 9.80 99.52 84.4 48 –9.80 –99.52 264.4

3 5 17 0.00 100.00 90.0 7 13 49 0.00 –100.00 270.0

18 –9.80 99.52 95.6 50 9.80 –99.52 275.6

19 –19.51 98.08 101.3 51 19.51 –98.08 281.3

20 –29.03 95.69 106.9 52 29.03 –95.69 286.9

6 21 –38.27 92.39 112.5 14 53 38.27 –92.39 292.5

22 –47.14 88.19 118.1 54 47.14 –88.19 298.1

23 –55.56 83.15 123.8 55 55.56 –83.15 303.8

24 –63.44 77.30 129.4 56 63.44 –77.30 309.4

2 4 7 25 –70.71 70.71 135.0 4 8 15 57 70.71 –70.71 315.0

26 –77.30 63.44 140.6 58 77.30 –63.44 320.6

27 –83.15 55.56 146.3 59 83.15 –55.56 326.3

28 –88.19 47.14 151.9 60 88.19 –47.14 331.9

8 29 –92.39 38.27 157.5 16 61 92.39 –38.27 337.5

30 –95.69 29.03 163.1 62 95.69 –29.03 343.1

31 –98.08 19.51 168.8 63 98.08 –19.51 348.8

32 –99.52 9.80 174.4 64 99.52 –9.80 354.4

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Terminal List Table

Number Name Description

1 SENSE1 Sense resistor for Bridge 1

2 HOME Logic Output

3 DIR Logic input

4 OUT1A Output A for Bridge 1

5 PFD Mixed decay setting

6 RC1 Analog input for fixed off-time for Bridge 1

7 AGND Analog Ground

8 REF Current trip reference voltage input

9 RC2 Analog input for fixed off-time for Bridge 2

10 VDD Logic supply

11 OUT2A Output A for Bridge 2

12 MS2 Logic input

13 MS1 Logic input

14 SENSE2 Sense resistor for Bridge 2

15 VBB2 Load supply for Bridge 2

16 SR Logic input

17 ¯R¯ ¯E¯ ¯S¯ ¯E¯ ¯T¯ Logic input

18 OUT2B Output B for Bridge 2

19 STEP Logic input

20 VREG Regulator decoupling

21 PGND Power Ground

22 VCP Reservoir capacitor

23 CP1 Charge pump capacitor 1

24 CP2 Charge pump capacitor 2

25 1OUT1B Output B for Bridge 1

26 ¯E¯ ¯N¯ ¯A¯ ¯B¯ ¯L¯ ¯E¯ Logic input

27 ¯S¯ ¯L¯ ¯E¯ ¯E¯ ¯P¯ Logic input

28 VBB1 Load supply for Bridge 1

DMOS Microstepping Driver with Translator

A3979

Allegro MicroSystems, Inc.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

LP Package, 28-pin TSSOP

1.20 MAX

0.10 MAX

SEATING

PLANE

C0.10

28X

6.10

0.65

0.45

1.65

3.00

5.00

0.25

0.65

GAUGE PLANE

SEATING PLANE

ATerminal #1 mark area

For reference only

(reference JEDEC MO-153 AET)

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances; when

mounting on a multilayer PCB, thermal vias at the exposed thermal pad land

can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

Exposed thermal pad (bottom surface)

4.40 ±0.10 6.40 ±0.20

(1.00)

9.70 ±0.10

0.60 ±0.15

4° ±4

0.15 +0.05

–0.06

0.25 +0.05

–0.06

The products described here are manufactured under one or more U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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