OKI Semiconductor MSC23408C/CL-xxDS8 4,194,304-Word x 8-Bit DRAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The OK] MSC23408C/CL-xxDS8 is a fully decoded 4,194,304-word x 8-bit CMOS Dynamic Random Access Memory Module composed of eight 4-Mb DRAMs (4M x 1) in SOJ packages mounted with eight decoupling capacitors on a 30-pin glass epoxy single-inline package. This module is generally used for non-parity memory expansion applications such as fax machines, printers and personal computers. The low-power version (CL) offers reduced powerconsumption for mobile computing applications like laptops and palmtops. FEATURES 4-Meg x 8-bit organization * 30-Pin Socket Insertable Module MSC23408C /CL-xxDS8 : Solder tab * Single 5 V supply 10% tolerance * Access times : 60, 70, 80 ns Input : TTL compatible Output : TTL compatible, 3-state * Refresh : 1024 cycles /16 ms (128 ms : L-version) * CAS before RAS refresh, CAS before RAS hidden refresh, RAS-only refresh capability * Multi-bit test mode capability Fast Page Mode capability PRODUCT FAMILY Family Access Time (Max.} Cycle Time Power Dissipation trac | taa | toac (Min.} Operating (Max.)| Standby (Max.) MSC23408C/CL-600S8 60ns | 30ns | 15ns 110 ns 4400 mW 4.4 mW/ MSC23408C/CL-70D88 7Ons | 35ns | 20n5 130 ns 3960 mW a8 mi (L-version) MSC23408C/CL-B0DS8 80ns | 40ns | 200s 150 ns . 3520 mW 27MSC23408C/CL-xxDS8 OKI Semiconductor PIN CONFIGURATION MSC23408C/CL-xxDS8 * 1 2 88.9 20.2 5.28 Max. 3.38 Typ. 82.14 Typ. ' $3.18 rT Pewye 20.45 Max. Ps ue b oe VET y i 2.54 Mi -') 6.35 1 MAnnnnnAnoMmnanonoaonnn onnAnnnAnAM 30 . In. 2.03 Typ. | | 5.59 Typ. 1p e 2.54 +0.1 4.78 Typ. 1.27 +0.4 **" 0.08 73,66 1 The common size difference of the board width 12.5 mm of its height is Specified as 20.2. The value above 12.5 mm is specitied as +0.5. Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 Veo 11 Ad 21 WE 2 CAS 12 AS 22 Vss 3 DQO 13 DQ3 23 DQ6 4 AO 14 A6 24 NC 5 Al 15 Ay 25 0Q7 6 Dai 16 pa4 26 NC 7 A2 V7 Ag 27 RAS 8 Ag 18 AQ 28 NC 9 Ves 19 Aid 29 NG 10 DQ2 20 DQ5 a0 Voc 28OKI Semiconductor MSC23408C/CL-xxDS8 BLOCK DIAGRAM AO - A10 RAS TAS pao WE oa1 ba2 DQ3 004 ba5 DQ6 DQ? Vec Vsg 29MSC23408C/CL-xxDS8 OKI Semiconductcr ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to Vss Vin, Vour -1.0to 7.0 V Voltage Voc Supply Relative to Vss Vee -1,0t0 7.0 V Short Circuit Output Current los 50 mA Power Dissipation Po 8 Ww Operating Temperature Topr Oto 70 * Storage Temperature Tatg 40 to 125 c Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Ta = 0C to 70C) Parameter Symbol Min. Typ. Max. Unit Voc 45 5.0 5.5 V Power Supply Voltage PP 9 Vss 0 0 0 Vv Input High Voltage Vin 24 _ 6.5 V Input Low Voltage Vie -1.0 _ 0.8 V Capacitance {Ta = 25C, tf = 1 MHz} Parameter Symbol Typ. Max. Unit Input Capacitance (AQ - A10) Cia _ 57 pF Input Capacitance (RAS, CAS, WE) Cina 65 pF \/0 Capacitance (DQO - DQ?) Coo _ 19 pF Note: Capacitance measured with Boonton Meter. 30OKI Semiconductor DC Characteristics MSC23408C/CL-xxDS8 (Voc = 5 V 210%, Ta = 0C to 70C) MSC23408C/CL| MSC23408C/CL/ MSC23408C/CL Parameter Symbol Condition -60DS8 -70DS8 -800S8 Unit |Note Min. | Max. | Min. | Max. | Min. | Max. OV Vis 6.5V; input Leakage Current lu | Allother pins not | 86 80 -80 80 -80 80 | pA under test = 0 V Output Leakage Current | tpg | COvr disable -20 | 20 | -20| 20 | -20] 20 | pa OVS Vo s5.5V Output High Voltage Von | lon =~5:0 mA 2.4 Vec 2.4 | Vec 24 | Veo ft V Output Low Voltage Vor j lop = 4.2 mA 0 0.4 0 0.4 0 0.4 Vv Average Power . Supply Current tecy | PAS CAS eveling, |___Fan | | zon | | ego | mal 1.2 . tac = Min. (Operating) Power Supply RAS, CAS = Vin _ 16 _ 16 - 16 | mA| 1 Current (Standby) lece | RAS, CAS j{ 8 {| ] @ | ~] 8 imal 2>VecO.2V _ 1.6 _ 1.6 _ 1.6 | mA} 1,5 Average Power RAS cycling, Supply Current lee | CAS = Vin, | 800) | 720 | | 640 | mA! 1,2 (RAS-only Refresh) tac = Min. ; Average Power RAS cycling, Supply Current lccs | GAS before RAS, 1 800; | 720 | | 640 | mA/ 1,2 (CAS betore RAS Refresh) tac = Min, Average Power RAS = Vit, Supply Current lec? | CAS cycling, | 640) | 560 | | 480 | mA) 1,3 (Fast Page Mode) tec = Min. Average Power tre = 125 ps, 12 Supply Current Ioc10 CAS before | 24} | 24 | 24 | mA 4, 5 (Battery Backup) RAS cycling Notes: 1. Specified values are obtained with the output open. . ae oN L-version Address can be changed once or less while RAS=Vj_. Address can be changed once or less while CAS=V)y. Veco - 0.2 V < Vip $6.5 V,-10V s Vip <0.2 V. 31MSC23408C/CL-xxDS8 AC Characteristics (4/2) OKI Semiconductor (Voc = 5 V 210%, Ta = OC to 70C) Note 1,2,3,9.10 IMSC23408C/CL|MSC23408C/CL|MSC23408C/CL Parameter Symbol -60DS8 -70DS8 -80DS8 Unit! Note Min. | Max.) Min. | Max.| Min. | Max, Random Read or Write Cycle Time tee | 110 _ 130 _ 160 ns Fast Page Mode Cycle Time tec 40 45 _ 50 _ ns Access Time from RAS trac | 60 70 80 ns 14.5.6 Access Time from CAS teac | 15 _ 20 20 | ns| 4.5 Access Time from Column Address taa ~ 30 _ 35 40 ns | 46 Access Time from CAS Precharge tepa | 35 40 45 | as} 4 Output Low Impedance Time from CAS tez | 0 0 0 | nm] 4 Output Buffer Turn-oft Delay Time torr 0 15 0 20 0 20 ns | 7 Transition Time tt 3 50 3 50 3 50 ns 3 Refresh Period tpep | 16 _ 16 _ 16 ms Retresh Period (L-version) ther | 128 _ 128 _ 128 | ms RAS Precharge Time tae | 40 50 _ 60 | nos RAS Pulse Width taas | 60 | 10K | 70 | 10K | B80 | 10K | os RAS Pulse Width (Fast Page Mode) taasp| 60 | 100K | 70 | 100K | 80 | 100K | ns RAS Hold Time tasy | 15 _ 20 _ 20 _ ns CAS Precharge Time tep 10 _ 10 10 | os CAS Pulse Width teas | 15 10K | 20 10K 20 | 10K | ns TAS Hold Time tee | 60 | | 70 | | 80 | | os TAS to RAS Precharge Time tear | 5 _ 5 _ 5 | os RAS to CAS Delay Time taco | 20 45 20 50 20 60 ns | RAS to Column Address Delay Time trap 15 30 16 35 15 40 ns 6 Row Address Set-up Time tasr 0 _ 0 _ 0 _ ns Row Address Hold Time tray 10 _ 10 _ 10 _ ns Column Address Set-up Time lasc 0 _ 0 _ 0 ns Column Address Hold Time teay 15 _ 15 _ 15 _ ns Column Address Hold Time from RAS tan | 50 55 60 ng Column Address to RAS Lead Time tra, | 30 _ 95 _ 40 | ns 32OKI Semiconductor AC Characteristics (2/2) MSC23408C/CL-xxDS5 (Veg = 5 V 210%, Ta =0C to 70C) Note 1,2,3,9,10 MSC23408C/CLIMS23408C/CL| MSC23408C/CL Parameter Symbo! -60DS8 -70D58 -80DS8 Unit | Note Min. | Max.| Min. | Max. | Min. | Max. Read Command Set-up Time tres 0 - _ 0 _ 0 _ ns Read Command Hold Time trcu 0 _ 0 _ 0 _ ns 8 Read Command Hold Time reterenced to RAS | tan | 0 0 = 0 |nsi 8 Write Command Set-up Time twes 0 _ 0 _ 0 _ ns Write Command Hold Time tweh | 10 _ 10 _ 10 jos Write Command Hold Time from RAS twen | 45 | 50 60 | - | as Write Command Pulse Width twp 10 _ 10 _ 10 _ ns. Write Command to RAS Lead Time taw. | 15 | 20 20 | | ns Write Command to CAS Lead Time towL 15 20 _ 20 _ ns Data-in Set-up Time tos 0 _ 0 _ 0 _ ns Data-in Hold Time tou 15 _ 16 _ 15 _ ns Data-in Hold Time from RAS tpyn | 50 | 55 _ 60 | | ns CAS Active Delay Time from RAS Precharge! trpc 5 _ 5 _ 5 | ns RAS to CAS Set-up Time (CAS before RAS)| tesr 5 5 5 I/nos RAS to CAS Hold Time (CAS before RAS) | tenn | 10 | 10 _ 10 | | ns CAS Precharge Time (Refresh Counter Fest}| tcptr | 30 _ 35 _ 40 | ns WE to RAS Precharge Time (CAS before RAS)| twee | 10 | | 10 | 10 | | ns WE Hold Time from RAS (CAS before RAS)| twrn | 10 _ 10 _ 10 | as RAS to WE Set-up Time (Fest Mode) tws | 10 |] | 10 | | 10 | | os RAS to WE Hold Time (Test Mode) twry | 10 10 10 | ns 33MSC23408C/CL-xxDS8 Notes: OE1 Semiconductor 1. A start-up delay of 200 ps is required after power-up followed by a minimum of * 10. eight initialization cycles (RAS-only refresh ar CAS before RAS refresh) betore proper device operation is achieved. When using the internal refresh counter, a minimum of eight CAS before RAS initialization cycles is required. AC mesurement assume ty = 5 ns. Vin (Min.) and V1, (Max.) are reference levels for measuring input timing signals. Transition times are measured between Vjy and Vj,. . Measured with a load circuit equivalent to 2 TTL loads and 100 pF. . Operation within the tpcp (Max.) limit ensures that trac (Max.) can be met. trcp (Max.) is specified as areference point only. If tpcpis greater than the specified tpcp (Max.) limit, access time is controlled by tcac. Operation within the trap (Max.) limit ensures that tpac (Max.) can be met. trap (Max.) is specified as a reference point only. Iftpapis greater than the specified trap (Max.) limit, access time is controlled by tas. torr (Max.) defines the time at which the output achieves an open circuit condition and is not referenced to output voltage levels. trcH or tprH must be satisfied for a read cycle. , The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is an 8-bit parallel test function. RA10, CA10 and CAO are not used. Ina read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. Ina test mode read cycle, the access time parameters are delayed by 5 ns. The test mode parameters are obtained by adding 5 ns to the normal read cycle values. See ADDENDUM E for AC Timing Waveforms