ICS84330CYLN - Integrated Circuit Systems, Inc.

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

GENERAL DESCRIPTION

The ICS84330C is a general purpose, single out-

put high frequency synthesizer and a member of

the HiPerClockS™ family of High Performance

Clock Solutions from ICS. The VCO operates at a

frequency range of 250MHz to 700MHz. The VCO

and output frequency can be programmed using the serial or

parallel interfaces to the configuration logic. The output can be

configured to divide the VCO frequency by 1, 2, 4, and 8. Output

frequency steps from 250KHz to 2MHz can be achieved using

a 16MHz crystal depending on the output divider setting.

FEATURES

•Fully integrated PLL, no external loop filter requirements

•1 differential 3.3V LVPECL output

•Crystal oscillator interface: 10MHz to 25MHz

•Output frequency range: 31.25MHz to 700MHz

•VCO range: 250MHz to 700MHz

•Parallel or serial interface for programming M and N dividers

during power-up

•RMS Period jitter: 5ps (maximum)

•Cycle-to-cycle jitter: 40ps (maximum)

•3.3V supply voltage

•0°C to 70°C ambient operating temperature

•Pin compatible with the MC12430

•Lead-Free package available

•Industrial temperature information available upon request

HiPerClockS™

ICS

PIN ASSIGNMENT

BLOCK DIAGRAM

ICS84330C

28-Lead PLCC

V Package

11.6mm x 11.4mm x 4.1mm

body package

Top View

25 24 23 22 21 20 19

5 6 7 8 9 10 11

S_CLOCK

S_DATA

S_LOAD

VCCA

FREF_EXT

XTAL_SEL

XTAL1

nP_LOAD

XTAL2

VEE

TEST

VCC

VEE

nFOUT

FOUT

VCC

OSC

XTAL1

XTAL2

FREF_EXT

XTAL_SEL

S_LOAD

S_DATA

S_CLOCK

nP_LOAD

M0:M8

N0:N1

VCO

PLL

TEST

CONFIGURATION

INTERFACE

LOGIC

÷ M

÷ 16

PHASE DETECTOR ÷2

÷4

÷8

÷1

÷ 2

FOUT

nFOUT

ICS84330C

32-Lead LQFP

Y package

7mm x 7mm x 1.4mm

body package

Top View

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

n/c

S_CLOCK

S_DATA

S_LOAD

VCCA

FREF_EXT

XTAL_SEL

XTAL1

nP_LOAD

XTAL2

VEE

TEST

VCC

VEE

nFOUT

FOUT

VCC

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

N0 through N1 is passed directly to the M divider and N output

divider. On the LOW-to-HIGH transition of the nP_LOAD input,

the data is latched and the M divider remains loaded until the

next LOW transition on nP_LOAD or until a serial event occurs.

The TEST output is Mode 000 (shift register out) when operat-

ing in the parallel input mode. The relationship between the VCO

frequency, the crystal frequency and the M divider is defined as

follows:

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock are

defined as 125 ≤ M ≤ 350. The frequency out is defined as

follows:

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the

shift register are loaded into the M divider when S_LOAD tran-

sitions from LOW-to-HIGH. The M divide and N output divide

values are latched on the HIGH-to-LOW transition of S_LOAD.

If S_LOAD is held HIGH, data at the S_DATA input is passed

directly to the M divider on each rising edge of S_CLOCK.

The serial mode can be used to program the M and N bits and

test bits T2:T0. The internal registers T2:T0 determine the state

of the TEST output as follows in the table below:

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes op-

eration using a 16MHz crystal. Valid PLL loop divider values

for different crystal or input frequencies are defined in the In-

put Frequency Characteristics, Table 6, NOTE 1.

The ICS84330C features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A quartz crystal is used as the input to the on-chip

oscillator. The output of the oscillator is divided by 16 prior to

the phase detector. With a 16MHz crystal this provides a 1MHz

reference frequency. The VCO of the PLL operates over a

range of 250MHz to 700MHz. The output of the M divider is

also applied to the phase detector.

The phase detector and the M divider force the VCO output fre-

quency to be 2M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too

high or too low), the PLL will not achieve lock. The output of the

VCO is scaled by a divider prior to being sent to each of the LVPECL

output buffers. The divider provides a 50% output duty cycle.

The programmable features of the ICS84330C support two in-

put modes to program the M divider and N output divider. The

two input operational modes are parallel and serial.

Figure 1

shows the timing diagram for each mode. In parallel mode the

nP_LOAD input is LOW. The data on inputs M0 through M8 and

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

16 2M

fVCO = fxtal x

fout =fVCO =16

2Mfxtal xN

T2 T1 T0 TEST Output

0 0 0 Shift Register Out

0 0 1 High

0 1 0 PLL Reference Xtal ÷ 16

0 1 1 (VCO ÷ M) /2 (non 50% Duty Cycle M divider)

1 0 0 fOUT

LVCMOS Output Frequency < 200MHz

1 0 1 Low

1 1 0 (S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)

1 1 1 fOUT ÷ 4

fOUT

S_CLOCK ÷ N divider

fOUT

Time

ERIAL

OADING

ARALLEL

OADING

M, N

T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

emaNepyTnoitpircseD

ACC

rewoP.nipylppusgolanA

2LATX,1LATX .tupnirotallicsonasi1LATX.ecafretnirotallicsolatsyrC

.tuptuorotallicson

asi2LATX

LES_LATXtupnIpulluP

ecnereferLLPehtsastupniTXE_FERFrorotallicsolatsyrcehtneewtebstceleS

.WOLnehwTXE_FERFstceleS.HGIHnehwstupniLATXstceleS.ecruos

.slevelecafretniLTTVL/SOMCVL

EOtupnIpulluP.slevelecafretni

LTTVL/SOMCVL.elbanetuptuO

DAOL_PntupnIpulluP

otnidedaolsi0M:8MtatneserpatadnehwsenimreteD.tupnidaollellar

.eulavedividtuptuoNehtstes0N:1Ntatneserpatadnehwdna,redividM

.slevelecafretniLTTVL/SOMCVL

2M,1M,0M

5M,

4M,3M

8M,7M,6M

tupnIpulluP .tupniDAOL_PnfonoitisnartHGIH-ot-WOLnodehctalataD.stupniredividM

.slevelecafret

niLTTVL/SOMCVL

1N,0NtupnIpulluP .elbaTnoitcnuFC3elbaTnidenifedsaeulavredividtuptuoNsenimreteD

.slevelecafr

etniLTTVL/SOMCVL

rewoP.snipylppusevitageN

TSETtuptuO .noitarepofoedomlairesehtnidesusihcihwtuptuotseT

.slevelecafretniLCEPV

Ldedne-elgniS

rewoP.snipylppuseroC

TUOF,TUOFntuptuO .slevelecafretniLCEPVLV3.3.rezisehtnysehtroftuptuolaitnereffiD

cndesu

nU.tcennocoN

TXE_FERFtupnInwodlluP.slevelecafretniLTTVL/SOMCVL.tupniecnereferLLP

KCOLC_StupnInwodlluP ehtnoret

sigertfihsehtotnitupniATAD_StatneserpatadlairesehtskcolC

.slevelecafretniLTTVL/SOMCVL.KCOLC_Sfoegdegni

sir

ATAD_StupnInwodlluP .KCOLC_SfoegdegnisirehtnodelpmasataD.tupnilairesretsigertfihS

.slevelecafretniLTTVL/SOMCVL

DAOL_StupnInwodlluP .redividMehtotniretsigertfihsmorfatadfonoitisnartslortnoC

.slevelecafretniLTT

VL/SOMCVL

:ETON

pulluP

dna

nwodlluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15KΩ

NWODLLUP

rotsiseRnwodlluPtupnI 15KΩ

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE

TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE

TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE

stupnI snoitidnoC

DAOL_PnMNDAOL_SKCOLC_SATAD_S

XXXX X X .HGIHtesllaerastibNdnaM.teseR

LataDataDX X X dnaredividMotyltceriddessa

pstupniNdnaMnoataD

.000edomTSET.redividtuptuoN

↑ataDataDX X X dedaolsniamerdnasretsigertupniotnidehctalsiataD

sruccotnevelairesalitnuronoitisnartWOLtxenlitnu

HXXL ↑ataD noatadhtiwdedaolsiretsigertfihS.edomtupnilaireS

.KCOLC_SfoegdegnisirhcaenoATAD_S

HXX

↑LataD redividMehtotdessaperaretsigertfihsehtfostnetnoC

.redividtuptuoNd

HXX↓LataD.dehctaleraseulavedividtuptuoNdnaedividM

HXXL X X .sretsigertfihstceffatonodtupnilairesrolellaraP

HXXH ↑ataD.d

ekcolcsitisaredividMotyltceriddessapATAD_S

WOL=L:ETON

HGIH=H

eract'noD=X

↑noitisnartegdegnisiR=

↓noitisnar

tegdegnillaF=

ycneuqerFOCV

)zHM( ediviDM 6528214623618421

8M7M6M5M4M3M2M1M0M

052521 00 111110 1

252621 00 1111110

452721 00 111110 1

652821 0 100000 10

• • •••••••••

696843 10 10 11100

896943 10 10 1110 1

007053 10 10 11110

.zHM61foycneuqerflatsyr

caotdnopserrocseicneuqerfgnitluserehtdnaseulavedividMesehT:1ETON

stupnI eulaVrediviDN )zHM(ycneuqerFtuptuO

1N0NmuminiMmumixaM

00 2 521053

01 4 5.26571

10 8 52.135.78

11 1 052007

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

1ETON;egatloVhgiHtuptuOV

4.1-V

0.1-V

1ETON;egatloVwoLtuptuOV

0.2-V

7.1-V

GNIWS

gniwSegatloVtuptuOkaeP-ot-kaeP 6.00.1V

05htiwdetanimretstuptuO:1ETON ΩVot

.V2-

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ACC

egatloVylppuSgolanA 531.33.3564.3V

tnerruCylppuSrewoP 061Am

ACC

tnerruCylppuSgolanA 61Am

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI 2V

3.0+V

egatloVwoLtupnI 3.0-8.0V

tnerruChgiHtupnI

,1N,0N,8M-0M

,DAOL_Pn,EO

LES_LATX

V564.3=5Aµ

KCOLC_S,DAOL_S

ATAD_S,TXE_FERF V

V564.3=051Aµ

tnerruCwoLtupnI

,1N,0N,8M-0M

,DAOL_Pn,EO

LES_LATX

V,V564.3=

V0=051-Aµ

KCOLC_S,DAOL_S

ATAD_S,TXE_FERF V

V,V564.3=

V0=5-Aµ

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

CC 4.6V

Inputs, VI-0.5V to VCC + 0.5 V

Outputs, IO

Continuous Current 50mA

Surge Current 100mA

Package Thermal Impedance, θJA 37.8°C/W (0 lfpm)

Storage Temperature, T

STG -65°C to 150°C

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ycneuqerFtupnI

1ETON;LATX0152zHM

KCOLC_S 05zHM

2ETON;TXE_FERF01zHM

ycneuqerfOCVmumixamromuminimehteveihcaotteseb

tsumeulavMehtegnarycneuqerflatsyrcehtroF:1ETON

002eraMfoseulavdilav,zHM01foycneuqerfmuminimehtgnisU.zH

M007otzHM052foegnar ≤M≤.115

08eraMfoseulavdilav,zHM52foycneuqerfmumixamehtgnisU ≤M≤.422

noitacilppAeeS.sn

oitatimilretnuocMlanretniehtnotnednepedsiTXE_FERFnoycneuqerfmumixaM:2ETON

.tupniTXE_FERFehtgnisuecnamr

ofrepehtgnizimitponosnoitadnemmocerrofnoitceSnoitamrofnI

TABLE 5. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 0152zHM

)RSE(ecnatsiseR

seireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 007zHM

)rep(tij2,1ETON;SMR,rettiJdoireP 5sp

)cc(tij2,1ETON;rettiJelcyC-ot-elcyC 04sp

emiTllaF/esiRtuptuO%08ot%02002006sp

emiTputeS

KCOLC_SotATAD_S02sn

DAOL_SotKCOLC_S02sn

DAOL_PnotN,M02sn

emiTdloH KCOLC_SotATAD_S02sn

DAOL_PnotN,M02sn

emiTkcoLLLP 01sm

cdoelcyCytuDtuptuO 5455%

.noitcesnoitamrofnItnemerusaeMretemaraPeeS

.tupniLATXagnisudeziretca

rahC

56dradnatSCEDEJhtiwecnadroccanidenifedsiretemarapsihT:1ETON

.noitcessnoitacilppAeeS:2ETON

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

PARAMETER MEASUREMENT INFORMATION

SCOPE

nQx

LVPECL

CYCLE-TO-CYCLE JITTER

PERIOD JITTER

3.3V OUTPUT LOAD AC TEST CIRCUIT

-1.3V ± 0.165V

FOUT

➤

OUTPUT RISE/FALL TIME

jit(cc) =

cycle n –

cycle n+1

1000 Cycles

cycle n

cycle n+1

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

VOH

VREF

VOL

Mean Period

(First edge after trigger)

Reference Point

(Trigger Edge)

1σ contains 68.26% of all measurements

2σ contains 95.4% of all measurements

3σ contains 99.73% of all measurements

4σ contains 99.99366% of all measurements

6σ contains (100-1.973x10-7)% of all measurements

Histogram

nFOUT

Pulse Width

PERIOD

odc =

FOUT

nFOUT

Clock

Outputs 20%

80% 80%

20%

SWING

VCC,

VCCA

VEE

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

- 2V

50Ω50Ω

RTT

= 50Ω

FOUT FIN

RTT = Z

((V

+ V

) / (V

– 2)) – 2

3.3V

125Ω125Ω

84Ω84Ω

Zo = 50Ω

FOUT FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

FIGURE 3B. LVPECL OUTPUT TERMINATIONFIGURE 3A. LVPECL OUTPUT TERMINATION

drive 50Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion.

Figures 3A and 3B

show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

TERMINATION FOR LVPECL OUTPUTS

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS84330C provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VCC and VCCA

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 2

illustrates how

a 10Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each VCCA pin. FIGURE 2. POWER SUPPLY FILTERING

10Ω

VCCA

10µF

.01µF

3.3V

.01µF

VCC

POWER SUPPLY FILTERING T ECHNIQUES

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

200 300 600 700400 500

Output Frequency (MHz)

Cycle-to-Cycle Jitter (ps)

N = 1

Spec Limit

LVCMOS TO XTAL INTERFACE

The XTAL1 input can accept single ended LVCMOS signal

through an AC couple capacitor. A general interface diagram

is shown in

Figure 4.

The XTAL2 input can be left floating. The

edge rate can be as slow as 10ns. If the incoming signal has

sharp edge rate and the signal path is a long trace, proper

termination for the driver and controlled characteristic imped-

Crystal Input Interfac

XTAL1

XTAL2

0.1uF

LVCMOS_Driver

VDD

Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE

ance trace may be required. The input can function with half

swing amplitude. Reducing amplitude from full swing of 3.3V

to half swing of about 1.65V can prevent signal interfere with

power rail and may reduce noise. Please refer to the LVCMOS

driver data sheet and application note for amplitude reduction

and termination approach.

FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

The schematic of the ICS84330C layout example used in

this layout guideline is shown in

Figure 6A.

The ICS84330C

recommended PCB board layout for this example is shown

Figure 6B.

This layout example is used as a general guide-

LAYOUT GUIDELINE

FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT

line. The layout in the actual system will depend on the

selected component types, the density of the components,

the density of the traces, and the stack up of the P.C. board.

0.1u

nPLoad

VCCA

0.1uF

SP = Space (i.e. not intstalled)

Fout = 200 MHz

RU0

nPLOAD

Zo = 50 Ohm

VCC

N[1:0] =00 (Divide by 2)

ICS84330

VCCA

FREF_EXT

XTA L_S E L

XTA L 1

XTAL2

nP_LOAD

VEE

TEST

S_DATA

S_CLOCK

VCC

FOUT

nFOUT

VEE

VCC

S_LOAD

VCC

RD9

VCC=3.3V

RU7

RU1

RD7

Zo = 50 Ohm

RU10

VCC

RD10

C11

0.01u

RU11

RU9

16MHz, 18pF

RU8

RD6

RU12

RD12

RD1

RD0

C16

10u

RD8

M[8:0]= 110010000 (400)

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

FIGURE 6B. PCB BOARD LAYOUT FOR ICS84330C

The following component footprints are used in this layout

example:

All the resistors and capacitors are size 0603.

POWER AND GROUNDING

Place the decoupling capacitors C3 and C4, as close as pos-

sible to the power pins. If space allows, placement of the

decoupling capacitor on the component side is preferred. This

can reduce unwanted inductance between the decoupling

capacitor and the power pin caused by the via.

Maximize the power and ground pad sizes and number of vias

capacitors. This can reduce the inductance between the power

and ground planes and the component power and ground pins.

The RC filter consisting of R7, C11, and C16 should be placed

as close to the VCCA pin as possible.

CLOCK TRACES AND TERMINATION

Poor signal integrity can degrade the system performance or

cause system failure. In synchronous high-speed digital systems,

the clock signal is less tolerant to poor signal integrity than other

signals. Any ringing on the rising or falling edge or excessive ring

back can cause system failure. The shape of the trace and the

trace delay might be restricted by the available space on the board

and the component location. While routing the traces, the clock

signal traces should be routed first and should be locked prior to

routing other signal traces.

• The differential 50Ω output traces should have the

same length.

• Avoid sharp angles on the clock trace. Sharp angle

turns cause the characteristic impedance to change on

the transmission lines.

• Keep the clock traces on the same layer. Whenever pos-

sible, avoid placing vias on the clock traces. Placement

of vias on the traces can affect the trace characteristic

impedance and hence degrade signal integrity.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace

widths between the differential clock trace and the other

signal trace.

• Make sure no other signal traces are routed between the

clock trace pair.

• The matching termination resistors should be located as

close to the receiver input pins as possible.

CRYSTAL

The crystal X1 should be located as close as possible to the pins

4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and

U1 should be kept to a minimum to avoid unwanted parasitic in-

ductance and capacitance. Other signal traces should not be

routed near the crystal traces.

Signals

Traces

VCCA

VCC

50 Ohm

Traces

C11

GND

PIN 2

PIN 1

C16

VIA

VCCA

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the

jitter performance can be improved by reducing the amplitude

swing and slowing down the edge rate.

Figure 7A

shows an

amplitude reduction approach for a long trace. The swing will

be approximately 0.85V for logic low and 2.5V for logic high

100

VDD

100

Ro ~ 7 Ohm

Driver_LVCMOS

Zo = 50 Ohm

VDD

GND

TEST_CLK

VDD

GND

TEST_CLK

200

100

Ro ~ 7 Ohm

Driver_LVCMOS

200

VDD

400

Ro ~ 7 Ohm

Driver_LVCMOS

200

VDD

GND

TEST_CLK

JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT

(instead of 0V to 3.3V).

Figure 7B

shows amplitude reduction

approach for a short trace. The circuit shown in

Figure 7C

reduces amplitude swing and also slows down the edge rate

by increasing the resistor value.

FIGURE 7C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE

FIGURE 7A. AMPLITUDE REDUCTION FOR A LONG TRACE

FIGURE 7B. AMPLITUDE REDUCTION FOR A SHORT TRACE

FREF_EXT

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 9A. THERMAL RESISTANCE θθ

θθ

θJA FOR 28-PIN PLCC, FORCED CONVECTION

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 9B. THERMAL RESISTANCE θθ

θθ

θJA FOR 32-PIN LQFP, FORCED CONVECTION

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS84330C.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS84330C is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 176mA = 609.8mW

•Power (outputs)MAX = 30.2mW/Loaded Output pair

If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW

Total Power_MAX (3.465V, with all outputs switching) = 609.8 + 30.2mW = 640mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA

must be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W per Table 9A below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.640W * 31.1°C/W = 89.9°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in the

Figure 8.

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V

- 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 1.0V

(VCC_MAX - VOH_MAX

) = 1.0V

• For logic low, VOUT = VOL_MAX = VCC_MAX

– 1.7V

(VCC_MAX - VOL_MAX

) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOH_MAX) = [(2V - (V

CC_MAX - VOH_MAX

))/R

] * (VCC_MAX

- VOH_MAX) =

[(2V - 1V)/50Ω] * 1V = 20.0mW

Pd_L = [(VOL_MAX

– (VCC_MAX

- 2V))/R

] * (VCC_MAX

- VOL_MAX) = [(2V - (V

CC_MAX - VOL_MAX

))/R

] * (VCC_MAX

- VOL_MAX) =

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW

FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION

VOUT

VCC

VCC - 2V

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

0 200 500

Multi-Layer PCB, JEDEC Standard Test Boards 37.8°C/W 31.1°C/W 28.3°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS84330C is: 4498

TABLE 10A. θJAVS. AIR FLOW 28 LEAD PLCC TABLE

θθ

θJA by Velocity (Linear Feet per Minute)

θθ

θJA by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TABLE 10B. θJAVS. AIR FLOW 32 LEAD LQFP TABLE

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC

NOITAIRAVCEDEJ

SRETEMILLIMNISNOISNEMIDLLA

LOBMYSMUMINIMMUMIXAM

N82

A91.475.4

1A 92.250.3

2A 75.111.2

b33.035.0

c91.023

D23.2175.21

1D 34.1185.11

2D 58.465.5

E23.2175.21

1E 34.1185.11

2E 58.465.5

TABLE 11A. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-018

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

TABLE 11B. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-026

NOITAIRAVCEDEJ

SRETEMILLIMNISNOISNEMIDLLA

LOBMYS

ABB

MUMINIMLANIMONMUMIXAM

N23

A----06.1

1A 50.0--51.0

2A 53.104.154.1

b03.073.054.0

c90.0--02.0

DCISAB00.9

1D CISAB00.7

2D .feR06.5

ECISAB00.9

1E CISAB00.7

2E .feR06.5

eCISAB08.0

L54.006.057.

θθ

θθ 0

-- 7

ccc ----01.0

PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

TABLE 12. ORDERING INFORMATION

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While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

84330CV www.icst.com/products/hiperclocks.html REV. B DECEMBER 7, 2004

Integrated

Circuit

Systems, Inc.

ICS84330C

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

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