Single-Supply, Rail-to-Rail, Low Cost
Instrumentation Amplifier
AD623
Rev. D
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©1997–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Easy to use
Higher performance than discrete design
Single-supply and dual-supply operation
Rail-to-rail output swing
Input voltage range extends 150 mV below
ground (single supply)
Low power, 550 μA maximum supply current
Gain set with one external resistor
Gain range: 1 (no resistor) to 1000
High accuracy dc performance
0.10% gain accuracy (G = 1)
0.35% gain accuracy (G > 1)
10 ppm maximum gain drift (G = 1)
200 μV maximum input offset voltage (AD623A)
2 μV/°C maximum input offset drift (AD623A)
100 μV maximum input offset voltage (AD623B)
1 μV/°C maximum input offset drift (AD623B)
25 nA maximum input bias current
Noise: 35 nV/√Hz RTI noise @ 1 kHz (G = 1)
Excellent ac specifications
90 dB minimum CMRR (G = 10); 70 dB minimum CMRR (G = 1)
at 60 Hz, 1 kΩ source imbalance
800 kHz bandwidth (G = 1)
20 μs settling time to 0.01% (G = 10)
APPLICATIONS
Low power medical instrumentation
Transducer interfaces
Thermocouple amplifiers
Industrial process controls
Difference amplifiers
Low power data acquisition
GENERAL DESCRIPTION
The AD623 is an integrated single-supply instrumentation
amplifier that delivers rail-to-rail output swing on a 3 V to 12 V
supply. The AD623 offers superior user flexibility by allowing
single gain set resistor programming and by conforming to the
8-lead industry standard pinout configuration. With no external
resistor, the AD623 is configured for unity gain (G = 1), and
with an external resistor, the AD623 can be programmed for
gains up to 1000.
CONNECTION DIAGRAM
1
–
R
G8
+R
G
2
–IN
7
+V
S
3
+IN
6
OUTPUT
4
–V
S5
REF
AD623
TOP VIEW
(Not to Scale)
0
0778-001
Figure 1. 8-Lead PDIP (N), SOIC (R), and MSOP (RM) Packages
120
30
40
50
60
70
80
90
100
110
1 10 100 1k 10k 100k
CMR (dB)
FREQUENCY (Hz)
×1000
×100
×10
×1
00778-002
Figure 2. CMR vs. Frequency, 5 VS, 0 VS
The AD623 holds errors to a minimum by providing superior
ac CMRR that increases with increasing gain. Line noise, as
well as line harmonics, are rejected because the CMRR remains
constant up to 200 Hz. The AD623 has a wide input common-
mode range and can amplify signals that have a common-mode
voltage 150 mV below ground. Although the design of the AD623
was optimized to operate from a single supply, the AD623 still
provides superior performance when operated from a dual
voltage supply (±2.5 V to ±6.0 V).
Low power consumption (1.5 mW at 3 V), wide supply voltage
range, and rail-to-rail output swing make the AD623 ideal
for battery-powered applications. The rail-to-rail output stage
maximizes the dynamic range when operating from low supply
voltages. The AD623 replaces discrete instrumentation amplifier
designs and offers superior linearity, temperature stability, and
reliability in a minimum of space.
AD623
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Single Supply ................................................................................. 3
Dual Supplies ................................................................................ 4
Both Dual and Single Supplies .................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 15
Applications Information .............................................................. 16
Basic Connection ....................................................................... 16
Gain Selection ............................................................................. 16
Reference Terminal .................................................................... 16
Input and Output Offset Voltage .............................................. 17
Input Protection ......................................................................... 17
RF Interference ........................................................................... 17
Grounding ................................................................................... 18
Input Differential and Common-Mode Range vs. Supply and
Gain .............................................................................................. 20
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/08—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Features Section and General Description Section . 1
Changes to Table 3 ............................................................................ 6
Changes to Figure 40 ...................................................................... 14
Changes to Theory of Operation Section .................................... 15
Changes to Figure 42 and Figure 43 ............................................. 16
Changes to Table 7 .......................................................................... 19
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 23
9/99—Rev. B to Rev. C
AD623
Rev. D | Page 3 of 24
SPECIFICATIONS
SINGLE SUPPLY
Typical @ 25°C single supply, VS = 5 V, and RL = 10 kΩ, unless otherwise noted.
Table 1.
AD623A AD623ARM AD623B
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
GAIN G =
1 + (100 k/RG)
Gain Range 1 1000 1 1000 1 1000
Gain Error1
G1 VOUT =
0.05 V to 3.5 V
G > 1 VOUT =
0.05 V to 4.5 V
G = 1 0.03 0.10 0.03 0.10 0.03 0.05 %
G = 10 0.10 0.35 0.10 0.35 0.10 0.35 %
G = 100 0.10 0.35 0.10 0.35 0.10 0.35 %
G = 1000 0.10 0.35 0.10 0.35 0.10 0.35 %
Nonlinearity G1 VOUT =
0.05 V to 3.5 V
G > 1 VOUT =
0.05 V to 4.5 V
G = 1 to 1000 50 50 50 ppm
Gain vs. Temperature
G = 1 5 10 5 10 5 10 ppm/°C
G > 11
50 50 50 ppm/°C
VOLTAGE OFFSET Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI 25 200 200 500 25 100 μV
Over Temperature 350 650 160 μV
Average Tempco 0.1 2 0.1 2 0.1 1 μV/°C
Output Offset, VOSO 200 1000 500 2000 200 500 μV
Over Temperature 1500 2600 1100 μV
Average Tempco 2.5 10 2.5 10 2.5 10 μV/°C
Offset Referred to the
Input vs. Supply (PSR)
G = 1 80 100 80 100 80 100 dB
G = 10 100 120 100 120 100 120 dB
G = 100 120 140 120 140 120 140 dB
G = 1000 120 140 120 140 120 140 dB
INPUT CURRENT
Input Bias Current 17 25 17 25 17 25 nA
Over Temperature 27.5 27.5 27.5 nA
Average Tempco 25 25 25 pA/°C
Input Offset Current 0.25 2 0.25 2 0.25 2 nA
Over Temperature 2.5 2.5 2.5 nA
Average Tempco 5 5 5 pA/°C
AD623
Rev. D | Page 4 of 24
AD623A AD623ARM AD623B
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
INPUT
Input Impedance
Differential 2||2 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 2||2 GΩ||pF
Input Voltage Range2VS = 3 V to 12 V (−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
(−VS) −
0.15
(+VS) −
1.5
V
Common-Mode Rejection
at 60 Hz with 1 kΩ Source
Imbalance
G = 1 VCM = 0 V to 3 V 70 80 70 80 77 86 dB
G = 10 VCM = 0 V to 3 V 90 100 90 100 94 100 dB
G = 100 VCM = 0 V to 3 V 105 110 105 110 105 110 dB
G = 1000 VCM = 0 V to 3 V 105 110 105 110 105 110 dB
OUTPUT
Output Swing RL = 10 kΩ 0.01 (+VS) −
0.5
0.01 (+VS) −
0.5
0.01 (+VS) −
0.5
V
R
L = 100 kΩ 0.01 (+VS) −
0.15
0.01 (+VS) −
0.15
0.01 (+VS) −
0.15
V
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 800 800 800 kHz
G = 10 100 100 100 kHz
G = 100 10 10 10 kHz
G = 1000 2 2 2 kHz
Slew Rate 0.3 0.3 0.3 V/μs
Settling Time to 0.01% VS = 5 V
G = 1 Step size: 3.5 V 30 30 30 μs
G = 10 Step size: 4 V,
VCM = 1.8 V
20 20 20 μs
1 Does not include effects of external resistor, RG.
2 One input grounded. G = 1.
DUAL SUPPLIES
Typical @ 25°C dual supply, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted.
Table 2.
AD623A AD623ARM AD623B
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
GAIN G =
1 + (100 k/RG)
Gain Range 1 1000 1 1000 1 1000
Gain Error1
G1 VOUT =
−4.8 V to +3.5 V
G > 1 VOUT =
0.05 V to 4.5 V
G = 1 0.03 0.10 0.03 0.10 0.03 0.05 %
G = 10 0.10 0.35 0.10 0.35 0.10 0.35 %
G = 100 0.10 0.35 0.10 0.35 0.10 0.35 %
G = 1000 0.10 0.35 0.10 0.35 0.10 0.35 %
AD623
Rev. D | Page 5 of 24
AD623A AD623ARM AD623B
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Nonlinearity G1 VOUT =
−4.8 V to +3.5 V
G > 1 VOUT =
−4.8 V to +4.5 V
G = 1 to 1000 50 50 50 ppm
Gain vs. Temperature
G = 1 5 10 5 10 5 10 ppm/°C
G > 11
50 50 50 ppm/°C
VOLTAGE OFFSET Total RTI error =
VOSI + VOSO/G
Input Offset, VOSI 25 200 200 500 25 100 μV
Over Temperature 350 650 160 μV
Average Tempco 0.1 2 0.1 2 0.1 1 μV/°C
Output Offset, VOSO 200 1000 500 2000 200 500 μV
Over Temperature 1500 2600 1100 μV
Average Tempco 2.5 10 2.5 10 2.5 10 μV/°C
Offset Referred to the Input
vs. Supply (PSR)
G = 1 80 100 80 100 80 100 dB
G = 10 100 120 100 120 100 120 dB
G = 100 120 140 120 140 120 140 dB
G = 1000 120 140 120 140 120 140 dB
INPUT CURRENT
Input Bias Current 17 25 17 25 17 25 nA
Over Temperature 27.5 27.5 27.5 nA
Average Tempco 25 25 25 pA/°C
Input Offset Current 0.25 2 0.25 2 0.25 2 nA
Over Temperature 2.5 2.5 2.5 nA
Average Tempco 5 5 5 pA/°C
INPUT
Input Impedance
Differential 2||2 2||2 2||2 GΩ||pF
Common-Mode 2||2 2||2 2||2 GΩ||pF
Input Voltage Range2VS = +2.5 V to
±6 V
(−VS) –
0.15
(+VS) –
1.5
(−VS) –
0.15
(+VS) –
1.5
(−VS) –
0.15
(+VS) –
1.5
V
Common-Mode Rejection at
60 Hz with 1 kΩ Source
Imbalance
G = 1 VCM = +3.5 V to
−5.15 V
70 80 70 80 77 86 dB
G = 10 VCM = +3.5 V to
−5.15 V
90 100 90 100 94 100 dB
G = 100 VCM = +3.5 V to
−5.15 V
105 110 105 110 105 110 dB
G = 1000 VCM = +3.5 V to
−5.15 V
105 110 105 110 105 110 dB
OUTPUT
Output Swing RL = 10 kΩ,
VS = ±5 V
(−VS) +
0.2
(+VS) −
0.5
(−VS) +
0.2
(+VS) −
0.5
(−VS) +
0.2
(+VS) −
0.5
V
R
L = 100 kΩ (−VS) +
0.05
(+VS) −
0.15
(−VS) +
0.05
(+VS) −
0.15
(−VS) +
0.05
(+VS) −
0.15
V
AD623
Rev. D | Page 6 of 24
AD623A AD623ARM AD623B
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal −3 dB Bandwidth
G = 1 800 800 800 kHz
G = 10 100 100 100 kHz
G = 100 10 10 10 kHz
G = 1000 2 2 2 kHz
Slew Rate 0.3 0.3 0.3 V/μs
Settling Time to 0.01% VS = ±5 V,
5 V step
G = 1 30 30 30 μs
G = 10 20 20 20 μs
1 Does not include effects of external resistor, RG.
2 One input grounded. G = 1.
BOTH DUAL AND SINGLE SUPPLIES
Table 3.
AD623A AD623ARM AD623B
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
NOISE
Voltage Noise, 1 kHz Total RTI noise =
()
()
2
2/Gee no
ni +
Input, Voltage Noise, eni 35 35 35 nV/√Hz
Output, Voltage Noise, eno 50 50 50 nV/√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 3.0 3.0 3.0 μV p-p
G = 1000 1.5 1.5 1.5 μV p-p
Current Noise f = 1 kHz 100 100 100 fA/√Hz
0.1 Hz to 10 Hz 1.5 1.5 1.5 pA p-p
REFERENCE INPUT
RIN 100 ±
20%
100 ±
20%
100 ±
20%
kΩ
IIN VIN+, VREF = 0 V 50 60 50 60 50 60 μA
Voltage Range −VS +VS −VS +VS −VS +VS V
Gain to Output 1 ±
0.0002
1 ±
0.0002
1 ±
0.0002
V
POWER SUPPLY
Operating Range Dual supply ±2.5 ±6 ±2.5 ±6 ±2.5 ±6 V
Single supply 2.7 12 2.7 12 2.7 12 V
Quiescent Current Dual supply 375 550 375 550 375 550 μA
Single supply 305 480 305 480 305 480 μA
Over Temperature 625 625 625 μA
TEMPERATURE RANGE
For Specified Performance −40 +85 −40 +85 −40 +85 °C
AD623
Rev. D | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±6 V
Internal Power Dissipation1
650 mW
Differential Input Voltage ±6 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
1 Specification is for device in free air:
8-Lead PDIP Package: θJA = 95°C/W
8-Lead SOIC Package: θJA = 155°C/W
8-Lead MSOP Package: θJA = 200°C/W.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD623
Rev. D | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
At 25°C, VS = ±5 V, and RL = 10 kΩ, unless otherwise noted.
–100 –80 –60 –40 –20 0 20 40 60 80 100 120 140
UNITS
INPUT OFFSET VOLTAGE (µV)
280
0
240
200
160
80
40
120
260
220
180
140
60
20
100
300
00778-003
Figure 3. Typical Distribution of Input Offset Voltage; Package Option N-8, R-8
–800 –600 –400 –200 0 200 400 600 800
UNITS
OUTPUT OFFSET VOLTAGE (µV)
0
480
420
360
300
240
180
120
60
00778-004
Figure 4. Typical Distribution of Output Offset Voltage; Package Option N-8, R-8
–80 –60 –40 –20 0 20 40 60 80 100
UNITS
INPUT OFFSET VOLTAGE (µV)
0
22
20
18
16
14
12
10
8
6
4
2
00778-005
Figure 5. Typical Distribution of Input Offset Voltage, VS = 5 V,
Single Supply, VREF = −0.125 V; Package Option N-8, R-8
–600 –500 –400 –300 –200 –100 0 100 200 300 400 500
UNITS
OUTPUT OFFSET VOLTAGE (µV)
0
22
20
18
16
14
12
10
8
6
4
2
00778-006
Figure 6. Typical Distribution of Output Offset Voltage, VS = 5 V,
Single Supply, VREF = −0.125 V; Package Option N-8, R-8
–0.245 –0.240 –0.235 –0.230 –0.225 –0.220 –0.215 –0.210
UNITS
INPUT OFFSET CURRENT (nA)
0
210
180
150
120
90
60
30
00778-007
Figure 7. Typical Distribution for Input Offset Current; Package Option N-8, R-8
–0.025 –0.020 –0.015 –0.010 –0.005 0 0.005 0.010
UNITS
INPUT OFFSET CURRENT (nA)
0
20
18
16
14
12
10
8
6
4
2
00778-008
Figure 8. Typical Distribution for Input Offset Current, VS = 5 V,
Single Supply, VREF = −0.125 V; Package Option N-8, R-8
AD623
Rev. D | Page 9 of 24
75 13012512011511010510095908580
UNITS
CMRR (dB)
0
1600
1400
1200
1000
800
600
400
200
00778-009
Figure 9. Typical Distribution for CMRR (G = 1)
1 100k10k1k10010
VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz RTI)
FREQUENCY (Hz)
10
1k
100
G= 1000
G= 100
G= 10
G = 1
00778-010
Figure 10. Voltage Noise Spectral Density vs. Frequency
420–2–4
I
BIAS
(nA)
CMV (V)
14
15
16
17
18
19
20
21
22
00778-011
Figure 11. IBIAS vs. CMV, VS = ±5 V
–60 –40 –20 0 20 40 60 80 100 120 140
IBIAS (nA)
TEMPERATURE (°C)
0
5
10
15
20
25
30
00778-012
Figure 12. IBIAS vs. Temperature
1110010
CURRENT NOISE SPECTRAL DENSITY (fA/ Hz)
FREQUENCY (Hz)
10
1k
100
k
00778-013
Figure 13. Current Noise Spectral Density vs. Frequency
–4 201–1–2–3
IBIAS (nA)
CMV (V)
16.0
16.5
17.0
17.5
18.0
18.5
19.0
19.5
20.0
00778-014
Figure 14. IBIAS vs. CMV, VS = ±2.5 V
AD623
Rev. D | Page 10 of 24
CH1 10mV A 1s 100mV VERT
00778-015
Figure 15. 0.1 Hz to 10 Hz Current Noise (0.71 pA/DIV)
1µV/DIV 1s
00778-016
Figure 16. 0.1 Hz to 10 Hz RTI Voltage Noise (1 DIV = 1 μV p-p)
120
30
40
50
60
70
80
90
100
110
1 10 100 1k 10k 100k
CMR (dB)
FREQUENCY (Hz)
×1000
×100
×10
×1
00778-017
Figure 17. CMR vs. Frequency, = 5 VS, 0 VS, VREF = 2.5 V
120
30
40
50
60
70
80
90
100
110
1 10 100 1k 10k 100k
CMR (dB)
FREQUENCY (Hz)
×1000
×100
×10
×1
00778-018
Figure 18. CMR vs. Frequency, ±5 VS
70
–30
–20
–10
0
10
20
30
40
50
60
100 1k 10k 100k 1M
GAIN (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-019
Figure 19. Gain vs. Frequency (VS = 5 V, 0 V), VREF = 2.5 V
5
–5
–4
–3
–2
–1
0
1
2
3
4
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
V
S
= ±5V
V
S
= ±2.5V
00778-020
Figure 20. Maximum Output Voltage vs. Common-Mode Input, G = 1, RL = 100 kΩ
AD623
Rev. D | Page 11 of 24
5
–5
–4
–3
–2
–1
0
1
2
3
4
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
V
S
= ±5V
V
S
= ±2.5V
00778-021
Figure 21. Maximum Output Voltage vs. Common-Mode Input, G ≥ 10, RL = 100 Ω
5
0
1
2
3
4
–1012345
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
00778-022
Figure 22. Maximum Output Voltage vs. Common-Mode Input,
G = 1, VS = 5 V, RL = 100 kΩ
5
0
1
2
3
4
–1012345
MAXIMUM OUTPUT VOLTAGE (V)
COMMON-MODE INPUT (V)
00778-023
Figure 23. Maximum Output Voltage vs. Common-Mode Input,
G ≥ 10, VS = 5 V, RL = 100 kΩ
140
120
100
80
60
40
20
0
1 10 100 1k 10k 100k
POSITIVE PSSR (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-024
Figure 24. Positive PSRR vs. Frequency, ±5 VS
140
120
100
80
60
40
20
0
1 10 100 1k 10k 100k
POSITIVE PSSR (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-025
Figure 25. Positive PSRR vs. Frequency, 5 VS, 0 VS
140
120
100
80
60
40
20
0
1 10 100 1k 10k 100k
NEGATIVE PSRR (dB)
FREQUENCY (Hz)
G = 1000
G = 100
G = 10
G = 1
00778-026
Figure 26. Negative PSRR vs. Frequency, ±5 VS
AD623
Rev. D | Page 12 of 24
10
8
6
4
2
0
020
V
S
= ±5V
V
S
= ±2.5V
40 60 80 100
OUTPUT VOLTAGE (V p-p)
FREQUENCY (kHz)
00778-027
Figure 27. Large Signal Response, G ≤ 10
1k
100
10
1
1 10 100 1k
SETTLING TIME (µs)
GAIN (V/V)
00778-028
Figure 28. Settling Time to 0.01% vs. Gain, for a 5 V Step at Output,
CL = 100 pF, VS = ±5 V
500µV 1V 20µs
00778-029
Figure 29. Large Signal Pulse Response and Settling Time,
G = −1 (0.250 mV = 0.01%), CL = 100 pF
500µV 1V 10µs
00778-030
Figure 30. Large Signal Pulse Response and Settling Time,
G = −10 (0.250 mV = 0.01%), CL = 100 pF
10mV 2V 50µs
00778-031
Figure 31. Large Signal Pulse Response and Settling Time,
G = 100, CL = 100 pF
20mV 2V 500µs
00778-032
Figure 32. Large Signal Pulse Response and Settling Time,
G = −1000 (5 mV = 0.01%), CL = 100 pF
AD623
Rev. D | Page 13 of 24
20mV 2µs
00778-033
Figure 33. Small Signal Pulse Response, G = 1, RL = 10 kΩ, CL = 100 pF
20mV 5µs
00778-034
Figure 34. Small Signal Pulse Response, G = 10, RL = 10 kΩ, CL = 100 pF
20mV 50µs
00778-035
Figure 35. Small Signal Pulse Response, G = 100, RL = 10 kΩ, CL = 100 pF
20mV 500µs
00778-036
Figure 36. Small Signal Pulse Response, G = 1000, RL = 10 kΩ, CL = 100 pF
200µV
1V
0
0778-037
Figure 37. Gain Nonlinearity, G = −1 (50 ppm/DIV)
20µV 1V
00778-038
Figure 38. Gain Nonlinearity, G = −10 (6 ppm/DIV)
AD623
Rev. D | Page 14 of 24
50µV 1V
00778-039
Figure 39. Gain Nonlinearity, G = −100, 15 ppm/DIV
V
+
(V+) –0.5
(V+) –1.5
(V+) –2.5
(V–) +0.5
V–
0 0.5 1.0 1.5 2.0
OUTPUT VOLTAGE SWING (V)
OUTPUT CURRENT (mA)
00778-040
Figure 40. Output Voltage Swing vs. Output Current
AD623
Rev. D | Page 15 of 24
THEORY OF OPERATION
The AD623 is an instrumentation amplifier based on a modified
classic 3-op-amp approach, to assure single or dual supply
operation even at common-mode voltages at the negative
supply rail. Low voltage offsets, input and output, as well as
absolute gain accuracy, and one external resistor to set the
gain, make the AD623 one of the most versatile instrumentation
amplifiers in its class.
The input signal is applied to PNP transistors acting as voltage
buffers and providing a common-mode signal to the input
amplifiers (see Figure 41). An absolute value 50 kΩ resistor in
each amplifier feedback assures gain programmability.
The differential output is
C
G
OV
R
V⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+= k100
1
The differential voltage is then converted to a single-ended
voltage using the output amplifier, which also rejects any
common-mode signal at the output of the input amplifiers.
Because the amplifiers can swing to either supply rail, as well as
have their common-mode range extended to below the negative
supply rail, the range over which the AD623 can operate is further
enhanced (see Figure 20 and Figure 21).
The output voltage at Pin 6 is measured with respect to the
potential at Pin 5. The impedance of the reference pin is 100 kΩ;
therefore, in applications requiring V/I conversion, a small
resistor between Pin 5 and Pin 6 is all that is needed.
POSITIVE SUPPLY
7
4
INVERTING
2
7
4
NEGATIVE SUPPLY
NONINVERTING
3
50kΩ50kΩ50kΩ
50kΩ50kΩ50kΩ
OTUPUT
6
REF
5
8
1
GAIN
00778-041
Figure 41. Simplified Schematic
Note that the bandwidth of the in-amp decreases as gain is
increased. This occurs because the internal op-amps are the
standard voltage feedback design. At unity gain, the output
amplifier limits the bandwidth.
AD623
Rev. D | Page 16 of 24
APPLICATIONS INFORMATION
BASIC CONNECTION
Figure 42 and Figure 43 show the basic connection circuits for
the AD623. The +VS and −VS terminals are connected to the
power supply. The supply can be either bipolar (VS = ±2.5 V to
±6 V) or single supply (−VS = 0 V, +VS = 3.0 V to 12 V). Power
supplies should be capacitively decoupled close to the power pins of
the device. For the best results, use surface-mount 0.1 µF ceramic
chip capacitors and 10 µF electrolytic tantalum capacitors.
00778-042
R
G
R
G
V
IN
OUTPUT V
OUT
REF
R
G
REF (INPUT)
+2.5V TO +6V
+
V
S
10µF0.1µF
–2.5V TO –6V
–V
S
10µF0.1µF
Figure 42. Dual-Supply Basic Connection
00778-055
RG
RG
VIN OUTPUT VOUT
REF
RG
REF (INPUT)
+3V TO +12V
+
V
S
10µF0.1µF
Figure 43. Single-Supply Basic Connection
The input voltage, which can be either single-ended (tie either
−IN or +IN to ground), or differential is amplified by the
programmed gain. The output signal appears as the voltage
difference between the OUTPUT pin and the externally applied
voltage on the REF input. For a ground-referenced output, REF
should be grounded.
GAIN SELECTION
The gain of the AD623 is resistor programmed by RG, or more
precisely, by whatever impedance appears between Pin 1 and
Pin 8. The AD623 is designed to offer accurate gains using 0.1%
to 1% tolerance resistors. Table 5 shows the required values of
RG for the various gains. Note that for G = 1, the RG terminals
are unconnected (RG = ∞). For any arbitrary gain, RG can be
calculated by
RG = 100 kΩ/(G − 1)
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output. The reference terminal is
also useful when bipolar signals are being amplified because it
can be used to provide a virtual ground voltage. The voltage on
the reference terminal can be varied from −VS to +VS.
Table 5. Required Values of Gain Resistors
Desired Gain 1% Standard Table Value of RG (Ω) Calculated Gain Using 1% Resistors
2 100 k 2
5 24.9 k 5.02
10 11 k 10.09
20 5.23 k 20.12
33 3.09 k 33.36
40 2.55 k 40.21
50 2.05 k 49.78
65 1.58 k 64.29
100 1.02 k 99.04
200 499 201.4
500 200 501
1000 100 1001
AD623
Rev. D | Page 17 of 24
INPUT AND OUTPUT OFFSET VOLTAGE
The low errors of the AD623 are attributed to two sources,
input and output errors. The output error is divided by the
programmed gain when referred to the input. In practice,
the input errors dominate at high gains and the output errors
dominate at low gains. The total VOS for a given gain is calculated
as the following:
Total Error RTI = Input Error + (Output Error/G)
Total Error RTO = (Input Error × G) + Output Error
RTI offset errors and noise voltages for different gains are
shown in Table 6.
INPUT PROTECTION
Internal supply referenced clamping diodes allow the input,
reference, output, and gain terminals of the AD623 to safely
withstand overvoltages of 0.3 V above or below the supplies.
This is true for all gains and for power on and power off. This
last case is particularly important because the signal source
and amplifier may be powered separately.
If the overvoltage is expected to exceed this value, the current
through these diodes should be limited to about 10 mA using
external current limiting resistors (see Figure 44). The size of
this resistor is defined by the supply voltage and the required
overvoltage protection.
R
G
V
OVER
V
OVER
AD623
OUTPUT
+
V
S
–V
S
R
LIM
R
LIM
I = 10mA MAX
R
LIM
= V
OVER
–V
S
+ 0.7V
10mA
00778-043
Figure 44. Input Protection
RF INTERFERENCE
All instrumentation amplifiers can rectify high frequency out-
of-band signals. Once rectified, these signals appear as dc offset
errors at the output. The circuit in Figure 45 provides good RFI
suppression without reducing performance within the pass band of
the in-amp. Resistor R1 and Capacitor C1 (and likewise, R2 and
C2) form a low-pass RC filter that has a −3 dB bandwidth equal
to F = 1/(2 π R1C1). Using the component values shown, this
filter has a −3 dB bandwidth of approximately 40 kHz. Resistors
R1 and R2 were selected to be large enough to isolate the input of
the circuit from the capacitors, but not large enough to significantly
increase the noise of the circuit. To preserve common-mode rejection
in the amplifier’s pass band, Capacitors C1 and C2 need to be 5%
or better units, or low cost 20% units can be tested and binned
to provide closely matched devices.
00778-044
R
G
–IN
+IN
AD623
V
OUT
R1
4.02kΩ
1%
R2
4.02kΩ
1% REFERENCE
+
V
S
0.01µF0.33µF
+V
S
0.01µF0.33µF
C1
1000pF
5%
C3
0.047µF
C2
1000pF
5%
NOTES:
1. LOCATE C1 TO C3 AS CLOSE TO THE INPUT PINS AS POSSIBLE.
Figure 45. Circuit to Attenuate RF Interference
Capacitor C3 is needed to maintain common-mode rejection at
the low frequencies. R1/R2 and C1/C2 form a bridge circuit whose
output appears across the input pins of the in-amp. Any mismatch
between C1 and C2 unbalances the bridge and reduces the
common-mode rejection. C3 ensures that any RF signals are
common mode (the same on both in-amp inputs) and are not
applied differentially. This second low-pass network, R1 + R2 and
C3, has a −3 dB frequency equal to 1/(2 π (R1 + R2) (C3)). Using a
C3 value of 0.047 µF, the −3 dB signal bandwidth of this circuit is
approximately 400 Hz. The typical dc offset shift over frequency is
less than 1.5 µV and the circuit’s RF signal rejection is better than
71 dB. The 3 dB signal bandwidth of this circuit may be increased
to 900 Hz by reducing Resistors R1 and R2 to 2.2 kΩ. The
performance is similar to using 4 kΩ resistors, except that the
circuitry preceding the in-amp must drive a lower impedance load.
Table 6. RTI Error Sources
Maximum Total Input Offset Error (μV) Maximum Total Input Offset Drift (μV/°C) Total Input Referred Noise (nV/√Hz)
Gain AD623A AD623B AD623A AD623B AD623A and AD623B
1 1200 600 12 11 62
2 700 350 7 6 45
5 400 200 4 3 38
10 300 150 3 2 35
20 250 125 2.5 1.5 35
50 220 110 2.2 1.2 35
100 210 105 2.1 1.1 35
1000 200 100 2 1 35
AD623
Rev. D | Page 18 of 24
The circuit in Figure 45 should be built using a PC board with a
ground plane on both sides. All component leads should be as
short as possible. Resistors R1 and R2 can be common 1% metal
film units, but Capacitors C1 and C2 need to be ±5% tolerance
devices to avoid degrading the circuit’s common-mode rejection.
Either the traditional 5% silver mica units or Panasonic ±2%
PPS film capacitors are recommended.
In many applications, shielded cables are used to minimize
noise; for best CMR over frequency, the shield should be properly
driven. Figure 46 shows an active guard driver that is configured
to improve ac common-mode rejection by bootstrapping the
capacitances of input cable shields, thus minimizing the capacitance
mismatch between the inputs.
AD623
OUTPUT
REF
+
V
S
–V
S
2
1
8
3
6
5
7
4
R
G
2
R
G
2
AD8031
100Ω
0
0778-045
–IN
+IN
Figure 46. Common-Mode Shield Driver
GROUNDING
Because the AD623 output voltage is developed with respect to
the potential on the reference terminal, many grounding problems
can be solved by simply tying the REF pin to the appropriate local
ground. The REF pin should, however, be tied to a low impedance
point for optimal CMR.
The use of ground planes is recommended to minimize the
impedance of ground returns (and hence the size of dc errors).
To isolate low level analog signals from a noisy digital environment,
many data acquisition components have separate analog and
digital ground returns (see Figure 47). All ground pins from
mixed signal components, such as analog-to-digital converters
(ADCs), should be returned through the high quality analog
ground plane. Maximum isolation between analog and digital is
achieved by connecting the ground planes back at the supplies.
The digital return currents from the ADC that flow in the analog
ground plane, in general, have a negligible effect on noise
performance.
If there is only a single power supply available, it must be shared
by both digital and analog circuitry. Figure 48 shows how to
minimize interference between the digital and analog circuitry.
As in the previous case, separate analog and digital ground planes
should be used (reasonably thick traces can be used as an
alternative to a digital ground plane). These ground planes
should be connected at the ground pin of the power supply.
Separate traces should be run from the power supply to the
supply pins of the digital and analog circuits. Ideally, each device
should have its own power supply trace, but these can be shared
by a number of devices, as long as a single trace is not used to
route current to both digital and analog circuitry.
AGND V
DD
MICROPROCESSOR
AD623
2
3
6
5
7
4
ANALOG POWER SUPPLY
GND–5V+5V
DIGITAL POWER SUPPLY
+5VGND
4
V
IN1
1
V
DD
6
AGND
14
DGND
3
V
IN2
ADC
AD7892-2
0.1µF0.1µF0.1µF 0.1µF
12
0
0778-046
Figure 47. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies
AGND VDD
MICROPROCESSOR
AD623
2
3
6
5
7
4
4VIN1
1
VDD
6
AGND
14
DGND
ADC
AD7892-2
0.1µF
0.1µF 0.1µF
12
POWER SUPPLY
+5V GND
0
0778-047
Figure 48. Optimal Ground Practice in a Single Supply Environment
AD623
Rev. D | Page 19 of 24
Ground Returns for Input Bias Currents
Input bias currents are those dc currents that must flow to bias
the input transistors of an amplifier. These are usually transistor
base currents. When amplifying floating input sources, such as
transformers or ac-coupled sources, there must be a direct dc
path into each input in order that the bias current can flow.
Figure 49, Figure 50, and Figure 51 show how a bias current
path can be provided for the cases of transformer coupling,
thermocouple, and capacitive ac coupling. In dc-coupled resistive
bridge applications, providing this path is generally not necessary
as the bias current simply flows from the bridge supply through
the bridge into the amplifier. However, if the impedances that
the two inputs see are large and differ by a large amount (>10 kΩ),
the offset current of the input stage causes dc errors
proportional with the input offset voltage of the amplifier.
AD623
OUTPUT
TO POWER
SUPPLY
GROUND
REF
LOAD
+
V
S
–V
S
2
1
8
3
6
5
7
4
R
G
–IN
+IN
00778-048
Figure 49. Ground Returns for Bias Currents with Transformer-Coupled Inputs
AD623
OTUPUT
TO POWER
SUPPLY
GROUND
REF
LOAD
+
V
S
–V
S
2
1
8
3
6
5
7
4
R
G
–IN
+IN
00778-049
Figure 50. Ground Returns for Bias Currents with Thermocouple Inputs
AD623
OUTPUT
TO POWER
SUPPLY
GROUND
REF
LOAD
+
V
S
–V
S
2
1
8
3
6
5
7
4
R
G
–IN
+IN
100kΩ100kΩ
00778-050
Figure 51. Ground Returns for Bias Currents with AC-Coupled Inputs
Output Buffering
The AD623 is designed to drive loads of 10 kΩ or greater. If
the load is less than this value, the output of the AD623 should
be buffered with a precision single-supply op amp, such as the
OP113. This op amp can swing from 0 V to 4 V on its output
while driving a load as small as 600 Ω. Tabl e 7 summarizes the
performance of some buffer op amps.
5
V
0.1µF 5V
0.1µF
AD623
OP113
R
G
V
IN
REFERENCE
V
OUT
00778-051
Figure 52. Output Buffering
Table 7. Buffering Options
Op Amp Description
OP113 Single supply, high output current
OP191 Rail-to-rail input and output, low supply current
Single-Supply Data Acquisition System
Interfacing bipolar signals to single-supply ADCs presents a
challenge. The bipolar signal must be mapped into the input
range of the ADC. Figure 53 shows how this translation can be
achieved.
5
V
0.1µF
5V 5V
0.1µF
AD623
R
G
1.02kΩ
REFERENCE
±10mV A
IN
REFOUT
REFIN
AD7776
00778-052
Figure 53. A Single-Supply Data Acquisition System
The bridge circuit is excited by a 5 V supply. The full-scale output
voltage from the bridge (±10 mV) therefore has a common-
mode level of 2.5 V. The AD623 removes the common-mode
component and amplifies the input signal by a factor of 100
(RGAIN = 1.02 kΩ). This results in an output signal of ±1 V. To
prevent this signal from running into the ground rail of the
AD623, the voltage on the REF pin must be raised to at least
1 V. In this example, the 2 V reference voltage from the AD7776
ADC is used to bias the output voltage of the AD623 to 2 V ± 1 V.
This corresponds to the input range of the ADC.
AD623
Rev. D | Page 20 of 24
Amplifying Signals with Low Common-Mode Voltage
Because the common-mode input range of the AD623 extends
0.1 V below ground, it is possible to measure small differential
signals which have low, or no, common-mode component.
Figure 54 shows a thermocouple application where one side
of the J-type thermocouple is grounded.
5
V
0.1µF
AD623
R
G
1.02kΩ
REF
J-TYPE
T
HERMOCOUPLE OUTPU
T
2V
00778-053
Figure 54. Amplifying Bipolar Signals with Low Common-Mode Voltage
Over a temperature range of −200°C to +200°C, the J-type thermo-
couple delivers a voltage ranging from −7.890 mV to +10.777 mV.
A programmed gain on the AD623 of 100 (RG = 1.02 kΩ) and a
voltage on the REF pin of 2 V, results in the output voltage ranging
from 1.110 V to 3.077 V relative to ground.
INPUT DIFFERENTIAL AND COMMON-MODE RANGE
vs. SUPPLY AND GAIN
Figure 55 shows a simplified block diagram of the AD623. The
voltages at the outputs of Amplifier A1 and Amplifier A2 are
given by
VA2 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V + VDIFF × Gain/2
VA1 = VCM + VDIFF/2 + 0.6 V + VDIFF × RF/RG
= VCM + 0.6 V − VDIFF × Gain/2
POSITIVE SUPPLY
7
4
INVERTING
2
7
4
NEGATIVE SUPPLY
NONINVERTING
3
RF
50kΩ50kΩ50kΩ
RF
50kΩ50kΩ50kΩ
OUTPU
T
6
REF
5
8
1
GAIN
RG
A1
A2
A3
VDIFF
2
–
+
VDIFF
2
–
+
VCM
00778-054
Figure 55. Simplified Block Diagram
The voltages on these internal nodes are critical in determining
whether the output voltage will be clipped. The VA1 and VA2
voltages can swing from approximately 10 mV above the negative
supply (V− or ground) to within approximately 100 mV of the
positive rail before clipping occurs. Based on this and from
the previous equations, the maximum and minimum input
common-mode voltages are given by the following equations:
VCMMAX = V+ − 0.7 V − VDIFF × Gain/2
VCMMIN = V− − 0.590 V + VDIFF × Gain/2
These equations can be rearranged to give the maximum
possible differential voltage (positive or negative) for a
particular common-mode voltage, gain, and power supply.
Because the signals on A1 and A2 can clip on either rail, the
maximum differential voltage are the lesser of the two equations.
|VDIFFMAX| = 2 (V+ − 0.7 V − VCM/Gain
|VDIFFMAX| = 2 (VCM − V− +0.590 V/Gain
However, the range on the differential input voltage range is
also constrained by the output swing. Therefore, the range of
VDIFF may have to be lower according the following equation.
Input Range ≤ Available Output Swing/Gain
For a bipolar input voltage with a common-mode voltage that is
roughly half way between the rails, VDIFFMAX is half the value that
the previous equations yield because the REF pin is at midsupply.
Note that the available output swing is given for different supply
conditions in the Specifications section.
The equations can be rearranged to give the maximum gain for
a fixed set of input conditions. Again, the maximum gain will be
the lesser of the two equations.
GainMAX = 2 (V+ − 0.7 V − VCM)/VDIFF
GainMAX = 2 (VCM − V− +0.590 V)/VDIFF
Again, it is recommended that the resulting gain times the input
range is less than the available output swing. If this is not the
case, the maximum gain is given by
GainMAX = Available Output Swing/Input Range
Also for bipolar inputs (that is, input range = 2 VDIFF), the
maximum gain is half the value yielded by the previous equations
because the REF pin must be at midsupply.
The maximum gain and resulting output swing for different
input conditions is given in Table 8. Output voltages are
referenced to the voltage on the REF pin.
For the purposes of computation, it is necessary to break down the
input voltage into its differential and common-mode component.
Therefore, when one of the inputs is grounded or at a fixed
voltage, the common-mode voltage changes as the differential
voltage changes. Take the case of the thermocouple amplifier
in Figure 54. The inverting input on the AD623 is grounded;
therefore, when the input voltage is −10 mV, the voltage on the
noninverting input is −10 mV. For the purpose of the signal swing
calculations, this input voltage should be composed of a common-
mode voltage of −5 mV (that is, (+IN + −IN)/2) and a differential
input voltage of −10 mV (that is, +IN − −IN).
AD623
Rev. D | Page 21 of 24
Table 8. Maximum Attainable Gain and Resulting Output Swing for Different Input Conditions
VCM (V) VDIFF (V) REF Pin (V) Supply Voltages (V) Maximum Gain
Closest 1% Gain
Resistor (Ω) Resulting Gain Output Swing (V)
0 ±10 m 2.5 +5 118 866 116 ±1.2
0 ±100 m 2.5 +5 11.8 9.31 k 11.7 ±1.1
0 ±10 m 0 ±5 490 205 488 ±4.8
0 ±100 m 0 ±5 49 2.1 k 48.61 ±4.8
0 ±1 0 ±5 4.9 26.1 k 4.83 ±4.8
2.5 ±10 m 2.5 +5 242 422 238 ±2.3
2.5 ±100 m 2.5 +5 24.2 4.32 k 24.1 ±2.4
2.5 ±1 2.5 +5 2.42 71.5 k 2.4 ±2.4
1.5 ±10 m 1.5 +3 142 715 141 ±1.4
1.5 ±100 m 1.5 +3 14.2 7.68 k 14 ±1.4
0 ±10 m 1.5 +3 118 866 116 ±1.1
0 ±100 m 1.5 +3 11.8 9.31 k 11.74 ±1.1
AD623
Rev. D | Page 22 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 56. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 57. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
AD623
Rev. D | Page 23 of 24
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 58. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Tem perat ur e
Range Package Description
Package
Option Branding
AD623AN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD623ANZ1
−40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD623AR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD623AR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD623AR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD623ARZ1
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD623ARZ-R71
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD623ARZ-RL1
−40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8
AD623ARM −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 J0A
AD623ARM-REEL −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel RM-8 J0A
AD623ARM-REEL7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel RM-8 J0A
AD623ARMZ1
−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 J0A
AD623ARMZ-REEL1
−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 13" Tape and Reel RM-8 J0A
AD623ARMZ-REEL71
−40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 7" Tape and Reel RM-8 J0A
AD623BN −40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD623BNZ1
−40°C to +85°C 8-Lead Plastic Dual In-Line Package [PDIP] N-8
AD623BR −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD623BR-REEL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD623BR-REEL7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD623BRZ1
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD623BRZ-R71
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD623BRZ-RL1
−40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
EVAL-INAMP-62RZ1
Evaluation Board
1 Z = RoHS Compliant Part.
AD623
Rev. D | Page 24 of 24
NOTES
©1997–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00788-0-7/08(D)
