SPRS161K - MARCH 2001 - REVISED JULY 2007 D High-Performance Static CMOS Technology D D D D - 25-ns Instruction Cycle Time (40 MHz) - 40-MIPS Performance - Low-Power 3.3-V Design Based on TMS320C2xx DSP CPU Core - Code-Compatible With 240x and F243/F241/C242 - Instruction Set Compatible With F240 On-Chip Memory - Up to 8K Words x 16 Bits of Flash EEPROM (2 Sectors) (LF2401A) - 8K Words x 16 Bits of ROM (LC2401A) - Programmable "Code-Security" Feature for the On-Chip Flash/ROM - Up to 1K Words x 16 Bits of Data/Program RAM - 544 Words of Dual-Access RAM - Up to 512 Words of Single-Access RAM Boot ROM - SCI Bootloader Event-Manager (EV) Module (EVA), Which Includes: - Two 16-Bit General-Purpose Timers - Seven 16-Bit Pulse-Width Modulation (PWM) Channels Which Enable: - Three-Phase Inverter Control - Center- or Edge-Alignment of PWM Channels - Emergency PWM Channel Shutdown With External PDPINTA Pin - Programmable Deadband (Deadtime) Prevents Shoot-Through Faults - One Capture Unit for Time-Stamping of External Events - Input Qualifier for Select Pins - Synchronized A-to-D Conversion - Designed for AC Induction, BLDC, Switched Reluctance, and Stepper Motor Control D Small Foot-Print (7 mm x 7 mm) Ideally D D D D D D D D D D D Suited for Space-Constrained Applications Watchdog (WD) Timer Module 10-Bit Analog-to-Digital Converter (ADC) - 5 Multiplexed Input Channels - 500 ns Minimum Conversion Time - Selectable Twin 8-State Sequencers Triggered by Event Manager Serial Communications Interface (SCI) Phase-Locked-Loop (PLL)-Based Clock Generation Up to 13 Individually Programmable, Multiplexed General-Purpose Input / Output (GPIO) Pins User-Selectable Dual External Interrupts (XINT1 and XINT2) Power Management: - Three Power-Down Modes - Ability to Power Down Each Peripheral Independently Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1 (JTAG) Development Tools Include: - Texas Instruments (TI) ANSI C Compiler, Assembler/ Linker, and Code Composer Studio Debugger - Evaluation Modules - Scan-Based Self-Emulation (XDS510) - Broad Third-Party Digital Motor Control Support 32-Pin VF Low-Profile Quad Flatpack (LQFP) Extended Temperature Options (A and S) - A: - 40C to 85C - S: - 40C to 125C Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Code Composer Studio and XDS510 are trademarks of Texas Instruments. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family. Copyright 2007, Texas Instruments Incorporated !" #!$% &"' &! #" #" (" " ") !" && *+' &! #", &" ""%+ %!&" ", %% #""' POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 1 SPRS161K - MARCH 2001 - REVISED JULY 2007 Table of Contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 TMS320x240xA device summary . . . . . . . . . . . . . . . 4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320x240xA device summary . . . . . . . . . . . . . . . 5 functional block diagram of the LF2401A DSP controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 functional block diagram of the LC2401A DSP controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 constraints while emulating with JTAG port pins and GPIO functions . . . . . . . . . . . . 17 in-circuit emulation options . . . . . . . . . . . . . . . . . . 18 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 peripheral memory map . . . . . . . . . . . . . . . . . . . . . 21 device reset and interrupts . . . . . . . . . . . . . . . . . . . 22 interrupt request structure . . . . . . . . . . . . . . . . . . . 24 DSP CPU core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 TMS320Lx2401A instruction set . . . . . . . . . . . . . . 25 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . 25 scan-based emulation . . . . . . . . . . . . . . . . . . . . . . . 26 functional block diagram of the 2401A DSP CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2401A legend for the internal hardware . . . . . . . . 28 status and control registers . . . . . . . . . . . . . . . . . . 29 central processing unit . . . . . . . . . . . . . . . . . . . . . . 30 internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 dual-access RAM (DARAM) . . . . . . . . . . . . . . . . . 34 single-access RAM (SARAM) . . . . . . . . . . . . . . . . 34 ROM (LC2401A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Flash EEPROM (LF2401A) . . . . . . . . . . . . . . . . . . 34 boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Flash/ROM security . . . . . . . . . . . . . . . . . . . . . . . . . 36 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 event manager module (EVA) . . . . . . . . . . . . . . . . 37 enhanced analog-to-digital converter (ADC) module . . . . . . . . . . . . . . . . . . . . . . . . . 41 serial communications interface (SCI) module . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PLL-based clock module . . . . . . . . . . . . . . . . . . . . 45 external reference crystal clock option . . . . . . . . . 46 external reference oscillator clock option . . . . . . . 46 2 POST OFFICE BOX 1443 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . other power-down options . . . . . . . . . . . . . . . . . . . digital I/O and shared pin functions . . . . . . . . . . . . watchdog (WD) timer module . . . . . . . . . . . . . . . . development support . . . . . . . . . . . . . . . . . . . . . . . . device and development support tool nomenclature . . . . . . . . . . . . . . . . . . . . . . documentation support . . . . . . . . . . . . . . . . . . . . . . LF2401A AND LC2401A ELECTRICAL SPECIFICATIONS DATA . . . . . . . . . . . . . . . . absolute maximum ratings over operating temperature range . . . . . . . . . . . . . recommended operating conditions . . . . . . . . . . . current consumption graphs . . . . . . . . . . . . . . . . . reducing current consumption . . . . . . . . . . . . . . . . emulator connection without signal buffering for the DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . PARAMETER MEASUREMENT INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . signal transition levels . . . . . . . . . . . . . . . . . . . . . . . timing parameter symbology . . . . . . . . . . . . . . . . . general notes on timing parameters . . . . . . . . . . . external reference crystal/clock with PLL circuit enabled . . . . . . . . . . . . . . . . . . . . . . . . . timing with the PLL circuit enabled . . . . . . . . . . . . RS timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . low-power mode timing . . . . . . . . . . . . . . . . . . . . . . LPM2 wake-up timing . . . . . . . . . . . . . . . . . . . . . . . timing event manager interface . . . . . . . . . . . . . . . PWM timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . capture timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . general-purpose input/output timing . . . . . . . . . . . 10-bit analog-to-digital converter (ADC) . . . . . . . . migrating from other 240xA devices to Lx2401A . . . . . . . . . . . . . . . . . . . . migrating from LF240xA (Flash) devices to LC240xA (ROM) devices . . . . . . peripheral register description . . . . . . . . . . . . . . . . mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . * HOUSTON, TEXAS 77251-1443 46 46 47 48 49 52 53 55 57 57 57 60 60 60 62 62 63 63 64 64 65 68 70 71 71 72 73 74 75 77 78 79 87 SPRS161K - MARCH 2001 - REVISED JULY 2007 REVISION HISTORY This data sheet revision history highlights the technical changes made to the SPRS161J device-specific data sheet to make it an SPRS161K revision. Scope: PAGE HIGHLIGHTS 20 Modified On-chip ROM part of Figure 10, TMS320LC2401A Memory Map 42 Added sentence to paragraph following Figure 15 57 Added note to receommended operating conditions table 60 Added section on emulator connection without signal buffering for the DSP 78 Added section on migrating from LF2401A to LC2401A POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 3 SPRS161K - MARCH 2001 - REVISED JULY 2007 description The TMS320Lx2401A device, a new member of the TMS320C24x generation of digital signal processor (DSP) controllers, is part of the TMS320C2000 platform of fixed-point DSPs. The Lx2401A device offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing 240x and C24x DSP controller devices, the Lx2401A offers increased processing performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary section for device-specific features. The Lx2401A device offers a peripheral suite tailored to meet the specific price/performance points required by various applications. The Lx2401A also offers a cost-effective reprogrammable solution for volume production. A password-based "code security" feature on the device is useful in preventing unauthorized duplication of proprietary code stored in on-chip Flash/ROM. Note that the LF2401A contains a 256-word boot ROM to facilitate in-circuit programming. The boot ROM on LC2401A is used for test purposes. The Lx2401A offers an event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include center- and/or edge-aligned PWM generation, programmable deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Select EV pins have been provided with an "input-qualifier" circuitry, which minimizes inadvertent pin-triggering by glitches. The high-performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and offers up to 5 channels of analog input. The autosequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead. A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. To maximize device flexibility, functional pins are also configurable as general-purpose inputs/outputs (GPIOs). To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code-generation tools from C compilers to the industry-standard Code Composer Studio debugger supports this family. Numerous third-party developers not only offer device-level development tools, but also system-level design and development support. NOTE: The Lx2401A device has reduced peripheral functionality compared to other 24x/240x devices. While peripherals such as SPI and CAN are absent on the Lx2401A, peripherals such as EV and ADC have reduced functionality. For example, in the case of EV, there is no QEP unit and the Capture unit has only one capture pin (as opposed to three or six pins in other devices). The ADC has only five input channels (as opposed to eight or sixteen channels in other devices). For these reasons, some bits that are valid in other 24x/240x devices are not applicable in the Lx2401A. The registers and their valid bits are described in Table 16, Lx2401A DSP Peripheral Register Description. For a description of those registers and bits that are valid, refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357). Any exceptions to SPRU357 have been described in the respective peripheral sections in this data sheet. TMS320C24x, TMS320C2000, TMS320, and C24x are trademarks of Texas Instruments. Throughout this document, TMS320Lx2401A is used as a generic name for the TMS320LF2401A and TMS320LC2401A devices. An abbreviated name, Lx2401A, denotes both devices as well. 4 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 TMS320x240xA device summary Table 1. Device Feature Comparison Between Lx2401A and Lx2402A FEATURE LF2401A LC2401A LF2402A LC2402A C2xx DSP Core Yes Yes Yes Yes Instruction Cycle 25 ns 25 ns 25 ns 25 ns MIPS (40 MHz) 40 MIPS 40 MIPS 40 MIPS 40 MIPS Dual-Access RAM (DARAM) 544 544 544 544 Single-Access RAM (SARAM) 512 512 512 -- 8K -- 8K -- 4K/4K -- 4K/4K -- RAM (16-bit word) 3.3-V Flash (Program Space, 16-bit word) Flash Sectors On-chip ROM (Program Space, 16-bit word) -- 8K -- 6K Code Security for On-Chip Flash/ROM Yes Yes Yes Yes Boot ROM Yes Yes Yes -- External Memory Interface Event Manager A (EVA) -- -- -- -- EVA EVA EVA EVA 2 2 S General-Purpose (GP) Timers 2 2 S Compare (CMP)/PWM 7 7 8 8 S Capture (CAP)/QEP 1 1 3/2 3/2 S Input qualifier circuitry on PDPINTx, CAPn, XINT1/2, and ADCSOC pins Yes Yes Yes Yes Watchdog Timer Yes Yes Yes Yes 10-Bit ADC Yes Yes Yes Yes S Channels S Conversion Time (minimum) 5 5 8 8 500 ns 500 ns 500 ns 500 ns SPI -- -- -- -- SCI Yes Yes Yes Yes CAN -- -- -- -- Digital I/O Pins (Shared) 13 13 21 21 External Interrupts 2 2 3 3 Core 3.3 V 3.3 V 3.3 V 3.3 V I/O 3.3 V 3.3 V 3.3 V 3.3 V 32-pin VF 32-pin VF 64-pin PG 64-pin PG PD PD PD PD Supply Voltage Packaging Product Status : Product Preview (PP) Advance Information (AI) Production Data (PD) Some pins may not be applicable to Lx2401A. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 5 SPRS161K - MARCH 2001 - REVISED JULY 2007 functional block diagram of the LF2401A DSP controller VDD (3.3 V) VSS RS XF XINT1 XINT2 CLKOUT DARAM (B0) 256 Words C2xx DSP Core XTAL1/CLKIN PLL Clock DARAM (B1) 256 Words DARAM (B2) 32 Words 10-Bit ADC (With Twin Autosequencer) XTAL2 ADCIN00-ADCIN04 VCCA VSSA ADCSOC SCITXD/IOPB3 SARAM (512 Words) VCCP (5V) Flash (8K Words - 4K/4K Sectors) SCI WD Digital I/O (Shared With Other Pins) PDPINTA/IOPA0 SCIRXD/IOPB4 Port A(0-7) IOPA[0:7] Port B(0-5) IOPB[0:5] PWM1/IOPA1 PWM2/IOPA2 PWM3/IOPA3 PWM4/IOPA4 PWM5/IOPA5 PWM6/IOPA6 CAP1 Event Manager A D 1 x Capture Input D 7 x Compare/PWM Output D 2 x GP Timers/PWM TRST TDO/IOPB2 JTAG Port T2PWM TDI/OPB5 TMS/XF TCK/IOPB1 T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0. XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT. 6 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 functional block diagram of the LC2401A DSP controller VDD (3.3 V) VSS RS XF XINT1 XINT2 CLKOUT DARAM (B0) 256 Words C2xx DSP Core XTAL1/CLKIN PLL Clock DARAM (B1) 256 Words DARAM (B2) 32 Words 10-Bit ADC (With Twin Autosequencer) XTAL2 ADCIN00-ADCIN04 VCCA VSSA ADCSOC SCITXD/IOPB3 SARAM (512 Words) ROM (8K Words) SCI WD Digital I/O (Shared With Other Pins) PDPINTA/IOPA0 SCIRXD/IOPB4 Port A(0-7) IOPA[0:7] Port B(0-5) IOPB[0:5] PWM1/IOPA1 PWM2/IOPA2 PWM3/IOPA3 PWM4/IOPA4 PWM5/IOPA5 PWM6/IOPA6 CAP1 Event Manager A D 1 x Capture Input D 7 x Compare/PWM Output D 2 x GP Timers/PWM TRST TDO/IOPB2 JTAG Port T2PWM TDI/OPB5 TMS/XF TCK/IOPB1 T2PWM, XINT1, and IOPB0 functionalities are multiplexed into a single pin, T2PWM/XINT1/IOPB0. XINT2, ADCSOC, CAP1, IOPA7, and CLKOUT functionalities are multiplexed into a single pin, XINT2/ADCSOC/CAP1/IOPA7/CLKOUT. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 7 SPRS161K - MARCH 2001 - REVISED JULY 2007 20 19 ADCIN00 21 VSSA 22 VCCA XINT2/ADCSOC/CAP1/IOPA7 /CLKOUT 23 TRST TDO/ IOPB2 24 VSS TDI/ OPB5 32-PIN VF PACKAGE (TOP VIEW) 18 17 VDD 25 16 ADCIN01 VCCP 26 15 ADCIN02 PWM1/IOPA1 27 14 ADCIN03 PWM2/IOPA2 28 13 ADCIN04 PWM3/IOPA3 29 12 PWM6/IOPA6 VSS 30 11 PWM5/IOPA5 T2PWM/XINT1/IOPB0 31 10 PWM4/IOPA4 PDPINTA/IOPA0 32 6 7 8 XTAL2 VSS SCITXD/ IOPB3 5 XTAL1/CLKIN SCIRXD/ IOPB4 4 VDD 3 TCK/ IOPB1 2 TMS/ XF 9 1 Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A. NOTE A: Bold face type indicates function of the device pin after reset. 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 RS SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions Terminal Functions TERMINAL NAME DESCRIPTION NO. Device Reset (in) and Watchdog Reset (out). RS 9 Device reset. RS causes the device to terminate execution and to set PC = 0. When RS is brought to a high level, execution begins at location 0x0000 of program memory. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the RS pin will be driven low for the watchdog reset duration of 128 CLKIN cycles. The output buffer of this pin is an open-drain with an internal pullup (20 A, typical). It is recommended that this pin be driven by an open-drain device. () Power drive protection input. When this pin is pulled low by an external event, an interrupt is generated and all PWM outputs go to high-impedance state. PDPINTA will keep PWM outputs in high-impedance state even when the DSP is not executing. () NOTES: 1) Upon reset, the PDPINTA function is active, in addition to the GPIO function. If the IOPA0 function is desired, the PDPINTA function must be disabled. (This can be done by writing to bit 0 of the EVAIMRA register.) Otherwise, the PWM outputs could inadvertently be put into a high-impedance state when the IOPA0 pin is driven low. 2) When PDPINTA is used to "wake up" the DSP from LPM2, the pin should be held low for (98304 CLKIN + 12 CLKOUT) cycles. 3) This pin must be held high when on-chip boot ROM is invoked. PDPINTA/IOPA0 32 PWM1/IOPA1 27 Compare/PWM output 1 or GPIO () PWM2/IOPA2 28 Compare/PWM output 2 or GPIO () PWM3/IOPA3 29 Compare/PWM output 3 or GPIO () PWM4/IOPA4 10 Compare/PWM output 4 or GPIO () PWM5/IOPA5 11 Compare/PWM output 5 or GPIO () PWM6/IOPA6 12 Compare/PWM output 6 or GPIO () 31 Upon reset, this pin comes up as XINT1/IOPB0 pin. To enable the XINT1 function, the appropriate bit in the XINT1CR register must be set. No special configuration sequence is needed to use this pin as a GPIO. However, a write to the PADATDIR register is necessary to configure this pin as a general-purpose output. Configuration of this pin as T2PWM is achieved by writing a one to bit 8 of the MCRA register. Note that the value of bit 8 in the MCRA register does not affect the XINT1 functionality of this pin. The XINT1 function is enabled/disabled by the value written into the XINT1CR register and is independent of the value written in bit 8 in the MCRA register. () 22 Upon reset, this pin can be configured as any one of the following: XINT2, ADCSOC, CAP1, or IOPA7. To configure this pin for XINT2 function, the appropriate bit in the XINT2CR register must be set. To configure this pin for ADCSOC function, the appropriate bit in the ADCTRL2 register must be set. To configure this pin for CAP1 function, the appropriate bits in the CAPCONA register must be configured. To summarize, the XINT2, ADCSOC, and CAP1 functions are enabled at the respective peripheral level. No special configuration sequence is needed to use this pin as a GPIO. However, a write to the PADATDIR register is necessary to configure this pin as a general-purpose output. This pin can also function as the CPU clock output. This is achieved by writing a one to bit 7 of the MCRA register. When CLKOUT is chosen, the internal logic for the XINT2, ADCSOC, and CAP1 sees the pin as a "1". () T2PWM/XINT1/IOPB0 XINT2/ADCSOC/CAP1/ IOPA7/CLKOUT Bold face type indicates function of the device pin after reset. It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. TDI is MUXed with digital output, not digital I/O. Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A. LEGEND: - Internal pullup - Internal pulldown (Typical active pullup/pulldown value is 20 A.) NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 9 SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions (continued) Terminal Functions (Continued) TERMINAL NAME DESCRIPTION NO. ADCIN00 17 Analog input channel 0 ADCIN01 16 Analog input channel 1 ADCIN02 15 Analog input channel 2 ADCIN03 14 Analog input channel 3 ADCIN04 13 Analog input channel 4 VCCA VSSA 19 Analog supply voltage for ADC (3.3 V) Internally connected to VREFHI 18 Analog ground reference for ADC. Internally connected to VREFLO . SCITXD/IOPB3 3 SCI asynchronous serial port transmit data or GPIO () SCIRXD/IOPB4 2 SCI asynchronous serial port receive data or GPIO () JTAG test clock or GPIO () TCK/IOPB1 TDI/OPB5 4 24 Function when TRST = 0: IOPB1 Function when TRST = 1: TCK JTAG test data input or GPO. When TRST is low (i.e., when the JTAG connector is not connected to the DSP), the TDI/OPB5 pin acts as an output. When RS is low, the OPB5 pin is asynchronously forced into a high-impedance state and when RS subsequently rises, it will remain in high-impedance state until software configures this pin as an output. The B5DIR bit (bit 13 of the PBDATDIR register) controls the enable to this output buffer. Bit 13 of the MCRA register will have no effect on this pin. () This pin must be held low during a reset to invoke the on-chip boot ROM. Function when TRST = 0: OPB5 Function when TRST = 1: TDI JTAG scan out, test data output or GPIO () TDO/IOPB2 23 Function when TRST = 0: IOPB2 Function when TRST = 1: TDO JTAG test mode select or GPO. External flag output (latched software-programmable signal). XF is a general-purpose output pin. It is set/reset by the SETC XF/CLRC XF instruction. This pin is configured as an external flag output by all device resets. () TMS/XF 1 Function when TRST = 0: XF Function when TRST = 1: TMS NOTE: The enabling/disabling of the XF pin is controlled by Bit 0 of the SCSR4 register at address 0x701B (in addition to the TRST pin). Upon reset, this bit is zero, disabling the XF pin. This bit must be set by user code before it can be used. This bit is not readable; hence, its status cannot be determined. Bold face type indicates function of the device pin after reset. It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. TDI is MUXed with digital output, not digital I/O. Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A. LEGEND: - Internal pullup - Internal pulldown (Typical active pullup/pulldown value is 20 A.) NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high. 10 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions (continued) Terminal Functions (Continued) TERMINAL NAME DESCRIPTION NO. JTAG test reset. The function of the TCK, TDI, TDO, and TMS pins depend on the state of the TRST pin. If TRST = 1 (Test or Debugging mode), the function of these pins will be JTAG function (the GPIO function of these pins is not available). If TRST = 0 (Functional mode), these pins function as GPIO. () NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. TRST is an active high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-k resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. TRST 20 XTAL1/CLKIN 6 Crystal/Clock input to PLL XTAL2 7 Crystal output VCCP 26 Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash programming. The Flash cannot be programmed if this pin is connected to GND. When not programming the Flash (i.e., during normal device operation), this pin can either be left connected to the 5-V supply or it can be tied to GND. This pin must not be left floating at any time. Do not use any current-limiting resistor in series with the 5-V supply on this pin. This pin is a "no connect" (NC) on ROM parts (i.e., this pin is not connected to any circuitry internal to the device). Connecting this pin to 5 V or leaving it open makes no difference on ROM parts. VDD VDD 5 Core supply (3.3 V) 25 Core supply (3.3 V) 8 Core ground 21 Core ground VSS VSS VSS 30 Core ground Bold face type indicates function of the device pin after reset. It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy and improve the noise immunity of the ADC. TDI is MUXed with digital output, not digital I/O. Pin 26 is VCCP on LF2401A and is a No Connect (NC) on LC2401A. LEGEND: - Internal pullup - Internal pulldown (Typical active pullup/pulldown value is 20 A.) NOTE: On the target hardware, pins 13 and 14 (EMU0/EMU1) of the JTAG header must be pulled high. NOTE: The I/O pins that are MUXed with the JTAG function cannot be used while debugging, since the emulator needs complete control of the JTAG pins. While debugging, there should not be any circuitry connected on these MUXed pins that could disturb the JTAG debug process. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 11 SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions (continued) NOTE: The multiplexing diagrams are functional representations of the multiplexing scheme. They do not represent the actual circuit elements within the silicon. PADATDIR.n [IOPAn - input data] PADATDIR.m (Direction) 0 FCOMPOE [COMCONA.9] 1 Pullup PWMn/IOPAn Pin MCRA.k PADATDIR.n [IOPAn - Output Data] 0 PWMn 1 MCRA.k PWMn/IOPAn DIRECTION BIT DATA BIT MCRA.1 PWM1/IOPA1 PADATDIR.9 PADATDIR.1 MCRA.2 PWM2/IOPA2 PADATDIR.10 PADATDIR.2 MCRA.3 PWM3/IOPA3 PADATDIR.11 PADATDIR.3 MCRA.4 PWM4/IOPA4 PADATDIR.12 PADATDIR.4 MCRA.5 PWM5/IOPA5 PADATDIR.13 PADATDIR.5 MCRA.6 PWM6/IOPA6 PADATDIR.14 PADATDIR.6 Figure 1. PWMn/IOPAn Pin Multiplexing Functional Block Diagram PADATDIR.0 [IOPA0 - Input Data] PADATDIR.0 [IOPA0 - Output Data] Pullup PDPINTA/IOPA0 Pin MCRA.0 PADATDIR.8 Input Qualifier Circuit PDPINTA EVAIMRA.0 Figure 2. PDPINTA/IOPA0 Pin Multiplexing Functional Block Diagram 12 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions (continued) 1 1 PADATDIR.7 [IOPA7 - Input Data] 0 XINT2 and XINT2 LPM1 Wakeup Logic Input Qualifier Circuit XINT2CR.0 CAP1 CAPCONA[14,13] Pullup XINT2/ADCSOC/ CAP1/IOPA7/ CLKOUT Pin ADSOC ADCTRL2.7 MCRA.7 PADATDIR.15 (Direction) CLKOUT 1 PADATDIR.7 [IOPA7 - Output Data] 0 Figure 3. XINT2/ADCSOC/CAP1/IOPA7/CLKOUT Pin Multiplexing Functional Block Diagram POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 13 SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions (continued) PBDATDIR.0 [IOPB0 - Input Data] XINT1CR.0 XINT1 and XINT1 LPM1 Wakeup Logic Input Qualifier Circuit Pullup T2PWM/XINT1/IOPB0 Pin PBDATDIR.8 (Direction Bit) 0 TCOMPOE [GPTCONA.6] 1 MCRA.8 PBDATDIR.0 [IOPB0 - Output Data] 0 T2PWM [PWM Signal] 1 Figure 4. T2PWM/XINT1/IOPB0 Pin Multiplexing Functional Block Diagram PBDATDIR.3 [IOPB3 - Input Data] PBDATDIR.11 (Direction Bit) Pullup SCITXD/ IOPB3 Pin MCRA.11 PBDATDIR.3 [IOPB3 - Output Data] 0 SCITXD 1 Figure 5. SCITXD/IOPB3 Pin Multiplexing Functional Block Diagram 14 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions (continued) SCIRXD PBDATDIR.4 [IOPB4 - Input Data] Pullup PBDATDIR.12 (Direction Bit) SCIRXD/IOPB4 Pin MCRA.12 PBDATDIR.4 [IOPB4 - Output Data] Figure 6. SCIRXD/IOPB4 Pin Multiplexing Functional Block Diagram POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 15 SPRS161K - MARCH 2001 - REVISED JULY 2007 terminal functions (continued) TCK Pullup PBDATDIR.1 [IOPB1 - Input Data] PBDATDIR.1 [IOPB1 - Output Data] TCK/IOPB1 Pin TRST To CPU RS PBDATDIR.9 (Direction Bit) Pullup TDI TDI/OPB5 Pin PBDATDIR.5 [OPB5 - Output Data] TRST RS PBDATDIR.13 (Direction Bit) IOPBDATDIR.2 [IOPB2 - Input Data] TDO/IOPB2 Pin PBDATDIR.2 [IOPB2 - Output Data] 0 TDO 1 Pulldown TRST RS PBDATDIR.10 (Direction Bit) Pullup TMS TMS/XF Pin XF TRST Bit 0 of SCSR4 TRST Pin Pulldown This bit is a write-only bit. Figure 7. JTAG/GPIO Pins Multiplexing Functional Block Diagram 16 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 constraints while emulating with JTAG port pins and GPIO functions This section highlights the constraints that are encountered if the emulation/debugging tool attempts to use the multiplexed JTAG/GPIO pins in their JTAG configuration while the application attempts to use them in the GPIO configuration at the same time: 1. Since the emulation/debugging tools need complete control of the JTAG port pins, the GPIO functions that are multiplexed with the JTAG port pins cannot be used when the JTAG pod is connected to the JTAG header. 2. Applications using the JTAG port pins for its GPIO function must provide some isolation mechanism (such as jumpers) to isolate the external circuitry associated with the GPIO circuits. This will ensure that the GPIO circuit does not conflict with the signals from the JTAG pod. To reiterate, the circuitry associated with the GPIO pins must be isolated from the DSP before the JTAG pod is connected to the JTAG header. 3. It is recommended that the Lx2401A application software does not enable GPIO function for the multiplexed JTAG/GPIO pins if emulation tools are ever planned to be used concurrently. This will avoid drive conflicts between JTAG pod signals and GPIO signals--particularly on TCK, TDI and TMS pins. Table 2 shows the configuration of the multiplexed JTAG/GPIO pins depending on the status of the TRST pin. Table 2. Configuration of Multiplexed JTAG/GPIO Pins TRST = 1 TRST = 0 TCK (signal from the JTAG pod) Can be configured as IOPB1 TDI (signal from the JTAG pod) Can be configured as OPB5 TMS (signal from the JTAG pod) Can be configured as XF 4. TRST pin is internally pulled down. When this pin is left unconnected, it puts the multiplexed JTAG/GPIO pins in their GPIO configuration. If TRST is driven high, it puts the multiplexed JTAG/GPIO pins in their JTAG configuration and the device enters emulation mode. All the emulation and flash programming tools use the JTAG port and will drive this pin high. TRST pin controls the functionality of the multiplexed JTAG/GPIO pins. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 17 SPRS161K - MARCH 2001 - REVISED JULY 2007 in-circuit emulation options The GPIO functionality of the JTAG/GPIO pins cannot be used when the JTAG function is used for debugging. In applications which require full emulation, it is easy to build an in-circuit emulation system using a 2407A EVM (or any TMS320LF240x target board). This requires some additional planning in the Lx2401A target board design. The following suggestions may be used as a guideline while planning the board layout: 1. Make provisions for a connector (port) which will bring out all the Lx2401A signals. 2. Map these signals (such as PWM, SCI, ADC, GPIO) through a cable to the 2407A EVM connector signals. 3. Using the 2407A EVM emulation device, there are two options to build your software: a. Use assembler directives to enable 2407A register mapping. - Build your application using 2407A emulation board with the 2401A target board connected using the harness suggested above. - After software development is complete, rebuild the code using the assembler directive to use 2401A registers. - Map and flash the code in Lx2401A. The end application should now run seamlessly on the 2401A target with Lx2401A device. b. Use the device IDs of 2407A and 2401A devices to select the required pin-mapping for your application. - The Device ID for these devices is a unique number located at 701Ch. - Build your application using the 2407A emulation board with the 2401A target board connected using the harness suggested above. - After software development is complete, flash the code in Lx2401A. The end application will select the map and the registers based on the device ID and should now run seamlessly on the 2401A target with Lx2401A device. Lx2401A Target Lx2401A/EVM Harness JTAG Link LF2407A EVM as In-Circuit Emulator Code Composer for LF2407A EVM Figure 8. Lx2401A Emulation Using LF2407A EVM as In-Circuit Emulator (Optional) 18 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 memory map Hex 0000 0FFF 1000 1FFF 2000 Hex 0000 Program FLASH SECTOR 0 (4K) Interrupt Vectors (0000-003Fh) Reserved (0040-0043h) User code begins at 0044h EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE FLASH SECTOR 1 (4K) Reserved 7FFF 8000 81FF 8200 87FF 8800 SARAM (512 words) Internal (PON = 1) Reserved (PON = 0) Memory-Mapped Registers/Reserved Addresses EEEEEEEEE EEEEEEEEE EEEEEEEEE 02FF 0300 03FF 0400 04FF 0500 07FF 0800 EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEE EEE EEE EEE 0FFF 1000 6FFF 7000 7FFF 8000 Reserved On-Chip DARAM B2 Illegal Reserved On-Chip DARAM (B0) (CNF = 0) Reserved (CNF = 1) On-Chip DARAM (B1) Reserved Illegal SARAM (512 words) Internal (DON = 1) Reserved (DON = 0) Reserved Illegal Peripheral Memory-Mapped Registers (System, WD, ADC, EV, SCI, I/O) FEFF FF00 FF0E FDFF FE00 Illegal Reserved FEFF FF00 Hex 0000 005F 0060 007F 0080 00FF 0100 01FF 0200 09FF 0A00 Reserved Data FF0F FF10 FFFE On-Chip DARAM (B0) (CNF = 1) Reserved (CNF = 0) FFFF FFFF On-Chip Flash Memory (Sectored) FFFF EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE I/O Reserved Reserved Flash Control Mode Register Reserved Reserved SARAM (See Table 1 for details.) Reserved or Illegal NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000-00FF in the program space will be occupied by boot ROM. Addresses 0040h-0043h in program memory are reserved for code security passwords. When CNF = 1, addresses FE00h-FEFFh and FF00h-FFFFh are mapped to the same physical block (B0) in program-memory space. For example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h-FEFFh are referred to as reserved. When CNF = 0, addresses 0100h-01FFh and 0200h-02FFh are mapped to the same physical block (B0) in data-memory space. For example, a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h-01FFh are referred to as reserved. Addresses 0300h-03FFh and 0400h-04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h has the same effect as a write to 0300h. For simplicity, addresses 0400h-04FFh are referred to as reserved. Figure 9. TMS320LF2401A Memory Map POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 19 SPRS161K - MARCH 2001 - REVISED JULY 2007 memory map (continued) Hex 0000 1FBF 1FCO EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE 1FFF 2000 Reserved Reserved 7FFF 8000 81FF 8200 87FF 8800 SARAM (512 words) Internal (PON = 1) Reserved (PON = 0) Reserved Reserved FDFF FE00 Reserved FEFF FF00 On-Chip DARAM (B0) (CNF = 1) Reserved (CNF = 0) FFFF EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEEEEEEEEE EEE EEE EEE EEE Hex 0000 Program On-chip ROM (8K) Interrupt Vectors (0000-003Fh) Reserved (0040-0043h) User code begins at 0044h 005F 0060 007F 0080 00FF 0100 01FF 0200 02FF 0300 03FF 0400 04FF 0500 07FF 0800 Data Memory-Mapped Registers/Reserved Addresses Illegal Reserved On-Chip DARAM (B0) (CNF = 0) Reserved (CNF = 1) On-Chip DARAM (B1) Reserved Illegal Reserved Illegal Peripheral Memory-Mapped Registers (System, WD, ADC, EV, SCI, I/O) FEFF FF00 Reserved Illegal FF10 FFFE Reserved Reserved FFFF FFFF On-chip ROM Reserved SARAM (512 words) Internal (DON = 1) Reserved (DON = 0) 0FFF 1000 7FFF 8000 I/O On-Chip DARAM B2 09FF 0A00 6FFF 7000 Hex 0000 SARAM (See Table 1 for details.) Reserved or Illegal NOTE A: Boot ROM: If the boot ROM is enabled, then addresses 0000-00FF in the program space will be occupied by boot ROM. Addresses 0040h-0043h in program memory are reserved for code security passwords. When CNF = 1, addresses FE00h-FEFFh and FF00h-FFFFh are mapped to the same physical block (B0) in program-memory space. For example, a write to FE00h has the same effect as a write to FF00h. For simplicity, addresses FE00h-FEFFh are referred to as reserved. When CNF = 0, addresses 0100h-01FFh and 0200h-02FFh are mapped to the same physical block (B0) in data-memory space. For example, a write to 0100h has the same effect as a write to 0200h. For simplicity, addresses 0100h-01FFh are referred to as reserved. Addresses 0300h-03FFh and 0400h-04FFh are mapped to the same physical block (B1) in data-memory space. For example, a write to 0400h has the same effect as a write to 0300h. For simplicity, addresses 0400h-04FFh are referred to as reserved. Figure 10. TMS320LC2401A Memory Map 20 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral memory map Interrupt-Mask Register Hex 0000 0003 0004 Reserved 0005 Interrupt Flag Register 0006 0007 Reserved Emulation Registers and Reserved Hex 0000 005F 0060 007F 0080 00FF 0100 Memory-Mapped Registers and Reserved EEEEEEEEE EEEEEEEEE On-Chip DARAM B2 Illegal Reserved 01FF 0200 On-Chip DARAM B0 02FF 0300 03FF 0400 On-Chip DARAM B1 EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEE EEEEE EEEEE 04FF 0500 07FF 0800 09FF 0A00 6FFF 7000 73FF 7400 743F 7440 74FF 7500 Reserved Illegal SARAM (512 words) Illegal Peripheral Frame 1 (PF1) Peripheral Frame 2 (PF2) Illegal Reserved 753F 7540 Illegal 77EF 77F0 77F3 77F4 77FF 7800 Code Security Passwords Reserved Illegal FFFF Illegal Reserved "Illegal" indicates that access to these addresses causes a nonmaskable interrupt (NMI). "Reserved" indicates addresses that are reserved for test. 005F EEEEEEEEE EEEEEEEEE Illegal 7000-700F System Configuration and Control Registers 7010-701F Watchdog Timer Registers 7020-702F Illegal 7030-703F Reserved 7040-704F EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE EEEEEEEEE SCI 7050-705F Illegal 7060-706F External interrupt registers 7070-707F Illegal 7080-708F Digital I/O Control Registers 7090-709F ADC Control Registers 70A0-70BF Illegal 70C0-70FF Reserved 7100-710E Illegal 710F-71FF Reserved 7200-722F Illegal 7230-73FF Event Manager - EVA General-Purpose Timer Registers Compare, PWM, and Deadband Registers 7400-7408 7411-7419 Capture Registers 7420-7429 Interrupt Mask, Vector and Flag Registers 742C-7431 Illegal 7432-743F EEEEEEEEE EEEEEEEEE Figure 11. Peripheral Memory Map POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 21 SPRS161K - MARCH 2001 - REVISED JULY 2007 device reset and interrupts The TMS320Lx2401A software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The Lx2401A recognizes three types of interrupt sources. D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any other executing functions. All maskable interrupts are disabled until the reset service routine enables them. The Lx2401A devices have two sources of reset: an external reset pin and a watchdog timer time-out (reset). D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two types: - External interrupts are generated by one of three external pins corresponding to the interrupts XINT1, XINT2, and PDPINTA. These three can be masked both by dedicated enable bits and by the CPU interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. - Peripheral interrupts are initiated internally by these on-chip peripheral modules: event manager A, SCI, and ADC. They can be masked both by enable bits for each event in each peripheral and by the CPU IMR, which can mask each maskable interrupt line at the DSP core. D Software-generated interrupts for the Lx2401A devices include: - The INTR instruction. This instruction allows initialization of any Lx2401A interrupt with software. Its operand indicates the interrupt vector location to which the CPU branches. This instruction globally disables maskable interrupts (sets the INTM bit to 1). - The NMI instruction. This instruction forces a branch to interrupt vector location 24h. This instruction globally disables maskable interrupts. Lx2401A devices do not have the NMI hardware signal, only software activation is provided. - The TRAP instruction. This instruction forces the CPU to branch to interrupt vector location 22h. The TRAP instruction does not disable maskable interrupts (INTM is not set to 1); therefore, when the CPU branches to the interrupt service routine, that routine can be interrupted by the maskable hardware interrupts. - An emulator trap. This interrupt can be generated with either an INTR instruction or a TRAP instruction. Six core interrupts (INT1-INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to the F24x devices. The PIE manages all the peripheral interrupts from the Lx2401A peripherals and are grouped to share the six core level interrupts. Figure 12 shows the PIE block diagram for hardware-generated interrupts. The PIE block diagram (Figure 12) and the interrupt table (Table 3) explain the grouping and interrupt vector maps. Lx2401A devices have interrupts identical to those of the F24x devices. See Table 3 for details. 22 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 device reset and interrupts (continued) PIE IMR PDPINTA IFR ADCINT RXINT TXINT Level 1 IRQ GEN INT1 XINT1 XINT2 INT2 CMP1INT CMP2INT CMP3INT T1PINT T1CINT T1UFINT T1OFINT Level 2 IRQ GEN CPU INT3 T2PINT T2CINT T2UFINT T2OFINT Level 3 IRQ GEN INT4 CAP1INT Level 4 IRQ GEN RXINT TXINT Level 5 IRQ GEN ADCINT XINT1 INT5 INT6 Level 6 IRQ GEN IACK XINT2 PIVR & Logic PIRQR# PIACK# Data Bus Addr Bus Interrupt from external interrupt pin. The remaining interrupts are internal to the peripherals. Figure 12. Peripheral Interrupt Expansion (PIE) Module Block Diagram for Hardware-Generated Interrupts POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 23 SPRS161K - MARCH 2001 - REVISED JULY 2007 interrupt request structure Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors OVERALL PRIORITY CPU INTERRUPT AND VECTOR ADDRESS Reset 1 Reserved PERIPHERAL INTERRUPT VECTOR (PIV) MASKABLE? SOURCE PERIPHERAL MODULE RSN 0000h N/A N RS pin, Watchdog Reset from timeout 2 - 0026h N/A N CPU Emulator trap NMI 3 NMI 0024h N/A N Nonmaskable Interrupt PDPINTA 4 0.0 0020h Y EVA Power device interrupt pin ADCINT 6 0.1 0004h Y ADC ADC interrupt in high-priority mode XINT1 7 0.2 0001h Y External Interrupt Logic INTERRUPT NAME INT1 0002h BIT POSITION IN PIRQRx AND PIACKRx DESCRIPTION pin, watchdog Nonmaskable interrupt, software interrupt only protection External interrupt pins in high priority 0.3 0011h Y External Interrupt Logic 10 0.5 0006h Y SCI SCI receiver interrupt high-priority mode in TXINT 11 0.6 0007h Y SCI SCI transmitter interrupt high-priority mode in CMP1INT 14 0.9 0021h Y EVA Compare 1 interrupt CMP2INT 15 0.10 0022h Y EVA Compare 2 interrupt CMP3INT 16 T1PINT 17 T1CINT XINT2 8 RXINT 0.11 0023h Y EVA Compare 3 interrupt 0.12 0027h Y EVA Timer 1 period interrupt 18 0.13 0028h Y EVA Timer 1 compare interrupt T1UFINT 19 0.14 0029h Y EVA Timer 1 underflow interrupt T1OFINT 20 0.15 002Ah Y EVA Timer 1 overflow interrupt T2PINT 28 1.0 002Bh Y EVA Timer 2 period interrupt T2CINT 29 1.1 002Ch Y EVA Timer 2 compare interrupt T2UFINT 30 1.2 002Dh Y EVA Timer 2 underflow interrupt T2OFINT 31 1.3 002Eh Y EVA Timer 2 overflow interrupt 1.4 0033h Y EVA Capture 1 interrupt 1.8 0006h Y SCI SCI receiver interrupt (low-priority mode) 1.9 0007h Y SCI SCI transmitter interrupt (low-priority mode) CAP1INT 36 RXINT 43 TXINT 44 INT2 0004h INT3 0006h INT4 0008h INT5 000Ah Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information. NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details. 24 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 interrupt request structure (continued) Table 3. TMS320Lx2401A Interrupt Source Priority and Vectors (Continued) INTERRUPT NAME OVERALL PRIORITY ADCINT 47 XINT1 48 XINT2 CPU INTERRUPT AND VECTOR ADDRESS BIT POSITION IN PIRQRx AND PIACKRx PERIPHERAL INTERRUPT VECTOR (PIV) MASKABLE? SOURCE PERIPHERAL MODULE 1.12 0004h Y ADC 1.13 0001h Y External Interrupt Logic 0011h Y External Interrupt Logic 000Eh N/A Y CPU Analysis interrupt INT6 000Ch 49 Reserved 1.14 DESCRIPTION ADC interrupt (low priority) External interrupt pins (low-priority mode) TRAP N/A 0022h N/A N/A CPU TRAP instruction Phantom Interrupt Vector N/A N/A 0000h N/A CPU Phantom interrupt vector INT8-INT16 N/A 0010h-0020h N/A N/A CPU Software interrupt vectors INT20-INT31 N/A 00028h-0603Fh N/A N/A CPU Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more information. NOTE: Some interrupts may not be available in a particular device due to the absence of a peripheral. See Table 1 for more details. DSP CPU core The TMS320Lx2401A device uses an advanced Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures -- program and data -- for full-speed execution. This multiple bus structure allows data and instructions to be read simultaneously. Instructions support data transfers between program memory and data memory. This architecture permits coefficients that are stored in program memory to be read in RAM. This, coupled with a four-deep pipeline, allows the Lx2401A device to execute most instructions in a single cycle. See the functional block diagram of the 2401A DSP CPU for more information. TMS320Lx2401A instruction set The 2401A DSP implements a comprehensive instruction set that supports both numeric-intensive signal-processing operations and general-purpose applications, such as multiprocessing and high-speed control. For maximum throughput, the next instruction is prefetched while the current one is being executed. addressing modes The TMS320Lx2401A instruction set provides four basic memory-addressing modes: direct, indirect, immediate, and register. In direct addressing, the instruction word contains the lower seven bits of the data memory address. This field is concatenated with the nine bits of the data memory page pointer (DP) to form the 16-bit data memory address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages, with each page containing 128 words. Indirect addressing accesses data memory through the auxiliary registers. In this addressing mode, the address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary registers (AR0-AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register, the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 25 SPRS161K - MARCH 2001 - REVISED JULY 2007 scan-based emulation TMS320x2xx devices incorporate scan-based emulation logic for code-development and hardwaredevelopment support. Scan-based emulation allows the emulator to control the processor in the system without the use of intrusive cables to the full pinout of the device. The scan-based emulator communicates with the x2xx by way of the IEEE 1149.1-compatible (JTAG) interface. The Lx2401A DSP does not include boundary scan. The scan chain of the device is useful for emulation function only. 26 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 functional block diagram of the 2401A DSP CPU Program Bus Data Bus Control XF RS NPAR 16 PC PAR Program Bus MUX XTAL1 CLKOUT XTAL2 MSTACK MUX Stack 8 x 16 XINT[1-2] 2 FLASH EEPROM Program Control (PCTRL) 16 16 16 Data Bus Data Bus 16 16 16 9 3 AR0(16) DP(9) AR1(16) 16 7 LSB from IR 16 16 AR2(16) ARP(3) 16 MUX MUX AR3(16) 3 16 16 9 AR4(16) 3 AR5(16) ARB(3) TREG0(16) AR6(16) Multiplier AR7(16) 3 ISCALE (0-16) PREG(32) 16 32 PSCALE (-6, 0, 1, 4) 32 32 16 MUX ARAU(16) MUX 32 CALU(32) 16 32 Memory Map Register 32 MUX MUX Data/Prog DARAM B0 (256 x 16) Data DARAM B2 (32 x 16) IFR (16) GREG (16) C ACCH(16) ACCL(16) 32 B1 (256 x 16) MUX OSCALE (0-7) Program Bus IMR (16) 16 16 16 16 NOTES: A. See Table 4 for symbol descriptions. B. For clarity, the data and program buses are shown as single buses although they include address and data bits. C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU instruction set information. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 27 SPRS161K - MARCH 2001 - REVISED JULY 2007 2401A legend for the internal hardware Table 4. Legend for the 2401A DSP CPU Internal Hardware SYMBOL NAME DESCRIPTION ACC Accumulator 32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift and rotate capabilities ARAU Auxiliary Register Arithmetic Unit An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs and outputs AUX REGS Auxiliary Registers 0 -7 These 16-bit registers are used as pointers to anywhere within the data space address range. They are operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used as an index value for AR updates of more than one and as a compare value to AR. C Carry Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator shifts and rotates. CALU Central Arithmetic Logic Unit 32-bit-wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and provides status results to PCTRL. DARAM Dual-Access RAM If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM (DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2 are mapped to data memory space only, at addresses 0300-03FF and 0060-007F, respectively. Blocks 0 and 1 contain 256 words, while block 2 contains 32 words. DP Data Memory Page Pointer The 9-bit DP register is concatenated with the seven least significant bits (LSBs) of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. GREG Global Memory Allocation Register GREG specifies the size of the global data memory space. Since the global memory space is not used in the 240x devices, this register is reserved. IMR Interrupt Mask Register IMR individually masks or enables the seven interrupts. IFR Interrupt Flag Register The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable interrupts. INT# Interrupt Traps A total of 32 interrupts by way of hardware and/or software are available. ISCALE Input Data-Scaling Shifter 16- to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations. MPY Multiplier 16 x 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either signed or unsigned 2s-complement arithmetic multiply. MSTACK Micro Stack MSTACK provides temporary storage for the address of the next instruction to be fetched when program address-generation logic is used to generate sequential addresses in data space. MUX Multiplexer Multiplexes buses to a common input NPAR Next Program Address Register NPAR holds the program address to be driven out on the PAB in the next cycle. OSCALE Output Data-Scaling Shifter 16- to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the data-write data bus (DWEB). PAR Program Address Register PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory operations scheduled for the current bus cycle. PC Program Counter PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential data-transfer operations. PCTRL Program Controller PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations. 28 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 2401A legend for the internal hardware (continued) Table 4. Legend for the 2401A DSP CPU Internal Hardware (Continued) SYMBOL NAME DESCRIPTION PREG Product Register 32-bit register holds results of 16 x 16 multiply PSCALE Product-Scaling Shifter 0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product. The left-shift options are used to manage the additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down the number to manage overflow of product accumulation in the CALU. PSCALE resides in the path from the 32-bit product shifter and from either the CALU or the data-write data bus (DWEB), and requires no cycle overhead. STACK Stack STACK is a block of memory used for storing return addresses for subroutines and interrupt-service routines, or for storing data. The C2xx stack is 16 bits wide and 8 levels deep. TREG Temporary Register 16-bit register holds one of the operands for the multiply operations. TREG holds the dynamic shift count for the LACT, ADDT, and SUBT instructions. TREG holds the dynamic bit position for the BITT instruction. status and control registers Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved and restored for subroutines. The load status register (LST) instruction is used to write to ST0 and ST1. The store status register (SST) instruction is used to read from ST0 and ST1 -- except for the INTM bit, which is not affected by the LST instruction. The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. Figure 13 shows the organization of status registers ST0 and ST1, indicating all status bits contained in each. Several bits in the status registers are reserved and are read as logic 1s. Table 5 lists status register field definitions. 15 ST0 13 ARP 15 ST1 13 ARB 12 11 10 9 OV OVM 1 INTM 8 0 12 11 10 9 8 7 6 5 4 3 2 CNF TC SXM C 1 1 1 1 XF 1 1 DP 1 0 PM Figure 13. Organization of Status Registers ST0 and ST1 Table 5. Status Register Field Definitions FIELD FUNCTION ARB Auxiliary register pointer buffer. When the ARP is loaded into ST0, the old ARP value is copied to the ARB except during an LST instruction. When the ARB is loaded by way of an LST #1 instruction, the same value is also copied to the ARP. ARP Auxiliary register (AR) pointer. ARP selects the AR to be used in indirect addressing. When the ARP is loaded, the old ARP value is copied to the ARB register. ARP can be modified by memory-reference instructions when using indirect addressing, and by the LARP, MAR, and LST instructions. The ARP is also loaded with the same value as ARB when an LST #1 instruction is executed. C Carry bit. C is set to 1 if the result of an addition generates a carry, or reset to 0 if the result of a subtraction generates a borrow. Otherwise, C is reset after an addition or set after a subtraction, except if the instruction is ADD or SUB with a 16-bit shift. In these cases, ADD can only set and SUB can only reset the carry bit, but cannot affect it otherwise. The single-bit shift and rotate instructions also affect C, as well as the SETC, CLRC, and LST #1 instructions. Branch instructions have been provided to branch on the status of C. C is set to 1 on a reset. CNF On-chip RAM configuration control bit. If CNF is set to 0, the reconfigurable data dual-access RAM blocks are mapped to data space; otherwise, they are mapped to program space. The CNF can be modified by the SETC CNF, CLRC CNF, and LST #1 instructions. RS sets the CNF to 0. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 29 SPRS161K - MARCH 2001 - REVISED JULY 2007 status and control registers (continued) Table 5. Status Register Field Definitions (Continued) FIELD FUNCTION DP Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions. INTM Interrupt mode bit. When INTM is set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled. INTM is set and reset by the SETC INTM and CLRC INTM instructions. RS also sets INTM. INTM has no effect on the unmaskable RS and NMI interrupts. Note that INTM is unaffected by the LST instruction. This bit is set to 1 by reset. It is also set to 1 when a maskable interrupt trap is taken. OV Overflow flag bit. As a latched overflow signal, OV is set to 1 when overflow occurs in the arithmetic logic unit (ALU). Once an overflow occurs, the OV remains set until a reset, BCND/D on OV/NOV, or LST instruction clears OV. OVM Overflow mode bit. When OVM is set to 0, overflowed results overflow normally in the accumulator. When set to 1, the accumulator is set to either its most positive or negative value upon encountering an overflow. The SETC and CLRC instructions set and reset this bit, respectively. LST can also be used to modify the OVM. PM Product shift mode. If these two bits are 00, the multiplier's 32-bit product is loaded into the ALU with no shift. If PM = 01, the PREG output is left-shifted one place and loaded into the ALU, with the LSB zero-filled. If PM = 10, the PREG output is left-shifted by 4 bits and loaded into the ALU, with the LSBs zero-filled. PM = 11 produces a right shift of 6 bits, sign-extended. Note that the PREG contents remain unchanged. The shift takes place when transferring the contents of the PREG to the ALU. PM is loaded by the SPM and LST #1 instructions. PM is cleared by RS. SXM Sign-extension mode bit. SXM = 1 produces sign extension on data as it is passed into the accumulator through the scaling shifter. SXM = 0 suppresses sign extension. SXM does not affect the definitions of certain instructions; for example, the ADDS instruction suppresses sign extension regardless of SXM. SXM is set by the SETC SXM instruction and reset by the CLRC SXM instruction and can be loaded by the LST #1 instruction. SXM is set to 1 by reset. TC Test/control flag bit. TC is affected by the BIT, BITT, CMPR, LST #1, and NORM instructions. TC is set to a 1 if a bit tested by BIT or BITT is a 1, if a compare condition tested by CMPR exists between AR (ARP) and AR0, if the exclusive-OR function of the 2 most significant bits (MSBs) of the accumulator is true when tested by a NORM instruction. The conditional branch, call, and return instructions can execute based on the condition of TC. XF XF pin status bit. XF indicates the state of the XF pin, a general-purpose output pin. XF is set by the SETC XF instruction and reset by the CLRC XF instruction. XF is set to 1 by reset. central processing unit The TMS320Lx2401A central processing unit (CPU) contains a 16-bit scaling shifter, a 16 x 16-bit parallel multiplier, a 32-bit central arithmetic logic unit (CALU), a 32-bit accumulator, and additional shifters at the outputs of both the accumulator and the multiplier. This section describes the CPU components and their functions. The functional block diagram shows the components of the CPU. input scaling shifter The TMS320Lx2401A provides a scaling shifter with a 16-bit input connected to the data bus and a 32-bit output connected to the CALU. This shifter operates as part of the path of data coming from program or data space to the CALU and requires no cycle overhead. It is used to align the 16-bit data coming from memory to the 32-bit CALU. This is necessary for scaling arithmetic as well as aligning masks for logical operations. The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros; the MSBs can either be filled with zeros or sign-extended, depending upon the value of the SXM bit (sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment operations specific to that point in the code. The TREG base shift allows the scaling factor to be adaptable to the system's performance. 30 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 multiplier The TMS320Lx2401A device uses a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated with the multiplier, as follow: D 16-bit temporary register (TREG) that holds one of the operands for the multiplier D 32-bit product register (PREG) that holds the product Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6. Table 6. PSCALE Product-Shift Modes PM SHIFT 00 No shift DESCRIPTION 01 Left 1 Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product 10 Left 4 Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when using the multiply-by-a-13-bit constant 11 Right 6 Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow Product feed to CALU or data bus with no shift The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit 2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY (multiply) instruction provides the second operand (also from the data bus). A multiplication also can be performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining of the TREG load operations with CALU operations using the previous product. The pipeline operations that run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC (LTS). Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data for these operations can be transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient addresses are generated by program address generation (PAGEN) logic, while the data addresses are generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values from the coefficient table sequentially and step through the data in any of the indirect addressing modes. The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to throw away the oldest sample. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 31 SPRS161K - MARCH 2001 - REVISED JULY 2007 multiplier (continued) The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This process allows the operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32 bits. The SQRA (square / add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value. After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register (PREG). The product from PREG can be transferred to the CALU or to data memory by way of the SPH (store product high) and SPL (store product low) instructions. Note: the transfer of PREG to either the CALU or data bus passes through the PSCALE shifter, and therefore is affected by the product shift mode defined by PM. This is important when saving PREG in an interrupt-service-routine context save as the PSCALE shift effects cannot be modeled in the restore operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by loading the saved low half into TREG and executing a MPY #1 instruction. The high half, then, is loaded using the LPH instruction. central arithmetic logic unit The TMS320Lx2401A central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate it from a second ALU used for indirect-address generation called the auxiliary register arithmetic unit (ARAU). Once an operation is performed in the CALU, the result is transferred to the accumulator (ACC) where additional operations, such as shifting, can occur. Data that is input to the CALU can be scaled by ISCALE when coming from one of the data buses (DRDB or PRDB) or scaled by PSCALE when coming from the multiplier. The CALU is a general-purpose ALU that operates on 16-bit words taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform Boolean operations, facilitating the bit-manipulation ability required for a high-speed controller. One input to the CALU is always provided from the accumulator, and the other input can be provided from the product register (PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator. The TMS320Lx2401A device supports floating-point operations for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the LACT/ADDT/SUBT (load/add to/subtract from accumulator with shift specified by TREG) instructions. These instructions are useful in floating-point arithmetic where a number must be denormalized -- that is, floating-point to fixed-point conversion. They are also useful in the execution of an automatic gain control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of TREG. The CALU overflow saturation mode can be enabled/disabled by setting/resetting the OVM bit of ST0. When the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator is loaded with either the most positive or the most negative value representable in the accumulator, depending on the direction of the overflow. The value of the accumulator at saturation is 07FFFFFFFh (positive) or 080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result in overflow.) The CALU can execute a variety of branch instructions that depend on the status of the CALU and the accumulator. These instructions can be executed conditionally based on any meaningful combination of these status bits. For overflow management, these conditions include OV (branch on overflow) and EQ (branch on accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory. 32 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 central arithmetic logic unit (continued) The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other such non-arithmetic or control instructions. The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions use the previous value of carry in their addition/subtraction operation. The one exception to the operation of the carry bit is in the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset the carry bit only if a borrow is generated; otherwise, neither instruction affects it. Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing, based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the carry bit. The carry bit is set to one on a hardware reset. accumulator The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage in data memory. Shifters at the output of the accumulator provide a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged. When the postscaling shifter is used on the high word of the accumulator (bits 16-31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0-15). When the postscaling shifter is used on the low word, the LSBs are zero-filled. The SFL and SFR (in-place one-bit shift to the left / right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM = 1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM = 0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left) instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT) instructions can be used with the shift and rotate instructions for multiple-bit shifts. auxiliary registers and auxiliary-register arithmetic unit (ARAU) The 2401A provides a register file containing eight auxiliary registers (AR0 -AR7). The auxiliary registers are used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7, designating AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of these registers also can be stored in data memory or used as inputs to the CALU. The auxiliary register file (AR0-AR7) is connected to the ARAU. The ARAU can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either by 1 or by the contents of the AR0 register can be performed. As a result, accessing tables of information does not require the CALU for address manipulation; therefore, the CALU is free for other operations in parallel. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 33 SPRS161K - MARCH 2001 - REVISED JULY 2007 internal memory The TMS320Lx2401A device is configured with the following memory modules: D D D D D Dual-access random-access memory (DARAM) Single-access random-access memory (SARAM) ROM (LC2401A) Flash (LF2401A) Boot ROM dual-access RAM (DARAM) There are 544 words x 16 bits of DARAM on the 2401A device. The 2401A DARAM allows writes to and reads from the RAM in the same cycle. The DARAM is configured in three blocks: block 0 (B0), block 1 (B1), and block 2 (B2). Block 1 contains 256 words and Block 2 contains 32 words, and both blocks are located only in data memory space. Block 0 contains 256 words, and can be configured to reside in either data or program memory space. The SETC CNF (configure B0 as program memory) and CLRC CNF (configure B0 as data memory) instructions allow dynamic configuration of the memory maps through software. When using on-chip RAM, the 2401A runs at full speed with no wait states. The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature of the 2401A architecture, enables the device to perform three concurrent memory accesses in any given machine cycle. single-access RAM (SARAM) There are 512 words x 16 bits of SARAM on the Lx2401A. The PON and DON bits select SARAM (512 words) mapping in program space, data space, or both. See Table 16 for details on the SCSR2 register and the PON and DON bits. At reset, these bits are 11, and the on-chip SARAM is mapped in both the program and data spaces. ROM (LC2401A) There are 8K words x 16 bits of ROM on the LC2401A. Flash EEPROM (LF2401A) Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, Flash is nonvolatile. However, it has the advantage of "in-target" reprogrammability. The LF2401A incorporates one 8K 16-bit Flash EEPROM module in program space. The Flash module has two sectors that can be individually protected while erasing or programming. The sector size is partitioned as 4K/4K sectors. Unlike most discrete Flash memory, the LF2401A Flash does not require a dedicated state machine, because the algorithms for programming and erasing the Flash are executed by the DSP core. This enables several advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming, the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the algorithms and Flash code. This Flash requires 5 V for programming (at VCCP pin only) the array. The Flash runs at zero wait state while the device is powered at 3.3 V. IEEE Standard 1149.1-1990, IEEE Standard Test Access Port. 34 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 boot ROM Boot ROM is a 256-word ROM mapped in program space 0000h-00FFh. This ROM will be enabled if the BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when: TRST = 0 RS = 0 TDI = 0 (In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected (TRST = 1), it can be achieved by writing a "0" into bit 3 of the SCSR2 register. The boot ROM has a generic bootloader to transfer code through the SCI port. The incoming code should disable the BOOT_ROM bit by writing 1 to bit 3 of the SCSR2 register, or else, the whole Flash array will not be enabled. The boot ROM code sets the PLL to x2 or x4 option based on the condition of the SCITXD pin during reset. The SCITXD pin should be pulled high/low to select the PLL multiplication factor. The choices made are as follows: D If the SCITXD pin is pulled low, the PLL multiplier is set to 2. D If the SCITXD pin is pulled high, the PLL multiplier is set to 4. (Default) D If the SCITXD pin is not driven at reset, the internal pullup selects the default multiplier of 4. Care should be taken such that a combination of CLKIN and the PLL multiplication factor does not result in a CPU clock speed of greater than 40 MHz, the maximum rated speed. For restrictions concerning the maximum frequency of CLKIN, see the latest revision of the TMS320LF2401A DSP Controller Silicon Errata (literature number SPRZ013). Furthermore, when the bootloader is used, only specific values of CLKIN would result in a baud-lock for the SCI. Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more details about the bootloader operation. The boot ROM on LC2401A is used for test purposes. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 35 SPRS161K - MARCH 2001 - REVISED JULY 2007 Flash/ROM security The 2401A device has a security feature that prevents external access to Flash/ROM memory. This feature is useful in preventing unauthorized duplication of proprietary code resident on the Flash/ROM memory. If access to Flash/ROM contents are desired for debugging purposes, two actions need to be taken: 1. A "dummy" read of locations 40h, 41h, 42h and 43h (of program memory space) is necessary. The word "dummy" indicates that the destination address of this read is not relevant. If 40h-43h contain all zeros or ones, then Step 2 is not required. 2. A 64-bit password (split as four 16-bit words) must be written to the data-memory locations 77F0h, 77F1h, 77F2h, and 77F3h. The four 16-bit words written to these locations must match the four words stored in 40h, 41h, 42h, and 43h (of program memory space), respectively. The device becomes "unsecured" one cycle after the last instruction that unsecures the part. Code Security Module Disclaimer The Code Security Module ("CSM") included on this device was designed to password protect the data stored in the associated memory (either ROM or Flash) and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI's published specifications for the warranty period applicable for this device. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 36 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 PERIPHERALS The integrated peripherals of the TMS320Lx2401A are described in the following subsections: D D D D D D Event-manager module (EVA) Enhanced analog-to-digital converter (ADC) module Serial communications interface (SCI) module PLL-based clock module Digital I/O and shared pin functions Watchdog (WD) timer module event manager module (EVA) The event-manager module includes general-purpose (GP) timers, full-compare/PWM units, and a capture unit. Table 7 shows the module and signal names used. Table 7 also shows the features and functionality available for the event-manager module. The EVA peripheral register set starts at 7400h. The paragraphs in this section describe the function of the GP timers, the compare units, and the capture unit. Table 7. Module and Signal Names for EVA EVENT MANAGER MODULES MODULE SIGNAL Timer 1 Timer 2 -- T2PWM/T2CMP Compare Units Compare 1 Compare 2 Compare 3 PWM1/2 PWM3/4 PWM5/6 Capture Unit Capture 1 CAP1 GP Timers POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 37 SPRS161K - MARCH 2001 - REVISED JULY 2007 event manager module (EVA) (continued) 2401A DSP Core Data Bus ADDR Bus Reset INT2,3,4 Clock 16 3 16 16 16 16 EV Control Registers and Control Logic ADC Start of Conversion GP Timer 1 Compare GP Timer 1 T1CON[8,9,10] 16 16 CLKOUT (Internal) Prescaler Full-Compare Units 3 SVPWM State Machine PWM1 3 Deadband Units 3 Output Logic PWM6 16 16 GP Timer 2 Compare Output Logic GP Timer 2 T2PWM Prescaler CLKOUT (Internal) T2CON[8,9,10] 16 16 MUX 16 Capture Unit CAP1 16 Figure 14. Event Manager A Block Diagram 38 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 general-purpose (GP) timers There are two GP timers. GP timer x (x = 1 or 2) includes: D D D D D D D A 16-bit timer, up-/down-counter, TxCNT, for reads or writes A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes A 16-bit timer-control register,TxCON, for reads or writes Internal input clock A programmable prescaler for internal clock input Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interrupts The GP timers can be operated independently or synchronized with each other. The compare register associated with GP timer 2 can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up / down-counting operations. An internal input clock with programmable prescaler is used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, and GP timer 2/1 for the capture unit. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed. full-compare units There are three full-compare units on the event manager (EVA). These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. programmable deadband generator The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values (from 0 to 16 s) can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register. PWM waveform generation Up to eight PWM waveforms (outputs) can be generated simultaneously by EVA: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 39 SPRS161K - MARCH 2001 - REVISED JULY 2007 PWM characteristics Characteristics of the PWMs are as follows: D D D D D D D D D 16-bit registers Programmable deadband for the PWM output pairs, from 0 to 12 s Minimum deadband width of 25 ns Change of the PWM carrier frequency for PWM frequency wobbling as needed Change of the PWM pulse widths within and after each PWM period as needed External-maskable power and drive-protection interrupts Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms Minimized CPU overhead using auto-reload of the compare and period registers The PWM pins are driven to a high-impedance state when the PDPINTA pin is driven low and after PDPINTA signal qualification. The status of the PDPINTA pin (after qualification) is reflected in bit 8 of the COMCONA register. capture unit The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stack when selected transitions are detected on the capture input pin, CAP1. The capture unit consists of three capture circuits. The capture unit includes the following features: D D D D D One 16-bit capture control register, CAPCONA (R/W) One 16-bit capture FIFO status register, CAPFIFOA Selection of GP timer 1/2 as the time base One 16-bit 2-level-deep FIFO stack One capture input pin (CAP1). [The input is synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock.] D User-specified transition (rising edge, falling edge, or both edges) detection D One maskable interrupt flag input qualifier circuitry An input-qualifier circuitry qualifies the input signal to the CAP1, XINT1/2, ADCSOC, and PDPINTA pins in the 2401A device. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. 40 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 enhanced analog-to-digital converter (ADC) module A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include: D D D D 10-bit ADC core with built-in S/H Fast conversion time (S/H + Conversion) of 500 ns 5-channel, MUXed inputs Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be programmed to select any 1 of 5 input channels D Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers) D Sixteen result registers (individually addressable) to store conversion values - The digital value of the input analog voltage is derived by: Digital Value + 1023 Input Analog Voltage * V REFLO V REFHI * V REFLO NOTE: VREFLO is internally tied to VSSA ; VREFHI is internally tied to VCCA . D Multiple triggers as sources for the start-of-conversion (SOC) sequence - S/W - software immediate start - EVA - Event manager A (multiple event sources within EVA) - Ext - External pin (ADCSOC) D Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS D Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize conversions D EVA triggers can operate independently in dual-sequencer mode D Sample-and-hold (S/H) acquisition time window has separate prescale control NOTE: The 2401A ADC module is identical to the LF2407A ADC module. However, only channels ADCIN00 through ADCIN04 are bonded out of the device. For this reason, the valid values for the CONVnn bit fields in the CHSELSEQn registers are from 0 to 4. Attempting to convert channels 5 through 15 would yield indeterminate results. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 41 SPRS161K - MARCH 2001 - REVISED JULY 2007 enhanced analog-to-digital converter (ADC) module (continued) The ADC module in the 2401A has been enhanced to provide flexible interface to the event manager (EVA). The ADC interface is built around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H + conversion). The ADC module has 5 channels to service EVA. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 15 shows the block diagram of the 2401A ADC module. Result Registers Analog MUX Result Reg 0 ADCIN00 70A8h Result Reg 1 ADCIN01 10-Bit ADC Module (500 ns) ADCIN02 Result Reg 7 70AFh Result Reg 8 70B0h Result Reg 15 70B7h ADCIN03 ADCIN04 ADC Control Registers S/W EVA SOC Sequencer 1 Sequencer 2 SOC S/W ADCSOC Figure 15. Block Diagram of the 2401A ADC Module To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCINn pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (such as VCCA and VSSA) from the digital supply. Unused ADC inputs should be connected to analog ground for improved accuracy and ESD protection. 42 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 serial communications interface (SCI) module The 2401A device includes a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register. Features of the SCI module include: D Two external pins: - SCITXD: SCI transmit-output pin - SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. D Baud rate programmable to 64K different rates - Up to 2500 Kbps at 40-MHz CPUCLK D Data-word format D D D D D - One start bit - Data-word length programmable from one to eight bits - Optional even/odd/no parity bit - One or two stop bits Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: idle-line and address bit Half- or full-duplex operation Double-buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. - Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) - Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) D Separate enable bits for transmitter and receiver interrupts (except BRKDT) D NRZ (non-return-to-zero) format D Ten SCI module control registers located in the control register frame beginning at address 7050h NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the register data is in the lower byte (7 -0), and the upper byte (15 -8) is read as zeros. Writing to the upper byte has no effect. Figure 16 shows the SCI module block diagram. SCI speed will be limited by the I/O buffer speed and external transceiver performance. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 43 SPRS161K - MARCH 2001 - REVISED JULY 2007 serial communications interface (SCI) module (continued) TXWAKE Frame Format and Mode SCICTL1.3 Parity Even/Odd Enable SCICCR.6 SCICCR.5 1 SCITXBUF.7-0 Transmitter-Data Buffer Register SCI TX Interrupt TXRDY TX INT ENA SCICTL2.7 TX EMPTY 8 TXINT SCICTL2.0 External Connections SCICTL2.6 WUT TXENA TXSHF Register SCITXD SCITXD SCICTL1.1 SCIHBAUD. 15 -8 SCI Priority Level 1 Level 5 Int. 0 Level 1 Int. SCI TX Priority Baud Rate MSbyte Register Internal Clock SCILBAUD. 7 -0 SCIPRI.6 Baud Rate LSbyte Register Level 5 Int. 1 0 Level 1 Int. SCI RX Priority SCIPRI.5 RXENA RX ERR INT ENA SCICTL1.6 RX Error SCIRXST.7 SCIRXST.4 -2 RX Error FE OE PE SCIRXD SCICTL1.0 8 Receiver-Data Buffer Register SCIRXBUF.7-0 SCI RX Interrupt RXRDY SCIRXST.6 BRKDT SCIRXST.5 RX/BK INT ENA SCICTL2.1 RXINT RXWAKE SCIRXST.1 SCIRXD RXSHF Register Figure 16. Serial Communications Interface (SCI) Module Block Diagram 44 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 PLL-based clock module The 2401A has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different CPU clock rates. See Figure 17 for the PLL Clock Module Block Diagram and Table 8 for clock rates. The PLL-based clock module provides two modes of operation: D Crystal-operation This mode allows the use of an external crystal/resonator to provide the time base to the device. D External clock source operation This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the XTAL1/CLKIN pin. XTAL1/CLKIN Cb1 Fin PLL CLKOUT XTAL OSC RESONATOR/ CRYSTAL 3-bit PLL Select (SCSR1.[11:9]) XTAL2 Cb2 Figure 17. PLL Clock Module Block Diagram Table 8. PLL Clock Selection Through Bits (11-9) in SCSR1 Register CLK PS2 CLK PS1 CLK PS0 CLKOUT 0 0 0 4 x Fin 0 0 1 2 x Fin 0 1 0 1.33 x Fin 0 1 1 1 x Fin 1 0 0 1 0 1 0.8 x Fin 0.66 x Fin 1 1 0 0.57 x Fin 1 1 1 0.5 x Fin Default multiplication factor after reset is (1,1,1), i.e., 0.5 x Fin. CAUTION: The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN used should not force CLKOUT to exceed the maximum rated device speed. See the "Boot ROM" section for more details. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 45 SPRS161K - MARCH 2001 - REVISED JULY 2007 external reference crystal clock option The internal oscillator is enabled by connecting a crystal across the XTAL1/CLKIN and XTAL2 pins as shown in Figure 18a. The crystal should be in fundamental operation and parallel resonant, with an effective series resistance of 30 -150 and draws no more than 1 mW; it should be specified at a load capacitance of 20 pF. To ensure reliable starting of the internal oscillator upon power up, a 1-M resistor in parallel with the crystal (across the XTAL1 and XTAL2 pins) is recommended. See the TMS320LF2401A, TMS320LC2401A DSP Controller Silicon Errata (literature number SPRZ013) for more details. external reference oscillator clock option The internal oscillator is disabled by connecting a clock signal to XTAL1/CLKIN and leaving the XTAL2 input pin unconnected as shown in Figure 18b. XTAL1/CLKIN Cb1 (see Note A) XTAL2 Crystal XTAL1/CLKIN Cb2 (see Note A) XTAL2 External Clock Signal (Toggling 0 -3.3 V) (a) NC (b) NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire operating range. Figure 18. Recommended Crystal / Clock Connection low-power modes The 2401A has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if it is reset, or, if it receives an interrupt request. clock domains All 2401A-based devices have two clock domains: 1. CPU clock domain - consists of the clock for most of the CPU logic 2. System clock domain - consists of the peripheral clock (which is derived from CLKOUT of the CPU) and the clock for the interrupt logic in the CPU. When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues to run. This mode is also known as IDLE1 mode. The 2401A CPU also contains support for a second IDLE mode, IDLE2. By asserting IDLE2 to the 2401A CPU, both the CPU clock domain and the system clock domain are stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the oscillator and WDCLK are also shut down when in IDLE2 mode. Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the IDLE instruction is executed (see Table 9). These bits are located in the System Control and Status Register 1 (SCSR1), and they are described in the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357). 46 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 clock domains (continued) Table 9. Low-Power Modes Summary LOW-POWER MODE LPMx BITS SCSR1 [13:12] CPU CLOCK DOMAIN SYSTEM CLOCK DOMAIN WDCLK STATUS PLL STATUS OSC STATUS FLASH POWER EXIT CONDITION CPU running normally XX On On On On On On -- On Peripheral Interrupt, External Interrupt, Reset, PDPINTA IDLE1 - (LPM0) 00 Off On On On On IDLE2 - (LPM1) 01 Off Off On On On On Wakeup Interrupts, External Interrupt, Reset, PDPINTA HALT - (LPM2) [PLL/OSC power down] 1X Off Off Off Off Off Off Reset, PDPINTA The Flash must be powered down by the user code prior to entering LPM2. For more details, see the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357). other power-down options 2401A devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, and EVA. Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device. Depending on the application, these peripherals can be turned on/off to achieve low power. Refer to the SCSR1 register for details on the peripheral clock enable bits. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 47 SPRS161K - MARCH 2001 - REVISED JULY 2007 digital I/O and shared pin functions The 2401A has up to 13 general-purpose, bidirectional, digital I/O (GPIO) pins--most of which are shared between primary functions and I/O. Most I/O pins of the 2401A are shared with other functions. The digital I/O ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types: D Output Control Registers -- used to control the multiplexer selection that chooses between the primary function of a pin or the general-purpose I/O function. D Data and Control Registers -- used to control the data and data direction of bidirectional I/O pins. description of shared I/O pins Each shared I/O pin has three bits that define its operation: D MUX control bit -- this bit selects between the primary function (1) and I/O function (0) of the pin. D I/O direction bit -- if the I/O function is selected for the pin (MUX control bit is set to 0), this bit determines whether the pin is an input (0) or an output (1). D I/O data bit -- if the I/O function is selected for the pin (MUX control bit is set to 0) and the direction selected is an input, data is read from this bit; if the direction selected is an output, data is written to this bit. The MUX control bit, I/O direction bit, and I/O data bit are in the I/O control registers. A summary of shared pin configurations and associated bits is shown in Table 10. Table 10. Shared Pin Configurations PIN FUNCTION SELECTED (MCRA.n = 1) Primary Function (MCRA.n = 0) Secondary Function MUX CONTROL REGISTER (name.bit #) MUX CONTROL VALUE AT RESET (MCRx.n) PDPINTA IOPA0 MCRA.0 0 PWM1 IOPA1 MCRA.1 PWM2 IOPA2 PWM3 PWM4 I/O PORT DATA AND DIRECTION DATA BIT NO. DIR BIT NO. PADATDIR 0 8 0 PADATDIR 1 9 MCRA.2 0 PADATDIR 2 10 IOPA3 MCRA.3 0 PADATDIR 3 11 IOPA4 MCRA.4 0 PADATDIR 4 12 PWM5 IOPA5 MCRA.5 0 PADATDIR 5 13 PWM6 IOPA6 MCRA.6 0 PADATDIR 6 14 CLKOUT XINT2/ADCSOC/ CAP1/IOPA7 MCRA.7 0 PADATDIR 7 15 T2PWM XINT1/IOPB0 MCRA.8 0 PBDATDIR 0 8 IOPB1 IOPB1 MCRA.9 0 PBDATDIR 1 9 IOPB2 IOPB2 MCRA.10 0 PBDATDIR 2 10 SCITXD IOPB3 MCRA.11 0 PBDATDIR 3 11 SCIRXD IOPB4 MCRA.12 0 PBDATDIR 4 12 OPB5 OPB5 MCRA.13 0 PBDATDIR 5 13 - MCRA.14 0 PBDATDIR 6 14 - MCRA.15 0 PBDATDIR 7 REGISTER PORT A PORT B 15 Valid only if the I/O function is selected on the pin If the GPIO pin is configured as an output, these bits can be written to. If the pin is configured as an input, these bits are read from. If the DIR bit is 0, the GPIO pin functions as an input. For a value of 1, the pin is configured as an output. Even when MCRA.0 = 0, the PDPINT circuitry is still active. 48 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 digital I/O control registers Table 11 lists the registers available in the digital I/O module. As with other 2401A peripherals, these registers are memory-mapped to the data space. Table 11. Addresses of Digital I/O Control Registers ADDRESS REGISTER NAME 7090h MCRA I/O MUX control register A 7098h PADATDIR I/O port A data and direction register 709Ah PBDATDIR I/O port B data and direction register CAUTION: The bit definitions of the MCRA, PADATDIR, and PBDATDIR registers are not compatible with those of other 24x/240x/240xA devices. watchdog (WD) timer module The 2401A device includes a watchdog (WD) timer module. The WD function of this module monitors software and hardware operation by generating a system reset if it is not periodically serviced by software by having the correct key written. The WD timer operates independently of the CPU. It does not need any CPU initialization to function. When a system reset occurs, the WD timer defaults to the fastest WD timer rate available (WDCLK signal = CLKOUT/512). As soon as reset is released internally, the CPU starts executing code, and the WD timer begins incrementing. This means that, to avoid a premature reset, WD setup should occur early in the power-up sequence. See Figure 19 for a block diagram of the WD module. The WD module features include the following: D WD Timer - Seven different WD overflow rates - A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and generates a system reset if an incorrect value is written to the register - WD check bits that initiate a system reset if an incorrect value is written to the WD control register (WDCR) D Automatic activation of the WD timer, once system reset is released - Three WD control registers located in control register frame beginning at address 7020h. NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte is read as zeros. Writing to the upper byte has no effect. Table 12 shows the different WD overflow (time-out) selections. Figure 19 shows the WD block diagram. The watchdog can be disabled in software by writing `1' to bit 6 of the WDCR register (WDCR.6) while bit 5 of the SCSR2 register (SCSR2.5) is 1. If SCSR2.5 is 0, the watchdog will not be disabled. SCSR2.5 is equivalent to the WDDIS pin of the TMS320F243/241 devices. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 49 SPRS161K - MARCH 2001 - REVISED JULY 2007 watchdog (WD) timer module (continued) Table 12. WD Overflow (Time-out) Selections WD PRESCALE SELECT BITS WDPS2 WDPS1 0 0 WDCLK DIVIDER 0 WDPS0 X 1 WDCLK/1 1 0 2 WDCLK/2 0 1 1 4 WDCLK/4 1 0 0 8 WDCLK/8 1 0 1 16 WDCLK/16 1 1 0 32 WDCLK/32 1 1 1 64 WDCLK/64 WDCLK = CLKOUT/512 X = Don't care 50 WATCHDOG CLOCK RATE POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 FREQUENCY (Hz) SPRS161K - MARCH 2001 - REVISED JULY 2007 watchdog (WD) timer module (continued) CLKOUT / 512 WDCLK System Reset 6-Bit FreeRunning Counter 3-bit Prescaler PLL CLKIN /64 /32 On-Chip Oscillator or External Clock /16 /8 /4 /2 CLR 000 001 010 011 WDPS WDCR.2 - 0 0 2 1 100 101 110 WDCR.6 WDFLAG WDCR.7 111 WDDIS WDCNTR.7 -0 8-Bit Watchdog Counter One-Cycle Delay CLR Reset Flag Internal Pullup PS/257 RS pin System Reset Request WDKEY.7 -0 Bad Key Watchdog Reset Key Register 55 + AA Detector Good Key WDCHK2-0 WDCR.5 -3 Bad WDCR Key 3 3 System Reset 1 0 1 (Constant Value) Writing to bits WDCR.5 -3 with anything but the correct pattern (101) generates a system reset. Figure 19. Block Diagram of the WD Module POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 51 SPRS161K - MARCH 2001 - REVISED JULY 2007 development support Texas Instruments (TI) offers an extensive line of development tools for the 240x generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of 240x-based applications: Software Development Tools: Assembler/linker Simulator Optimizing ANSI C compiler Application algorithms C/Assembly debugger and code profiler Hardware Development Tools: Emulator XDS510 (supports x24x multiprocessor system debug) TMS320LF2407 EVM (Evaluation module for 2407 DSP) See Table 13 and Table 14 for complete listings of development support tools for the 240x. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor. Table 13. Development Support Tools DEVELOPMENT TOOL PLATFORM PART NUMBER Software Code Composer Studio v.2.2 PC TMDSCCS2000-1 Hardware - Emulation Debug Tools XDS510PP Pod (Parallel Port) with JTAG cable PC TMDS3P701014 Table 14. TMS320x24x-Specific Development Tools DEVELOPMENT TOOL PLATFORM PART NUMBER Hardware - Evaluation/Starter Kits 2401A eZdsp PC TMDSeZD2401 F2407A EVM PC TMDS3P701016A XDS510, Code Composer Studio, and XDS510PP are trademarks of Texas Instruments. PC is a trademark of International Business Machines Corp. 52 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 device and development support tool nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX / TMDX) through fully qualified production devices/tools (TMS / TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas Instruments reserves the right to change or discontinue these products without notice. TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices ( TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TMS320 is a trademark of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 53 SPRS161K - MARCH 2001 - REVISED JULY 2007 device and development support tool nomenclature (continued) TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, VF) and temperature range (for example, A). Figure 20 provides a legend for reading the complete TMS320Lx2401A device name. TMS 320 LF 2401A VF A PREFIX TMX = experimental device TMP = prototype device TMS = qualified device TEMPERATURE RANGE A = -40C to 85C S = -40C to 125C PACKAGE TYPE VF = 32-pin LQFP DEVICE FAMILY 320 = TMS320 DSP Family TECHNOLOGY LC = Low-voltage CMOS (3.3 V) LF = Flash EEPROM (3.3 V) LQFP = DEVICE 2401A Low-Profile Quad Flatpack Figure 20. TMS320Lx2401A Device Nomenclature 54 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 documentation support Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets, such as this document, with design specifications; complete user's guides for all devices and development support tools; and hardware and software applications. Useful reference documentation includes: D Silicon Errata - TMS320LF2401A, TMS320LC2401A DSP Controller Silicon Errata (literature number SPRZ013) describes the known advisories of various revisions of the silicon. D User's Guides - TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) describes the TMS320C24x 16-bit fixed-point digital signal processor controller. Covered are its architecture, internal register structure, data and program addressing, and instruction set. Also includes instruction set comparisons and design considerations for using the XDS510 emulator. - TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357). This reference guide describes the architecture, system hardware, peripherals, and general operation of the TMS320Lx2407A/x2406A/x2404A/x2403A/x2402A/x2401A digital signal processor (DSP) controllers. This book is also applicable to TMS320Lx2407/2406/2402 and future derivatives of the 240x family. D Application Reports - Getting Started in C and Assembly Code with the TMS320LF240x DSP (literature number SPRA755) This application report presents basic code for initializing and operating the TMS320LF240x DSP devices. Two functionally equivalent example programs are presented: one written in assembly language and the other in C language. Detailed discussions of each program are provided that explain numerous compiler and assembler directives, code requirements, and hardware-related requirements. The programs are ready to run on either the TMS320LF2407 Evaluation Module (EVM) or the eZdspo.si LF2407 development kit. However, they are also intended for use as a code template for any TMS320LF240x (LF240x) or TMS320LF240xA (LF240xA) DSP target system. - Motor Speed Measurement Considerations Using TMS320C24x DSPs (literature number SPRA771) The TMS320C24x generation of DSPs provide appropriate internal hardware for interfacing with low-cost, external-speed sensors for motor speed measurement applications. The periodic output signal from the speed sensor is applied to the capture input pin of the DSP and the signal's period is measured. This information is then used to calculate the motor speed. However, this calculation of motor speed depends on several system parameters. These parameters affect the scaling and normalization factors that must be used in the speed calculation routine for accurate measurements. This application report, therefore, gives an analysis of the speed measurement system to show the effect of system parameters on the calculated speed. The choice of appropriate scaling and normalization factors for a given system is also discussed. Finally, code examples are given to show the software implementation of the speed calculation routine. - 3.3 V DSP for Digital Motor Control (literature number SPRA550) describes a scenario of a 3.3-V-only motor controller indicating that for most applications, no significant issue of interfacing between 3.3 V and 5 V exists. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADC is also discussed. Guidelines for component layout and printed circuit board (PCB) design that can reduce system noise and EMI effects are summarized. To receive copies of TMS320 DSP literature, contact the Literature Response Center at 800-477-8924. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 55 SPRS161K - MARCH 2001 - REVISED JULY 2007 A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information. Updated information on the TMS320 DSP controllers can be found on the worldwide web at: http://www.ti.com. To send comments regarding the TMS320LF2401A/TMS320LC2401A data sheet (literature number SPRS161), use the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site. 56 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 LF2401A AND LC2401A ELECTRICAL SPECIFICATIONS DATA This document contains information on products in more than one phase of development. The electrical specifications for the TMS320LF2401A device are Production Data (PD) and those for the TMS320LC2401A device are Product Preview (PP). These electrical specifications are subject to change. absolute maximum ratings over operating temperature range (unless otherwise noted) Supply voltage range, VDD, VDDO, and VCCA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V VCCP range (LF2401A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 5.5 V Input voltage range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating ambient temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Clamp current stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963). NOTE 1: All voltage values are with respect to VSS. recommended operating conditions VDDO = VDD 0.3 V MIN NOM MAX 3 3.3 3.6 UNIT V VDD/VDDO VSS VCCA Supply voltage VCCP fCLKOUT Flash programming supply voltage (LF2401A)# VIH VIL High-level input voltage All inputs Low-level input voltage All inputs 0.8 V -2 mA High-level output source current, VOH = 2.4 V Output pins Group 1|| Output pins Group 2|| -4 mA Output pins Group 3|| Output pins Group 1|| -8 mA 2 mA Output pins Group 2|| Output pins Group 3|| 4 mA IOH IOL TA Supply ground 0 0 0 V ADC supply voltage 3 3.3 3.6 V 4.75 5 5.25 V Device clock frequency (system clock) Low-level output sink current, VOL = VOL MAX Ambient temperature 2 MHz V 8 mA A version - 40 85 C S version - 40 125 Nf Flash endurance for the array (Write/erase cycles) - 40C to 85C 10K See the mechanical data package page for thermal resistance values, JA (junction-to-ambient) and JC (junction-to-case). VCCA should not exceed VDD by 0.3 V. # For applications that involve millions of power cycles, it is recommended that VCCP be powered after VDD. || Primary signals and their groupings: Group 1: PDPINTA/IOPA0, T2PWM, PWM1-PWM6 (IOPA1-IOPA6), IOPB0, IOPB1, OPB5, TMS/XF, RS, TCK, TDI Group 2: SCITXD/IOPB3, SCIRXD/IOPB4, TDO/IOPB2 Group 3: CAP1, IOPA7, CLKOUT POST OFFICE BOX 1443 40 2 * HOUSTON, TEXAS 77251-1443 C cycles 57 SPRS161K - MARCH 2001 - REVISED JULY 2007 electrical characteristics over recommended operating temperature range (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN VDD = 3.0 V, IOH = IOHMAX All outputs at 50 A TYP MAX UNIT 2.4 V VDDO - 0.2 IOL = IOLMAX 0.4 With pullup -10 -16 V A A IIL Input current (low level) IIH Input current (high level) IOZ Ci Output current, high-impedance state (off-state) Input capacitance 2 pF Co Output capacitance 3 pF With pulldown VDD = 3.3 V, VIN = 0 V -30 2 2 With pullup With pulldown VDD = 3.3 V, VIN = VDD 10 16 30 2 VO = VDD or 0 V A A A current consumption by power-supply pins over recommended operating temperature range at 40-MHz CLOCKOUT (LF2401A) PARAMETER IDD Operational Current TEST CONDITIONS A test code running in Flash does the following: 1. Enables clock to all peripherals 2. Toggles all PWM outputs at 20 kHz 3. Performs a continuous conversion of all ADC channels 4. An infinite loop which transmits a character out of SCI and executes MACD instructions NOTE: All I/O pins are floating. TEMPERATURE MIN TYP MAX UNIT -40C to 85C (A) 75 90 mA -40C to 125C (S) 75 110 mA 10 22 mA -40C to 85C (A) ICCA ADC module current -40C to 125C (S) IDD is the current flowing into the VDD and VDDO pins. IDD current includes the current drawn by the PLL module. The MAX numbers are at maximum temperature and voltage. current consumption by power-supply pins over recommended operating temperature range at 40-MHz CLOCKOUT (LC2401A) PARAMETER IDD Operational Current TEST CONDITIONS A test code running in Flash does the following: 1. Enables clock to all peripherals 2. Toggles all PWM outputs at 20 kHz 3. Performs a continuous conversion of all ADC channels 4. An infinite loop which transmits a character out of SCI and executes MACD instructions NOTE: All I/O pins are floating. TEMPERATURE MIN TYP MAX UNIT -40C to 85C (A) 55 70 mA -40C to 125C (S) 55 90 mA 11 25 mA -40C to 85C (A) ICCA ADC module current -40C to 125C (S) IDD is the current flowing into the VDD and VDDO pins. IDD current includes the current drawn by the PLL module. 58 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 current consumption by power-supply pins over recommended operating temperature range during low-power modes at 40-MHz CLOCKOUT (LF2401A) PARAMETER IDD MODE Operational Current OPERATING CONDITIONS TEMPERATURE MIN TYP MAX UNIT Clock to all peripherals is enabled. No I/O pins are switching. -40C to 85C (A) 60 70 mA -40C to 125C (S) 60 90 mA LPM0 ADC module current Clock to all peripherals is enabled. No I/O pins are switching. -40C to 85C (A) 12 18 mA ICCA -40C to 125C (S) 12 18 mA Operational Current Clock to all peripherals is disabled. No I/O pins are switching. -40C to 85C (A) 35 40 mA IDD -40C to 125C (S) 35 50 mA LPM1 ADC module current Clock to all peripherals is disabled. No I/O pins are switching. -40C to 85C (A) 5 10 A ICCA -40C to 125C (S) 5 20 A Operational Current Clock to all peripherals is disabled. Flash is powered down. -40C to 85C (A) 80 100 A IDD -40C to 125C (S) 80 200 A Clock to all peripherals is disabled. Flash is powered down. -40C to 85C (A) 5 10 A -40C to 125C (S) 5 20 A LPM2 ICCA ADC module current IDD is the current flowing into the VDD and VDDO pins. current consumption by power-supply pins over recommended operating temperature range during low-power modes at 40-MHz CLOCKOUT (LC2401A) PARAMETER IDD MODE Operational Current OPERATING CONDITIONS TEMPERATURE MIN TYP MAX UNIT Clock to all peripherals is enabled. No I/O pins are switching. -40C to 85C (A) 40 50 mA -40C to 125C (S) 40 70 mA LPM0 ADC module current Clock to all peripherals is enabled. No I/O pins are switching. -40C to 85C (A) 12 18 mA ICCA -40C to 125C (S) 12 18 mA Operational Current Clock to all peripherals is disabled. No I/O pins are switching. -40C to 85C (A) 15 22 mA IDD -40C to 125C (S) 15 32 mA -40C to 85C (A) 5 10 A -40C to 125C (S) 5 15 A -40C to 85C (A) 50 70 A -40C to 125C (S) 50 170 A -40C to 85C (A) 5 10 A -40C to 125C (S) 5 15 A LPM1 ICCA ADC module current Clock to all peripherals is disabled. No I/O pins are switching. IDD Operational Current Clock to all peripherals is disabled. LPM2 ICCA ADC module current Clock to all peripherals is disabled. IDD is the current flowing into the VDD and VDDO pins. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 59 SPRS161K - MARCH 2001 - REVISED JULY 2007 Current (mA) I DD current consumption graphs 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 CLKOUT Frequency (MHz) Figure 21. LF2401A Typical Current Consumption (With Peripheral Clocks Enabled) reducing current consumption 240x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 15 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals. Refer to the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for further information on how to turn off the clock to the peripherals. Table 15. Typical Current Consumption by Various Peripherals (at 40 MHz) PERIPHERAL MODULE CURRENT REDUCTION (mA) EVA 6.1 ADC 2.8 SCI 1.9 ADC current shown is at 30 MHz. emulator connection without signal buffering for the DSP Figure 22 shows the connection between the DSP and JTAG header for a single-processor configuration. If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 22 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on buffering JTAG signals and multiple processor connections, see TMS320F/C24x DSP Controllers CPU and Instruction Set Reference Guide (literature number SPRU160). 60 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 emulator connection without signal buffering for the DSP (continued) 6 inches or less VDD VDD 13 EMU0 14 EMU1 2 TRST 1 TMS 3 TDI 7 TDO 11 TCK 9 DSP EMU0 PD EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 5 4 6 8 10 12 TCK_RET JTAG Header Figure 22. Emulator Connection Without Signal Buffering for the DSP POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 61 SPRS161K - MARCH 2001 - REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics Output Under Test 50 VLOAD CT IOH Where: IOH VLOAD CT = = = -2 mA (all outputs) 1.5 V 50-pF typical load-circuit capacitance Figure 23. Test Load Circuit signal transition levels The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.4 V. Figure 24 shows output levels. 2.4 V (VOH) 80% 20% 0.4 V (VOL) Figure 24. Output Levels Output transition times are specified as follows: D For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower. D For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage range and higher and the level at which the output is said to be high is 80% of the total voltage range and higher. Figure 25 shows the input levels. 2.0 V (VIH) 90% 10% 0.8 V (VIL) Figure 25. Input Levels Input transition times are specified as follows: D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower. D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher. 62 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: CI XTAL1 CO CLKOUT RS RESET pin RS INT XINT1, XINT2 Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) general notes on timing parameters All output signals from the 2401A device (including CLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, refer to the appropriate cycle description section of this data sheet. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 63 SPRS161K - MARCH 2001 - REVISED JULY 2007 external reference crystal/clock with PLL circuit enabled timing with the PLL circuit enabled PARAMETER MIN Input clock frequency fx MAX Resonator 4 13 Crystal 4 20 CLKIN 4 20 UNIT MHz Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum. switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 26) PARAMETER PLL MODE MIN X4 mode tc(CO) Cycle time, CLKOUT tf(CO) tr(CO) Fall time, CLKOUT tw(COL) tw(COH) Pulse duration, CLKOUT low LF2401A Pulse duration, CLKOUT high LF2401A tw(COL) tw(COH) Pulse duration, CLKOUT low LC2401A TYP MAX UNIT 25 ns 4 Rise time, CLKOUT ns 4 ns X4 mode @ 2 mA load X4 mode @ 2 mA load H -3 H H +3 ns H -3 H H +3 ns X4 mode @ 2 mA load X4 mode @ 2 mA load H -5 H H +5 ns Pulse duration, CLKOUT high LC2401A H -5 H H +5 Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 2 MHz minimum. ns timing requirements (see Figure 26) MIN MAX UNIT tc(Cl) Cycle time, XTAL1/CLKIN tf(Cl) tr(Cl) Fall time, XTAL1/CLKIN tw(CIL) tw(CIH) Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl) 40 Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl) 40 60 % Rise time, XTAL1/CLKIN 250 ns 5 ns 5 ns 60 % tc(CI) tw(CIH) tf(Cl) tr(Cl) tw(CIL) XTAL1/CLKIN tw(COH) tc(CO) tw(COL) tr(CO) CLKOUT Figure 26. CLKIN-to-CLKOUT Timing With PLL and External Clock in x4 Mode 64 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 tf(CO) SPRS161K - MARCH 2001 - REVISED JULY 2007 RS timing timing requirements for a reset [H = 0.5tc(CO)] (see Figure 27 and Figure 28) MIN NOM MAX UNIT tw(RSL) Pulse duration, stable CLKIN to RS high 8tc(CI) cycles tw(RSL2) Pulse duration, RS low 8tc(CI) cycles tp PLL lock-up time td(EX) 98304tc(CI) 36H Delay time, reset vector executed after PLL lock time cycles cycles During power-on reset, the device can continue to hold the RS pin low for another 128 CLKIN cycles. VDD/VDDO tw(RSL) tp td(EX) RS CLKIN XTAL1 (See Note B) tOSCST (See Note C) TDI (See Note D) TDI/OPB5 BOOT_EN CLKOUT (See Note E) I/Os Code-Dependent Hi-Z NOTES: A. Be certain that the emulation logic is reset before de-asserting the device reset. That is, TRST of the device is not driven high before the device reset is de-asserted. This is applicable to XDS510, XDS510PP, and XDS510PP+ class of emulators. New generation emulators such as SPI515 and XDS510 USB emulators have a built-in protection mechanism to take care of this requirement. B. XTAL1 refers to the internal oscillator clock if an on-chip oscillator is used. C. tOSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design. D. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the "TDI/OPB5" phase, this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low). E. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. Figure 27. Power-On Reset XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital. XDS510 and XDS510PP, are trademarks of Texas Instruments. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 65 SPRS161K - MARCH 2001 - REVISED JULY 2007 RS timing (continued) tp tw(RSL2) td(EX) RS CLKIN XTAL1 TDI TDI/OPB5 BOOT_EN CLKOUT I/Os Hi-Z Code-Dependent XTAL1 refers to internal oscillator clock if on-chip oscillator is used. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the "TDI/OPB5" phase, this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low). Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. NOTE A: During warm resets, if the watchdog module is enabled and issues a reset, then the RS pin will be an output and driven low for the WD pulse duration - 128 CLKIN cycles. Figure 28. Warm Reset 66 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 RS timing (continued) switching characteristics over recommended operating conditions for a reset [H = 0.5tc(CO)] (see Figure 29) PARAMETER MIN tw(RSL1) Watchdog reset pulse width td(EX) Delay time, reset vector executed after PLL lock time tp PLL lock time (input cycles) MAX 128tc(CI) ns 36H ns 98 304tc(CI) tw(RSL1) tp UNIT ns td(EX) RS CLKIN XTAL1 TDI TDI/OPB5 BOOT_EN CLKOUT I/Os Code-Dependent Hi-Z XTAL1 refers to internal oscillator clock if on-chip oscillator is used. The TDI pin is used to determine whether or not the on-chip boot ROM is invoked in the BOOT_EN phase. In the "TDI/OPB5" phase, this pin functions as TDI (if TRST is high) or OPB5 (if TRST is low). Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. Figure 29. Watchdog Initiated Reset POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 67 SPRS161K - MARCH 2001 - REVISED JULY 2007 low-power mode timing switching characteristics over recommended operating conditions [H = 0.5tc(CO)] (see Figure 30, Figure 31, and Figure 32) PARAMETER LOW-POWER MODES MIN TYP IDLE1 LPM0 12 x tc(CO) MAX UNIT td(WAKE-A) Delay time, CLKOUT switching to program execution resume IDLE2 LPM1 15 x tc(CO) ns td(IDLE-COH) Delay time, Idle instruction executed to IDLE2 CLKOUT high LPM1 4tc(CO) ns td(WAKE-OSC) Delay time, wake-up interrupt asserted to oscillator running ms LPM2 OSC start-up and PLL lock time 4tc(CO) ns HALT {PLL/OSC power down} td(IDLE-OSC) Delay time, Idle instruction executed to oscillator power off td(EX) Delay time, reset vector executed after RS high 36H ns td(WAKE-A) A0-A15 CLKOUT WAKE INT In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. WAKE INT can be any valid interrupt or RESET. Figure 30. IDLE1 Entry and Exit Timing - LPM0 td(IDLE-COH) A0-A15 CLKOUT WAKE INT td(WAKE-A) In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. WAKE INT can be any valid interrupt or RESET. Figure 31. IDLE2 Entry and Exit Timing - LPM1 68 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 low-power mode timing (continued) tp td(EX) A0-A15 td(IDLE-OSC) td(IDLE-COH) CLKOUT td(WAKE-OSC) tw(RSL) RESET In 2401A, CLKOUT will not be seen at the pin, only in some modes; it can be enabled in software. Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. Figure 32. HALT Mode - LPM2 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 69 SPRS161K - MARCH 2001 - REVISED JULY 2007 LPM2 wake-up timing switching characteristics over recommended operating conditions (see Figure 33) PARAMETER MIN Delay time, PDPINTA low to PWM td(PDP-PWM)HZ high-impedance state MAX UNIT if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12 ns if bit 6 of SCSR2 = 1 (12+ 1)tc(CO) + 12 ns Delay time, INT low/high to interrupt-vector fetch td(INT) 10tc(CO) + tw(PDP-WAKE) ns Includes i/p qualifier cycles plus synchronization plus propagation delay timing requirements (see Figure 33) MIN tw(PDP-WAKE) Pulse duration, PDPINTA input low tp PLL lock-up time XTAL1 if bit 6 of SCSR2 = 0 6tc(CO) if bit 6 of SCSR2 = 1 12tc(CO) MAX UNIT ns 98 304tc(CI) cycles Oscillator Disabled tOSC tp CLKIN CLKOUT tw(PDP-WAKE) PDPINTA td(PDP-PWM)HZ PWM td(INT) CPU Status CPU IDLE State (LPM2) Interrupt Vector or Next Instruction# tOSC is the oscillator start-up time. CLKOUT frequency after LPM2 wake-up will be the same as that upon entering LPM2 (x4 shown as an example). Unlike other 24x/240x devices, the CLKOUT signal does not appear on the CLKOUT pin by default (after a device reset). The CLKOUT waveform depicted in the figure is present internally in the DSP. However, in order to route the internal CLKOUT signal to the XINT2/ADCSOC/CAP1/IOPA7/CLKOUT pin, bit 7 of the MCRA register must be programmed appropriately. PDPINTA interrupt vector, if PDPINTA interrupt is enabled. # If PDPINTA interrupt is disabled. Figure 33. LPM2 Wakeup Using PDPINTA 70 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 TIMING EVENT MANAGER INTERFACE PWM timing PWM refers to all PWM outputs on EVA. switching characteristics over recommended operating conditions for PWM timing [H = 0.5tc(CO)] (see Figure 34) PARAMETER tw(PWM) MIN MAX 2H+5 Pulse duration, PWMx output high/low td(PWM)CO Delay time, CLKOUT low to PWMx output switching PWM outputs may be 100%, 0%, or increments of tc(CO) with respect to the PWM period. 13 UNIT ns 21 ns CLKOUT td(PWM)CO tw(PWM) PWMx Figure 34. PWM Output Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 71 SPRS161K - MARCH 2001 - REVISED JULY 2007 capture timing timing requirements (see Figure 35) MIN tw(CAP) if bit 6 of SCSR2 = 0 6tc(CO) if bit 6 of SCSR2 = 1 12tc(CO) Pulse duration, CAP1 input low/high CLKOUT tw(CAP) CAP1 Figure 35. Capture Input Timing 72 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 MAX UNIT ns SPRS161K - MARCH 2001 - REVISED JULY 2007 interrupt timing INT refers to XINT1, XINT2, and PDPINTA. switching characteristics over recommended operating conditions (see Figure 36) PARAMETER td(PDP-PWM)HZ td(INT) Delay time, PDPINTA low to PWM high-impedance state MIN MAX UNIT if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12 ns if bit 6 of SCSR2 = 1 (12+ 1)tc(CO) + 12 ns Delay time, INT low/high to interrupt-vector fetch 10tc(CO) +tw(INT) ns Includes i/p qualifier cycles plus synchronization plus propagation delay timing requirements (see Figure 36) MIN tw(INT) Pulse duration, INT input low/high tw(PDP) Pulse duration, PDPINTA input low if bit 6 of SCSR2 = 0 6tc(CO) if bit 6 of SCSR2 = 1 12tc(CO) if bit 6 of SCSR2 = 0 6tc(CO) if bit 6 of SCSR2 = 1 12tc(CO) MAX UNIT ns ns CLKOUT tw(PDP) PDPINTA td(PDP-PWM)HZ PWM tw(INT) XINT1, XINT2 td(INT) A0-A15 (Internal Bus) Interrupt Vector PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTA is taken high depends on the state of the FCOMPOE bit. Figure 36. External Interrupts Timing POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 73 SPRS161K - MARCH 2001 - REVISED JULY 2007 general-purpose input/output timing switching characteristics over recommended operating conditions (see Figure 37) PARAMETER MIN MAX 13 UNIT td(GPO)CO tr(GPO) Delay time, CLKOUT low to GPIO low/high All GPIOs 21 ns Rise time, GPIO switching low to high All GPIOs 12 ns tf(GPO) Fall time, GPIO switching high to low All GPIOs 15 ns timing requirements [H = 0.5tc(CO)] (see Figure 38) MIN tw(GPI) 2H+15 Pulse duration, GPI high/low CLKOUT td(GPO)CO GPIO tr(GPO) tf(GPO) Figure 37. General-Purpose Output Timing CLKOUT tw(GPI) GPIO Figure 38. General-Purpose Input Timing 74 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 MAX UNIT ns SPRS161K - MARCH 2001 - REVISED JULY 2007 10-bit analog-to-digital converter (ADC) The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA. The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic circuitry that can be present on VSS and VCC from coupling into the ADC analog stage. All ADC specifications are given with respect to VSSA unless otherwise noted. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-bit (1024 values) Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . 000h to 3FFh (000h for VI VSSA; 3FFh for VI VCCA) Conversion time (including sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns recommended operating conditions MIN VCCA VSSA Analog supply voltage NOM MAX 3.3 3.6 3.0 Analog ground UNIT V 0 V VAI Analog input voltage, ADCIN00-ADCIN04 VREFLO VCCA and VSSA must be stable, within 1/2 LSB of the required resolution, during the entire conversion time. VREFHI V ADC operating frequency MIN ADC operating frequency 2 MAX UNIT 30 MHz operating characteristics over recommended operating condition ranges PARAMETER DESCRIPTION MIN TYP MAX 1 UNIT mA IADCIN Analog input leakage Cai Analog input capacitance Typical capacitive load on analog input pin EDNL Differential nonlinearity error Difference between the actual step width and the ideal value 2 LSB EINL Integral nonlinearity error Maximum deviation from the best straight line through the ADC transfer characteristics, excluding the quantization error 2 LSB td(PU) Delay time, power-up to ADC valid Time to stabilize analog stage after power-up 10 ms ZAI Analog input source impedance Analog input source impedance needed for conversions to remain within specifications at min tw(SH) 10 10 LSB Non-sampling 10 Sampling 30 Zero-offset error 8 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 pF 75 SPRS161K - MARCH 2001 - REVISED JULY 2007 internal ADC module timing (see Figure 39) MIN MAX 33.3 UNIT tc(AD) tw(SHC) Cycle time, ADC prescaled clock tw(SH) tw(C) Pulse duration, sample and hold time Delay time, start of conversion to beginning of sample and hold 10tc(AD) 2tc(CO) ns td(SOC-SH) td(EOC) Delay time, end of conversion to data loaded into result register 2tc(CO) ns Pulse duration, total sample/hold and conversion time 500 2tc(AD) Pulse duration, total conversion time ns ns 32tc(AD) ns ns td(ADCINT) Delay time, ADC flag to ADC interrupt 2tc(CO) ns The ADC timing diagram represents a typical conversion sequence. Refer to the ADC chapter in the TMS320LF/LC240xA DSP Controllers Reference Guide: System and Peripherals (literature number SPRU357) for more details. The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC) . Can be varied by ACQ Prescaler bits in the ADCCTRL1 register tc(AD) Bit Converted 9 8 7 6 5 4 3 2 1 0 ADC Clock Analog Input AAAAAA AAAAAAAAAAAAAAAAAAAAA tw(C) EOC/Convert tw(SH) Internal Start/ Sample Hold td(SOC-SH) Start of Convert td(EOC) tw(SHC) XFR to RESULTn td(ADCINT) ADC Interrupt Figure 39. Analog-to-Digital Internal Module Timing 76 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 Flash parameters @40 MHz CLOCKOUT (LF2401A) PARAMETER MIN TYP MAX UNIT 30 s Time/4K Sector 130 ms Erase time Time/4K Sector 350 ms ICCP (VCCP pin current) Indicates the typical/maximum current consumption during the Clear-Erase-Program (C-E-P) cycle Time/Word (16-bit) Clear/Programming time 5 15 mA The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values specified are when VDD = 3.3 V and VCCP = 5 V, and any deviation from these values could affect the timing parameters. Aging and process variance could also impact the timing parameters. migrating from other 240xA devices to Lx2401A This section outlines some of the issues to be considered while migrating a design from the 240xA family to the Lx2401A. The Lx2401A shares the same CPU core (and hence, the same instruction set) as the 240xA. Furthermore, the peripherals implemented on the Lx2401A are a subset of those found in the 240xA family. However, some features of a particular peripheral may not be present on the 2401A. This must be taken into consideration while porting code to the Lx2401A. Other issues to be considered for migration are as follows. PLL The PLL used in the Lx2401A is different than the one used in the 240xA family. The Lx2401A PLL does not need the external loop-filter components. The PLL is bypassed when the TMS and TRST pins are sensed low at reset. NOTE: The device may come up in PLL bypass mode if the TMS and TRST pins are sensed low when the emulator/debugger is brought up (with the XDS510/XDS510PP/XDS510PP+ pod connected to the target hardware). If this happens, the device reset pin (RS) must be activated once (after the emulator is up and running) to bring it out of PLL bypass mode. Note that this is a concern only when the JTAG connector is connected for debug and does not have an impact when the code is free-run without the JTAG connector--i.e., there are no issues when the target hardware is powered up without the JTAG connector. Before attempting to program flash through JTAG, it must be ensured that the PLL is not in bypass mode. on-chip bootloader Boot ROM is a 256-word ROM mapped in program space 0000h-00FFh. This ROM will be enabled if the BOOT_EN mode is enabled during reset. Boot-enable function is implemented using combinational logic of the TDI, TRST, and RS pins as described below. The on-chip bootloader is invoked when: TRST = 0 RS = 0 TDI = 0 (In addition to the three pins mentioned above, the application must ensure that PDPINTA stays high during the execution of the boot ROM code.) Since it has an internal pulldown, the TRST pin will be low, provided the JTAG connector is not connected. Therefore, the BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if TDI is low upon reset. If on-chip bootloader is desired while debugging with the JTAG connector connected (TRST = 1), it can be achieved by writing a "0" into bit 3 of the SCSR2 register. GPIO The multiplexing scheme of the GPIO pins with other functional pins is different in the Lx2401A. Because of this, the bit assignments for the MCRA, PADATDIR, and PBDATDIR registers of the Lx2401A is not compatible with the bit assignments of the 240xA family. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 77 SPRS161K - MARCH 2001 - REVISED JULY 2007 EV The Event Manager of the Lx2401A has reduced functionality when compared to that of the 240xA family. Following are the important differences: D D D D D There is no QEP unit. There is only one "Capture" input (CAP1). Although Timer 1 is present, there is no compare output pin (T1CMP/T1PWM). There is no provision to feed an external clock to the timers. There is no external direction control pin for the timers. Due to these differences, some of the bits in the EV registers are not applicable in the Lx2401A and are shaded gray. Refer to Table 16, Lx2401A DSP Peripheral Register Description, for more details. ADC The Lx2401A ADC has only five input channels as compared to eight or sixteen channels in the 240xA family. Therefore, the 4-bit fields in the CHSELSEQn registers should be programmed with values from 0-4 only. The Lx2401A ADC does not have dedicated VREFHI and VREFLO pins. Instead, the VCCA and VSSA pins provide the necessary reference. pins The following pins, which are available in other 240xA devices, have been internally tied as indicated: CAP2, CAP3 - low TDIRA - low TCLKINA - low BIO - high DINR The device ID contained in the DINR register is 0810h for LF2401A and 0910h for LC2401A. XF pin The XF pin has to be enabled by writing a 1 to Bit 0 of the SCSR4 register before it can be used. migrating from LF2401A (Flash) device to LC2401A (ROM) device When migrating from Flash to ROM device, be sure to review this section for a list of important differences that should be considered. Customer applications should consider these differences in their design, prior to ROM code submission. Due to the fact that the flash and ROM are different silicon, the following parameters may be similar but not exactly identical. Refer to the respective datasheet sections for more detail: D EMI/ESD behavior D ADC performance D Current consumption D Device ID register values D The last 64 words of ROM are reserved for TI internal testing. User code should not occupy these locations. See the device memory map for details. 78 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description Table 16 is a collection of all the programmable registers of the Lx2401A and is provided as a quick reference. Table 16. Lx2401A DSP Peripheral Register Description ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG DATA MEMORY SPACE CPU STATUS REGISTERS ARP DP(7) DP(6) DP(5) ARB 1 OV OVM 1 INTM DP(8) DP(4) DP(3) DP(2) DP(1) DP(0) CNF TC SXM C XF 1 1 1 1 1 PM -- -- -- -- -- -- -- -- -- -- INT6 MASK INT5 MASK INT4 MASK INT3 MASK INT2 MASK INT1 MASK -- -- -- -- -- -- -- -- -- -- INT6 FLAG INT5 FLAG INT4 FLAG INT3 FLAG INT2 FLAG INT1 FLAG IRQ0.15 IRQ0.14 IRQ0.13 IRQ0.12 IRQ0.11 IRQ0.10 IRQ0.9 IRQ0.8 IRQ0.7 IRQ0.6 IRQ0.5 IRQ0.4 IRQ0.3 IRQ0.2 IRQ0.1 IRQ0.0 IRQ1.15 IRQ1.14 IRQ1.13 IRQ1.12 IRQ1.11 IRQ1.10 IRQ1.9 IRQ1.8 IRQ1.7 IRQ1.6 IRQ1.5 IRQ1.4 IRQ1.3 IRQ1.2 IRQ1.1 IRQ1.0 IRQ2.15 IRQ2.14 IRQ2.13 IRQ2.12 IRQ2.11 IRQ2.10 IRQ2.9 IRQ2.8 IRQ2.7 IRQ2.6 IRQ2.5 IRQ2.4 IRQ2.3 IRQ2.2 IRQ2.1 IRQ2.0 IAK0.15 IAK0.14 IAK0.13 IAK0.12 IAK0.11 IAK0.10 IAK0.9 IAK0.8 IAK0.7 IAK0.6 IAK0.5 IAK0.4 IAK0.3 IAK0.2 IAK0.1 IAK0.0 IAK1.15 IAK1.14 IAK1.13 IAK1.12 IAK1.11 IAK1.10 IAK1.9 IAK1.8 IAK1.7 IAK1.6 IAK1.5 IAK1.4 IAK1.3 IAK1.2 IAK1.1 IAK1.0 IAK2.15 IAK2.14 IAK2.13 IAK2.12 IAK2.11 IAK2.10 IAK2.9 IAK2.8 IAK2.7 IAK2.6 IAK2.5 IAK2.4 IAK2.3 IAK2.2 IAK2.1 IAK2.0 -- CLKSRC LPM1 LPM0 CLK PS2 CLK PS1 CLK PS0 -- ADC CLKEN SCI CLKEN SPI CLKEN CAN CLKEN EVB CLKEN EVA CLKEN -- ILLADR -- -- -- -- -- -- -- -- -- I/P QUALIFIER CLOCKS WD OVERRIDE -- BOOT_EN -- DON PON -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- XF ENABLE DIN15 DIN14 DIN13 DIN12 DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 ST0 ST1 GLOBAL MEMORY AND CPU INTERRUPT REGISTERS 00004h 00005h 00006h Reserved IMR GREG IFR SYSTEM REGISTERS 07010h 07011h 07012h 07013h 07014h 07015h 07016h 07019h 0701Ch PIACKR0 PIACKR1 PIACKR2 SCSR1 SCSR2 Illegal 0701Dh 0701Eh PIRQR2 Illegal 0701Ah 0701Bh PIRQR1 Illegal 07017h 07018h PIRQR0 SCSR4 DINR Illegal 0701Fh PIVR Illegal These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 79 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description (continued) Table 16. Lx2401A DSP Peripheral Register Description (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 D3 D2 D1 D0 WDCNTR D3 D2 D1 D0 WDKEY WDCHK0 WDPS2 WDPS1 WDPS0 WDCR REG WD CONTROL REGISTERS 07020h to 07022h 07023h Illegal D7 D6 D5 D4 07024h 07025h Illegal D7 D6 D5 D4 07026h to 07028h 07029h Illegal WDFLAG WDDIS WDCHK2 WDCHK1 0702Ah to 0703Fh Illegal 07040h to 0704Fh Reserved SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS 07050h STOP BITS EVEN/ODD PARITY PARITY ENABLE LOOP BACK ENA ADDR/IDLE MODE SCI CHAR2 SCI CHAR1 SCI CHAR0 SCICCR 07051h -- RX ERR INT ENA SW RESET -- TXWAKE SLEEP TXENA RXENA SCICTL1 07052h BAUD15 (MSB) BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8 SCIHBAUD 07053h BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0 (LSB) SCILBAUD 07054h TXRDY TX EMPTY -- -- -- -- RX/BK INT ENA TX INT ENA SCICTL2 07055h RX ERROR RXRDY BRKDT FE OE PE RXWAKE -- SCIRXST 07056h ERXDT7 ERXDT6 ERXDT5 ERXDT4 ERXDT3 ERXDT2 ERXDT1 ERXDT0 SCIRXEMU 07057h RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 SCIRXBUF TXDT3 TXDT2 TXDT1 TXDT0 SCITXBUF SCI FREE -- -- -- 07058h 07059h Illegal TXDT7 TXDT6 TXDT5 TXDT4 0705Ah to 0705Eh 0705Fh Illegal -- SCITX PRIORITY SCIRX PRIORITY SCI SOFT 07060h to 0706Fh Illegal These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. 80 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 SCIPRI SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description (continued) Table 16. Lx2401A DSP Peripheral Register Description (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG EXTERNAL INTERRUPT CONTROL REGISTERS XINT1 FLAG -- -- -- -- -- -- -- -- -- -- -- -- XINT1 POLARITY XINT1 PRIORITY XINT1 ENA XINT2 FLAG -- -- -- -- -- -- -- -- -- -- -- -- XINT2 POLARITY XINT2 PRIORITY XINT2 ENA 07070h 07071h 07072h to 0708Fh XINT1CR XINT2CR Illegal DIGITAL I/O CONTROL REGISTERS 07090h MCRA.15 MCRA.14 MCRA.13 MCRA.12 MCRA.11 MCRA.10 MCRA.9 MCRA.8 MCRA.7 MCRA.6 MCRA.5 MCRA.4 MCRA.3 MCRA.2 MCRA.1 MCRA.0 MCRB.15 MCRB.14 MCRB.13 MCRB.12 MCRB.11 MCRB.10 MCRB.9 MCRB.8 MCRB.7 MCRB.6 MCRB.5 MCRB.4 MCRB.3 MCRB.2 MCRB.1 MCRB.0 MCRC.15 MCRC.14 MCRC.13 MCRC.12 MCRC.11 MCRC.10 MCRC.9 MCRC.8 MCRC.7 MCRC.6 MCRC.5 MCRC.4 MCRC.3 MCRC.2 MCRC.1 MCRC.0 E7DIR E6DIR E5DIR E4DIR E3DIR E2DIR E1DIR E0DIR IOPE7 IOPE6 IOPE5 IOPE4 IOPE3 IOPE2 IOPE1 IOPE0 -- F6DIR F5DIR F4DIR F3DIR F2DIR F1DIR F0DIR -- IOPF6 IOPF5 IOPF4 IOPF3 IOPF2 IOPF1 IOPF0 A7DIR A6DIR A5DIR A4DIR A3DIR A2DIR A1DIR A0DIR IOPA7 IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0 07091h 07092h Illegal 07093h 07094h 07095h 07096h B7DIR B6DIR B5DIR B4DIR B3DIR B2DIR B1DIR B0DIR IOPB7 IOPB6 IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0 C7DIR C6DIR C5DIR C4DIR 0709Fh PFDATDIR PADATDIR C3DIR C2DIR C1DIR C0DIR IOPC7 IOPC6 IOPC5 IOPC4 IOPC3 IOPC2 IOPC1 IOPC0 D7DIR D6DIR D5DIR D4DIR D3DIR D2DIR D1DIR D0DIR IOPD7 IOPD6 IOPD5 IOPD4 IOPD3 IOPD2 IOPD1 IOPD0 PBDATDIR Illegal 0709Dh 0709Eh PEDATDIR Illegal 0709Bh 0709Ch MCRC Illegal 07099h 0709Ah MCRB Illegal 07097h 07098h MCRA PCDATDIR Illegal PDDATDIR Illegal These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 81 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description (continued) Table 16. Lx2401A DSP Peripheral Register Description (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS 070A0h 070A1h 070A2h 070A3h 070A4h 070A5h 070A6h 070A7h 070A8h 070A9h 070AAh 070ABh 070ACh 070ADh 070AEh 070AFh -- ADC S/W RESET SOFT FREE ACQ PRESCALE3 ACQ PRESCALE2 ACQ PRESCALE1 ACQ PRESCALE0 CONV PRESCALE (CPS) CONTINUOUS RUN INT PRIORITY SEQ1/2 CASCADE -- -- -- -- EVB SOC EN SEQ1 Reset SEQ1 SOC SEQ1 SEQ1 BUSY INT ENA SEQ1 Mode1 INT ENA SEQ1 Mode0 INT FLAG SEQ1 EVA SOC EN SEQ1 EXT SOC EN SEQ1 Reset SEQ2 SOC SEQ2 SEQ2 BUSY INT ENA SEQ2 Mode1 INT ENA SEQ2 Mode0 INT FLAG SEQ2 EVB SOC EN SEQ2 ADCCTRL1 -- -- -- -- -- -- -- -- -- MAXCONV2 2 MAXCONV2 1 MAXCONV2 0 MAXCONV1 3 MAXCONV1 2 MAXCONV1 1 MAXCONV1 0 CONV 3 CONV 3 CONV 3 CONV 3 CONV 2 CONV 2 CONV 2 CONV 2 CONV 1 CONV 1 CONV 1 CONV 1 CONV 0 CONV 0 CONV 0 CONV 0 CONV 7 CONV 7 CONV 7 CONV 7 CONV 6 CONV 6 CONV 6 CONV 6 CONV 5 CONV 5 CONV 5 CONV 5 CONV 4 CONV 4 CONV 4 CONV 4 CONV 11 CONV 11 CONV 11 CONV 11 CONV 10 CONV 10 CONV 10 CONV 10 CONV 9 CONV 9 CONV 9 CONV 9 CONV 8 CONV 8 CONV 8 CONV 8 CONV 15 CONV 15 CONV 15 CONV 15 CONV 14 CONV 14 CONV 14 CONV 14 CONV 13 CONV 13 CONV 13 CONV 13 CONV 12 CONV 12 CONV 12 CONV 12 -- -- -- -- SEQ CNTR3 SEQ CNTR2 SEQ CNTR1 SEQ CNTR0 SEQ2 STATE 3 SEQ2 STATE 2 SEQ2 STATE 1 SEQ2 STATE 0 SEQ1 STATE 3 SEQ1 STATE 2 SEQ1 STATE 1 SEQ1 STATE 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 00 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. 82 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 ADCCTRL2 MAXCONV CHSELSEQ1 CHSELSEQ2 CHSELSEQ3 CHSELSEQ4 AUTO_SEQ_SR RESULT0 RESULT1 RESULT2 RESULT3 RESULT4 RESULT5 RESULT6 RESULT7 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description (continued) Table 16. Lx2401A DSP Peripheral Register Description (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG ANALOG-TO-DIGITAL CONVERTER (ADC) REGISTERS (CONTINUED) 070B0h 070B1h 070B2h 070B3h 070B4h 070B5h 070B6h 070B7h D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 070B8h Reserved 070B9h to 070FFh Illegal 07100h to 073FFh Reserved RESULT8 RESULT9 RESULT10 RESULT11 RESULT12 RESULT13 RESULT14 RESULT15 GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS - EVA 07400h 07401h 07402h 07403h 07404h -- T2STAT T1TOADC(0) TCOMPOE T1STAT -- T2TOADC D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- T1TOADC(1) T2PIN GPTCONA T1PIN FREE SOFT -- TMODE1 TMODE0 TPS2 TPS1 TPS0 -- TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR -- T1CNT T1CMPR T1PR T1CON These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 83 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description (continued) Table 16. Lx2401A DSP Peripheral Register Description (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG GENERAL-PURPOSE (GP) TIMER CONFIGURATION CONTROL REGISTERS - EVA (CONTINUED) 07405h 07406h 07407h 07408h D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FREE SOFT -- TMODE1 TMODE0 TPS2 TPS1 TPS0 T2SWT1 TENABLE TCLKS1 TCLKS0 TCLD1 TCLD0 TECMPR SELT1PR 07409h to 07410h T2CNT T2CMPR T2PR T2CON Illegal FULL AND SIMPLE COMPARE UNIT REGISTERS - EVA CENABLE CLD1 CLD0 SVENABLE ACTRLD1 ACTRLD0 FCOMPOE PDPINTA STATUS -- -- -- -- -- -- -- -- SVRDIR D2 D1 D0 CMP6ACT1 CMP6ACT0 CMP5ACT1 CMP5ACT0 CMP4ACT1 CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP2ACT0 CMP1ACT1 CMP1ACT0 -- -- -- -- DBT3 DBT2 DBT1 DBT0 EDBT3 EDBT2 EDBT1 DBTPS2 DBTPS1 DBTPS0 -- -- D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 07411h 07412h 07413h Illegal 07414h 07415h 07418h 07419h 0741Ah to 0741Fh DBTCONA Illegal Illegal These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. 84 ACTRA Illegal 07416h 07417h COMCONA POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 CMPR1 CMPR2 CMPR3 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description (continued) Table 16. Lx2401A DSP Peripheral Register Description (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CAP3TSEL CAP12TSEL REG CAPTURE UNIT REGISTERS - EVA CAPRES 07420h CAPQEPN CAP3EN CAP1EDGE CAP2EDGE -- CAP3FIFO CAP3EDGE 07421h 07422h 07423h 07424h 07425h 07428h 07429h CAP3TOADC CAPCONA -- Illegal CAP2FIFO CAP1FIFO -- -- -- -- -- -- -- -- D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 07426h 07427h -- CAPFIFOA CAP1FIFO CAP2FIFO CAP3FIFO Illegal 0742Ah to 0742Bh CAP1FBOT CAP2FBOT CAP3FBOT Illegal EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS 0742Ch 0742Dh 0742Eh -- -- -- -- -- T1OFINT ENA T1UFINT ENA T1CINT ENA T1PINT ENA -- -- -- CMP3INT ENA CMP2INT ENA CMP1INT ENA PDPINTA ENA -- -- -- -- -- -- -- -- T2UFINT ENA T2CINT ENA T2PINT ENA -- -- -- -- T2OFINT ENA -- -- -- -- -- -- -- -- -- CAP3INT ENA CAP2INT ENA CAP1INT ENA -- -- -- -- EVAIMRA EVAIMRB EVAIMRC These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 85 SPRS161K - MARCH 2001 - REVISED JULY 2007 peripheral register description (continued) Table 16. Lx2401A DSP Peripheral Register Description (Continued) ADDR BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REG EVENT MANAGER (EVA) INTERRUPT CONTROL REGISTERS (CONTINUED) 0742Fh 07430h 07431h -- -- -- -- -- T1OFINT FLAG T1UFINT FLAG T1CINT FLAG T1PINT FLAG -- -- -- CMP3INT FLAG CMP2INT FLAG CMP1INT FLAG PDPINTA FLAG -- -- -- -- -- -- -- -- T2UFINT FLAG T2CINT FLAG T2PINT FLAG -- -- -- -- T2OFINT FLAG -- -- -- -- -- -- -- -- -- CAP3INT FLAG CAP2INT FLAG CAP1INT FLAG -- -- -- -- 07432h to 074FFh Illegal 07500h to 0753Fh Reserved EVAIFRA EVAIFRB EVAIFRC I/O MEMORY SPACE 0FF0Fh -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BVIS.1 BVIS.0 ISWS.2 ISWS.1 ISWS.0 DSWS.2 DSWS.1 DSWS.0 PSWS.2 PSWS.1 PSWS.0 FCMR WAIT-STATE GENERATOR CONTROL REGISTER 0FFFFh These bits are not applicable in the Lx2401A since either (i) the peripheral functionality is absent or (ii) the corresponding pins have not been bonded out of the device. 86 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 WSGR SPRS161K - MARCH 2001 - REVISED JULY 2007 MECHANICAL DATA VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0- 7 1,45 1,35 0,75 0,45 Seating Plane 0,10 1,60 MAX 4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. Typical Thermal Resistance Characteristics PARAMETER DESCRIPTION C / W JA Junction-to-ambient 55.61 JC Junction-to-case 13.89 JT Junction-to-top of package 2.5 POST OFFICE BOX 1443 * HOUSTON, TEXAS 77251-1443 87 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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