PE43614
Document Category: Product Specification
UltraCMOS® RF Digital Step Attenuator, 9 kHz–45 GHz
©2019–2021, pSemi Corporation. All rights reserved. • Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121
Product Specification DOC-93670-3 – (02/2021)
www.psemi.com
Features
• Wideband support from 9 kHz to 45 GHz
• Glitch-safe attenuation state transitions
• Flexible attenuation steps of 0.5 dB and 1 dB up to
31.5 dB
• +105 °C operating temperature
• Parallel and serial programming interfaces with
serial addressability
• High HBM ESD of 1 kV
• Packaging – 24-lead 4 x 4 mm LGA
Applications
• Test and measurement (T&M)
• Point-to-point communication systems
• Very small aperture terminals (VSAT)
Product Description
The PE43614 is a 50Ω, HaRP™ technology-enhanced, 6-bit RF digital step attenuator (DSA) that supports a
wide frequency range from 9 kHz to 45 GHz. The PE43614 features glitch-safe attenuation state transitions,
supports 1.8V control voltage and optional VSS_EXT bypass mode to improve spurious performance, making this
device ideal for test and measurement, point-to-point communication systems, and very small aperture
terminals (VSAT).
The PE43614 provides an integrated digital control interface that supports both serial addressable and parallel
programming of the attenuation. The PE43614 covers a 31.5 dB attenuation range in 0.5 dB and 1 dB steps. It is
capable of maintaining 0.5 dB and 1 dB monotonicity through 45 GHz. In addition, no external blocking capac-
itors are required if 0 VDC is present on the RF ports.
The PE43614 is manufactured on pSemi’s UltraCMOS® process, a patented variation of silicon-on-insulator
(SOI) technology.
Figure 1 • PE43614 Functional Diagram
6-bit
RF
Input
RF
Output
Control Logic Interface
Switched Attenuator Array
V
SS_EXT
V
DD
P/SA0 A1 A2
Parallel
Control
Serial In Serial Out
CLK
(optional)
LE
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 2 of 23 DOC-93670-3 – (02/2021)
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pSemi’s HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an
innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and
integration of conventional CMOS.
Optional External VSS Control
For proper operation, the VSS_EXT control pin must be grounded or tied to the VSS voltage specified in Table 2.
When the VSS_EXT control pin is grounded, FETs in the switch are biased with an internal negative voltage
generator. For applications that require the lowest possible spur performance, VSS_EXT can be applied externally
to bypass the internal negative voltage generator.
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for the PE43614
Parameter/Condition Min Max Unit
Positive supply voltage, VDD –0.3 5.5 V
Negative supply voltage, VSS_EXT –3.6 0.3 V
Digital input voltage –0.3 3.6 V
Maximum junction temperature +150 °C
Storage temperature range –65 +150 °C
ESD voltage HBM, all pins(1) 1000 V
ESD voltage CDM, all pins(2) 500 V
Notes:
1) Human body model (MIL–STD 883 Method 3015)
2) Charged device model (JEDEC JESD22-C101).
DOC-93670-3 – (02/2021) Page 3 of 23
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PE43614
UltraCMOS® RF Digital Step Attenuator
Recommended Operating Conditions
Table 2 lists the recommending operating condition for the PE43614. Devices should not be operated outside
the recommended operating conditions listed below.
Table 2 • Recommended Operating Condition for the PE43614
Parameter Min Typ Max Unit
Normal mode, VSS_EXT = 0V(1)
Positive supply voltage, VDD 2.3 3.3 5.5 V
Positive supply current, IDD(3) 170 260 µA
Bypass mode, VSS_EXT = –3.0V(2)
Positive supply voltage, VDD (VDD ≥ 3.4V. See Table 3 for full spec
compliance.) 3.1 3.4 5.5 V
Positive supply current, IDD(3) 125 170 µA
Negative supply voltage, VSS_EXT –3.3 –3.0 –2.7 V
Negative supply current, ISS -40 -16 µA
Normal or bypass mode
Digital input high 1.17 3.60 V
Digital input low –0.3 0.6 V
Digital input current(4) 10 20 µA
RF input power, CW(5) (7) 28 dBm
RF input power, pulsed(6) (7) 31 dBm
Operating temperature range –40 +25 +105 °C
Notes:
1) Normal mode: Connect VSS_EXT (pin 2) to GND (VSS_EXT = 0V) to enable internal negative voltage generator.
2) Bypass mode: Use VSS_EXT (pin 2) to bypass and disable internal negative voltage generator.
3) Due to startup inrush current, a minimum current limit of 600 µA is allowed for normal operation of the DSA.
4) Applies to all pins except pins 18, 22, 23 and 24. P/S (pin 18), A0/D4 (pin 22), A1/D5 (pin 23), and A2/D6 (pin 24) have internal 1.5 MΩ pull-up
resistor to internal 1.8V VDD.
5) 100% duty cycle, all bands, 50Ω.
6) ≤ 5% duty cycle, 50Ω.
7) The maximum peak envelope of any OFDM complex waveform signal, such as CP-OFDM, should not exceed the maximum peak RF input
power in Table 1. The maximum average power of any complex waveform should not exceed the operating maximum RF input power, CW.
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 4 of 23 DOC-93670-3 – (02/2021)
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Electrical Specifications
Table 3 provides the PE43614 key electrical specifications at 25 °C, ZS = ZL = 50Ω, unless otherwise specified.
Normal mode is at VDD = 3.3V and VSS_EXT = 0V. Bypass mode is at VDD = 3.4V and VSS_EXT = –3.0V.
Table 3 • PE43614 Electrical Specifications
Parameter Condition Min Typ Max Unit
Operation Frequency 9 kHz min frequency 9 kHz 45.00 GHz
Attenuation Range
5-bit, 1.0 dB step programming 0.00 31.00 dB
6-bit, 0.5 dB step programming 0.00 31.50 dB
Attenuation Error
0.5 dB step, 0–31.5 dB, 9 kHz–13.0 GHz
+(1.00+4.5% of
attenuation set-
ting) / -1
dB
0.5 dB step, 0–31.5 dB, 13.0–26.5 GHz
+(1.15+4.5% of
attenuation set-
ting) / -1
dB
0.5 dB step, 0–15.5 dB, 26.5–40.0 GHz
+(1.00+4.5% of
attenuation set-
ting) / -1
dB
0.5 dB step, 16–31.5 dB, 26.5–40.0 GHz
+(1.60+8.5% of
attenuation set-
ting) / -1
dB
0.5 dB step, 0–15.5 dB, 40–43.5 GHz
+(1.00+4.5% of
attenuation set-
ting) / -1
dB
0.5 dB step, 16–31.5 dB, 40–43.5 GHz
+(1.60+12.5% of
attenuation set-
ting) / -1
dB
0.5 dB step, 0–15.5 dB, 43.5–45.0 GHz
+(1.00+4.5% of
attenuation set-
ting) / -1
dB
0.5 dB step, 16–31.5 dB, 43.5–45.0 GHz
+(1.80+15% of
attenuation set-
ting) / -1
dB
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PE43614
UltraCMOS® RF Digital Step Attenuator
Attenuation Error
1 dB step, 0–31 dB, 9 kHz–13.0 GHz
+(1.0+4.5% of
attenuation set-
ting) / -1
dB
1 dB step, 0–31 dB, 13.0–26.5 GHz
+(1.15+4.5% of
attenuation set-
ting) / -1
dB
1dB step, 0–15 dB, 26.5–40.0 GHz
+(1.0+4.5% of
attenuation set-
ting) / -1
dB
1dB step, 16–31 dB, 26.5–40.0 GHz
+(1.60+8.5% of
attenuation set-
ting) / -1
dB
1dB step, 0–15 dB, 40–43.5 GHz
+(1.0+4.5% of
attenuation set-
ting) / -1
dB
1dB step, 16–31 dB, 40–43.5 GHz
+(1.6+12.5% of
attenuation set-
ting) / -1
dB
1dB step, 0–15 dB, 43.5–45.0 GHz
+(1.0+4.5% of
attenuation set-
ting) / -1
dB
1dB step, 16–31 dB, 43.5–45.0 GHz
+(1.80+15% of
attenuation set-
ting) / -1
dB
Insertion Loss
9 kHz–13.0 GHz 2.50 3.00 dB
13.0–26.5 GHz 4.30 4.60 dB
26.5–40.0 GHz 4.90 5.25 dB
40.0–43.5 GHz 4.50 5.00 dB
43.5–45.0 GHz 5.40 5.80 dB
Return Loss
All States, 9 kHz–13.0 GHz 13.00 dB
All States, 13.0–26.5 GHz 13.00 dB
All States, 26.5–40.0 GHz 13.00 dB
All States, 40.0–43.5 GHz 13.00 dB
All States, 43.5–45.0 GHz 13.00 dB
Relative Phase
All States, 9 kHz–13.0 GHz 20.00 deg
All States, 13.0–26.5 GHz 43.00 deg
All States, 26.5–40.0 GHz 70.00 deg
All States, 40.0–43.5 GHz 63.00 deg
All States, 43.5–45.0 GHz 83.00 deg
Table 3 • PE43614 Electrical Specifications (Cont.)
Parameter Condition Min Typ Max Unit
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 6 of 23 DOC-93670-3 – (02/2021)
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Input IP2 18 dBm tone @ 13 GHz 95.00 dBm
Input IP3 18 dBm per tone, 20 MHz spacing @ 13
GHz 50.00 dBm
Input 1dB Compression
Pt. Bi-directional 32.00 34.00 dBm
Input 0.1dB Compres-
sion Pt. Bi-directional 25.00 28.00 dBm
RF Rise and Fall Time 10%/90% RF 250.00 ns
Settling Time RF settled to within 0.05 dB of final value 500.00 ns
Switching Time 50% CTRL to 90% or 10% RF 330.00 430.00 ns
Attenuation Transient Any state change -7.50 dB
Table 3 • PE43614 Electrical Specifications (Cont.)
Parameter Condition Min Typ Max Unit
DOC-93670-3 – (02/2021) Page 7 of 23
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PE43614
UltraCMOS® RF Digital Step Attenuator
Switching Frequency
The PE43614 has a maximum 400 kHz switching rate
in normal mode (pin 2 tied to ground). A faster
switching rate is available in bypass mode (pin 2 tied
to VSS_EXT). The rate at which the PE43614 can be
switched is then limited to the switching time as
specified in Table 3.
Switching frequency is defined to be the speed at
which the DSA can be toggled across attenuation
states. Switching time is the time duration between
the point the control signal reaches 50% of the final
value and the point the output signal reaches within
10% or 90% of its target value.
Spur-free Performance
The PE43614 spur fundamental occurs around 4
MHz. Typical spurious performance in normal mode is
–168 dBm/Hz (pin 2 tied to ground), with 30 kHz
bandwidth. If spur-free performance is desired, the
internal negative voltage generator can be disabled
by applying a negative voltage to VSS_EXT (pin 2).
Glitch-safe Attenuation State
The PE43614 features a novel architecture to provide
safe transition behavior when changing attenuation
states. When RF input power is applied, positive out-
put power spikes are prevented during attenuation
state changes by optimized internal timing control.
Truth Tables
Table 4–Table 6 provide the truth tables for the
PE43614.
Table 4 • Parallel Truth Table
Parallel Control Setting Attenuation
Setting
RF1–RF2
D6
(MSB) D5 D4 D3 D2 D1
(LSB)
L L L L L L Reference IL
L L L L L H 0.5 dB
L L L L H L 1 dB
L L L H L L 2 dB
L L H L L L 4 dB
L H L L L L 8 dB
HLLLLL 16 dB
H H H H H H 31.5 dB
Table 5 • Serial Address Word Truth Table
Address Word
Address
Setting
A7
(MSB) A6 A5 A4 A3 A2 A1 A0
(LSB)
L LLLLLL L 000
L LLLLLL H 001
L L L L L L H L 010
LLLLLLHH 011
L L L L L H L L 100
L L L L L H L H 101
LLLLLHHL 110
LLLLLHHH 111
Table 6 • Serial Attenuation Word Truth Table
Attenuation Word Attenuatio
n Setting
RF1–RF2
D7
(MSB) D6 D5 D4 D3 D2 D1 D0
(LSB)
L LLLLLL L Reference IL
L LLLLLH L 0.5 dB
L L L L L H L L 1 dB
L L L L H L L L 2 dB
L LLHLLL L 4 dB
L LHLLLL L 8 dB
L HLLLLL L 16 dB
L H H H H H H L 31.5 dB
Table 4 • Parallel Truth Table (Cont.)
Parallel Control Setting Attenuation
Setting
RF1–RF2
D6
(MSB) D5 D4 D3 D2 D1
(LSB)
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 8 of 23 DOC-93670-3 – (02/2021)
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Serial Addressable Register Map
Figure 2 provides the serial addressable register map for the PE43614.
Figure 2 • Serial Addressable Register Map
Attenuation Word
LSB (first in)
MSB (last in)
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8
A[6] A[7] A[5] A[4] A[3] A[2] A[1] A[0]
Address Word
Must be set to logic low
4 × 18.5 = 74
74 → 01001010
A
ddress Word: 00000011
A
ttenuation Word: 01001010
Serial Input: 0000001101001010
For example, to program the 18.5 dB state at address 3:
The attenuation word is derived directly from the value of the attenuation state. To find
the attenuation word, multiply the value of the state by four, then convert to binary.
DOC-93670-3 – (02/2021) Page 9 of 23
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PE43614
UltraCMOS® RF Digital Step Attenuator
Programming Options
Parallel/Serial Selection
Either a parallel or serial addressable interface can be
used to control the PE43614. The P/S bit provides this
selection, with P/S = LOW selecting the parallel
interface and P/S = HIGH selecting the serial
interface. The P/S pin has an internal tie HIGH
(namely, the pin is internally tied to the 1.8V VDD), so if
this is left floating, the part defaults to serial mode. If
there is a need to put this part in parallel mode, a
LOW logic should be applied to this pin.
Parallel Mode Interface
The parallel interface consists of six CMOS-
compatible control lines that select the desired attenu-
ation state, as shown in Table 4.
The parallel interface timing requirements are defined
by Figure 4 (Latched-Parallel/Direct-Parallel Timing
Diagram), Table 10 (Parallel and Direct Interface AC
Characteristics) and switching time (Table 3).
For latched parallel programming, the latch enable
(LE) should be held LOW while changing attenuation
state control values then pulse LE HIGH to LOW (per
Figure 4) to latch new attenuation state into the
device.
For direct parallel programming, the LE line should be
pulled HIGH. Changing attenuation state control val-
ues changes the device state to new attenuation.
Direct mode is ideal for manual control of the device
(using hardwire, switches, or jumpers).
Serial-Addressable Interface
The serial-addressable interface is a 16-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The 16-bits make up two words comprised of 8-
bits each. The first word is the attenuation word,
which controls the state of the DSA. The second word
is the address word, which is compared to the static
(or programmed) logical states of the A0, A1 and A2
digital inputs. If there is an address match, the DSA
changes state; otherwise its current state remains
unchanged. Figure 3 illustrates an example timing
diagram for programming a state.
The serial-addressable interface is controlled using
three CMOS-compatible signals: SDI, CLK, and LE.
The SDI and CLK inputs allow data to be serially
entered into the shift register. Serial data is clocked in
LSB first. The serial interface data output, SDO,
outputs serial input data delayed by 16 clock cycles to
control the cascaded attenuator using a single serial
peripheral interface (SPI) bus.
The shift register must be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data into the DSA. The Address Word truth table
is listed in Table 5. The address pins A0 (pin 22), A1
(pin 23), and A2 (pin 24) can either be grounded logic
LOW or left floating (logic HIGH due to internal pull-up
to 1.8V VDD) depending upon what fixed address the
user wants the DSA to be set at.The Attenuation Word
truth table is listed in Table 6. A programming
example of the serial register is illustrated in Figure 2.
The serial timing diagram is illustrated in Figure 3.
Power-up Control Settings
The PE43614 always initializes to the maximum atten-
uation setting (31.5 dB) on power-up for both the
serial addressable and latched parallel modes of
operation (as long as the LE pin is logic LOW during
start up) and it remains in this setting until the user
latches in the next programming word.
In direct parallel mode (P/S = LOW and logic HIGH
present on the LE pin during the power-up), the DSA
can be preset to any state within the 31.5 dB range by
pre-setting the parallel control pins D[6:1] prior to
power-up. In this mode, there is a 4 µs delay between
the time the DSA is powered-up to the time the
desired state is set. If the control pins are left floating
in this mode during power-up, the device defaults to
the 28dB attenuation setting.
In latched parallel mode (P/S = LOW), if the LE pin
is kept LOW during power-up, the part should default
to maximum attenuation state (31.5 dB). Logic LOW
should be present on the LE pin during power-up and
then logic HIGH should be written on the LE pin when
the user wants to program the part. If the LE is kept
floating during power-up, the part should default to
maximum attenuation state (31.5 dB).
In serial mode (P/S = HIGH or left floating) logic
HIGH on the LE pin during the power up: The part
should default to minimum attenuation state
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 10 of 23 DOC-93670-3 – (02/2021)
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(reference state). But a logic LOW on the LE pin
during the power up, the part should default to
maximum attenuation state.
Dynamic operation between serial and parallel
programming modes is not supported.
If the DSA powers up in serial mode (P/S = HIGH),
prior to toggling to parallel mode, the user must
ensure that the pins LE, SDI/D1, CLK/D2, A0/D4, A1/
D5, and A2/D6 are set to logic LOW.
If the DSA powers up in either latched or direct
parallel mode, the pins LE, SDI/D1, CLK/D2, A0/D4,
A1/D5, and A2/D6 must be set to logic LOW and the
pin SDO/D3 set to high impedance prior to toggling to
serial addressable mode (P/S = HIGH).
Table 7 • Summary of Power-up Functionality of the PE43614
Mode P/S LE During Power-up D[6:1] Pin Status DSA State at Power-up
Serial mode
1 0 Maximum attenuation
1 1 Reference state
1 Floating Maximum attenuation
Latch parallel mode
0 0 Don’t care Maximum attenuation
0 Floating Don’t care Maximum attenuation
Direct parallel mode 0 1
Data present on the D[6:1] lines
Attenuation state depends
upon the logic present on the
pins D[6:1]
D[6:1] lines floating 28 dB attenuation state
Figure 3 • Serial Addressable Timing Diagram
Notes:
1. SPI mode 0:
- SDI data is captured on the CLK’s rising edge
- SDO data is valid on CLK falling edge
2. CLK shared pin with 1 dB parallel control bit D2
3. SDI shared pin with 0.5 dB parallel control bit D1
4. SDO shared pin with 2 dB parallel control bit D3
5. A0 shared pin with 4 dB parallel control bit D4
6. A1 shared pin with 8 dB parallel control bit D5
7. A2 shared pin with 16 dB parallel control bit D6
8. Serial data bits D[7], D[0], and A[7:3] must be set to logic low
9. X = Undefined
CLK
LE
TSISU
TLESU
T
SIH
TCLK
T
CLKH TCLKL
TLEPW
D[4] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]
SDO
X
X
X
D[2] D[3]
D[0] D[1]
TSDOP D
D[1]
D[2] D[3] D[4] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]
SDI
D[0]
D[5]
D[5]
P/S
A[2:0]
0 00000
00000
0
0
0
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PE43614
UltraCMOS® RF Digital Step Attenuator
Table 8 • Serial Interface AC Characteristics(1)
Parameter/Condition Min Max Unit
Serial clock frequency, FCLK 10 MHz
Serial clock time period, TCLK 100 ns
Serial clock HIGH time, TCLKH 30 ns
Serial clock LOW time, TCLKL 30 ns
Last serial clock rising edge setup time to latch enable rising edge, TLESU 10 ns
Latch enable minimum pulse width, TLEPW 30 ns
Serial data setup time, TSISU 10 ns
Serial data hold time, TSIH 10 ns
Serial interface data output (SDO) propagation delay, TSDOPD 30(2) ns
1) VDD = 3.3V or 5.5V, –40 °C, < TA < +105 °C, unless otherwise specified.
2) Measured with 10 pF SDO load capacitance.
Table 9 • Latch and Clock Specifications
Latch
Enable (LE) Clock (CLK) Function
0↑Shift register clocked
↑
(rising edge) X
Contents of shift register
transferred to attenuator
core
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 12 of 23 DOC-93670-3 – (02/2021)
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Figure 4 • Latched-Parallel/Direct-Parallel Timing Diagram
Notes:
1. D1 is shared with serial interface data input SDI
2. D2 is shared with serial interface clock input CLK
3. D3 is shared with serial interface data output SDO
4. D4 is shared with serial address bit A0
5. D5 is shared with serial address bit A1
6. D6 is shared with serial address bit A2
7. X = Undefined
LE T
LEPW
D[1]
D[2]
D[3]
X
X
X
X
X
X
X
X
X
X
X
X
D[4]
D[5]
D[6]
P/S T
DISU
T
DIH
Table 10 • Parallel and Direct Interface AC Characteristics(*)
Parameter/Condition Min Max Unit
Latch enable minimum pulse width, TLEPW 30 ns
Parallel data setup time, TDISU 100 ns
Parallel data hold time, TDIH 100 ns
Note: * VDD = 3.3V or 5.5V, –40 °C < TA < +105 °C, unless otherwise specified.
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PE43614
UltraCMOS® RF Digital Step Attenuator
The following example shows a scenario where two DSAs are connected in series.
The following table provides the complete SDI and SDO content for the example shown in Figure 5.
Figure 5 • Serial Addressable Cascaded Devices Example
Example Scenario: 2 DSAs connected in series (SDO to SDI).
First write after power up
Signals from first DSA in chain
X = Undefined
0100
CLK
SDI X
LE
0
D[7] A[0] A[7]
D[1]D[0]
XXXXX
SDO XX
D[6] D[7] A[0] A[6] A[7]
D[1]D[0]
P/S X
D[7] A[0] A[7]
D[1]D[0]
0100000
D[6] D[7] A[0] A[6] A[7]
D[1]D[0]
00000
A[2:0]X
3125241817169810
Figure 6 • Serial Addressable Cascaded Devices Table
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]
CLK0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031
SDI01100000000000000000000000000000
SDOXXXXXXXXXXXXXXXX0110000000000000
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 14 of 23 DOC-93670-3 – (02/2021)
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Typical Performance Data
Figure 7–Figure 36 show the typical performance data at 25 °C, ZS = ZL = 50Ω, unless otherwise specified.
Figure 7 • Insertion Loss vs. Temperature @VDD 3.3 V
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
0 1020304050
Insertion Loss (dB)
Frequency (GHz)
-40 deg C
+25 deg C +105 deg C
Figure 8 • Input Return Loss (Ref State) vs.
Temperature
-35
-30
-25
-20
-15
-10
-5
0
0 1020304050
Return Loss (dB)
Frequency (GHz)
-40 deg C +25 deg C +105 deg C
Figure 9 • Input Return Loss (31.5dB Attn) vs.
Temperature
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 1020304050
Return Loss (dB)
Frequency (GHz)
-40 deg C +25 deg C
+105 deg C
-35
-30
-25
-20
-15
-10
-5
0
0 1020304050
Return Loss (dB)
Frequency (GHz)
-40 deg C +25 deg C +105 deg C
Figure 10 • Output Return Loss (Ref State) vs.
Temperature
Figure 11 • Output Return Loss (Ref State) vs.
Temperature
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
01020304050
Return Loss (dB)
Frequency (GHz)
-40 deg C +25 deg C +105 deg C
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
01020304050
Return Loss (dB)
Frequency (GHz)
0dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.5dB
Figure 12 • Input Return Loss (Major Attenuation
States)
DOC-93670-3 – (02/2021) Page 15 of 23
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PE43614
UltraCMOS® RF Digital Step Attenuator
Figure 13 • Input Return Loss (All Attenuation States)
-50
-40
-30
-20
-10
0
01020304050
Return Loss (dB)
Frequency (GHz)
Figure 14 • Output Return Loss (Major Attenuation
States)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0 1020304050
Return Loss (dB)
Frequency (GHz)
0dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.5dB
Figure 15 • Output Return Loss (All Attenuation
States)
-50
-40
-30
-20
-10
0
0 1020304050
Return Loss (dB)
Frequency (GHz)
-10
0
10
20
30
40
50
60
70
80
90
100
0 1020304050
Relative Phase Error (deg)
Frequency (GHz)
0dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.5dB
Figure 16 • Relative Phase Error vs. Frequency [GHz]
Figure 17 • Relative Phase Error (31.5 dB Attn State) vs
Temperature
0
20
40
60
80
100
-60 -40 -20 0 20 40 60 80 100 120
Phase Error (degrees)
Temperature (deg C)
1 GHz 6 GHz 8 GHz 13 GHz
26.5 GHz 43.5 GHz 44.5 GHz 50 GHz
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
Figure 18 • Attenuation Error @ 1 GHz vs.
Temperature
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 16 of 23 DOC-93670-3 – (02/2021)
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Figure 19 • Attenuation Error @ 6 GHz vs.
Temperature
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
Figure 20 • Attenuation Error @ 8 GHz vs.
Temperature
-1.5
-1
-0.5
0
0.5
1
1.5
2
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
Figure 21 • Attenuation Error @ 13 GHz vs.
Temperature
-1.5
-1
-0.5
0
0.5
1
1.5
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
-1
-0.5
0
0.5
1
1.5
2
2.5
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
Figure 22 • Attenuation Error @ 26.5 GHz vs.
Temperature
Figure 23 • Attenuation Error @ 40 GHz vs.
Temperature
-1
0
1
2
3
4
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
-1
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
Figure 24 • Attenuation Error @ 43.5 GHz vs.
Temperature
DOC-93670-3 – (02/2021) Page 17 of 23
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PE43614
UltraCMOS® RF Digital Step Attenuator
Figure 25 • Attenuation Error @ 45 GHz vs.
Temperature
-1
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35
Attenuation Error (dB)
Attenuation State (dB)
-40 deg C +25 deg C +105 deg C
Figure 26 • 0.5 dB Setup Attenuation vs Frequency
0
0.5
1
1.5
2
0 5 10 15 20 25 30 35
Step Attenuation (dB)
Attenuation State (dB)
1 GHz 6 GHz 8 GHz 13 GHz
26.5 GHz 40 GHz 43.5 GHz 45 GHz
Figure 27 • 1 dB Step Attenuation vs. Frequency
0
0.5
1
1.5
2
0 5 10 15 20 25 30 35
Step Attenuation (dB)
Attenuation State (dB)
1 GHz 6 GHz 8 GHz 13 GHz
26.5 GHz 40 GHz 43.5 GHz 45 GHz
0
5
10
15
20
25
30
35
40
0 5 10 15 20 25 30 35
Actual Attenuation (dB)
Ideal Attenuation (dB)
1 GHz 6 GHz 8 GHz 13 GHz
26.5 GHz 40 GHz 43.5 GHz 45 GHz
Figure 28 • 0.5 dB Step Actual vs. Frequency
Figure 29 • 0.5 dB Step Actual vs. Frequency
0
5
10
15
20
25
30
35
40
0 5 10 15 20 25 30 35
Actual Attenuation (dB)
Ideal Attenuation (dB)
1 GHz 6 GHz 8 GHz 13 GHz
26.5 GHz 40 GHz 43.5 GHz 45 GHz
-1
0
1
2
3
4
5
6
0 1020304050
Attenuation Error (dB)
Frequency (GHz)
0dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.5dB
Figure 30 • 0.5 dB Major State Bit Error vs. Attenu-
ation State
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 18 of 23 DOC-93670-3 – (02/2021)
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Figure 31 • 0.5 dB Attenuation Error vs. Frequency
-1
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35
Step Attenuation (dB)
Attenuation State (dB)
1 GHz 6 GHz 8 GHz 13 GHz
26.5 GHz 40 GHz 43 GHz 45 GHz
Figure 32 • 1 dB Attenuation Error vs. Frequency
-1
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35
Step Attenuation (dB)
Attenuation State (dB)
1 GHz 6 GHz 8 GHz 13 GHz
26.5 GHz 40 GHz 43.5 GHz 45 GHz
Figure 33 • Attenuation Transient (23.5 dB to 24 dB)
-10
-8
-6
-4
-2
0
2
-6 -4 -2 0 2 4 6
Envelop Power (dB)
Time (μsec)
Glitch ≈ 7 dB
(prevents excess
output power)
Glitch duration ≈ 250 nsec
-10
-8
-6
-4
-2
0
2
-6 -4 -2 0 2 4 6
Envelop Power (dB)
Time (μsec)
Glitch ≈ 7 dB
(prevents excess
output power)
Glitch duration ≈ 250 nsec
Figure 34 • Attenuation Transient (24 dB to 23.5 dB)
Figure 35 • IIP2
80.00
85.00
90.00
95.00
100.00
105.00
110.00
0 5 10 15 20
IIP2 (dBm)
Frequency (GHz)
0dB 31.5dB
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
0 5 10 15 20
IIP3 (dBm)
Frequency (GHz)
0 dB 31.5 dB
Figure 36 • IIP3
DOC-93670-3 – (02/2021) Page 19 of 23
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PE43614
UltraCMOS® RF Digital Step Attenuator
Pin Configuration
This section provides pin information for the
PE43614. Figure 37 shows the pin configuration of
this device. Table 11 provides a description for each
pin.
Figure 37 • Pin Configuration (Top View) for the PE43614
24 23 22 21 20 19
1
Exposed
GND
Pad
18
217
316
415
514
613
7 8 9 10 11 12
VDD
VSS_EXT
GND
GND
RF2
GND
P/S
LE
GND
GND
RF1
GND
GND A2/D6
A1/D5
A0/D4
SDO/D3
SDI/D1
CLK/D2
GND
GND
GND
GND
GND
Ex
po
se
d
G
N
D
Pa
d
Table 11 • Pin Descriptions for the PE43614
Pin No. Pin Name Description
3–4, 6–13,
15–16 GND Ground
1VDD Supply voltage
2VSS_EXT(3) External VSS negative voltage
control
5RF2(1) RF2 port
14 RF1(1) RF1 port
17 LE Serial/parallel interface latch
enable input
18 P/S(2) Serial/parallel mode select
19 CLK/D2 Serial interface clock input/par-
allel control bit, 1 dB
20 SDI/D1 Serial interface data input/paral-
lel control bit, 0.5 dB
21 SDO/D3 Serial interface data output/par-
allel control bit, 2 dB
22 A0/D4(2) Address bit A0 connection/par-
allel control bit, 4 dB
23 A1/D5(2) Address bit A1 connection/par-
allel control bit, 8 dB
24 A2/D6(2) Address bit A2 connection/par-
allel control bit, 16 dB
Notes:
1) RF pins 14 and 5 must be at 0 VDC. The RF pins do not require
DC blocking capacitors for proper operation if the 0 VDC
requirement is met.
2) P/S (pin 18), A0/D4 (pin 22), A1/D5 (pin 23) and A2/D6 (pin 24)
have internal 1.5 MΩ pull-up resistor to internal 1.8V VDD. These
pins will have an internal logic HIGH on them if they are left float-
ing by the user. In serial mode, the user can leave the P/S pin
floating and the part will default to serial mode.
3) Use VSS_EXT (pin 2) to bypass and disable internal negative volt-
age generator. Connect VSS_EXT (pin 2) to GND (VSS_EXT = 0V)
to enable internal negative voltage generator.
PE43614
UltraCMOS® RF Digital Step Attenuator
Page 20 of 23 DOC-93670-3 – (02/2021)
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Packaging Information
This section provides packaging data including the moisture sensitivity level, package drawing, package
marking and tape-and-reel information.
Moisture Sensitivity Level
The moisture sensitivity level rating for the PE43614 in the 24-lead 4 x 4 mm LGA package is MSL 3.
Package Drawing
Figure 38 • Package Mechanical Drawing for 24-lead 4 x 4 mm LGA
Third Angle
Projection
Unless otherwise specified
dimensions are in millimeters
Refer to comment for
overall tolerance
DOC-93670-3 – (02/2021) Page 21 of 23
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PE43614
UltraCMOS® RF Digital Step Attenuator
Top-Marking Specification
Figure 39 • Package Marking Specifications for PE43614
=
PPPPP =
YY =
WW =
ZZZZZZ =
Pin 1 indicator
Product part number
Last two digits of assembly year (2020 = 20)
Work week of assembly lot start date (01, ..., 52)
Assembly lost code (max six characters)
DOC-93717-1
PPPPP
YYWW
ZZZZZZ
PE43614
Product Specification www.psemi.com DOC-93670-3 – (02/2021)
Document Categories
Advance Information
The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and
features may change in any manner without notice.
Preliminary Specification
The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the right to change specifications at any
time without notice in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by
issuing a CNF (Customer Notification Form).
Sales Contact
For additional information, contact Sales at sales@psemi.com.
Disclaimers
The information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirely
at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’s
products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or
sustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur.
pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications.
Patent Statement
pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2019–2021, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are
registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries.
UltraCMOS® RF Digital Step
Attenuator
Ordering Information
Table 12 lists the available ordering code for the PE43614 as well as the available shipping method.
Table 12 • Order Code for the PE43614
Order Codes Description Packaging Shipping Method
PE43614A–X PE43614 Digital step attenuator 24-lead 4 x 4 mm LGA 500/T&R
EK43614-01 PE43614 Evaluation Kit Evaluation kit 1/box
