KSZ8895MQX/RQX/FQX/ML
Integrated 5-Port 10/100 Managed Ethernet
Switch with MII/RMII Interface
Revision 1.1
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 28, 2014
Revision-1.1
General Description
The KSZ8895MQX/RQX/FQX/ML is a highly-integrated,
Layer 2 managed, five-port switch with numerous features
designed to reduce system cost. Intended for cost-
sensitive 10/100Mbps five-port switch systems with low
power consumption, on-chip termination, and internal core
power controllers, it supports high-performance memory
bandwidth and shared memory-based switch fabric with
non-blocking configuration. Its extensive feature set
includes power management, programmable rate limit and
priority ratio, tag/port-based VLAN, packets filtering, four-
queue QoS prioritization, management interfaces, and MIB
counters. The KSZ8895 family provides multiple CPU data
interfaces to effectively address both current and emerging
fast Ethernet applications when port 5 is configured to
separate MAC5 with SW5-MII/RMII and PHY5 with P5-
MII/RMII interfaces.
The KSZ8895 family offers three configurations, providing
the flexibility to meet different requirements:
KSZ8895MQX/ML: 5 10/100Base-T/TX transceivers,
1 SW5-MII and 1 P5-MII interface
KSZ8895RQX: 5 10/100Base-T/TX transceivers, 1
SW5-RMII and 1 P5-RMII interface
KSZ8895FQX: 4 10/100Base-T/TX transceivers on
Ports 1, 2, 3 and 5 (port 3 can be set to the fiber
mode). 1 100Base-FX transceivers on Port 4. 1 SW5-
MII and 1 P5-MII interface
All registers of MACs and PHYs units can be managed by
the SPI or the SMI interface. MIIM registers can be
accessed through the MDC/MDIO interface. EEPROM can
set all control registers for the unmanaged mode.
KSZ8895MQX/RQX/FQX are 128-pin PQFP package.
KSZ8895ML is 128-pin LQFP package.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Look Up
Engine
Queue
Management
10/100
MAC 1
FIFO, Flow Control, VLAN
Tagging, Priority
SPI
EEPROM
Interface
LED I/F
Auto MDI/MDIX
Control Reg SPI I/F
MIB
Counters
LED0[5:1]
LED1[5:1]
LED2[5:1]
Control
Registers
MDC/MDIO for MIIM and SMI
SW5-MII/RMII or SNI
Auto MDI/MDIX
Auto MDI/MDIX
Auto MDI/MDIX
Auto MDI/MDIX
P5-MII/RMII
10/100
T/TX/FX
PHY3
10/100
T/TX/FX
PHY4
10/100
T/TX
PHY5
KSZ8895MQX/RQX/FQX/ML
10/100
T/TX
PHY1
10/100
T/TX
PHY2
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
Buffer
Management
Frame
Buffers
Note: SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
2
Revision-1.1
Features
Advanced Switch Features
IEEE 802.1q VLAN support for up to 128 active VLAN
groups (full-range 4096 of VLAN IDs).
Static MAC table supports up to 32 entries.
VLAN ID tag/untag options, per port basis
IEEE 802.1p/q tag insertion or removal on a per port
basis based on ingress port (egress).
Programmable rate limiting at the ingress and egress
on a per port basis.
Jitter-free per packet based rate limiting support.
Broadcast storm protection with percentage control
(global and per port basis).
IEEE 802.1d rapid spanning tree protocol RSTP
support.
Tail tag mode (1 byte added before FCS) support at
Port 5 to inform the processor which ingress port
receives the packet.
1.4Gbps high-performance memory bandwidth and
shared memory-based switch fabric with fully non-
blocking configuration.
Dual MII with MAC5 and PHY5 on port 5, SW5-
MII/RMII for MAC 5 and P5-MII/RMII for PHY 5.
Enable/Disable option for huge frame size up to 2000
Bytes per frame.
IGMP v1/v2 snooping (Ipv4) support for multicast
packet filtering.
IPv4/IPv6 QoS support.
Support unknown unicast/multicast address and
unknown VID packet filtering.
Self-address filtering.
Comprehensive Configuration Register Access
Serial management interface (MDC/MDIO) to all PHYs
registers and SMI interface (MDC/MDIO) to all registers.
High speed SPI (up to 25MHz) and I2C master
Interface to all internal registers.
I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode.
Control registers configurable on the fly (port-priority,
802.1p/d/q, AN and so on).
QoS/CoS Packet Prioritization Support
Per port, 802.1p and DiffServ-based.
1/2/4-queue QoS prioritization selection.
Programmable weighted fair queuing for ratio control.
Re-mapping of 802.1p priority field per port basis.
Integrated Five-Port 10/100 Ethernet Switch
New generation switch with five MACs and five PHYs
with fully compliant with IEEE 802.3u standard.
PHYs designed with patented enhanced mixed-signal
technology.
Non-blocking switch fabric assures fast packet delivery
by utilizing a 1K MAC address lookup table and a store-
and-forward architecture.
On-chip 64Kbyte memory for frame buffering (not
shared with 1K unicast address table).
Full duplex IEEE 802.3x flow control (PAUSE) with
force mode option.
Half-duplex back pressure flow control.
HP Auto MDI/MDI-X and IEEE Auto crossover support.
SW-MII interface supports both MAC mode and PHY
mode.
7-wire serial network interface (SNI) support for legacy
MAC.
Per port LED Indicators for link, activity, and 10/100
speed.
Register port status support for link, activity, full/half
duplex and 10/100 speed.
Micrel LinkMD® cable diagnostic capabilities.
On-chip terminations and internal biasing technology
for cost down and lowest power consumption.
Switch Monitoring Features
Port mirroring/monitoring/sniffing: ingress and/or egress
traffic to any port or MII.
MIB counters for fully compliant statistics gathering 34
MIB counters per port.
Loop-back support for MAC, PHY and remote
diagnostic of failure.
Interrupt for the link change on any ports.
Low Power Dissipation
Full-chip hardware power-down.
Full-chip software power-down and per port software
power down.
Energy-detect mode support < 100mW full chip-power
consumption when all ports have no activity.
Very low full chip power consumption (<0.5W) in
standalone 5-port, without extra power consumption on
transformers.
Dynamic clock tree shutdown feature.
Voltages: Single 3.3V supply with 3.3V VDDIO and
Internal 1.2V LDO controller enabled, or external 1.2V
LDO solution.
– Analog VDDAT 3.3V only.
– VDDIO support 3.3V, 2.5V and 1.8V.
– Low 1.2V core power .
0.11µm CMOS technology.
Commercial temperature range: 0°C to +70°C.
Industrial Temperature Range: -40°C to +85°C.
128-pin PQFP and 128-pin LQFP, lead-free package.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
3
Revision-1.1
Applications
Typical
VOIP phone
Set-top/game box
Automotive
Industrial control
IPTV POF
SOHO residential gateway
Broadband gateway/firewall/VPN
Integrated DSL/cable modem
Wireless LAN access point + gateway
Standalone 10/100 5-port switch
Ordering Information
Part Number
Temperature Range
Package
Lead Finish/Grade
KSZ8895MQXCA
0°C to 70°C
128-Pin PQFP
Pb-Free/Commercial
KSZ8895MQXIA
-40°C to +85°C
128-Pin PQFP
Pb-Free/Industrial
KSZ8895RQXCA
0°C to 70°C
128-Pin PQFP
Pb-Free/Commercial
KSZ8895RQXIA
-40°C to +85°C
128-Pin PQFP
Pb-Free/Industrial
KSZ8895FQXCA
0°C to 70°C
128-Pin PQFP
Pb-Free/Commercial
KSZ8895FQXIA
-40°C to +85°C
128-Pin PQFP
Pb-Free/Industrial
KSZ8895ML
0°C to 70°C
128-Pin LQFP
Pb-Free/Commercial
KSZ8895MLI(1)
-40°C to +85°C
128-Pin LQFP
Pb-Free/Industrial
KSZ8895MQX-EVAL
Evaluation Board for KSZ8895MQX
KSZ8895RQX-EVAL
Evaluation Board for KSZ8895RQX
KSZ8895FQX-EVAL
Evaluation Board for KSZ8895FQX
KSZ8895ML-EVAL
Evaluation Board for KSZ8895ML
Note:
1. Please consult sales regarding availability.
Revision History
Revision
Date
Description
1.0
O2/21/14
Initial document created
1.1
04/28/14
Update description for Register 1 bits [7:4], update the descriptions
in the section of the internal 1.2V LDO controller. Update the pin
125/pin126 descriptions. Add evaluation boards in ordering
information.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
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Revision-1.1
Contents
General Description......................................................................................................................................................... 1
Functional Diagram ......................................................................................................................................................... 1
Applications ..................................................................................................................................................................... 3
Ordering Information ....................................................................................................................................................... 3
Revision History .............................................................................................................................................................. 3
System Level Application .............................................................................................................................................. 15
Pin Configuration ........................................................................................................................................................... 17
Pin Description .............................................................................................................................................................. 19
Pin for Strap-in Options ................................................................................................................................................. 27
Introduction .................................................................................................................................................................... 31
Functional Overview: Physical Layer Transceiver ........................................................................................................ 31
100BASE-TX Transmit .............................................................................................................................................. 31
100BASE-TX Receive ............................................................................................................................................... 31
PLL Clock Synthesizer............................................................................................................................................... 32
Scrambler/Descrambler (100BASE-TX only) ............................................................................................................ 32
100BASE-FX Operation ............................................................................................................................................ 32
100BASE-FX Signal Detection .................................................................................................................................. 32
100BASE-FX Far End Fault ...................................................................................................................................... 32
10BASE-T Transmit ................................................................................................................................................... 32
10BASE-T Receive .................................................................................................................................................... 32
MDI/MDI-X Auto Crossover ....................................................................................................................................... 32
Straight Cable ........................................................................................................................................................ 33
Crossover Cable .................................................................................................................................................... 34
Auto-Negotiation ........................................................................................................................................................ 34
LinkMD® Cable Diagnostics ....................................................................................................................................... 36
Access .................................................................................................................................................................... 36
Usage ..................................................................................................................................................................... 36
A LinkMD example ................................................................................................................................................. 37
On-chip Termination Resistors .................................................................................................................................. 37
Internal 1.2V LDO Controller ..................................................................................................................................... 37
Functional Overview: Power ......................................................................................................................................... 38
Using Internal 1.2V LDO Controller ........................................................................................................................... 38
Using External 1.2V LDO Regulator .......................................................................................................................... 39
Functional Overview: Power Management ................................................................................................................... 40
Normal Operation Mode ............................................................................................................................................ 40
Energy Detect Mode .................................................................................................................................................. 40
Soft Power Down Mode ............................................................................................................................................. 41
Power Saving Mode................................................................................................................................................... 41
Port-based Power Down Mode .................................................................................................................................. 41
Functional Overview: Switch Core ................................................................................................................................ 41
Address Look-Up ....................................................................................................................................................... 41
Learning ..................................................................................................................................................................... 41
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KSZ8895MQX/RQX/FQX/ML
April 28, 2014
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Revision-1.1
Migration .................................................................................................................................................................... 41
Aging .......................................................................................................................................................................... 42
Forwarding ................................................................................................................................................................. 42
KSZ8895MQX/RQX/FQX/ML will not forward the following packets: .................................................................... 42
Switching Engine ....................................................................................................................................................... 42
Media Access Controller (MAC) Operation ............................................................................................................... 42
Inter-Packet Gap (IPG) .......................................................................................................................................... 42
Backoff Algorithm ................................................................................................................................................... 42
Late Collision .......................................................................................................................................................... 42
Illegal Frames ......................................................................................................................................................... 42
Flow Control ........................................................................................................................................................... 42
Half-Duplex Back Pressure .................................................................................................................................... 44
Broadcast Storm Protection ................................................................................................................................... 45
MII Interface Operation .............................................................................................................................................. 46
Port 5 PHY 5 P5-MII/RMII Interface .......................................................................................................................... 46
Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQX ............................................................................. 48
SNI Interface Operation ............................................................................................................................................. 50
Advanced Functionality ................................................................................................................................................. 51
QoS Priority Support .................................................................................................................................................. 51
Port-Based Priority ................................................................................................................................................. 51
802.1p-Based Priority ............................................................................................................................................ 51
DiffServ-Based Priority ........................................................................................................................................... 52
Spanning Tree Support ............................................................................................................................................. 52
Rapid Spanning Tree Support ................................................................................................................................... 53
Tail Tagging Mode ..................................................................................................................................................... 54
IGMP Support ............................................................................................................................................................ 55
IGMP Snooping ...................................................................................................................................................... 55
IGMP Send Back to the Subscribed Port ............................................................................................................... 55
Port Mirroring Support ............................................................................................................................................... 55
“Receive Only” mirror on a port .............................................................................................................................. 55
“Transmit Only” mirror on a port ............................................................................................................................. 55
“Receive and Transmit” mirror on two ports .......................................................................................................... 55
VLAN Support ............................................................................................................................................................ 55
Rate Limiting Support ................................................................................................................................................ 56
Ingress Rate Limit .................................................................................................................................................. 56
Egress Rate Limit ................................................................................................................................................... 57
Transmit Queue Ratio Programming ..................................................................................................................... 57
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ................. 57
Configuration Interface .................................................................................................................................................. 57
I2C Master Serial Bus Configuration .......................................................................................................................... 57
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SPI Slave Serial Bus Configuration ....................................................................................................................... 58
MII Management Interface (MIIM).......................................................................................................................... 61
Serial Management Interface (SMI) ....................................................................................................................... 61
Register Description ...................................................................................................................................................... 63
Global Registers ........................................................................................................................................................ 65
Register 0 (0x00): Chip ID0 ................................................................................................................................... 65
Register 1 (0x01): Chip ID1 / Start Switch ............................................................................................................. 65
Register 2 (0x02): Global Control 0 ....................................................................................................................... 65
Register 3 (0x03): Global Control 1 ....................................................................................................................... 66
Register 4 (0x04): Global Control 2 ....................................................................................................................... 67
Register 5 (0x05): Global Control 3 ....................................................................................................................... 68
Register 6 (0x06): Global Control 4 ....................................................................................................................... 69
Register 7 (0x07): Global Control 5 ....................................................................................................................... 70
Register 8 (0x08): Global Control 6 ....................................................................................................................... 70
Register 9 (0x09): Global Control 7 ....................................................................................................................... 70
Register 10 (0x0A): Global Control 8 ..................................................................................................................... 71
Register 11 (0x0B): Global Control 9 ..................................................................................................................... 71
Register 12 (0x0C): Global Control 10 ................................................................................................................... 72
Register 13 (0x0D): Global Control 11 ................................................................................................................... 72
Register 14 (0x0E): Power Down Management Control 1 ..................................................................................... 72
Register 15 (0x0F): Power Down Management Control 2 ..................................................................................... 73
Port Registers ............................................................................................................................................................ 74
Register 16 (0x10): Port 1 Control 0 ...................................................................................................................... 74
Register 32 (0x20): Port 2 Control 0 ...................................................................................................................... 74
Register 48 (0x30): Port 3 Control 0 ...................................................................................................................... 74
Register 64 (0x40): Port 4 Control 0 ...................................................................................................................... 74
Register 80 (0x50): Port 5 Control 0 ...................................................................................................................... 74
Register 17 (0x11): Port 1 Control 1 ...................................................................................................................... 75
Register 33 (0x21): Port 2 Control 1 ...................................................................................................................... 75
Register 49 (0x31): Port 3 Control 1 ...................................................................................................................... 75
Register 65 (0x41): Port 4 Control 1 ...................................................................................................................... 75
Register 81 (0x51): Port 5 Control 1 ...................................................................................................................... 75
Register 18 (0x12): Port 1 Control 2 ...................................................................................................................... 76
Register 34 (0x22): Port 2 Control 2 ...................................................................................................................... 76
Register 50 (0x32): Port 3 Control 2 ...................................................................................................................... 76
Register 66 (0x42): Port 4 Control 2 ...................................................................................................................... 76
Register 82 (0x52): Port 5 Control 2 ...................................................................................................................... 76
Register 19 (0x13): Port 1 Control 3 ...................................................................................................................... 77
Register 35 (0x23): Port 2 Control 3 ...................................................................................................................... 77
Register 51 (0x33): Port 3 Control 3 ...................................................................................................................... 77
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
7
Revision-1.1
Register 67 (0x43): Port 4 Control 3 ...................................................................................................................... 77
Register 83 (0x53): Port 5 Control 3 ...................................................................................................................... 77
Register 20 (0x14): Port 1 Control 4 ...................................................................................................................... 77
Register 36 (0x24): Port 2 Control 4 ...................................................................................................................... 77
Register 52 (0x34): Port 3 Control 4 ...................................................................................................................... 77
Register 68 (0x44): Port 4 Control 4 ...................................................................................................................... 77
Register 84 (0x54): Port 5 Control 4 ...................................................................................................................... 77
Register 87 (0x57): RMII Management Control Register ...................................................................................... 77
Register 25 (0x19): Port 1 Status 0........................................................................................................................ 78
Register 41 (0x29): Port 2 Status 0........................................................................................................................ 78
Register 57 (0x39): Port 3 Status 0........................................................................................................................ 78
Register 73 (0x49): Port 4 Status 0........................................................................................................................ 78
Register 89 (0x59): Port 5 Status 0........................................................................................................................ 78
Register 26 (0x1A): Port 1 PHY Special Control/Status ........................................................................................ 78
Register 42 (0x2A): Port 2 PHY Special Control/Status ........................................................................................ 78
Register 58 (0x3A): Port 3 PHY Special Control/Status ........................................................................................ 78
Register 74 (0x4A): Port 4 PHY Special Control/Status ........................................................................................ 78
Register 90 (0x5A): Port 5 PHY Special Control/Status ........................................................................................ 78
Register 27 (0x1B): Port 1 LinkMD result .............................................................................................................. 79
Register 43 (0x2B): Port 2 LinkMD result .............................................................................................................. 79
Register 59 (0x3B): Port 3 LinkMD result .............................................................................................................. 79
Register 75 (0x4B): Port 4 LinkMD result .............................................................................................................. 79
Register 91 (0x5B): Port 5 LinkMD result .............................................................................................................. 79
Register 28 (0x1C): Port 1 Control 5...................................................................................................................... 79
Register 44 (0x2C): Port 2 Control 5...................................................................................................................... 79
Register 60 (0x3C): Port 3 Control 5...................................................................................................................... 79
Register 76 (0x4C): Port 4 Control 5...................................................................................................................... 79
Register 92 (0x5C): Port 5 Control 5...................................................................................................................... 79
Register 29 (0x1D): Port 1 Control 6...................................................................................................................... 81
Register 45 (0x2D): Port 2 Control 6...................................................................................................................... 81
Register 61 (0x3D): Port 3 Control 6...................................................................................................................... 81
Register 77 (0x4D): Port 4 Control 6...................................................................................................................... 81
Register 93 (0x5D): Port 5 Control 6...................................................................................................................... 81
Register 30 (0x1E): Port 1 Status 1 ....................................................................................................................... 82
Register 46 (0x2E): Port 2 Status 1 ....................................................................................................................... 82
Register 62 (0x3E): Port 3 Status 1 ....................................................................................................................... 82
Register 78 (0x4E): Port 4 Status 1 ....................................................................................................................... 82
Register 94 (0x5E): Port 5 Status 1 ....................................................................................................................... 82
Register 31 (0x1F): Port 1 Control 7 and Status 2 ................................................................................................. 82
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
8
Revision-1.1
Register 47 (0x2F): Port 2 Control 7 and Status 2 ................................................................................................. 82
Register 63 (0x3F): Port 3 Control 7 and Status 2 ................................................................................................. 82
Register 79 (0x4F): Port 4 Control 7 and Status 2 ................................................................................................. 82
Register 95 (0x5F): Port 5 Control 7 and Status 2 ................................................................................................. 82
Advanced Control Registers ...................................................................................................................................... 83
Register 104 (0x68): MAC Address Register 0 ...................................................................................................... 83
Register 105 (0x69): MAC Address Register 1 ...................................................................................................... 83
Register 106 (0x6A): MAC Address Register 2 ..................................................................................................... 83
Register 107 (0x6B): MAC Address Register 3 ..................................................................................................... 83
Register 108 (0x6C): MAC Address Register 4 ..................................................................................................... 83
Register 109 (0X6D): MAC Address Register 5 .................................................................................................... 83
Register 110 (0x6E): Indirect Access Control 0 ..................................................................................................... 84
Register 111 (0x6F): Indirect Access Control 1 ..................................................................................................... 84
Register 112 (0x70): Indirect Data Register 8 ....................................................................................................... 84
Register 113 (0x71): Indirect Data Register 7 ....................................................................................................... 84
Register 114 (0x72): Indirect Data Register 6 ....................................................................................................... 84
Register 115 (0x73): Indirect Data Register 5 ....................................................................................................... 84
Register 116 (0x74): Indirect Data Register 4 ....................................................................................................... 84
Register 117 (0x75): Indirect Data Register 3 ....................................................................................................... 84
Register 118 (0x76): Indirect Data Register 2 ....................................................................................................... 84
Register 119 (0x77): Indirect Data Register 1 ....................................................................................................... 84
Register 120 (0x78): Indirect Data Register 0 ....................................................................................................... 84
Register 124 (0x7C): Interrupt Status Register ...................................................................................................... 85
Register 125 (0x7D): Interrupt Mask Register ....................................................................................................... 85
Register 128 (0x80): Global Control 12 ................................................................................................................. 86
Register 129 (0x81): Global Control 13 ................................................................................................................. 86
Register 130 (0x82): Global Control 14 ................................................................................................................. 86
Register 131 (0x83): Global Control 15 ................................................................................................................. 88
Register 132 (0x84): Global Control 16 ................................................................................................................. 88
Register 133(0x85): Global Control 17 .................................................................................................................. 88
Register 134 (0x86): Global Control 18 ................................................................................................................. 89
Register 135 (0x87): Global Control 19 ................................................................................................................. 89
Register 144 (0x90): TOS Priority Control Register 0............................................................................................ 90
Register 145 (0x91): TOS Priority Control Register 1............................................................................................ 90
Register 146 (0x92): TOS Priority Control Register 2............................................................................................ 90
Register 147 (0x93): TOS Priority Control Register 3............................................................................................ 90
Register 148 (0x94): TOS Priority Control Register 4............................................................................................ 90
Register 149 (0x95): TOS Priority Control Register 5............................................................................................ 91
Register 150 (0x96): TOS Priority Control Register 6............................................................................................ 91
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
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Revision-1.1
Register 151 (0x97): TOS Priority Control Register 7............................................................................................ 91
Register 152 (0x98): TOS Priority Control Register 8............................................................................................ 91
Register 153 (0x99): TOS Priority Control Register 9............................................................................................ 91
Register 154 (0x9A): TOS Priority Control Register 10 ......................................................................................... 91
Register 155 (0x9B): TOS Priority Control Register 11 ......................................................................................... 91
Register 156 (0x9C): TOS Priority Control Register 12 ......................................................................................... 92
Register 157 (0x9D): TOS Priority Control Register 13 ......................................................................................... 92
Register 158 (0x9E): TOS Priority Control Register 14 ......................................................................................... 92
Register 159 (0x9F): TOS Priority Control Register 15 ......................................................................................... 92
Register 165 (0xA5): Reserved .............................................................................................................................. 92
Register 176 (0xB0): Port 1 Control 8 .................................................................................................................... 92
Register 192 (0xC0): Port 2 Control 8.................................................................................................................... 92
Register 208 (0xD0): Port 3 Control 8.................................................................................................................... 92
Register 224 (0xE0): Port 4 Control 8 .................................................................................................................... 92
Register 240 (0xF0): Port 5 Control 8 .................................................................................................................... 92
Register 177 (0xB1): Port 1 Control 9 .................................................................................................................... 93
Register 193 (0xC1): Port 2 Control 9.................................................................................................................... 93
Register 209 (0xD1): Port 3 Control 9.................................................................................................................... 93
Register 225 (0xE1): Port 4 Control 9 .................................................................................................................... 93
Register 241 (0xF1): Port 5 Control 9 .................................................................................................................... 93
Register 178 (0xB2): Port 1 Control 10 .................................................................................................................. 94
Register 194 (0xC2): Port 2 Control 10 ................................................................................................................. 94
Register 210 (0xD2): Port 3 Control 10 ................................................................................................................. 94
Register 226 (0xE2): Port 4 Control 10 .................................................................................................................. 94
Register 242 (0xF2): Port 5 Control 10 .................................................................................................................. 94
Register 179 (0xB3): Port 1 Control 11 .................................................................................................................. 94
Register 195 (0xC3): Port 2 Control 11 ................................................................................................................. 94
Register 211 (0xD3): Port 3 Control 11 ................................................................................................................. 94
Register 227 (0xE3): Port 4 Control 11 .................................................................................................................. 94
Register 243 (0xF3): Port 5 Control 11 .................................................................................................................. 94
Register 180 (0xB4): Port 1 Control 12 .................................................................................................................. 94
Register 196 (0xC4): Port 2 Control 12 ................................................................................................................. 94
Register 212 (0xD4): Port 3 Control 12 ................................................................................................................. 94
Register 228 (0xE4): Port 4 Control 12 .................................................................................................................. 94
Register 244 (0xF4): Port 5 Control 12 .................................................................................................................. 94
Register 181 (0xB5): Port 1 Control 13 .................................................................................................................. 95
Register 197 (0xC5): Port 2 Control 13 ................................................................................................................. 95
Register 213 (0xD5): Port 3 Control 13 ................................................................................................................. 95
Register 229 (0xE5): Port 4 Control 13 .................................................................................................................. 95
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
10
Revision-1.1
Register 245 (0xF5): Port 5 Control 13 .................................................................................................................. 95
Register 182 (0xB6): Port 1 Rate Limit Control ..................................................................................................... 95
Register 198 (0xC6): Port 2 Rate Limit Control ..................................................................................................... 95
Register 214 (0xD6): Port 3 Rate Limit Control ..................................................................................................... 95
Register 230 (0xE6): Port 4 Rate Limit Control ..................................................................................................... 95
Register 246 (0xF6): Port 5 Rate Limit Control ...................................................................................................... 95
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1 ............................................................................... 96
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1 ............................................................................... 96
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1 ............................................................................... 96
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1 ............................................................................... 96
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1 ............................................................................... 96
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2 ............................................................................... 96
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2 ............................................................................... 96
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2 ............................................................................... 96
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2 ............................................................................... 96
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2 ............................................................................... 96
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3 ............................................................................... 96
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3 ............................................................................... 96
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3 ............................................................................... 96
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3 ............................................................................... 96
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3 ............................................................................... 96
Register 186 (0xBA): Port 1 Priority 3 Ingress Limit Control 4 .............................................................................. 97
Register 202 (0xCA): Port 2 Priority 3 Ingress Limit Control 4 .............................................................................. 97
Register 218 (0xDA): Port 3 Priority 3 Ingress Limit Control 4 .............................................................................. 97
Register 234 (0xEA): Port 4 Priority 3 Ingress Limit Control 4 .............................................................................. 97
Register 250 (0xFA): Port 5 Priority 3 Ingress Limit Control 4 ............................................................................... 97
Register 187 (0xBB): Port 1 Queue 0 Egress Limit Control 1 ............................................................................... 97
Register 203 (0xCB): Port 2 Queue 0 Egress Limit Control 1 ............................................................................... 97
Register 219 (0xDB): Port 3 Queue 0 Egress Limit Control 1 ............................................................................... 97
Register 235 (0xEB): Port 4 Queue 0 Egress Limit Control 1 ............................................................................... 97
Register 251 (0xFB): Port 5 Queue 0 Egress Limit Control 1 ................................................................................ 97
Register 188 (0xBC) : Port 1 Queue 1 Egress Limit Control 2 .............................................................................. 97
Register 204 (0xCC) : Port 2 Queue 1 Egress Limit Control 2 .............................................................................. 97
Register 220 (0xDC) : Port 3 Queue 1 Egress Limit Control 2 .............................................................................. 97
Register 236 (0xEC) : Port 4 Queue 1 Egress Limit Control 2 .............................................................................. 97
Register 252 (0xFC) : Port 5 Queue 1 Egress Limit Control 2 .............................................................................. 97
Register 189 (0xBD): Port 1 Queue 2 Egress Limit Control 3 ............................................................................... 98
Register 205 (0xCD): Port 2 Queue 2 Egress Limit Control 3 ............................................................................... 98
Register 221 (0xDD): Port 3 Queue 2 Egress Limit Control 3 ............................................................................... 98
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
11
Revision-1.1
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3 ............................................................................... 98
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3 ............................................................................... 98
Data Rate Limit Selection Limit Table ....................................................................................................................... 99
Register 191(0xBF): Testing Register 1 ................................................................................................................ 99
Register 207(0xCF): Reserved Control Register .................................................................................................. 99
Register 223(0xDF): Testing Register 2 ................................................................................................................ 99
Register 239(0xEF): Port 3 Copper or Fiber Control ............................................................................................. 99
Register 255(0xFF): Testing Register 3 ................................................................................................................. 99
Static MAC Address Table .......................................................................................................................................... 100
Format of Static MAC Table for Reads (32 entries) ................................................................................................ 100
Format of Static MAC Table for Writes (32 entries) ................................................................................................ 100
Dynamic MAC Address Table ..................................................................................................................................... 104
Format of Dynamic MAC Address Table (1K entries) ............................................................................................. 104
MIB (Management Information Base) Counters ......................................................................................................... 106
For Port 1 ............................................................................................................................................................. 106
For port 2, the base is 0x20, same offset definition (0x20-0x3f) .......................................................................... 107
For port 3, the base is 0x40, same offset definition (0x40-0x5f) .......................................................................... 107
For port 4, the base is 0x60, same offset definition (0x60-0x7f) .......................................................................... 107
For port 5, the base is 0x80, same offset definition (0x80-0x9f) .......................................................................... 107
Format of Per Port MIB Counters (16 entries) ......................................................................................................... 107
Format of All Port Dropped Packet MIB Counters ................................................................................................... 107
MIIM Registers ............................................................................................................................................................ 109
Register 0h: MII Control ........................................................................................................................................... 109
Register 1h: MII Status ............................................................................................................................................ 110
Register 2h: PHYID HIGH ....................................................................................................................................... 110
Register 3h: PHYID LOW ........................................................................................................................................ 110
Register 4h: Advertisement Ability ........................................................................................................................... 110
Register 5h: Link Partner Ability .............................................................................................................................. 111
Register 1dh: LinkMD Control/Status ..................................................................................................................... 111
Register 1fh: PHY Special Control/Status ............................................................................................................... 112
Absolute Maximum Ratings(1) ...................................................................................................................................... 113
Operating Ratings(2) .................................................................................................................................................... 113
Electrical Characteristics(4,5) ........................................................................................................................................ 113
Timing Diagrams ......................................................................................................................................................... 115
EEPROM Timing ..................................................................................................................................................... 115
SNI Timing ............................................................................................................................................................... 116
MII Timing ................................................................................................................................................................ 117
SPI Timing ............................................................................................................................................................... 120
Auto-Negotiation Timing .......................................................................................................................................... 122
MDC/MDIO Timing .................................................................................................................................................. 123
Reset Timing ............................................................................................................................................................ 124
Reset Circuit Diagram.............................................................................................................................................. 125
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
12
Revision-1.1
Selection of Isolation Transformer(1)............................................................................................................................ 126
Selection of Reference Crystal .................................................................................................................................... 126
..................................................................................................................................................................................... 128
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
13
Revision-1.1
List of Figures
Figure 1. Broadband Gateway ..................................................................................................................................... 15
Figure 2. Integrated Broadband Router ....................................................................................................................... 15
Figure 3. Standalone Switch ........................................................................................................................................ 16
Figure 4. Using KSZ8895FQX for Dual Media Converter ............................................................................................. 16
Figure 5. Typical Straight Cable Connection ................................................................................................................ 33
Figure 6. Typical Crossover Cable Connection ............................................................................................................ 34
Figure 7. Auto-Negotiation ............................................................................................................................................ 35
Figure 8. Recommended 1.2V Power Connection using Internal 1.2V LDO Controller .............................................. 38
Figure 9. Recommended 1.2V Power Connection Using the External 1.2V Regulator ............................................... 39
Figure 10. Destination Address Lookup Flow Chart, Stage 1 ....................................................................................... 43
Figure 11. Destination Address Resolution Flow Chart, Stage 2 .................................................................................. 44
Figure 12. 802.1p Priority Field Format........................................................................................................................ 51
Figure 13. Tail Tag Frame Format ................................................................................................................................ 54
Figure 14. KSZ8895MQX/RQX/FQX/ML EEPROM Configuration Timing Diagram .................................................... 58
Figure 15. SPI Write Data Cycle .................................................................................................................................. 59
Figure 16. SPI Read Data Cycle .................................................................................................................................. 59
Figure 17. SPI Multiple Write ....................................................................................................................................... 60
Figure 18. SPI Multiple Read ....................................................................................................................................... 60
Figure 19. EEPROM Interface Input Receive Timing Diagram ................................................................................... 115
Figure 20. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 115
Figure 21. SNI Input Timing ........................................................................................................................................ 116
Figure 22. SNI Output Timing ..................................................................................................................................... 116
Figure 23. MAC Mode MII Timing – Data Received from MII ..................................................................................... 117
Figure 24. MAC Mode MII Timing – Data Transmitted from MII ................................................................................. 117
Figure 25. PHY Mode MII Timing – Data Received from MII ...................................................................................... 118
Figure 26. PHY Mode MII Timing – Data Transmitted from MII .................................................................................. 118
Figure 27. RMII Timing – Data Received from RMII ................................................................................................... 119
Figure 28. RMII Timing – Data Transmitted to RMII ................................................................................................... 119
Figure 29. SPI Input Timing ........................................................................................................................................ 120
Figure 30. SPI Output Timing ...................................................................................................................................... 121
Figure 31: Auto-Negotiation Timing ............................................................................................................................ 122
Figure 32. MDC/MDIO Timing ..................................................................................................................................... 123
Figure 33. Reset Timing .............................................................................................................................................. 124
Figure 34. Recommended Reset Circuit ..................................................................................................................... 125
Figure 35. Recommended Circuit for Interfacing with CPU/FPGA Reset ................................................................... 125
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
14
Revision-1.1
List of Tables
Table 1. MDI/MDI-X Pin Definitions .......................................................................................................................... 33
Table 2. Voltages and Power Pins ........................................................................................................................... 38
Table 3. Internal Function Block Status ..................................................................................................................... 40
Table 4. Port 5 PHY P5-MII/RMII Signals ................................................................................................................. 46
Table 5. Switch MAC5 MII Signals ............................................................................................................................ 47
Table 6. Port 5 MAC5 SW5-RMII Connection ........................................................................................................... 49
Table 7. SNI Signals ................................................................................................................................................. 50
Table 8. Tail Tag Rules ............................................................................................................................................ 54
Table 9. FID+DA Look-Up in the VLAN Mode .......................................................................................................... 56
Table 10. FID+SA Look-Up in the VLAN Mode ........................................................................................................ 56
Table 11. SPI Connections ....................................................................................................................................... 59
Table 12. MII Management Interface Frame Format ................................................................................................ 61
Table 13. Serial Management Interface (SMI) Frame Format ................................................................................. 61
Table 14. 10/100BT Rate Selection for the Rate limit ............................................................................................... 99
Table 15. Static MAC Address Table ...................................................................................................................... 100
Table 16. VLAN Table ............................................................................................................................................. 102
Table 17. VLAN ID and Indirect Registers .............................................................................................................. 103
Table 18. Dynamic MAC Address Table ................................................................................................................. 104
Table 19. Port1 MIB Counter Indirect Memory Offerts ........................................................................................... 106
Table 20. Format of “Per Port” MIB Counter .......................................................................................................... 107
Table 21. All Port Dropped Packet MIB Counters .................................................................................................. 107
Table 22. Format of “All Dropped Packet” MIB Counter......................................................................................... 107
Table 23. EEPROM Timing Parameters................................................................................................................. 115
Table 24. SNI Timing Parameters ........................................................................................................................... 116
Table 25. MAC Mode MII Timing Parameters ......................................................................................................... 117
Table 26. PHY Mode MII Timing Parameters .......................................................................................................... 118
Table 27. RMII Timing Parameters .......................................................................................................................... 119
Table 28. SPI Input Timing Parameters .................................................................................................................. 120
Table 29. SPI Output Timing Parameters................................................................................................................ 121
Table 30. Auto-Negotiation Timing Parameters ...................................................................................................... 122
Table 31. MDC/MDIO Typical Timing Parameters .................................................................................................. 123
Table 32. Reset Timing Parameters ....................................................................................................................... 124
Table 33. Transformer Selection Criteria................................................................................................................. 126
Table 34. Qualified Magnetic Vendors ................................................................................................................... 126
Table 35. Typical Reference Crystal Characteristics ............................................................................................. 126
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
15
Revision-1.1
System Level Application
Figure 1. Broadband Gateway
Figure 2. Integrated Broadband Router
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
16
Revision-1.1
Figure 3. Standalone Switch
Figure 4. Using KSZ8895FQX for Dual Media Converter
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
17
Revision-1.1
Pin Configuration
TXM5
VDDAT
FXSD3
TXP5
33
34
35
36
37
38
KSZ8895MQX/RQX/FQX
(Top View) NC
PMRXDV/PMCRSDV
NC
NC
NC
NC
NC
NC
PWRDN_N
INTR_N
GNDD
VDDC
PMTXEN
PMTXD3
PMTXD2
PMTXD1
PMTXD0
PMTXER
PMTXC/PMREFCLK
GNDD
PMRXD1
VDDIO
PMRXC
PMRXD3
PMRXD263
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
64
FXSD4
LED3-1
LED4-0
LED3-2
SCONF1
SCOL
SMRXD2
VDDIO
SMTXC/SMREFCLK
SMTXD0
SMTXD2
SMTXEN
PCOL
PCRS
PMRXER
LED4-1
LED4-2
LED5-1
LED5-2
VDDC
GNDD
SCONF0
SCRS
SMRXD0
SMRXD1
SMRXD3
SMRXDV/SMCRSDV
SMRXC
GNDD
SMTXER
SMTXD1
SMTXD3
PMRXD0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LED2-1
LED2-2
VDDIO
GNDD
LED3-0
101
100
99
98
97
LED2-0
102
103
GNDA
LED1-0
MDIXDIS
TEST2
GNDA
IN_PWR_SEL
LDO_O
NC
X2
X1
NC
SCANEN
TESTEN
VDDC
GNDD
RST_N
PS0
PS1
SPIS_N
SPID/SDA
SPIC/SCL
SPIQ
MDIO
MDC
LED1-1
LED1-2 104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VDDAR
RXP1
RXM1
GNDA
TXP1
TXM1
VDDAT
RXP2
RXM2
RXM3
TXP3
RXP4
TXM4
VDDAR
RXM5
GNDA
GNDA
TXP2
TXM2
VDDAR
GNDA
ISET
VDDAT
RXP3
GNDA
TXM3
VDDAT
RXM4
GNDA
TXP4
GNDA
RXP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
LED5-0
128-Pin PQFP Pin Configuration
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
18
Revision-1.1
TXM5
VDDAT
NC
TXP5
33
34
35
36
37
38
KSZ8895ML
(Top View) NC
PMRXDV
NC
NC
NC
NC
NC
NC
PWRDN_N
INTR_N
GNDD
VDDC
PMTXEN
PMTXD3
PMTXD2
PMTXD1
PMTXD0
PMTXER
PMTXC
GNDD
PMRXD1
VDDIO
PMRXC
PMRXD3
PMRXD263
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
64
NC
LED3-1
LED4-0
LED3-2
SCONF1
SCOL
SMRXD2
VDDIO
SMTXC
SMTXD0
SMTXD2
SMTXEN
PCOL
PCRS
PMRXER
LED4-1
LED4-2
LED5-1
LED5-2
VDDC
GNDD
SCONF0
SCRS
SMRXD0
SMRXD1
SMRXD3
SMRXDV
SMRXC
GNDD
SMTXER
SMTXD1
SMTXD3
PMRXD0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LED2-1
LED2-2
VDDIO
GNDD
LED3-0
101
100
99
98
97
LED2-0 102
103
GNDA
LED1-0
MDIXDIS
TEST2
GNDA
IN_PWR_SEL
LDO_O
NC
X2
X1
NC
SCANEN
TESTEN
VDDC
GNDD
RST_N
PS0
PS1
SPIS_N
SPID/SDA
SPIC/SCL
SPIQ
MDIO
MDC
LED1-1
LED1-2 104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VDDAR
RXP1
RXM1
GNDA
TXP1
TXM1
VDDAT
RXP2
RXM2
RXM3
TXP3
RXP4
TXM4
VDDAR
RXM5
GNDA
GNDA
TXP2
TXM2
VDDAR
GNDA
ISET
VDDAT
RXP3
GNDA
TXM3
VDDAT
RXM4
GNDA
TXP4
GNDA
RXP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
LED5-0
128-Pin LQFP Pin Configuration
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
19
Revision-1.1
Pin Description
Pin
Number
Pin Name
Type(1)
Port
Pin Function(2)
1
MDI-XDIS
IPD
1 5
Disable auto MDI/MDI-X.
PD (default) = normal operation.
PU = disable auto MDI/MDI-X on all ports.
2
GNDA
GND
Analog ground.
3
VDDAR
P
1.2V analog VDD.
4
RXP1
I
1
Physical receive signal + (differential).
5
RXM1
I
1
Physical receive signal - (differential).
6
GNDA
GND
Analog ground.
7
TXP1
O
1
Physical transmit signal + (differential).
8
TXM1
O
1
Physical transmit signal - (differential).
9
VDDAT
P
3.3V analog VDD.
10
RXP2
I
2
Physical receive signal + (differential).
11
RXM2
I
2
Physical receive signal - (differential).
12
GNDA
GND
Analog ground.
13
TXP2
O
2
Physical transmit signal + (differential).
14
TXM2
O
2
Physical transmit signal - (differential).
15
VDDAR
P
1.2V analog VDD.
16
GNDA
GND
Analog ground.
17
ISET
Set physical transmit output current. Pull-down with a
12.4kΩ1% resistor.
18
VDDAT
P
3.3V analog VDD.
19
RXP3
I
3
Physical receive signal + (differential).
20
RXM3
I
3
Physical receive signal - (differential).
21
GNDA
GND
Analog ground.
22
TXP3
O
3
Physical transmit signal + (differential).
23
TXM3
O
3
Physical transmit signal – (differential).
24
VDDAT
P
3.3V analog VDD.
25
RXP4
I
4
Physical receive signal + (differential).
26
RXM4
I
4
Physical receive signal - (differential).
27
GNDA
GND
Analog ground.
28
TXP4
O
4
Physical transmit signal + (differential).
29
TXM4
O
4
Physical transmit signal - (differential).
30
GNDA
GND
Analog ground.
31
VDDAR
P
1.2V analog VDD.
32
RXP5
I
5
Physical receive signal + (differential).
33
RXM5
I
5
Physical receive signal - (differential).
34
GNDA
GND
Analog ground.
35
TXP5
O
5
Physical transmit signal + (differential).
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
April 28, 2014
20
Revision-1.1
Pin
Number
Pin Name
Type(1)
Port
Pin Function(2)
36
TXM5
O
5
Physical transmit signal - (differential).
37
VDDAT
P
3.3V analog VDD.
38
NC/FXSD3
IPD
3
FQX: This pin can be floating when port 3 is used as copper port
(default). Port 3 can be set to fiber mode by Register 239 bit [7], this
pin is used for fiber signal detect pin on Port 3 in Fiber mode.
MQX/RQX/ML: no connection.
39
FXSD4
IPD
4
FQX: Fiber signal detect pin for Port 4.
MQX/RQX/ML: no connection.
40
NC
NC
No connection. Leave NC pin floating.
41
NC
NC
No connection. Leave NC pin floating.
42
NC
NC
No connection. Leave NC pin floating.
43
NC
NC
No connection. Leave NC pin floating.
44
NC
NC
No connection. Leave NC pin floating.
45
NC
NC
No connection. Leave NC pin floating.
46
NC
NC
No connection. Leave NC pin floating.
47
PWRDN_N
IPU
Full-chip power down. Active low.
48
INTR_N
OPU
Interrupt. This pin is Open-Drain output pin.
49
GNDD
GND
Digital ground.
50
VDDC
P
1.2V digital core VDD.
51
PMTXEN
IPD
5
PHY [5] MII/RMII transmit enable.
52
PMTXD3
IPD
5
MQX/FQX/ML: PHY [5] MII transmit bit 3.
RQX: no connection for RMII.
53
PMTXD2
IPD
5
MQX/FQX/ML: PHY [5] MII transmit bit 2.
RQX: no connection for RMII.
54
PMTXD1
IPD
5
PHY [5] MII/RMII transmit bit 1.
55
PMTXD0
IPD
5
PHY [5] MII/RMII transmit bit 0.
56
PMTXER
IPD
5
MQX/FQX/ML: PHY [5] MII transmit error. RQX: no connection for
RMII.
57
PMTXC/PMREFCLK
I/O
5
MQX/FQX/ML: Output PHY [5] MII transmit clock
RQX: Input PHY [5] RMII reference clock, 50MHz 50ppm, the
50MHz clock comes from PMRXC Pin 60.
58
GNDD
GND
Digital ground.
59
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
60
PMRXC
I/O
5
MQX/FQX/ML: Output PHY [5] MII receive clock.
RQX: Output PHY [5] RMII reference clock, this clock is used when
opposite doesn’t provide RMII 50MHz clock or the system doesn’t
provide an external 50MHz clock for the P5-RMII interface.
61
PMRXDV/PMCRSDV
IPD/O
5
MQX/FQX/ML: PMRXDV is for PHY [5] MII receive data valid.
RQX: PMCRSDV is for PHY [5] RMII Carrier Sense/Receive Data
Valid Output.
62
PMRXD3
IPD/O
5
MQX/FQX/ML: PHY [5] MII receive bit 3.
RQX: no connection for RMII.
Strap option: