GS74117AX
256K x 16
4Mb Asynchronous SRAM
8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
FP-BGA
Commercial Temp
Industrial Temp
Rev: 1.05 12/2004 1/12 © 2001, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Fast access time: 8, 10, 12 ns
• CMOS low power operation: 130/105/95 mA at minimum
cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package:
X: 6 mm x 10 mm Fine Pitch Ball Grid Array package
GX: Pb-Free 6 mm x 10 mm Fine Pitch Ball Grid Array
package
Description
The GS74117A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS74117A is available in a 6 x 10 mm Fine
Pitch BGA package.
Fine Pitch BGA 256K x 16 Bump Configuration
Package X
6 x 10 mm Bump Pitch
Top View
Pin Descriptions
Symbol Description
A0–A17 Address input
DQ1–DQ16 Data input/output
CE Chip enable input
LB Lower byte enable input
(DQ1 to DQ8)
UB Upper byte enable input
(DQ9 to DQ16)
WE Write enable input
OE Output enable input
VDD +3.3 V power supply
VSS Ground
NC No connect
123456
ALB
OE A0A1A2NC
BDQ1UB A3A4CE DQ16
CDQ3DQ2A5A6DQ15 DQ14
DVSS DQ4A17 A7DQ13 VDD
EVDD DQ5NC A16 DQ12 VSS
FDQ6DQ7A8A9DQ10 DQ11
GDQ8NC A10 A11 WE DQ9
HNCA12 A13 A14 A15 NC
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 2/12 © 2001, GSI Technology
X: “H” or “L”
Truth Table
CE OE WE LB UB DQ1 to DQ8DQ9 to DQ16 VDD Current
H X X X X Not Selected Not Selected ISB1, ISB2
LLH
L L Read Read
IDD
L H Read High Z
H L High Z Read
LXL
LL Write Write
L H Write Not Write, High Z
H L Not Write, High Z Write
L H H X X High Z High Z
L X X H H High Z High Z
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control I/O Buffer
A0
CE
WE
OE
DQ1
A17
DQ16
UB _____
Block Diagram
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 3/12 © 2001, GSI Technology
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Notes:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage VDD –0.5 to +4.6 V
Input Voltage VIN –0.5 to VDD +0.5
(≤ 4.6 V max.) V
Output Voltage VOUT –0.5 to VDD +0.5
(≤ 4.6 V max.) V
Allowable power dissipation PD 0.7 W
Storage temperature TSTG –55 to 150 oC
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage for -8/-10/-12 VDD 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 — VDD +0.3 V
Input Low Voltage VIL –0.3 — 0.8 V
Ambient Temperature,
Commercial Range TAc 0—70
oC
Ambient Temperature,
Industrial Range TAI–40 — 85 oC
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 4/12 © 2001, GSI Technology
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance CIN VIN = 0 V 5 pF
Output Capacitance COUT VOUT = 0 V 7 pF
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage
Current IIL VIN = 0 to VDD – 1 uA 1 uA
Output Leakage
Current ILO Output High Z
VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH IOH = –4 mA 2.4 —
Output Low Voltage VOL ILO = +4 mA — 0.4 V
Power Supply Currents
Parameter Symbol Test Conditions
0 to 70°C –40 to 85°C
Unit
8 ns 10 ns 12 ns 8 ns 10 ns 12 ns
Operating
Supply
Current
IDD
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
130 105 90 140 115 100 mA
Standby
Current ISB1
CE ≥ VIH
All other inputs
≥ VIH or ≤VIL
Min. cycle time
30 25 22 40 35 32 mA
Standby
Current ISB2
CE ≥ VDD – 0.2 V
All other inputs
≥ VDD – 0.2 V or ≤ 0.2 V
10 20 mA
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 5/12 © 2001, GSI Technology
AC Test Conditions
DQ
VT = 1.4 V
50Ω30pF1
DQ
3.3 V
Output Load 1
Output Load 2
589Ω
434Ω
5pF1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Parameter Conditions
Input high level VIH = 2.4 V
Input low level VIL = 0.4 V
Input rise time tr = 1 V/ns
Input fall time tf = 1 V/ns
Input reference level 1.4 V
Output reference level 1.4 V
Output load Fig. 1& 2
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 6/12 © 2001, GSI Technology
AC Characteristics
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
Read Cycle
Parameter Symbol
-8 -10 -12
Unit
MinMaxMinMaxMinMax
Read cycle time tRC 8 — 10 — 12 — ns
Address access time tAA — 8 — 10 — 12 ns
Chip enable access time (CE)tAC — 8 — 10 — 12 ns
Byte enable access time (UB, LB)tAB —3.5—4—5 ns
Output enable to output valid (OE)tOE —3.5—4—5 ns
Output hold from address change tOH 3—3—3—ns
Chip enable to output in low Z (CE)tLZ*3—3—3—ns
Output enable to output in low Z (OE)tOLZ*0—0—0—ns
Byte enable to output in low Z (UB, LB)tBLZ*0—0—0—ns
Chip disable to output in High Z (CE)tHZ*—4—5—6 ns
Output disable to output in High Z (OE)tOHZ*—3.5—4—5 ns
Byte disable to output in High Z (UB, LB)tBHZ*—3.5—4—5 ns
tAA
tOH
tRC
Address
Data Out Previous Data Data valid
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 7/12 © 2001, GSI Technology
Read Cycle 2: WE = VIH
* These parameters are sampled and are not 100% tested.
Write Cycle
Parameter Symbol
-8 -10 -12
Unit
Min Max Min Max Min Max
Write cycle time tWC 8 — 10 — 12 — ns
Address valid to end of write tAW 5.5 — 7 — 8 — ns
Chip enable to end of write tCW 5.5 — 7 — 8 — ns
Byte enable to end of write tBW 5.5 — 7 — 8 — ns
Data set up time tDW 4 — 4.5 — 6 — ns
Data hold time tDH 0 — 0 — 0 — ns
Write pulse width tWP 5.5 — 7 — 8 — ns
Address set up time tAS 0 — 0 — 0 — ns
Write recovery time (WE) tWR 0—0—0—ns
Write recovery time (CE)tWR10—0—0—ns
Output Low Z from end of write tWLZ*3—3—3—ns
Write to output in High Z tWHZ*—3.5— 4 — 5 ns
tAA
tRC
Address
tAC
tLZ
tAB
tBLZ
tOE
tOLZ
CE
UB, LB
OE
Data Out
tHZ
tBHZ
tOHZ
Data valid
High impedance
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 8/12 © 2001, GSI Technology
Write Cycle 1: WE control
Write Cycle 2: CE control
tWC
Address
CE
UB, LB
WE
Data In
OE
Data Out
tAW
tCW
tBW
tAS tWP
tWR
tDW tDH
tWLZtWHZ
Data valid
High impedance
tWC
Address
CE
UB, LB
WE
Data In
OE
Data Out
tAW
tWP
tAS tCW
tWR1
tDW tDH
Data valid
High impedance
tBW
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 9/12 © 2001, GSI Technology
Write Cycle 3: UB, LB control
tWC
Address
CE
UB, LB
WE
Data In
OE
Data Out
tAW
tWP
tAS tCW
tWR1
tDW tDH
Data valid
High impedance
tBW
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 10/12 © 2001, GSI Technology
Package X—6 mm x 10 mm FP-BGA
Pin A1
Index
A1
E
Top View
Side View
D
A
aaa
Pin A1
Index
E1
Bottom View
D1
c
e
e
Solder Ballfb
Symbol Unit: mm
A 1.10±0.10
A1 0.20~0.30
fbf0.30~0.40
c 0.36(TYP)
D 10.0±0.05
D1 5.25
E 6.0±0.05
E1 3.75
e 0.75(TYP)
aaa 0.10
A B C D E F G H
1
2
3
4
5
6
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 11/12 © 2001, GSI Technology
* Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS74117AX-8T
Ordering Information
Part Number*Package Access Time Temp. Range Status
GS74117AX-8 6 mm x 10 mm BGA 8 ns Commercial
GS74117AX-10 6 mm x 10 mm BGA 10 ns Commercial
GS74117AX-12 6 mm x 10 mm BGA 12 ns Commercial
GS74117AX-8I 6 mm x 10 mm BGA 8 ns Industrial
GS74117AX-10I 6 mm x 10 mm BGA 10 ns Industrial
GS74117AX-12I 6 mm x 10 mm BGA 12 ns Industrial
GS74117AGX-8 Pb-free 6 mm x 10 mm BGA 8 ns Commercial
GS74117AGX-10 Pb-free 6 mm x 10 mm BGA 10 ns Commercial
GS74117AGX-12 Pb-free 6 mm x 10 mm BGA 12 ns Commercial
GS74117AGX-8I Pb-free 6 mm x 10 mm BGA 8 ns Industrial
GS74117AGX-10I Pb-free 6 mm x 10 mm BGA 10 ns Industrial
GS74117AGX-12I Pb-free 6 mm x 10 mm BGA 12 ns Industrial
GS74117AX
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.05 12/2004 12/12 © 2001, GSI Technology
4Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content Page #/Revisions/Reason
74117A_r1 Format/Content • Creation of new datasheet
74117A_r1; 74117A_r1_01 Content • Updated Recommended Operating Conditions table on page 3
• Updated Read Cycle and Write Cycle AC Characteristics tables
74117A_r1_01; 74117A_r1_02 Content • Removed 6 ns speed bin from entire document
74117A_r1_02; 74117A_r1_03 Content • Removed 7 ns speed bin from entire document
74117A_r1_03; 74117A_r1_04 Format • Updated format
74117A_r1_04; 74117A_r1_05 Content • Added Pb-free information for FP-BGA package
