VND5012AK-E Double channel high side driver with analog current sense for automotive applications Features Max supply voltage VCC 41 V Operating voltage range VCC 4.5 to 36 V Max on-state resistance (per ch.) RON 12 m Current limitation (typ) ILIMH 60 A IS 2 A(1) Off-state supply current (typ.) 1. Typical value with all loads connected. General features - Inrush current active management by power limitation - Very low standby current - 3.0 V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC european directive PowerSSO-24 - Reverse battery protection (see Application schematic) - Electrostatic discharge protection Application All types of resistive, inductive and capacitive loads Description Diagnostic functions - Proportional load current sense - High current sense precision for wide range currents - Current sense disable - Thermal shutdown indication - Very low current sense leakage Protections - Undervoltage shutdown - Overvoltage clamp - Output stuck to Vcc detection - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shutdown The VND5012AK-E a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Table 1. Device summary Order codes Package PowerSSO-24 December 2009 Tube Tape and reel VND5012AK-E VND5012AKTR-E Doc ID 12285 Rev 7 1/31 www.st.com 1 Contents VND5012AK-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 4 6 2/31 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 22 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 5 GND Protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 PowerSSO-24 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 12285 Rev 7 VND5012AK-E List of tables List of tables Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC=13V; Tj=25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Doc ID 12285 Rev 7 3/31 List of figures VND5012AK-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. 4/31 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay response time between rising edge of output current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . 24 PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25 Thermal fitting model of a single channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . . 25 PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-24 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Doc ID 12285 Rev 7 VND5012AK-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC UNDERVOLTAGE VCC CLAMP OUTPUT1 PwCLAMP 1 GND CURRENT SENSE1 DRIVER 1 ILIM 1 INPUT1 LOGIC VDSLIM 1 PwrLIM 1 PwCLAMP 2 DRIVER 2 OUTPUT2 ILIM 2 OVERTEMP. 1 INPUT2 VDSLIM 2 IOUT1 K1 CURRENT SENSE2 OVERTEMP. 2 IOUT2 K2 PwrLIM 2 CS_DIS Table 2. Pin function Name VCC OUTPUT1,2 GND INPUT1,2 CURRENT SENSE1,2 CS_DIS Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state. Analog current sense pin, delivers a current proportional to the load current. Active high CMOS compatible pin, to disable the current sense pin. Doc ID 12285 Rev 7 5/31 Block diagram and pin description Figure 2. VND5012AK-E Configuration diagram (top view) VCC GND N.C. INPUT2 N.C. INPUT1 N.C. CURRENT SENSE1 N.C. CURRENT SENSE2 CS_DIS VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 TAB = VCC Table 3. 6/31 Suggested connections for unused and not connected pins Connection / pin Current Sense N.C. Output Input CS_DIS Floating Not allowed X X X X To ground Through 1 K resistor X Not allowed Through 10 K resistor Through 10 K resistor Doc ID 12285 Rev 7 VND5012AK-E 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions IS VCC ICSD OUTPUT1 CS_DIS VCSD CURRENT SENSE1 IIN1 INPUT1 VIN1 IIN2 VIN2 OUTPUT2 VF (*) IOUT1 VOUT1 ISENSE1 VSENSE1 IOUT2 VOUT2 INPUT2 CURRENT SENSE2 GND VCC ISENSE2 VSENSE2 IGND Note: VFn = VOUTn - VCC during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 4. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 41 V -VCC Reverse DC supply voltage 0.3 V -IGND DC reverse ground pin current 200 mA IOUT DC output current Internally limited A -IOUT Reverse DC output current -30 A DC Input current -1 to 10 mA DC current sense disable input current -1 to 10 mA 200 mA VCC-41 +VCC V V IIN ICSD -ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage Doc ID 12285 Rev 7 7/31 Electrical specifications Table 4. Absolute maximum ratings (continued) Symbol Value Unit 508 mJ Maximum switching energy (L=1.25 mH; RL=0 ; Vbat=13.5 V; Tjstart=150 C; IOUT = IlimL(Typ.)) VESD Electrostatic discharge (Human body model: R= 1.5 K; C= 100 pF) - INPUT - CURRENT SENSE - CS_DIS - OUTPUT - VCC 4000 2000 4000 5000 5000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Junction operating temperature -40 to 150 C Storage temperature -55 to 150 C Max value Unit 0.4 C/W See Figure 29 C/W Tstg Thermal data Table 5. Symbol 8/31 Parameter EMAX Tj 2.2 VND5012AK-E Thermal data Parameter Rthj-case Thermal resistance junction-case (max) (With one channel on) Rthj-amb Thermal resistance junction-ambient (max) Doc ID 12285 Rev 7 VND5012AK-E 2.3 Electrical specifications Electrical characteristics 8V<VCC<36V; -40C<Tj<150C, unless otherwise specified. Table 6. Power section Symbol Parameter VCC Operating supply voltage VUSD VUSDhyst RON Vclamp IS IL(off) VF Test conditions Min. Typ. 4.5 13 36 V Undervoltage shutdown 3.5 4.5 V Undervoltage shutdown hysteresis 0.5 On-state resistance(2) IOUT=5A; Tj=25C IOUT=5A; Tj=150C IOUT=5A; VCC=5V; Tj=25C Clamp voltage IS=20mA Supply current Off-state; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On-state; VCC=13V; VIN=5V; IOUT=0A 41 Off-state output current(2) VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C Output VCC diode voltage(2) -IOUT= 8A; Tj=150C 0 0 Max. Unit V 12 24 16 m m m 46 52 V 2(1) 5(1) A 3 6 mA 0.01 3 5 A 0.7 V Max. Unit 1. PowerMOS leakage included. 2. For each channel. Table 7. Symbol Switching (VCC=13V; Tj=25C) Parameter Test conditions Min. Typ. td(on) Turn-on delay time RL= 2.6 (see Figure 8) 20 s td(off) Turn-off delay time RL= 2.6 (see Figure 8) 35 s dVOUT/dt(on) Turn-on voltage slope RL= 2.6 See Figure 21 V/s dVOUT/dt(off) Turn-off voltage slope RL= 2.6 See Figure 22 V/s WON Switching energy losses during twon RL= 2.6 (see Figure 8) 1.1 mJ WOFF Switching energy losses during twoff RL= 2.6 (see Figure 8) 0.7 mJ Doc ID 12285 Rev 7 9/31 Electrical specifications Table 8. Symbol VND5012AK-E Logic inputs Parameter Test conditions VIL Input low level voltage IIL Low level input current VIH Input high level voltage IIH High level input current VI(hyst) Input hysteresis voltage VICL VIN=0.9 V CS_DIS low level voltage ICSDL Low level CS_DIS current VCSD=0.9 V VCSDH CS_DIS high level voltage ICSDH High level CS_DIS current VCSD=2.1 V VCSCL Table 9. Symbol CS_DIS hysteresis voltage CS_DIS clamp voltage ICSD=1 mA ICSD=-1 mA Parameter Test conditions VCC=13 V 5 V<VCC<36 V IlimL Short circuit current during thermal cycling VCC=13 V TR<Tj<TTSD TTSD Shutdown temperature TR Reset temperature TRS Thermal reset of STATUS VON 0.9 V 1 A 2.1 V 10 V 5.5 7 V V 0.9 V -0.7 1 A 2.1 V 10 A V 5.5 7 V V -0.7 Min. Typ. Max. Unit 42 60 84 84 A A 24 150 175 TRS + 1 TRS + 5 A 200 135 Thermal hysteresis (TTSD -TR) C 7 Turn-off output voltage clamp IOUT=2 A; VIN=0; L=6 mH Output voltage drop limitation IOUT= 0.4 A; Tj= -40 C...+150 C (see Figure 26) VCC-41 Doc ID 12285 Rev 7 C C VCC-46 C VCC-52 25 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. 10/31 A Protections and diagnostics (1) DC short circuit current VDEMAG Unit 0.25 IlimH THYST Max. 0.25 VCSDL VCSD(hyst) Typ. VIN=2.1 V IIN=1 mA IIN=-1 mA Input clamp voltage Min. V mV VND5012AK-E Electrical specifications Table 10. Symbol K0 K1 dK1/K1(1) K2 dK2/K2(1) K3 dK3/K3(1) ISENSE0 Current sense (8V<VCC<16V) Parameter Test conditions IOUT/ISENSE IOUT= 0.25 A; VSENSE=0.5 V; VCSD=0 V; Tj= -40 C...150 C IOUT/ISENSE IOUT= 5 A; VSENSE=0.5 V; VCSD=0 V; Tj= -40 C...150 C IOUT=5 A; VSENSE=0.5 V; VCSD=0 V; Tj= 25 C...150 C Current sense ratio drift IOUT= 5 A; VSENSE= 0.5 V; VCSD=0 V; TJ= -40 C to 150 C IOUT/ISENSE IOUT= 10 A; VSENSE=4 V; VCSD=0 V; Tj= -40 C...150 C IOUT= 10 A; VSENSE=4 V; VCSD=0 V; Tj= 25 C...150 C Current sense ratio drift IOUT= 10 A; VSENSE= 4 V; VCSD=0 V; TJ= -40 C to 150 C IOUT/ISENSE IOUT= 25 A; VSENSE=4 V; VCSD=0 V; Tj= -40 C...150 C IOUT= 25 A; VSENSE=4 V; VCSD=0 V; Tj= 25 C...150 C Current sense ratio drift IOUT= 25 A; VSENSE= 4 V; VCSD=0 V; TJ= -40 C to 150 C Analog sense leakage current IOUT=0 A; VSENSE=0 V; VCSD=5 V; VIN=0 V; Tj=-40 C...150 C VCSD=0 V; VIN=5 V; Tj=-40 C...150 C IOUT=2 A; VSENSE=0 V; VCSD=5 V; VIN=5 V; Tj=-40 C...150 C Min. Typ. Max. Unit 2780 5580 8390 3590 5100 6630 4110 5100 6090 -8 +8 % 4400 5090 5930 4600 5090 5590 -5 +5 % 4820 5060 5420 4860 5060 5250 -4 +4 % 0 0 1 2 A A 0 1 A 45 mA IOL Open-load on-state current detection threshold VIN = 5 V, ISENSE= 5 A 10 VSENSE Max analog sense output voltage IOUT=15 A; VCSD=0 V 5 V Analog sense output voltage in VSENSEH over temperature condition VCC= 13 V; RSENSE= 3.9 K 9 V Analog sense output current in ISENSEH over temperature condition VCC= 13 V; VSENSE= 5 V 8 mA VSENSE<4 V, 1.5 A<Iout<25 A Delay response tDSENSE1H time from falling ISENSE= 90 % of ISENSE max edge of CS_DIS pin (see Figure 4) Doc ID 12285 Rev 7 50 100 s 11/31 Electrical specifications Table 10. Symbol VND5012AK-E Current sense (8V<VCC<16V) (continued) Parameter Test conditions Min. VSENSE<4V, 1.5A<Iout<25A Delay response tDSENSE1L time from rising ISENSE= 10% of ISENSE max edge of CS_DIS pin (see Figure 4) Delay response tDSENSE2H time from rising edge of INPUT pin VSENSE<4 V, 1.5 A<Iout<25 A ISENSE= 90 % of ISENSE max (see Figure 4) Delay response time between rising edge of output tDSENSE2H current and rising edge of current sense VSENSE<4 V, ISENSE = 90 % of ISENSEMAX, IOUT = 90 % of IOUTMAX IOUTMAX= 5 A (see Figure 5) Delay response tDSENSE2L time from falling edge of INPUT pin VSENSE<4 V, 1.5 A<Iout<25 A ISENSE=10 % of ISENSE max (see Figure 4) Typ. 5 20 s 270 400 s 300 s 250 s 100 1. Parameter guaranteed by design, it is not tested. Figure 4. Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H 12/31 tDSENSE1L Doc ID 12285 Rev 7 tDSENSE1H Max. Unit tDSENSE2L VND5012AK-E Electrical specifications Figure 5. Delay response time between rising edge of output current and rising edge of current sense (CS enabled) VIN tDSENSE2H t IOUT IOUTMAX 90% IOUTMAX t ISENSE ISENSEMAX 90% ISENSEMAX t Doc ID 12285 Rev 7 13/31 Electrical specifications Figure 6. VND5012AK-E IOUT/ISENSE vs IOUT 7000 6500 max Tj = -40C to 150C 6000 5500 max Tj= 25C to 150C typical value 5000 min Tj= 25C to 150C 4500 4000 min Tj= -40C to 150C 3500 3000 5 Figure 7. 10 15 20 25 Maximum current sense ratio drift vs load current dk/k(%) 15 10 5 0 -5 -10 -15 5 10 15 IOUT (A) Note: Parameter guaranteed by design; it is not tested. 14/31 Doc ID 12285 Rev 7 20 25 VND5012AK-E Electrical specifications Table 11. Truth table Input Output Sense (VCSD=0V)(1) Normal operation L H L H 0 Nominal Over temperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 Short circuit to GND (Rsc 10 m) L H H L L L 0 0 if Tj < TTSD VSENSEH if Tj > TTSD Short circuit to VCC L H H H 0 < Nominal Negative output voltage clamp L L 0 Conditions 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit. Figure 8. Switching characteristics VOUT tWon tWoff 90% 80% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t INPUT td(on) td(off) t Doc ID 12285 Rev 7 15/31 Electrical specifications Figure 9. VND5012AK-E Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC Von Iout Von/Ron(T) Table 12. ISO 7637-2: 2004(E) Electrical transient requirements (part 1/3) Test levels(1) test pulse III IV 1 -75V -100V 2a +37V 3a Number of pulses or test times Burst cycle/pulse repetition time Min. Max. 5000 pulses 0.5 s 5s 2 ms, 10 +50V 5000 pulses 0.2 s 5s 50 s, 2 -100V -150V 1h 90 ms 100 ms 0.1 s, 50 3b +75V +100V 1h 90 ms 100 ms 0.1 s, 50 4 -6V -7V 1 pulse 100 ms, 0.01 5b(2) +65V +87V 1 pulse 400 ms, 2 Table 13. Electrical transient requirements (part 2/3) Test level results (1) ISO 7637-2: 2004(E) test pulse III IV 1 C C 2 C C 3a C C 3b C C 4 C C 5(2) C C 1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5 b. 2. 16/31 Delays and impedance Valid in case of external load dump clamp: 40 V maximum referred to ground. Doc ID 12285 Rev 7 VND5012AK-E Electrical specifications Table 14. Electrical transient requirements (part 3/3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Figure 10. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst VCC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERLOAD OPERATION Tj TTSD TR TRS INPUT CS_DIS ILIMH ILIML LOAD CURRENT VSENSEH SENSE CURRENT thermal cycling current power limitation limitation SHORTED LOAD Doc ID 12285 Rev 7 NORMAL LOAD 17/31 Electrical specifications VND5012AK-E 2.4 Electrical characteristics curves Figure 11. Off-state output current Figure 12. High level input current Figure 13. Input clamp voltage Figure 14. Input high level Figure 15. Input low level Figure 16. Input hysteresis voltage 18/31 Doc ID 12285 Rev 7 VND5012AK-E Electrical specifications Figure 17. On-state resistance vs Tcase Figure 18. On-state resistance vs VCC Figure 19. Undervoltage shutdown Figure 20. ILIMH vs Tcase Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope Doc ID 12285 Rev 7 19/31 Electrical specifications Figure 23. CS_DIS high level voltage VND5012AK-E Figure 24. CS_DIS clamp voltage Figure 25. CS_DIS low level voltage 20/31 Doc ID 12285 Rev 7 VND5012AK-E 3 Application information Application information Figure 26. Application schematic +5V VCC Rprot CS_DIS Dld C Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE VGND Cext RGND DGND Note: Channel 2 has the same internal circuit as channel 1. 3.1 GND Protection network against reverse battery 3.1.1 Solution 1: resistor in the ground line (RGND only) This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. RGND 600 mV / (IS(on)max). 2. RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. Doc ID 12285 Rev 7 21/31 Application information VND5012AK-E If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below). 3.1.2 Solution 2: diode (DGND) in the ground line A resistor (RGND=1 k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table. 3.3 MCU I/Os protection If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100 V and Ilatchup 20 mA; VOHC 4.5 V 5 k Rprot 180 k. Recommended values: Rprot =10 k, CEXT=10 nF. 22/31 Doc ID 12285 Rev 7 VND5012AK-E 3.4 Application information Maximum demagnetization energy (VCC = 13.5V) Figure 27. Maximum turn-off current versus inductance (for each channel) 100 A B C I (A) 10 1 0,1 1 L (mH) 10 100 A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. Doc ID 12285 Rev 7 23/31 Package and PCB thermal data VND5012AK-E 4 Package and PCB thermal data 4.1 PowerSSO-24 thermal data Figure 28. PowerSSO-24 PC board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77 mm x 86 mm,PCB thickness=1.6 mm, Cu thickness=70 m (front and back side), Copper areas: from minimum pad layout to 8 cm2). Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on) RTHj_amb(C/W) 55 50 45 40 35 30 0 2 4 6 PCB Cu heatsink area (cm^2) 24/31 Doc ID 12285 Rev 7 8 10 VND5012AK-E Package and PCB thermal data Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) ZTH ( C/ W) 100 foot print 2 cm2 8 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 Time ( s) 10 100 1000 Equation 1: pulse calculation formula Z TH = R TH +Z THtp (1 - ) where = tP/T Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-24(a) a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Doc ID 12285 Rev 7 25/31 Package and PCB thermal data Table 15. 26/31 VND5012AK-E Thermal parameter Area/island (cm2) Footprint R1 (C/W) 0.1 R2 (C/W) 0.3 R3 (C/W) 6 R4 (C/W) 7.7 R5 (C/W) 2 8 9 9 8 R6 (C/W) 28 17 10 R7 (C/W) 0.1 R8 (C/W) 0.3 C1 (W.s/C) 0.0025 C2 (W.s/C) 0.0024 C3 (W.s/C) 0.025 C4 (W.s/C) 0.75 C5 (W.s/C) 1 4 9 C6 (W.s/C) 2.2 5 17 C7 (W.s/C) 0.0025 C8 (W.s/C) 0.0024 Doc ID 12285 Rev 7 VND5012AK-E Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 PowerSSO-24 package mechanical data Figure 32. PowerSSO-24 package dimensions Table 16. PowerSSO-24 mechanical data Symbol Millimeters Min. Typ. Max. A 2.15 2.47 A2 2.15 2.40 a1 0 0.1 b 0.33 0.51 Doc ID 12285 Rev 7 27/31 Package and packing information Table 16. VND5012AK-E PowerSSO-24 mechanical data (continued) Millimeters Symbol Min. Typ. Max. c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.8 e3 8.8 G 0.1 G1 0.06 H 10.1 10.5 h 0.4 L 0.55 0.85 N 5.3 10deg X 4.1 4.7 Y 6.5 7.1 PowerSSO-24 packing information Figure 33. PowerSSO-24 tube shipment (no suffix) C B Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm. A 28/31 Doc ID 12285 Rev 7 49 1225 532 3.5 13.8 0.6 VND5012AK-E Package and packing information Figure 34. PowerSSO-24 tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) 1000 1000 330 1.5 13 20.2 24.4 100 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 All dimensions are in mm. End Start Top cover tape No components Components No components 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed Doc ID 12285 Rev 7 29/31 Revision history 6 VND5012AK-E Revision history Table 17. Document revision history Date Revision 10-Apr-2006 1 Initial release. 2 Document reformatted and restructured. Added lists of tables and figures. Added ECOPACK(R) packages information. Table 4: Absolute maximum ratings: updated EMAX entries. Table 10: Current sense (8V<VCC<16V): added dk1/k1, dk2/k2, dk3/k3, tDSENSE2H. Added Figure 5: Delay response time between rising edge of output current and rising edge of current sense (CS enabled). Updated Figure 6: IOUT/ISENSE vs IOUT. Added Figure 7: Maximum current sense ratio drift vs load current. Table 12: Electrical transient requirements (part 1/3): updated Test level values III and IV for test pulse 5b and notes. Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V). 12-Feb-2008 3 Updated Table 10: Current sense (8V<VCC<16V): - changed dk3/k3 values from 3 to 4% - changed tDSENSE2H max value from 250 s to 300 s - added IOL parameter Updated Figure 7: Maximum current sense ratio drift vs load current with new dk3/k3 value. 18-Jul-2008 4 Updated Table 4: Absolute maximum ratings: corrected typing error in VESD parameter. 01-Aug-2008 5 Updated Table 16: PowerSSO-24 mechanical data: changed a1 max. value from 0.075 mm to 0.1 mm. 26-May-2009 6 Updated Section 5.1: ECOPACK(R) packages. Updated Figure 13, Figure 15, Figure 16, Figure 17, Figure 18, Figure 20, Figure 21, Figure 22 and Figure 23. 02-Dec-2009 7 Added Table 8: Logic inputs. 02-Jul-2007 30/31 Changes Doc ID 12285 Rev 7 VND5012AK-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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