VND5012AK-E - STMicroelectronics - Datasheet.Directory

December 2009 Doc ID 12285 Rev 7 1/31

VND5012AK-E

Double channel high side driver with analog current sense

for automotive applications

Features

■General features

– Inrush current active management by

power limitation

– Very low standby current

– 3.0 V CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– In compliance with the 2002/95/EC

european directive

■Diagnostic functions

– Proportional load current sense

– High current sense precision for wide range

currents

– Current sense disable

– Thermal shutdown indication

– Very low current sense leakage

■Protections

– Undervoltage shutdown

– Overvoltage clamp

– Output stuck to Vcc detection

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss

of VCC

– Thermal shutdown

– Reverse battery protection (see Application

schematic)

– Electrostatic discharge protection

Application

■All types of resistive, inductive and capacitive

loads

Description

The VND5012AK-E a monolithic device made

using STMicroelectronics VIPower M0-5

technology. It is intended for driving resistive or

inductive loads with one side connected to

ground. Active VCC pin voltage clamp protects the

device against low energy spikes (see ISO7637

transient compatibility table). This device

integrates an analog current sense which delivers

a current proportional to the load current

(according to a known ratio) when CS_DIS is

driven low or left open. When CS_DIS is driven

high, the CURRENT SENSE pin is in a high

impedance condition. Output current limitation

protects the device in overload condition. In case

of long overload duration, the device limits the

dissipated power to safe level up to thermal

shutdown intervention. Thermal shutdown with

automatic restart allows the device to recover

normal operation as soon as fault condition

disappears.

Max supply voltage VCC 41 V

Operating voltage range VCC 4.5 to 36 V

Max on-state resistance (per ch.)

RON 12 mΩ

Current limitation (typ) ILIMH 60 A

Off-state supply current (typ.) IS2µA

(1)

1. Typical value with all loads connected.

PowerSSO-24

Table 1. Device summary

Package Order codes

Tube Tape and reel

PowerSSO-24 VND5012AK-E VND5012AKTR-E

www.st.com

         
Contents VND5012AK-E
2/31  Doc ID 12285 Rev 7
Contents
Block diagram and pin description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
2 Thermal data   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
4 Electrical characteristics curves  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
Application information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1 GND Protection network against reverse battery  . . . . . . . . . . . . . . . . . . .  21
1.1 Solution 1: resistor in the ground line (RGND only)  . . . . . . . . . . . . . . . . 21
1.2 Solution 2: diode (DGND) in the ground line  . . . . . . . . . . . . . . . . . . . . . 22
2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
4 Maximum demagnetization energy (VCC = 13.5V)   . . . . . . . . . . . . . . . . .  23
Package and PCB thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1 PowerSSO-24 thermal data  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
Package and packing information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1 ECOPACK® packages  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
2 PowerSSO-24 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . .  27
3 PowerSSO-24 packing information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

VND5012AK-E List of tables
Doc ID 12285 Rev 7 3/31
         
List of tables
Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and not connected pins  . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Switching (VCC=13V; Tj=25°C)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Current sense (8V<VCC<16V)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 14. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

         
List of figures VND5012AK-E
4/31  Doc ID 12285 Rev 7
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Delay response time between rising edge of output current and rising edge of current
sense (CS enabled)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. IOUT/ISENSE vs IOUT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Maximum current sense ratio drift vs load current  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Switching characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Undervoltage shutdown  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. ILIMH vs Tcase  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. CS_DIS high level voltage  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel on). . . . . . . . . 24
Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on)  . . . . . 25
Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. PowerSSO-24 tube shipment (no suffix)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

VND5012AK-E Block diagram and pin description

Doc ID 12285 Rev 7 5/31

1 Block diagram and pin description

Figure 1. Block diagram

Table 2. Pin function

Name Function

VCC Battery connection.

OUTPUT1,2 Power output.

GND Ground connection. Must be reverse battery protected by an external diode/resistor

network.

INPUT1,2

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output

switch state.

CURRENT

SENSE1,2

Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

LOGIC

UNDERVOLTAGE

OVERTEMP. 1

LIM

PwCLAMP 1

OUT1

GND

INPUT1

OUTPUT1

CURRENT

SENSE1

DRIVER 1

CLAMP

DSLIM

LIM

PwCLAMP 2

DRIVER 2

DSLIM

OVERTEMP. 2

OUT2

OUTPUT2

CURRENT

SENSE2

CS_DIS

K 2

INPUT2

K 1

Pwr

LIM

Pwr

LIM

Block diagram and pin description VND5012AK-E

6/31 Doc ID 12285 Rev 7

Figure 2. Configuration diagram (top view)

Table 3. Suggested connections for unused and not connected pins

Connection / pin Current Sense N.C. Output Input CS_DIS

Floating Not allowed X X X X

To ground Through 1 KΩ

resistor X Not allowed Through 10 KΩ

resistor

Through 10 KΩ

resistor

N.C.

INPUT1

GND

N.C.

INPUT2

TAB = V

CS_DIS

CURRENT SENSE1

N.C.

CURRENT SENSE2

OUTPUT2

OUTPUT1

VND5012AK-E Electrical specifications

Doc ID 12285 Rev 7 7/31

2 Electrical specifications

Figure 3. Current and voltage conventions

Note: VFn = VOUTn - VCC during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to the conditions in table below for extended

periods may affect device reliability. Refer also to the STMicroelectronics SURE Program

and other relevant quality document.

GND

SENSE2

OUTPUT1

OUT1

CURRENT I

SENSE1

INPUT1

IN1

IN2

OUT2

GND

CS_DIS

CSD

INPUT2

IN2

IN1

SENSE1

OUTPUT2

OUT2

CURRENT I

SENSE2

SENSE1

OUT1

(*)

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage 41 V

-VCC Reverse DC supply voltage 0.3 V

-IGND DC reverse ground pin current 200 mA

IOUT DC output current Internally limited A

-IOUT Reverse DC output current -30 A

IIN DC Input current -1 to 10 mA

ICSD DC current sense disable input current -1 to 10 mA

-ICSENSE DC reverse CS pin current 200 mA

VCSENSE Current sense maximum voltage VCC-41

+VCC

Electrical specifications VND5012AK-E

8/31 Doc ID 12285 Rev 7

2.2 Thermal data

EMAX

Maximum switching energy

(L=1.25 mH; RL=0 Ω; Vbat=13.5 V; Tjstart=150 °C;

IOUT = IlimL(Typ.))

508 mJ

VESD

Electrostatic discharge

(Human body model: R= 1.5 KΩ; C= 100 pF)

– INPUT

– CURRENT SENSE

–CS_DIS

–OUTPUT

–V

4000

2000

4000

5000

VESD Charge device model (CDM-AEC-Q100-011) 750 V

TjJunction operating temperature -40 to 150 °C

Tstg Storage temperature -55 to 150 °C

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Table 5. Thermal data

Symbol Parameter Max value Unit

Rthj-case

Thermal resistance junction-case (max) (With one

channel on) 0.4 °C/W

Rthj-amb Thermal resistance junction-ambient (max) See Figure 29 °C/W

VND5012AK-E Electrical specifications

Doc ID 12285 Rev 7 9/31

2.3 Electrical characteristics

8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage 4.5 13 36 V

VUSD Undervoltage shutdown 3.5 4.5 V

VUSDhyst

Undervoltage shutdown

hysteresis 0.5 V

RON On-state resistance(2)

IOUT=5A; Tj=25°C

IOUT=5A; Tj=150°C

IOUT=5A; VCC=5V; Tj=25°C

mΩ

Vclamp Clamp voltage IS=20mA 41 46 52 V

ISSupply current

Off-state; VCC=13V; Tj=25°C;

VIN=VOUT=VSENSE=VCSD=0V

On-state; VCC=13V; VIN=5V;

IOUT=0A

2(1)

1. PowerMOS leakage included.

5(1)

µA

IL(off)

Off-state output

current(2)

VIN=VOUT=0V; VCC=13V; Tj=25°C

VIN=VOUT=0V; VCC=13V;

Tj=125°C

0.01 3

5µA

Output VCC diode

voltage(2)

2. For each channel.

-IOUT= 8A; Tj=150°C 0.7 V

Table 7. Switching (VCC=13V; Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time RL= 2.6 Ω (see Figure 8)20µs

td(off) Turn-off delay time RL= 2.6 Ω (see Figure 8)35µs

OUT

/dt

(on)

Turn-on voltage slope RL= 2.6 Ω See Figure 21 V/µs

OUT

/dt

(off)

Turn-off voltage slope RL= 2.6 Ω See Figure 22 V/µs

WON

Switching energy losses

during twon

RL= 2.6 Ω (see Figure 8)1.1mJ

WOFF

Switching energy losses

during twoff

RL= 2.6 Ω (see Figure 8)0.7mJ

Electrical specifications VND5012AK-E

10/31 Doc ID 12285 Rev 7

Table 8. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.9 V

IIL Low level input current VIN=0.9 V 1 µA

VIH Input high level voltage 2.1 V

IIH High level input current VIN=2.1 V 10 µA

VI(hyst) Input hysteresis voltage 0.25 V

VICL Input clamp voltage IIN=1 mA

IIN=-1 mA

5.5

-0.7

VCSDL CS_DIS low level voltage 0.9 V

ICSDL Low level CS_DIS current VCSD=0.9 V 1 µA

VCSDH CS_DIS high level voltage 2.1 V

ICSDH High level CS_DIS current VCSD=2.1 V 10 µA

VCSD(hyst)

CS_DIS hysteresis

voltage 0.25 V

VCSCL CS_DIS clamp voltage ICSD=1 mA

ICSD=-1 mA

5.5

-0.7

Table 9. Protections and diagnostics (1)

1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

diagnostic signals must be used together with a proper software strategy. If the device is subjected to

abnormal conditions, this software must limit the duration and number of activation cycles.

Symbol Parameter Test conditions Min. Typ. Max. Unit

IlimH DC short circuit current VCC=13 V

5V<V

CC<36 V

42 60 84

IlimL

Short circuit current

during thermal cycling VCC=13 V TR<Tj<TTSD 24 A

TTSD Shutdown temperature 150 175 200 °C

TRReset temperature

+ 1 T

+ 5

°C

TRS

Thermal reset of

STATUS 135 °C

THYST

Thermal hysteresis

TSD

-T

)

7°C

VDEMAG

Turn-off output voltage

clamp

IOUT=2 A; VIN=0;

L=6 mH

-41 V

-46 V

-52

VON

Output voltage drop

limitation

IOUT= 0.4 A;

Tj= -40 °C...+150 °C

(see Figure 26)

25 mV

VND5012AK-E Electrical specifications

Doc ID 12285 Rev 7 11/31

Table 10. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

K0IOUT/ISENSE

IOUT= 0.25 A; VSENSE=0.5 V;

VCSD=0 V;

Tj= -40°C...150°C 2780 5580 8390

K1IOUT/ISENSE

IOUT= 5 A; VSENSE=0.5 V; VCSD=0 V;

Tj= -40°C...150°C

IOUT=5 A; VSENSE=0.5 V; VCSD=0 V;

Tj= 25 °C...150 °C

3590

4110

5100

6630

6090

1(1)

Current sense ratio

drift

IOUT= 5 A; VSENSE= 0.5 V; VCSD=0 V;

TJ= -40°C to 150°C -8 +8 %

K2IOUT/ISENSE

IOUT= 10 A; VSENSE=4 V; VCSD=0 V;

Tj= -40°C...150°C

IOUT= 10 A; VSENSE=4 V; VCSD=0 V;

Tj= 25 °C...150 °C

4400

4600

5090

5930

5590

2(1)

Current sense ratio

drift

IOUT= 10 A; VSENSE= 4 V; VCSD=0 V;

TJ= -40°C to 150°C -5 +5 %

K3IOUT/ISENSE

IOUT= 25 A; VSENSE=4 V; VCSD=0 V;

Tj= -40°C...150°C

IOUT= 25 A; VSENSE=4 V; VCSD=0 V;

Tj= 25 °C...150 °C

4820

4860

5060

5420

5250

3(1)

Current sense ratio

drift

IOUT= 25 A; VSENSE= 4 V; VCSD=0 V;

TJ= -40°C to 150°C -4 +4 %

ISENSE0

Analog sense

leakage current

IOUT=0 A; VSENSE=0 V;

VCSD=5 V; VIN=0 V; Tj=-40 °C...150 °C

VCSD=0 V; VIN=5 V; Tj=-40 °C...150 °C

IOUT=2 A; VSENSE=0 V;

VCSD=5 V; VIN=5 V; Tj=-40 °C...150 °C

µA

IOL

Open-load on-state

current detection

threshold

VIN = 5 V, ISENSE= 5 µA 10 45 mA

VSENSE

Max analog sense

output voltage IOUT=15 A; VCSD=0 V 5 V

VSENSEH

Analog sense

output voltage in

over temperature

condition

VCC= 13 V; RSENSE= 3.9 KΩ9V

ISENSEH

Analog sense

output current in

over temperature

condition

VCC= 13 V; VSENSE= 5 V 8 mA

DSENSE1H

Delay response

time from falling

edge of CS_DIS pin

VSENSE<4 V, 1.5 A<Iout<25 A

ISENSE= 90 % of ISENSE max

(see Figure 4)

50 100 µs

Electrical specifications VND5012AK-E

12/31 Doc ID 12285 Rev 7

Figure 4. Current sense delay characteristics

DSENSE1L

Delay response

time from rising

edge of CS_DIS pin

VSENSE<4V, 1.5A<Iout<25A

ISENSE= 10% of ISENSE max

(see Figure 4)

520µs

DSENSE2H

Delay response

time from rising

edge of INPUT pin

VSENSE<4 V, 1.5 A<Iout<25 A

ISENSE= 90 % of ISENSE max

(see Figure 4)

270 400 µs

DSENSE2H

Delay response

time between rising

edge of output

current and rising

edge of current

sense

VSENSE<4 V,

ISENSE =90% of I

SENSEMAX,

IOUT =90% of I

OUTMAX

IOUTMAX= 5 A (see Figure 5)

300 µs

DSENSE2L

Delay response

time from falling

edge of INPUT pin

VSENSE<4 V, 1.5 A<Iout<25 A

ISENSE=10 % of ISENSE max

(see Figure 4)

100 250 µs

1. Parameter guaranteed by design, it is not tested.

Table 10. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

SENSE CURRENT

INPUT

LOAD CURRENT

CS_DIS

tDSENSE2H tDSENSE2L

tDSENSE1L tDSENSE1H

VND5012AK-E Electrical specifications

Doc ID 12285 Rev 7 13/31

Figure 5. Delay response time between rising edge of output current and rising

edge of current sense (CS enabled)

VIN

IOUT

ISENSE

IOUTMAX

ISENSEMAX

90% ISENSEMAX

90% IOUTMAX

ΔtDSENSE2H

Electrical specifications VND5012AK-E

14/31 Doc ID 12285 Rev 7

Figure 6. IOUT/ISENSE vs IOUT

Figure 7. Maximum current sense ratio drift vs load current

Note: Parameter guaranteed by design; it is not tested.

3000

3500

4000

4500

5000

5500

6000

6500

7000

510152025

max Tj = -40°C to 150°C

max Tj= 25°C to 150°C

typical value

min Tj= 25°C to 150°C

min Tj= -40°C to 150°C

-15

-10

-5

5 10152025

IOUT (A)

dk/k(%)

VND5012AK-E Electrical specifications

Doc ID 12285 Rev 7 15/31

Figure 8. Switching characteristics

Table 11. Truth table

Conditions Input Output Sense (VCSD=0V)(1)

1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents

and external circuit.

Normal operation L

Nominal

Over temperature L

VSENSEH

Undervoltage L

Short circuit to GND

(Rsc ≤ 10 mΩ)

0 if Tj < TTSD

VSENSEH if Tj > TTSD

Short circuit to VCC

< Nominal

Negative output voltage

clamp LL 0

OUT

/dt

(on)

80%

10% t

OUT

/dt

(off)

d(off)

d(on)

INPUT

90%

Won

Woff

Electrical specifications VND5012AK-E

16/31 Doc ID 12285 Rev 7

Figure 9. Output voltage drop limitation

Table 12. Electrical transient requirements (part 1/3)

ISO 7637-2:

2004(E)

test pulse

Test levels(1) Number of

pulses or

test times

Burst cycle/pulse

repetition time Delays and

impedance

III IV Min. Max.

1 -75V -100V 5000

pulses 0.5 s 5 s 2 ms, 10 Ω

2a +37V +50V 5000

pulses 0.2 s 5 s 50 µs, 2 Ω

3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4-6V-7V1 pulse 100 ms, 0.01

5b(2) +65V +87V 1 pulse 400 ms, 2 Ω

Table 13. Electrical transient requirements (part 2/3)

ISO 7637-2:

2004(E)

test pulse

Test level results (1)

1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5 b.

III IV

1C C

2C C

3a C C

3b C C

4C C

5(2)

2. Valid in case of external load dump clamp: 40 V maximum referred to ground.

Von

Iout

Vcc-Vout

Tj=150oCTj=25oC

Tj=-40oC

Von/Ron(T)

VND5012AK-E Electrical specifications

Doc ID 12285 Rev 7 17/31

Figure 10. Waveforms

Table 14. Electrical transient requirements (part 3/3)

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.

EOne or more functions of the device are not performed as designed after exposure to

disturbance and cannot be returned to proper operation without replacing the device.

SENSE CURRENT

INPUT

NORMAL OPERATION

UNDERVOLTAGE

USD

USDhyst

INPUT

SENSE CURRENT

LOAD CURRENT

OVERLOAD OPERATION

INPUT

SENSE CURRENT

TSD

LOAD CURRENT

INPUT

LOAD VOLTAGE

SENSE CURRENT

LOAD CURRENT

<Nominal <Nominal

SHORT TO V

CS_DIS

LIMH

LIML

SENSEH

thermal cycling

power

limitation

current

limitation

SHORTED LOAD NORMAL LOAD

Electrical specifications VND5012AK-E

18/31 Doc ID 12285 Rev 7

2.4 Electrical characteristics curves

Figure 11. Off-state output current Figure 12. High level input current

Figure 13. Input clamp voltage Figure 14. Input high level

Figure 15. Input low level Figure 16. Input hysteresis voltage

VND5012AK-E Electrical specifications

Doc ID 12285 Rev 7 19/31

Figure 17. On-state resistance vs Tcase Figure 18. On-state resistance vs VCC

Figure 19. Undervoltage shutdown Figure 20. ILIMH vs Tcase

Figure 21. Turn-on voltage slope Figure 22. Turn-off voltage slope

Electrical specifications VND5012AK-E

20/31 Doc ID 12285 Rev 7

Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage

Figure 25. CS_DIS low level voltage

VND5012AK-E Application information

Doc ID 12285 Rev 7 21/31

3 Application information

Figure 26. Application schematic

Note: Channel 2 has the same internal circuit as channel 1.

3.1 GND Protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (RGND only)

This can be used with any type of load.

The following is an indication on how to dimension the RGND resistor.

1. RGND ≤ 600 mV / (IS(on)max).

2. RGND ≥ (−VCC) / (-IGND)

where -IGND is the DC reverse ground pin current and can be found in the absolute

maximum rating section of the device datasheet.

Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:

PD= (-VCC)2/RGND

This resistor can be shared amongst several different HSDs. Please note that the value of

this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the

maximum on-state currents of the different devices.

Please note that if the microprocessor ground is not shared by the device ground then the

RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output

values. This shift will vary depending on how many devices are ON in the case of several

high side drivers sharing the same RGND.

VCC

GND

OUTPUT

DGND

RGND

Dld

+5V

VGND

CS_DIS

INPUT

Rprot

CURRENT SENSE

RSENSE

Rprot

Cext

Application information VND5012AK-E

22/31 Doc ID 12285 Rev 7

If the calculated power dissipation leads to a large resistor or several devices have to share

the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2: diode (DGND) in the ground line

A resistor (RGND=1 kΩ) should be inserted in parallel to DGND if the device drives an

inductive load.

This small signal diode can be safely shared amongst several different HSDs. Also in this

case, the presence of the ground network will produce a shift (≈600mV) in the input

threshold and in the status output values if the microprocessor ground is not common to the

device ground. This shift will not vary if more than one HSD shares the same diode/resistor

network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the

VCC max DC rating. The same applies if the device is subject to transients on the VCC line

that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,

the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to

prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the leakage current of µC and the

current required by the HSD I/Os (input levels compatibility) with the latch-up limit of µC

I/Os.

-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax

Calculation example:

For VCCpeak= - 100 V and Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V

5kΩ ≤ Rprot ≤ 180 kΩ.

Recommended values: Rprot =10 kΩ, CEXT=10 nF.

VND5012AK-E Application information

Doc ID 12285 Rev 7 23/31

3.4 Maximum demagnetization energy (VCC = 13.5V)

Figure 27. Maximum turn-off current versus inductance (for each channel)

Note: Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each

demagnetization) of every pulse must not exceed the temperature specified above for

curves A and B.

100

0,1110100L (mH)

I (A)

C: Tjstart = 125°C repetitive pulse

A: Tjstart = 150°C single pulse

B: Tjstart = 100°C repetitive pulse

Demagnetization Demagnetization Demagnetization

VIN, IL

Package and PCB thermal data VND5012AK-E

24/31 Doc ID 12285 Rev 7

4 Package and PCB thermal data

4.1 PowerSSO-24 thermal data

Figure 28. PowerSSO-24 PC board

Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4

area= 77 mm x 86 mm,PCB thickness=1.6 mm, Cu thickness=70 µm (front and back side),

Copper areas: from minimum pad layout to 8 cm2).

Figure 29. Rthj-amb vs PCB copper area in open box free air condition (one channel

on)

0246810

RTHj_amb(°C/W)

PCB Cu heatsink area (cm^2)

VND5012AK-E Package and PCB thermal data

Doc ID 12285 Rev 7 25/31

Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one

channel on)

Equation 1: pulse calculation formula

where δ = tP/T

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-24(a)

a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded

protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

0,1

100

0,0001 0,001 0,01 0,1 1 10 100 1000

Time ( s)

ZTH (°C/ W)

foot print

2 cm2

8 cm2

ZTHδRTH δZTHtp 1δ–()+⋅=

Package and PCB thermal data VND5012AK-E

26/31 Doc ID 12285 Rev 7

Table 15. Thermal parameter

Area/island (cm2)Footprint28

R1 (°C/W) 0.1

R2 (°C/W) 0.3

R3 (°C/W) 6

R4 (°C/W) 7.7

R5 (°C/W) 9 9 8

R6 (°C/W) 28 17 10

R7 (°C/W) 0.1

R8 (°C/W) 0.3

C1 (W.s/°C) 0.0025

C2 (W.s/°C) 0.0024

C3 (W.s/°C) 0.025

C4 (W.s/°C) 0.75

C5 (W.s/°C) 1 4 9

C6 (W.s/°C) 2.2 5 17

C7 (W.s/°C) 0.0025

C8 (W.s/°C) 0.0024

VND5012AK-E Package and packing information

Doc ID 12285 Rev 7 27/31

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

5.2 PowerSSO-24 package mechanical data

Figure 32. PowerSSO-24 package dimensions

Table 16. PowerSSO-24 mechanical data

Symbol

Millimeters

Min. Typ. Max.

A 2.15 2.47

A2 2.15 2.40

a1 0 0.1

b 0.33 0.51

Package and packing information VND5012AK-E

28/31 Doc ID 12285 Rev 7

5.3 PowerSSO-24 packing information

Figure 33. PowerSSO-24 tube shipment (no suffix)

c 0.23 0.32

D 10.10 10.50

E7.4 7.6

e0.8

e3 8.8

G0.1

G1 0.06

H 10.1 10.5

h0.4

L 0.55 0.85

N 10deg

X4.1 4.7

Y6.5 7.1

Table 16. PowerSSO-24 mechanical data (continued)

Symbol

Millimeters

Min. Typ. Max.

All dimensions are in mm.

Base Q.ty 49

Bulk Q.ty 1225

Tube length (± 0.5) 532

A3.5

B13.8

C (± 0.1) 0.6

VND5012AK-E Package and packing information

Doc ID 12285 Rev 7 29/31

Figure 34. PowerSSO-24 tape and reel shipment (suffix “TR”)

Base Q.ty 1000

Bulk Q.ty 1000

A (max) 330

B (min) 1.5

C (± 0.2) 13

F20.2

G (+ 2 / -0) 24.4

N (min) 100

Reel dimensions

Tape dimensions

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

All dimensions are in mm.

Tape width W 24

Tape Hole Spacing P0 (± 0.1) 4

Component Spacing P 12

Hole Diameter D (± 0.05) 1.55

Hole Diameter D1 (min) 1.5

Hole Position F (± 0.1) 11.5

Compartment Depth K (max) 2.85

Hole Spacing P1 (± 0.1) 2

Top

cover

tape

End

Start

No componentsNo components Components

500mm min

Empty components pockets

saled with cover tape.

User direction of feed

         
Revision history VND5012AK-E
30/31  Doc ID 12285 Rev 7
6 Revision history
         
Table 17. Document revision history
Date Revision Changes
10-Apr-2006 1Initial release.
02-Jul-2007 2
Document reformatted and restructured.
Added lists of tables and figures.
Added ECOPACK® packages information.
Table 4: Absolute maximum ratings: updated EMAX entries.
Table 10: Current sense (8V<VCC<16V): added dk1/k1, dk2/k2, dk3/k3, 
tDSENSE2H.
Added Figure 5: Delay response time between rising edge of output 
current and rising edge of current sense (CS enabled). 
Updated Figure 6: IOUT/ISENSE vs IOUT.
Added Figure 7: Maximum current sense ratio drift vs load current.
Table 12: Electrical transient requirements (part 1/3): updated Test 
level values III and IV for test pulse 5b and notes.
Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V).
12-Feb-2008 3
Updated Table 10: Current sense (8V<VCC<16V):
– changed dk3/k3 values from ± 3 to ± 4%
– changed tDSENSE2H max value from 250 µs to 300 µs
–  added IOL parameter
Updated Figure 7: Maximum current sense ratio drift vs load current 
with new dk3/k3 value.
18-Jul-2008 4 Updated Table 4: Absolute maximum ratings: corrected typing error in 
VESD parameter.
01-Aug-2008 5 Updated Table 16: PowerSSO-24 mechanical data: changed a1 max. 
value from 0.075 mm to 0.1 mm.
26-May-2009 6
Updated Section 5.1: ECOPACK® packages.
Updated Figure 13, Figure 15, Figure 16, Figure 17, Figure 18, 
Figure 20, Figure 21, Figure 22 and Figure 23.
02-Dec-2009 7 Added Table 8: Logic inputs.

VND5012AK-E

Doc ID 12285 Rev 7 31/31

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