6AT93C46/56/66 0172U–SEEPR–8/03
Functional
Description The A T93C4 6/56 /66 is accessed via a simple and v ersatile 3-wire serial commun ication
interface. Device operation is controlled by seven instructions issued by the host pro-
cessor. A valid instruction starts w ith a rising ed ge of CS and cons ist s of a Sta rt Bit
(logic “1”) followed by the appropriate Op Code and the desired memory Address
location.
REA D (READ): The Read (READ ) instruction cont ains the Ad dress code for the m em-
ory location to be read. After the inst ruction and address are decoded, data from the
selec ted m em ory location i s avai labl e at the serial output pi n DO. O ut put data changes
are synchron ized with the rising edges of serial clock SK. It should be noted that a
dumm y bit (logic “0”) prece des the 8- or 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Era se/W rite D isable (EWD S) stat e when pow er is first appl ied. An E rase/ Write E nabl e
(EWEN) instruc tion must be executed f irst before any program ming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruc tion is executed or VCC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY /BUSY
status of the part if CS i s brought high after being kept low for a mini mum of 250 ns (tCS).
A logic “1” at pi n DO ind icate s th at the select ed mem ory l ocation has been eras ed, and
the part is ready for another instruction.
WRI TE (WRITE): The Write (W RITE) instruct ion contain s the 8 or 16 b its of d ata to be
written into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (tCS). A logic “0” at DO indica tes that progra mming is still in progress . A lo gic
“1” indicates that the memory location at the specified address has been written with the
data pattern contain ed in the inst ruc tion and the part is ready f or further instruct ions. A
READY/ BUSY status can not be ob tained if the CS is brought high after the end of
the self-timed programm ing cycle, tWP.
ERASE AL L (ERAL): The Erase A ll (E RA L) instruc tion prog rams every bit i n the m em -
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the READY/BUSY status of the part if CS is brought high after being kept l ow for
a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE AL L (WRAL): The Write All (WRA L) instruction progra ms all mem ory locations
with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY
status of the part if CS i s brought high after being kept low for a mini mum of 250 ns (tCS).
The WRA L instruction is valid only at VCC = 5.0V ± 10% .
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations . The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.