AT93C46-10SE-2.7 - Atmel Corporation

Features

•Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 5.5V)

•User-selectable Internal O rganization

– 1K: 128 x 8 or 64 x 16

– 2K: 256 x 8 or 128 x 16

– 4K: 512 x 8 or 256 x 16

•3-w ire Serial Interface

•2 MHz Clock Rate (5V)

•Self-timed Wri te Cycle (10 ms max)

•High Reliabilit y

– Endurance: 1 Million Wr it e Cycles

– Data Retention: 100 Years

•A utomotive Grade, Exte nded Temperature and Lead-Fre e Devices Av ailable

•8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP

and 8-ball dBGA2™ Packages

Description

The AT 93C 46/5 6/66 pr ovides 10 24/20 48/4 096 bi ts of se rial electr ical ly erasable p ro-

gramm able read only m emo ry (E EP ROM) org anize d as 64/ 128/2 56 wo rds of 16 b its

each, when the ORG pi n is co nnected to VCC and 128 /256/512 words of 8 bits each

when it is tied to ground. The device is optimized fo r use in many industri al and com-

mercial applications where low power and low voltage operations ar e essential. The

AT93C46/56 /66 is availabl e in sp ace-saving 8-lead P DI P, 8-lead J ED EC SO IC, 8-lead

EIAJ SOIC, 8-lead MAP, 8-lead TSSOP and 8-ball dBGA2™ packages.

3-wire Se rial

EEPROMs

1K (128 x 8 or 64 x 16)

2K (256 x 8 or 128 x 16)

4K (512 x 8 or 256 x 16)

AT93C46

AT93C56(1)

AT93C66(2)

Note: 1. This device is not recom-

mended for new designs.

Please refer to AT93C56A.

2. This device is not recom-

mended for new designs.

Please refer to AT93C66A.

Rev. 0172U–SEEPR–8/03

Pin Configurati ons

Pin Name Function

CS Chip Select

SK Seria l Data Cloc k

DI Seria l Dat a Input

DO Seria l Data Output

GND Ground

VCC Power Supply

ORG Internal Organization

DC Don’t Connect

8-l ead PDIP

VCC

ORG

GND

8-lead SOI C

Rotated (R)

(1K JEDEC Only)

VCC

ORG

GND

8-lead SOIC

VCC

ORG

GND

8-le ad TSSO P

VCC

ORG

GND

8-lead MAP

Bottom View

VCC

ORG

GND

8-ball dBGA2

Bottom View

VCC

ORG

GND

2AT93C46/56/66 0172U–SEEPR–8/03

The AT9 3C46/ 56/66 is ena bled throu gh the Chip Select p in (CS), an d accesse d via a 3-wire serial interface consistin g of

Data Input (DI), Dat a Ou tput (DO ), and S hift Clock (SK). Upon receiving a RE AD instruction at DI , the address is decod ed

and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely s elf-timed and no sepa rate

ERASE cycle is required bef ore WRITE. The WRITE cycle is only enabled when the part is in the ERASE/WRITE ENABLE

state. When CS is brought “high” following the initiation of a W RITE cycle, the DO pin outputs the READY/BUSY status of

the part.

The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.

Block Diagram

Note: 1. When t he OR G pin is connected to VCC, the x 16 organization is selected. When it is con nected to ground , the x 8 organiza-

tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the

internal 1 Meg ohm pullup, then the x 16 organi zation is selected. The feature is not available on the 1.8V devices.

2. For t he AT93C46, if x 16 organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends using

the AT93C46A device. For more details, see the AT93C46A datashee t.

Absolute Ma ximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absol ute

Maxim um Ratin gs” may cause permanent dam -

age to the de vice . This is a st ress rati ng only and

functional op eration of the de vice a t thes e or an y

other conditions beyond those indi cated in the

operational sections of this specifi cation is not

implied. Exposure to absol ute maxi m um rating

condit ions for extended periods may affect

device reliability

Storage Temperature.................... ................. -65°C to +150°C

Vol tage on An y Pin

wit h R e spe ct to Gr o und ........... ......... .......... .......-1.0V to +7.0 V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT93C46/56/66

0172U–SEEPR–8/03

Note: 1. This paramete r is characteriz ed and is not 100% tested.

Note: 1. VIL min and VIH max are reference only and ar e not tested.

Pin C apacitance(1)

Applicable over recomm ended operating range from TA = 25°C, f = 1 .0 MHz, VCC = +5.0V (unless otherwise noted).

Symbol Test Conditions Max Units Conditi ons

COUT Output Capacitance (DO) 5 pF VOUT = 0V

CIN Input Capacitance (CS , SK, DI) 5 pF VIN = 0 V

DC Characteristics

Applicable over recomm ended operating range from: TAI = -4 0°C to +85°C, VCC = +1.8V to +5.5V,

TAE = -40°C to +125°C, VCC = +1. 8V to +5.5V (unless otherwise noted).

Symbol P arameter Test Conditi on Min Typ Max Unit

VCC1 Supply Vol tage 1.8 5.5 V

VCC2 Supply Vol tage 2.7 5.5 V

VCC3 Supply Vol tage 4.5 5.5 V

ICC Supply Current VCC = 5.0V READ at 1.0 MHz 0.5 2.0 mA

WRITE at 1.0 MHz 0.5 2.0 mA

ISB1 Standby Current VCC = 1.8V CS = 0V 0 0.1 µA

ISB2 Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA

ISB3 Standby Current VCC = 5.0V CS = 0V 17 30 µA

IIL Input Leakage VIN = 0V to VCC 0.1 1.0 µA

IOL Output Leakage VIN = 0V to VCC 0.1 1.0 µA

VIL1(1)

VIH1(1) Input Low Voltage

Input High Vol tage 2.7V ≤ VCC ≤ 5.5 V -0.6

2.0 0.8

VCC + 1 V

VIL2(1)

VIH2(1) Input Low Voltage

Input High Vol tage 1.8V ≤ VCC ≤ 2.7V -0.6

VCC x 0.7 VCC x 0.3

VCC + 1 V

VOL1

VOH1

Output Lo w Vo ltage

Output High Voltage 2.7V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V

IOH = -0.4 mA 2.4 V

VOL2

VOH2

Output Lo w Vo ltage

Output High Voltage 1.8V ≤ VCC ≤ 2.7V IOL = 0.15 mA 0.2 V

IOH = -100 µA VCC - 0.2 V

4AT93C46/56/66 0172U–SEEPR–8/03

Note: 1. This paramete r is characteriz ed and is not 100% tested.

AC Characteristics

Applicable over recomm ended operating range from TAI = -4 0°C to + 85°C, TAE = -40°C to + 1 2 5 °C, VCC = As Specified,

CL = 1 TTL Gate and 100 pF (unless otherwise noted).

Symbol Parameter Te st Condition Min Ty p Max Units

fSK SK Clock

Frequency

4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

0.25 MHz

tSKH SK High Time 4.5V ≤ VCC ≤ 5. 5 V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

250

1000 ns

tSKL SK Low Time 4.5V ≤ VCC ≤ 5.5 V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

250

1000 ns

tCS Minimum CS

Low Tim e

4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

250

1000 ns

tCSS CS Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

200 ns

tDIS DI Setup Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

100

400 ns

tCSH CS Hold Time Relative to SK 0 ns

tDIH DI Hold Time Relative to SK 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

100

400 ns

tPD1 Output Delay to ‘1’ AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

250

1000 ns

tPD0 Output Delay to ‘0’ AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

250

1000 ns

tSV CS to Status Valid AC Test 4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

250

1000 ns

tDF CS to DO in High

Impedance AC Test

CS = VIL

4.5V ≤ VCC ≤ 5.5V

2.7V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V

100

400 ns

tWP Write Cycle Time 10 ms

4.5V ≤ VCC ≤ 5.5V 3 ms

Endurance(1) 5.0V, 25°C, Page Mo de 1M W ri t e Cycl es

AT93C46/56/66

0172U–SEEPR–8/03

Note: Th e X’s in the address field r epresent don’t care values and m ust be clock ed.

Notes: 1. This device i s not re com m ended f or new designs. Please refer to AT93C56A.

2. This device i s not re com m ended f or new designs. Please refer to AT93C66A.

3. The X’s in the address fi eld represent don’t care values and must be cl ocked .

Instruction Set for the AT93C46

Instruction SB Op

Code

Address Data

Commentsx 8 x 16 x 8 x 16

READ 1 10 A6 - A0A5 - A0Reads data stored in memory, at

specif ied address.

EWEN 1 00 11XXXXX 11XXXX Write enable must precede all

programming modes .

ERASE 1 11 A6 - A0A5 - A 0Erase memory location An - A0.

WRITE 1 01 A6 - A0A5 - A0D7 - D0D15 - D0Writes memo ry locat ion An - A0.

ERAL 1 00 10XXXXX 10XXXX Erases all memory locations. Valid

only at VCC = 4.5V to 5.5V.

WRAL 1 00 01XXXXX 01XXXX D7 - D0D15 - D0Writ es all memory locati ons. Val id

only at VCC = 4.5V to 5.5V.

EWDS 1 00 00XXXXX 00XXXX Disab les all pro grammi ng instructions .

Instruction Set for the AT93C56(1) and AT93C66(2)

Instruction SB Op

Code

Address(3) Data

Commentsx 8 x 16 x 8 x 16

READ 1 10 A8 - A0A7 - A0Rea ds data stored in memory, at

specified address.

EWEN 1 00 11XXXXXXX 11XXXXXX Write enable m ust precede all

programming modes .

ERASE 1 11 A8 - A 0A7 - A0Erase memory location An - A0.

WRITE 1 01 A8 - A0A7 - A0D7 - D0D15 - D0Writes memory location An - A0.

ERAL 1 00 10XXXXXXX 10XXXXXX Erases all memory locations. Valid

only at VCC = 4.5V to 5.5V.

WRAL 1 00 01XXXXXXX 01XXXXXX D7 - D0D15 - D0

Wr it e s a ll me m o r y lo catio n s. Va lid

only at V CC = 5.0V ±10% and Disable

Regist e r cleared.

EWDS 1 00 00XXXXXX X 00XXXXXX Disab les al l prog ramming i nstruct ions .

6AT93C46/56/66 0172U–SEEPR–8/03

Functional

Description The A T93C4 6/56 /66 is accessed via a simple and v ersatile 3-wire serial commun ication

interface. Device operation is controlled by seven instructions issued by the host pro-

cessor. A valid instruction starts w ith a rising ed ge of CS and cons ist s of a Sta rt Bit

(logic “1”) followed by the appropriate Op Code and the desired memory Address

location.

REA D (READ): The Read (READ ) instruction cont ains the Ad dress code for the m em-

ory location to be read. After the inst ruction and address are decoded, data from the

selec ted m em ory location i s avai labl e at the serial output pi n DO. O ut put data changes

are synchron ized with the rising edges of serial clock SK. It should be noted that a

dumm y bit (logic “0”) prece des the 8- or 16-bit data output string.

ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the

Era se/W rite D isable (EWD S) stat e when pow er is first appl ied. An E rase/ Write E nabl e

(EWEN) instruc tion must be executed f irst before any program ming instructions can be

carried out. Please note that once in the Erase/Write Enable state, programming

remains enabled until an Erase/Write Disable (EWDS) instruc tion is executed or VCC

power is removed from the part.

ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified

memory location to the logical “1” state. The self-timed erase cycle starts once the

ERASE instruction and address are decoded. The DO pin outputs the READY /BUSY

status of the part if CS i s brought high after being kept low for a mini mum of 250 ns (tCS).

A logic “1” at pi n DO ind icate s th at the select ed mem ory l ocation has been eras ed, and

the part is ready for another instruction.

WRI TE (WRITE): The Write (W RITE) instruct ion contain s the 8 or 16 b its of d ata to be

written into the specified memory location. The self-timed programming cycle, tWP, starts

after the last bit of data is received at serial data input pin DI. The DO pin outputs the

READY/BUSY status of the part if CS is brought high after being kept low for a minimum

of 250 ns (tCS). A logic “0” at DO indica tes that progra mming is still in progress . A lo gic

“1” indicates that the memory location at the specified address has been written with the

data pattern contain ed in the inst ruc tion and the part is ready f or further instruct ions. A

READY/ BUSY status can not be ob tained if the CS is brought high after the end of

the self-timed programm ing cycle, tWP.

ERASE AL L (ERAL): The Erase A ll (E RA L) instruc tion prog rams every bit i n the m em -

ory array to the logic “1” state and is primarily used for testing purposes. The DO pin

outputs the READY/BUSY status of the part if CS is brought high after being kept l ow for

a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.

WRITE AL L (WRAL): The Write All (WRA L) instruction progra ms all mem ory locations

with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY

status of the part if CS i s brought high after being kept low for a mini mum of 250 ns (tCS).

The WRA L instruction is valid only at VCC = 5.0V ± 10% .

ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the

Erase/Write Disable (EWDS) instruction disables all programming modes and should be

executed after all programming operations . The operation of the READ instruction is

independent of both the EWEN and EWDS instructions and can be executed at any

time.

AT93C46/56/66

0172U–SEEPR–8/03

Timing Diagrams

Synchronous Data Timing

Note: 1. This is the mini m um SK period .

Notes: 1. This device i s not r ecom m ended f or new des igns. Please refer to AT93C56A.

2. This device i s not r ecom m ended for new des igns. Ple ase refer to AT93C66A.

3. A8 is a DON’T CARE val ue, but the extra cloc k is require d.

4. A7 is a DON’T CARE val ue, but the extra cloc k is require d.

READ Timing

Organization Key for Timing Diagrams

I/O

AT93C46 (1K) AT93C56 (2K)(1) AT93C66 (4K)(2)

x 8 x 16 x 8 x 16 x 8 x 16

ANA6A5A8(3) A7(4) A8A7

DND7D15 D7D15 D7D15

High Impedance

tCS

8AT93C46/56/66 0172U–SEEPR–8/03

EWE N Timing

EWDS Timing

WRITE Timing

11 ...

001

tCS

CS tCS

DI 1 0 000 ...

CS tCS

tWP

ANDN

0A0D0

... ...

DO HIGH IMPEDANCE BUSY READY

AT93C46/56/66

0172U–SEEPR–8/03

WRAL Timing(1)

Note: 1. Valid only at VCC = 4.5V to 5.5V.

ERASE Timing

DO HIGH IMPEDANCE BUSY

READY

1 0 0 1 ... DN

tCS

tWP

... D00

1 1 ...1

DI AN

tCS

tSV tDF

tWP

AN-1 AN-2 A0

CHECK

STATUS STANDBY

READY

BUSY

DO HIGH IMPEDANCE HIGH IMPEDANCE

10 AT93C46/56/66 0172U–SEEPR–8/03

ERAL Timing (1)

Note: 1. Valid only at VCC = 4.5V to 5.5V.

DI 1 1000

HIGH IMPEDANCE HIGH IMPEDANCE

READY

BUSY

CHECK

STATUS STANDBY

tWP

tCS

tSV tDF

AT93C46/56/66

0172U–SEEPR–8/03

Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance va lues in the AC and DC characteristics tab le.

AT93C46 Ordering Information

Order ing Code Package Operation Range

AT93C46-10PI-2.7

AT93C46-10SI-2.7

AT93C46R-10SI-2.7

AT93C46W-10SI-2.7

AT93C46-10TI-2.7

AT93C46U3-10UI-2.7

AT93C46Y1-10YI-2.7

8P3

8S1

8S2

8A2

8U3-1

8Y1

Industrial

(-40°C to 85°C)

AT93C46-10PI-1.8

AT93C46-10SI-1.8

AT93C46R-10SI-1.8

AT93C46W-10SI-1.8

AT93C46-10TI-1.8

AT93C46U3-10UI-1.8

AT93C46Y1-10YI-1.8

8P3

8S1

8S2

8A2

8U3-1

8Y1

Industrial

(-40°C to 85°C)

AT93C46-10SJ-2.7

AT93C46-10SJ-1.8 8S1

8S1 Lead-Free/Industrial Temperature

(-40°C to 85°C)

AT93C46-10SE-2.7 8S1 High Grade/Extended Temperature

(-40°C to 125°C)

Package Type

8P3 8-lea d, 0.300" Wide, Plast ic Dual Inline Package (PDIP)

8S1 8-lea d, 0. 150" Wide , Pl astic Gull Wing Sma ll Outl ine (JEDEC SOIC)

8S2 8-lead, 0.200" W ide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8A2 8-lea d, 0.170" Wide, Thin Shrink Small Ou tl ine P ackage (TSSOP)

8U3-1 8-ball, di e Ball Grid Array Package (dBGA2)

8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non- leaded, Miniature Arr ay P ackage (MAP)

Options

-2.7 Low-voltage ( 2.7V t o 5.5V)

-1.8 Low-voltage ( 1.8V t o 5.5V)

RRotated Pinout

12 AT93C46/56/66 0172U–SEEPR–8/03

Note: 1. This device i s not r ecom m ended f or new des igns. Please refer to AT93C56A.

2. For 2.7V devices used in the 4.5V t o 5.5V range, please ref er to performance values in t he AC and DC char acteristics table.

AT93C56(1) Ordering Information

Order ing Code(2) Packa ge Operation Range

AT93C56-10PI-2.7

AT93C56-10SI-2.7

AT93C56W-10SI-2.7

AT93C56-10TI-2.7

AT93C56Y1-10YI-2.7

8P3

8S1

8S2

8A2

8Y1

Industrial

(-40°C to 85°C)

AT93C56-10PI-1.8

AT93C56-10SI-1.8

AT93C56W-10SI-1.8

AT93C56-10TI-1.8

AT93C56Y1-10YI-1.8

8P3

8S1

8S2

8A2

8Y1

Industrial

(-40°C to 85°C)

Package Type

8P3 8-lea d, 0.300" Wide, Plast ic Dual Inline Package (PDIP)

8S1 8-lea d, 0. 150" Wide , Pl astic Gull Wing Sma ll Outl ine (JEDEC SOIC)

8S2 8-lead, 0.200" W ide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8A2 8-lead, 0.170” Wide, Thin Shrink Small Outli ne Package (TSSOP)

8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non- leaded, Miniature Arr ay P ackage (MAP)

Options

-2.7 Low-voltage ( 2.7V t o 5.5V)

1.8 Low-voltage ( 1.8V to 5.5V)

AT93C46/56/66

0172U–SEEPR–8/03

Notes: 1. This device i s not r ecom m ended f or new des igns. Please refer to AT93C66A.

2. For 2.7V devices used in the 4.5V t o 5.5V range, please ref er to performance values in t he AC and DC char acteristics table.

AT93C66(1) Ordering Information

Order ing Code(2) Pa ckage Operat i on R ange

AT93C66-10PI-2.7

AT93C66-10SI-2.7

AT93C66W-10SI-2.7

AT93C66-10TI-2.7

AT93C66Y1-10YI-2.7

8P3

8S1

8S2

8A2

8Y1

Industrial

(-40°C to 85°C)

AT93C66-10PI-1.8

AT93C66-10SI-1.8

AT93C66W-10SI-1.8

AT93C66-10TI-1.8

AT93C66Y1-10YI-1.8

8P3

8S1

8S2

8A2

8Y1

Industrial

(-40°C to 85°C)

Package Type

8P3 8-lea d, 0.300" Wide, Plast ic Dual Inline Package (PDIP)

8S1 8-lea d, 0. 150" Wide , Pl astic Gull Wing Sma ll Outl ine (JEDEC SOIC)

8S2 8-lead, 0.200" W ide, Plastic Gull Wing Small Outline (EIAJ SOIC)

8A2 8-lea d, 0.170" Wide, Thin Shrink Small Ou tl ine P ackage (TSSOP)

8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non- leaded, Miniature Arr ay P ackage (MAP)

Options

-2.7 Low-voltage ( 2.7V t o 5.5V)

-1.8 Low-voltage ( 1.8V t o 5.5V)

14 AT93C46/56/66 0172U–SEEPR–8/03

Packaging Inf ormation

8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

01/09/02

8P3 B

A2 A

4 PLCS

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

A 0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005 3

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

AT93C46/56/66

0172U–SEEPR–8/03

8S1 – JEDEC SOIC

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

Note:

10/10/01

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) 8S1 A

Top View

End View

Side View COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

A – – 1.75

B – – 0.51

C – – 0.25

D – – 5.00

E – – 4.00

e 1.27 BSC

H – – 6.20

L – – 1.27

16 AT93C46/56/66 0172U–SEEPR–8/03

8S2 – EIAJ SOIC

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8S2, 8-lead, 0.209" Body, Plastic Small

Outline Package (EIAJ)

5/2/02

8S2 B

Top View

Side View

End View

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs aren't included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.

A 1.78 2.03

A1 0.05 0.33

b 0.35 0.51 5

C 0.18 0.25 5

D 5.13 5.38

E 5.13 5.41 2, 3

H 7.62 8.38

L 0.51 0.89

e 1.27 BSC 4

AT93C46/56/66

0172U–SEEPR–8/03

8A2 – TSSO P

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

5/30/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b 0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8A2 B

Side View

End View

Top View

123

Pin 1 indicator

this corner

18 AT93C46/56/66 0172U–SEEPR–8/03

8U3-1 – dBGA2

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

PO8U3-1 A

6/24/03

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,

Small Die Ball Grid Array Package (dBGA2)

A 0.71 0.81 0.91

A1 0.10 0.15 0.20

A2 0.40 0.45 0.50

b 0.20 0.25 0.30

D 1.50 BSC

E 2.00 BSC

e 0.50 BSC

e1 0.25 REF

d 1.00 BSC

d1 0.25 REF

1. Dimension 'b' is measured at the maximum solder ball diameter.

This drawing is for general information only.

Bottom View

8 SOLDER BALLS

Top View

PIN 1 BALL PAD CORNER

Side View

PIN 1 BALL PAD CORNER

(e1)

(d1)

AT93C46/56/66

0172U–SEEPR–8/03

8Y1 – MAP

A – – 0.90

A1 0.00 – 0.05

D 4.70 4.90 5.10

E 2.80 3.00 3.20

D1 0.85 1.00 1.15

E1 0.85 1.00 1.15

b 0.25 0.30 0.35

e 0.65 TYP

L 0.50 0.60 0.70

PIN 1 INDEX AREA

A1 b

876

PIN 1 INDEX AREA

1234

Top View End View Bottom View

Side View

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package

(MAP) Y1 C

8Y1

2/28/03

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN NOM MAX

NOTE

Pr inted o n rec ycled pa per.

0172U–SEEPR–8/03 xM

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standa rd

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for a ny

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel are

gran ted by th e Com pany in conn ecti on w ith th e sale of A tme l prod uc ts, exp ressl y or by im pli catio n. Atme l’s pro duct s ar e no t aut ho rized for us e

as critical components in life support devices or systems.

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