FUJITSU SEMICONDUCTOR DATA SHEET DS07-13722-4E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90480/485 Series MB90F481/F482/487/F488/V480/V485 DESCRIPTION The MB90480/485 series is a 16-bit general-purpose FUJITSU microcontroller designed for process control in consumer devices and other applications requiring high-speed real-time processing. The F2MC-16LX CPU core instruction set retains the AT architecture of the F2MC*1 family, with additional instructions for high-level languages, expanded addressing mode, enhanced multiply-drive instructions, and complete bit processing. In addition, a 32-bit accumulator is provided to enable long-word processing. The MB90480/485 series features embedded peripheral resources including 8/16-bit PPG, expanded I/O serial interface, UART, 10-bit A/D converter, 16-bit I/O timer, 8/16-bit up-counter, PWC timer, I2C*2 interface, DTP/external interrupt, chip select, and 16-bit reload timer. *1 : F2MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU, Ltd. *2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C stand a Specification as defined by Philips. PACKAGES 100-pin plastic QFP 100-pin plastic LQFP (FPT-100P-M06) (FPT-100P-M05) MB90480/485 Series FEATURES * Clock Minimum instruction execution time: 40.0 ns/6.25 MHz base frequency multiplied x 4 (25 MHz internal operating frequency/3.3 V 0.3 V) 62.5 ns/4 MHz base frequency multiplied x 4 (16 MHz internal operating frequency/3.0 V 0.3 V) PLL clock multiplier * Maximum memory space: 16 Mbyte * Instruction set optimized for controller applications Supported data types (bit, byte, word, or long word) Typical addressing modes (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions 32-bit accumulator for enhanced high-precision calculation * Instruction set designed for high-level language (C) and multi-task operations System stack pointer adopted Instruction set compatibility and barrel shift instructions * Non-multiplex bus/multiplex bus compatible * Enhanced execution speed 4 byte instruction queue * Enhanced interrupt functions 8 levels setting with programmable priority, 8 external interrupts * Data transmission function (DMA) Up to 16 channels * Embedded ROM Flash versions : 192 KB, 256 KB, MASK versions : 192 KB * Embedded RAM Flash versions : 4 KB, 6 KB, 10 KB, MASK versions : 10 KB * General purpose ports Up to 84 ports (Except MB90V480 : Includes 16 ports with input pull-up resistance, 16 ports with output open drain settings) * A/D converter 8-channel RC sequential comparison type (10-bit resolution, 3.68 s conversion time (at 25 MHz) ) * I2C interface (MB90485 series only) : 1channel, P76/P77 Nch OD pin (without Pch) Do not apply high voltage in excess of recommended operating ranges to the Nch open drain pin (with Pch) in MB90V485. * PG (MB90485 series only) : 1 channel * UART: 1 channel * I/O expanded serial interface (SIO) : 2 channels * 8/16-bit PPG: 3 channels (with 8-bit x 6 channel/16-bit x 3 channel mode switching function) * 8/16-bit up/down timer: 1 channel (with 8-bit x 2 channel/16-bit x 1-channel mode switching function) * PWC (MB90485 series only) : 3 channels (Capable of compare the inputs to two of the three) * 3 V/5 V I/F pin (MB90485 series only) P20 to P27, P30 to P37, P40 to P47, P70 to P77 * 16-bit reload timer: 1 channel * 16-bit I/O timer: 2-channel input capture, 6-channel output compare, 1-channel free run timer * On chip dual clock generator system * Low-power consumption mode With stop mode, sleep mode, CPU intermittent operation mode, watch mode, timebase timer mode * Packages: QFP 100/LQFP 100 * Process: CMOS technology * Power supply voltage: 3 V, single source (some ports can be operated by 5 V power supply at MB90485 series) 2 MB90480/485 Series PRODUCT LINEUP * MB90480 series Part number MB90F481 MB90F482 MB90V480 ROM size FLASH 192 KB FLASH 256 KB RAM size 4 KB 6 KB 16 KB CPU function Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time Item : 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bits, 16-bits : 40 ns (25 MHz machine clock) General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain) Ports UART 1 channel, start-stop synchronized 8/16-bit PPG timer 8-bit x 6 channel/16-bit x 3 channel 8/16-bit up/down counter/timer 6 event input pins, 8-bit up/down counters: 2 8-bit reload/compare registers: 2 16-bit free run timer 16-bit Output compare I/O timers (OCU) Input capture (ICU) Number of channels: 1 Overflow interrupt Number of channels: 6 Pin input factor: A match signal of compare register Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) DTP/external interrupt circuit Number of external interrupt channels: 8 (edge or level detection) Extended I/O serial interface 2 channels, embedded Timebase timer 18-bit counter Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) A/D converter Conversion resolution: 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 MHz base oscillator) Low-power consumption (standby) modes Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase timer mode Process Type Emulator power supply* CMOS FLASH model Not included security function Evaluation product, user terminal, 3 V/5 V versions Included * : It is setting of Jumper switch (TOOL VCC) when emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply switching) about details. 3 MB90480/485 Series * MB90485 series Part number MB90487*1 MB90F488*2 MB90V485*1 ROM size 192 KB FLASH 256 KB RAM size 10 KB 10 KB 16 KB Item Number of instructions Instruction bit length Instruction length Data bit length Minimum execution time CPU function : 351 : 8-bit, 16-bit : 1 byte to 7 bytes : 1-bit, 8-bits, 16-bits : 40 ns (25 MHz machine clock) Ports General-purpose I/O ports: up to 84 General-purpose I/O ports (CMOS output) General-purpose I/O ports (with pull-up resistance) General-purpose I/O ports (N-ch open drain) UART 1 channel, start-stop synchronized 8/16-bit PPG timer 8-bit x 6 channel/16-bit x 3 channel 8/16-bit up/down counter/timer 6 event input pins, 8-bit up/down counters: 2 8-bit reload/compare registers: 2 16-bit free run timer 16-bit Output compare I/O timers (OCU) Input capture (ICU) Number of channels: 1 Overflow interrupt Number of channels: 6 Pin input factor: A match signal of compare register Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges) DTP/external interrupt circuit Number of external interrupt channels: 8 (edge or level detection) Extended I/O serial interface 2 channels, embedded 2 4 I C interface * 1 ch PG 1 ch PWC 3 ch Timebase timer 18-bit counter Interrupt cycles: 1.0 ms, 4.1 ms, 16.4 ms, 131.1 ms (at 4 MHz base oscillator) A/D converter Conversion resolution: 8/10-bit, switchable One-shot conversion mode (converts selected channel 1 time only) Scan conversion mode (conversion of multiple consecutive channels, programmable up to 8 channels) Continuous conversion mode (repeated conversion of selected channels) Stop conversion mode (conversion of selected channels with repeated pause) Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (minimum value, at 4 MHz base oscillator) Low-power consumption (standby) modes Sleep mode, stop mode, CPU intermittent mode, watch timer mode, timebase timer mode Process CMOS (Continued) 4 MB90480/485 Series (Continued) Part number Item Type Emulator power supply*5 MB90487*1 MB90F488*2 MB90V485*1 MASK model 3 V/5 V power supply*3 FLASH model 3 V/5 V power supply*3 Included security function Evaluation product 3 V/5 V power supply*3 Included *1 : Under development *2 : Being planed *3 : 3 V/5 V I/F pin : All pins should be for 3 V power supply without P20 to P27, P30 to P37, P40 to P47, and P70 to P77. *4 : P76/P77 pins are Nch open drain pins (without Pch) at built-in I2C. However, MB90V485 uses the Nch open drain pin (with Pch) . *5 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switch ing) about details. Note : As for MB90V485, Input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/PG/I2C become CMOS input. 5 MB90480/485 Series PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2 P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 P71/SOT0 P72/SCK0 P73/TIN0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS (TOP VIEW) (FPT-100P-M06) * : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/A11, P44/A12, P45/A13, P75, P76 and P77. Note : MB90485 series only * I2C pin P77 and P76 are Nch open drain pin (without Pch) . However, MB90V485 uses the Nch open drain pin (with Pch) . * P20 to P27, P30 to P37, P40 to P47 and P70 to P77 also used as 3 V/5 V I/F pin. * As for MB90V485, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ PG/I2C become CMOS input. 6 MB90480/485 Series 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 VCC3 X1 X0 VSS X0A X1A P57/CLK (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P71/SOT0 P72/SCK0 P73/TIN0 P74/TOT0 P75/PWC2* P76/SCL* P77/SDA* AVCC AVRH AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P82/IRQ2 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 VSS P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0* P37/A07/PWC1* P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00* P44/A12/MT01* VCC5 P45/A13/EXTC* P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 (FPT-100P-M05) * : These are the pins for MB90485 series. The pins for MB90480 series are P36/A06, P37/A07, P43/ A11, P44/A12, P45/A13, P75, P76 and P77. Note : MB90485 series only * I2C pin P77 and P76 are Nch open drain pin (without Pch) . However, MB90V485 uses the Nch open drain pin (with Pch) . * P20 to P27, P30 to P37, P40 to P47 and P70 to P77 also used as 3 V/5 V I/F pin. * As for MB90V485, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ PG/I2C become CMOS input. 7 MB90480/485 Series PIN DESCRIPTIONS Pin No. LQFP*1 QFP*2 Pin name Circuit type Function 80 82 X0 A Oscillator pin 81 83 X1 A Oscillator pin 78 80 X0A A 32 kHz oscillator pin 77 79 X1A A 32 kHz oscillator pin 75 77 RST B Reset input pin This is a general purpose I/O port. A setting in the pull-up resistance setting register (RDR0) can be used to apply pull-up resistance (RD00RD07 = "1") . (Disabled when pin is set for output.) P00 to P07 83 to 90 85 to 92 91 to 98 99, 100, 1,2 3 to 6 93 to 100 1 to 4 AD00 to AD07 C (CMOS) D00 to D07 In non-multiplex mode, these pins function as the external data bus low output pins. P10 to P17 This is a general purpose I/O port. A setting in the pull-up resistance setting resister (RDR1) can be used to apply pull-up resistance (RD10RD17 = "1") . (Disabled when pin is set for output.) AD08 to AD15 C (CMOS) In non-multiplex mode, these pins function as the external data bus high output pins. P20 to P23 This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. A16 to A19 When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (CMOS/H) (A16-A19). A16 to A19 When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A16-A19). P24 to P27 This is a general purpose I/O port. When the bits of external address output control register (HACR) are set to "1" in external bus mode, these pins function as general purpose I/O ports. A20 to A23 When the bits of external address output control register (HACR) are set to "0" in multiplex mode, these pins function as address high output pins (A20-A23). 5 to 8 E E (CMOS/H) PPG0 to PPG3 A00 AIN0 When the bits of external address output control register (HACR) are set to "0" in non-multiplex mode, these pins function as address high output pins (A20-A23). PPG timer output pins. This is a general purpose I/O port. P30 9 In multiplex mode, these pins function as the external address/data bus high I/O pins. D08 to D15 A20 to A23 7 In multiplex mode, these pins function as the external address/data bus low I/O pins. E (CMOS/H) In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down timer input pin (channel 0) . (Continued) 8 MB90480/485 Series Pin No. Pin name LQFP*1 QFP*2 P31 8 10 A01 BIN0 P32 A02 10 12 ZIN0 P33 A03 11 13 AIN1 P34 A04 12 14 BIN1 P35 A05 13 15 ZIN1 P36, P37 A06, A07 P36, P37 14 16 15 17*3 A06, A07 PWC0, PWC1 P40 A08 16 18 SIN2 P41 17 19 A09 SOT2 P42 A10 18 20 SCK2 P43, P44 A11, A12 P43, P44 19 21 20 22 A11, A12 MT00, MT01 Circuit type E (CMOS/ H) E (CMOS/ H) E (CMOS/ H) E (CMOS/ H) E (CMOS/ H) D (CMOS) E (CMOS/ H) G Function This is a general purpose I/O port. In non-multplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 0) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 0) This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 1) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 1) . This is a general purpose I/O port. In non-multiplex mode, this pin functions as an external address pin. 8/16-bit up/down counter input pin (channel 1) MB90480 This is a general purpose I/O port. series In non-multiplex mode, this pin functions as an external address pin. This is a general purpose I/O port. MB90485 In non-multiplex mode, this pin functions as an external address pin. series This is a PWC input pin. This is a general purpose I/O port. (CMOS/ In non-multiplex mode, this pin functions as an external address pin. H) Simple serial I/O input pin. This is a general purpose I/O port. F In non-multiplex mode, this pin functions as an external address pin. (CMOS) Simple serial I/O output pin. This is a general purpose I/O port. G (CMOS/ In non-multiplex mode, this pin functions as an external address pin. H) Simple serial I/O clock input/output pin. F MB90480 This is a general purpose I/O port. (CMOS) series In non-multiplex mode, this pin functions as an external address pin. This is a general purpose I/O port. MB90485 In non-multiplex mode, this pin functions as an external address pin. F (CMOS) series PG output pin. (Continued) 9 MB90480/485 Series Pin No. 1 LQFP* QFP* 2 Pin name P45 A13 22 24 P45 A13 EXTC*3 P46, P47 23 24 25 26 A14, A15 OUT4/ OUT5 P50 68 70 ALE P51 69 71 RD P52 70 71 F MB90480 This is a general purpose I/O port. (CMOS) series In non-multiplex mode, this pin functions as an external address pin. G This is a general purpose I/O port. MB90485 (CMOS/ In non-multiplex mode, this pin functions as an external address pin. series H) PG input pin (MB90485 series only) . This is a general purpose I/O port. F In non-multiplex mode, this pin functions as an external address pin. (CMOS) Output compare event output pins. This is a general purpose I/O port. In external bus mode, this pin functions as the ALE pin. D (CMOS) In external bus mode, this pin functions as the address load enable (ALE) signal pin. This is a general purpose I/O port. In external bus mode, this pin functions as the RD pin. D (CMOS) In external bus mode, this pin functions as the read strobe output (RD) signal pin. This is a general purpose I/O port. In external bus mode, when the WRE pin in the EPCR register is set to "1", this pin functions as the WRL pin. WRL P53 This is a general purpose I/O port. In external bus mode with 16-bit bus width, when the WRE bit in the EPCR register is set to "1", this pin functions as the WRH pin. 73 P54 73 Function D (CMOS) In external bus mode, this pin functions as the lower data write strobe output (WRL) pin. When the WRE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. 72 WRH 72 Circuit type D (CMOS) In external bus mode with 16-bit bus width, this pin functions as the upper data write strobe output (WRH) pin. When the WRE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to "1", this pin functions as the HRQ pin. HRQ D (CMOS) In external bus mode, this pin functions as the hold request input (HRQ) pin. When the HDE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. P55 This is a general purpose I/O port. In external bus mode, when the HDE bit in the EPCR register is set to "1", this pin functions as the HAK pin. 74 75 HAK D (CMOS) In external bus mode, this pin functions as the hold acknowledge (HAK) pin. When the HDE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. (Continued) 10 MB90480/485 Series Pin No. LQFP* 1 QFP* 2 Pin name Circuit type This is a general purpose I/O port. In external bus mode, when the RYE bit in the EPCR register is set to "1", this pin functions as the RDY pin. P56 74 76 Function RDY D (CMOS) In external bus mode, this pin functions as the external ready (RDY) input pin. When the RYE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. P57 This is a general purpose I/O port. In external bus mode, when the CKE bit in the EPCR register is set to "1", this pin functions as the CLK pin. 76 78 CLK D (CMOS) In external bus mode, this pin functions as the machine cycle clock (CLK) output pin. When the CKE bit in the EPCR register is set to "0", this pin functions as a general purpose I/O port. 36 to 39 38 to 41 P60 to P63 These are general purpose I/O ports. H (CMOS) AN0 to AN3 These are the analog input pins. 41 to 44 43 to 46 P64 to P67 25 27 26 28 27 29 28 30 29 31 These are general purpose I/O ports. H (CMOS) AN4 to AN7 These are the analog input pins. P70 G SIN0 (CMOS/ H) P71 SOT0 G SCK0 (CMOS/ H) P73 G TIN0 (CMOS/ H) TOT0 P75 30 32 P75 PWC2*3 P76 31 33 P76 SCL*3 P77 32 34 P77 SDA*3 45, 46 47, 48 P80, P81 IRQ0, IRQ1 This is the UART data input pin. This is a general purpose I/O port. F (CMOS) This is the UART data output pin. P72 P74 This is a general purpose I/O port. This is a general purpose I/O port. This is the UART clock I/O pin. This is a general purpose I/O port. This is the 16-bit reload timer event input pin. This is a general purpose I/O port. F (CMOS) This is the 16-bit reload timer output pin. F MB90480 series This is a general purpose I/O port. (CMOS) G (CMOS/ H) This is a general purpose I/O port. MB90485 series This is a PWC input pin. F (CMOS) MB90480 series This is a general purpose I/O port. I (NMOS/ H) This is a general purpose I/O port. MB90485 2 series Serves as the I C interface data I/O pin. During operation of the I2C interface, leave the port output in a high impedance state. F (CMOS) MB90480 series This is a general purpose I/O port. I (NMOS/ H) This is a general purpose I/O port. MB90485 2 series Serves as the I C interface data I/O pin. During operation of the I2C interface, leave the port output in a high impedance state. E These are general purpose I/O ports. (CMOS/ External interrupt input pins. H) (Continued) 11 MB90480/485 Series (Continued) Pin No. LQFP*1 QFP*2 Pin name Circuit type Function P82 to P87 These are general purpose I/O ports. E ( CMOS / H ) IRQ2 to IRQ7 External interrupt input pins. This is a general purpose I/O port. P90 E SIN1 Simple serial I/O data input pin. 56 58 (CMOS/H) CS0 Chip select 0. P91 This is a general purpose I/O port. D 57 59 SOT1 Simple serial I/O data output pin. (CMOS) CS1 Chip select 1. This is a general purpose I/O port. P92 E SCK1 Simple serial I/O data input/output pin. 58 60 (CMOS/H) CS2 Chip select 2. This is a general purpose I/O port. P93 When the free run timer is in use, this pin functions as the external FRCK clock input pin. E 59 61 (CMOS/H) When the A/D converter is in use, this pin functions as the external ADTG trigger input pin. CS3 Chip select 3. P94 This is a general purpose I/O port. D 60 62 (CMOS) PPG timer output pin. PPG4 P95 This is a general purpose I/O port. D 61 63 (CMOS) PPG timer output pin. PPG5 P96 This is a general purpose I/O port. E 62 64 ( CMOS / H ) IN0 Input capture channel 0 trigger input pin. This is a general purpose I/O port. P97 E 63 65 CMOS / H ) ( IN1 Input capture channel 1 trigger input pin. PA0 to PA3 These are general purpose I/O ports. D 64 to 67 66 to 69 (CMOS) OUT0 to OUT3 Output compare event output pins. A/D converter power supply pin. 33 35 AVCC 34 36 AVRH A/D converter external reference voltage supply pin. A/D converter power supply pin. 35 37 AVSS J (CMOS/ Operating mode selection input pins. 47 to 49 49 to 51 MD0 to MD2 H) 82 84 VCC3 3.3 V 0.3 V power supply pins (VCC3) . MB90480 3.3 V 0.3 V power supply pin. seriesv Usually, use VCC = VCC3 = VCC5 as a 3 V power supply. 3 V/5 V power supply pin. 21 23 VCC5 5 V power supply pin when P20 to P27, P30 to P37, MB90485 P40 to P47, P70 to P77 are used as 5 V I/F pins. series Usually, use VCC = VCC3 = VCC5 as a 3 V power supply (when the 3 V power supply is used alone) . 9 11 Power supply input pins (GND) . 40 42 VSS 79 81 50 to 55 52 to 57 *1 : LQFP : FPT-100P-M05 *2 : QFP : FPT-100P-M06 *3 : As for MB90V485, input pins become CMOS input. 12 MB90480/485 Series I/O CIRCUIT TYPES Type Circuit Remarks X1, X1A X0, X0A A Standby control signal B Oscillator feedback resistance X1, X0 : approx. 1 M X1A, X0A : approx. 10 M with standby control Hysteresis input with pull-up resistance Resistance : approx. 50 k HYS CTL With input pull-up resistance control Resistance : approx. 50 k CMOS level input/output C CMOS D CMOS level input/output CMOS Hysteresis input CMOS level output E CMOS (Continued) 13 MB90480/485 Series (Continued) Type Circuit Remarks Open drain control signal F CMOS level input/output with open drain control CMOS Open drain control signal G CMOS level output Hysteresis input With open drain control HYS CMOS level input/output Analog input H CMOS Analog input Digital output Hysteresis input Nch open drain output I FLASH model Control signal (FLASH model) CMOS level input with high voltage control for flash testing J Mode input Diffusion resistance MASK model Hysteresis input 14 (Mask model) Hysteresis input MB90480/485 Series HANDLING DEVICES 1. Be careful never to exceed maximum rated voltages (preventing latchup) In CMOS IC devices, a condition known as latchup may occur if voltages higher than VCC or loser than VSS are applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and VSS exceeds the rated voltage level. When latchup occurs, the power supply current increases rapidly causing the possibility of thermal damage to circuit elements. Therefore it is necessary to ensure that maximum ratings are not exceeded in circuit operation. Similarly, when turning the analog power supply on or off, it is necessary to ensure that the analog power supply voltages (AVCC and AVRH) and analog input voltages do not exceed the digital power supply (VCC) . 2. Treatment of unused pins Leaving unused input pins unconnected can cause abnormal operation or latchup, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. 3. Notes on Using External Clock Even when using an external clock signal, an oscilltion stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When using an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. X0 OPEN X1 4. Treatment of Power Supply Pins (VCC/VSS) When multiple VCC/VSS pins are present, device design considerations for prevention of latch-up and unwanted electromagnetic interference, abnormal storobe signal operation due to ground level rise, and conformity with total output current ratings require that all power supply pins must be externally connected to power supply or ground. Consideration should be given to connecting power supply sources to the VCC/VSS terminals of this device with as low impedane as possible. It is also recommended that a bypass capacitor of approximately 0.1 F be placed between the VCC and VSS lines as close to this device as possible. 5. Crystal Oscillator Circuits Noise around the X0/X1, or X0A/X1A pins may cause this device to operate abnormally. In the interest of stable operation it is strongly recommended that printed circuit artwork places ground bypass capacitors as close as possible to the X0/X1, X0A/X1A and crystal oscillator (or ceramic oscillator) and that oscillator lines do not cross the lines of other circuits. 15 MB90480/485 Series 6. Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 7. Proper power-on/off sequence The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be turned on after the digital power supply (VCC) is turned on. The A/D converter power (AVCC, AVRH) and analog input (AN0 to AN7) must be shut off before the digital power supply (VCC) is shut off. Care should be taken that AVRH does not exceed AVCC. Even when pins used as analog input pins are doubled as input ports, be sure that the input voltage does not exceed AVCC. 8. Treatment of power supply pins on models with A/D converters Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC, and AVSS = VSS. 9. Precautions when turning the power supply on In order to prevent abnormal operation in the chip's internal step-down circuits, a voltage rise time during poweron of 50 s (0.2 V to 2.7 V) or greater should be assured. 10. Supply Voltage Stabilization Even within the operating range of VCC supply voltage, rapid voltage fluctuations may cause abnormal operation. As a standard for power supply voltage stability, it is recommended that the peak-to-peak VCC ripple voltage at commercial supply frequency (50 Hz to 60 Hz) be 10 % or less of VCC, and that the transient voltage fluctuation be no more than 0.1 V/ms or less when the power supply is turned on or off. 11. Notes on Using Power Supply Only the MB90485 series usually uses a 3 V power supply. By setting VCC3 = 3 V power supply and VCC5 = 5 V power supply, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 can be intefaced as 5 V power supplies separately from the main 3 V power supply. Note that the analog power supplies (such as AVCC and AVSS) for the A/D converter can be used only as 3 V power supplies. Programming into FLASH memory must be performed at an operating voltage (VCC) between 3.13 V and 3.6 V. 12. Treatment of N.C. pins N.C. (internally connected) pins should always be left open. 13. When the MB90480/485 series microcontroller is used as a single system When the MB90480/485 series microcontroller is used as a single system, use connections so the X0A = VSS, and X1A = Open. 14. Writing to FLASH memory For serial writing to FLASH memory, always ensure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to FLASH memory, always ensure that the operating voltage VCC is between 3.0 V and 3.6 V. 16 MB90480/485 Series BLOCK DIAGRAM X0, X1, RST X0A, X1A MD2, MD1, MD0 8 CPU F2MC16LX series core Clock control Circuit RAM Interrupt controller ROM 8/16 bit PPG PPG0, PPG1 PPG2, PPG3 PPG4, PPG5 DMA AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 8/16 bit U/D counter Communication prescaler SIN1, SIN2 SOT1, SOT 2 SCK1, SCK2 F2MC-16LX Bus 2 SIN0 SOT0 SCK0 UART I/O extended serial interface 2ch EXTC MT00 MT01 mPG Chip select CS0, CS1, CS2, CS3 Input/output timer AVCC AVRH AVSS ADTG AN0 to AN7 16 bit input capture 2ch A/D converter ( 10 bit ) IN0, IN1 16 bit output compare 2ch 16 bit free-run timer OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 16 bit reload timer TIN0 TOT0 I2C interface SCL SDA PWC0 PWC1 PWC 3ch PWC2 External interrupt 8 IRQ0 to IRQ7 I/O port 8 8 8 8 8 8 8 8 8 8 4 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 to to to to to to to to to to PA0 to P07 P17 P27 P37 P47 P57 P67 P77 P87 P97 PA3 : Only MB90485 series P00 to P07 (8 pins) P10 to P17 (8 pins) P40 to P47 (8 pins) P70 to P75 (6 pins) : with an input pull-up resistance setting register. : with an input pull-up resistance setting register. : with an open drain setting register. : with an open drain setting register. MB90485 series only * I2C pin P77 and P76 are Nch open drain pin (without Pch) . However, MB90V485 uses the Nch open drain pin (with Pch) . * P20 to P27, P30 to P37, P40 to P47 and P70 to P77 also used as 3 V/5 V I/F pin. * As for MB90V485, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/ PG/I2C become CMOS input. Note : In the above diagram, I/O ports share internal function blocks and pins. However, when a set of pins is used with an internal module, it cannot also be used as an I/O port. 17 MB90480/485 Series MEMORY MAP Single chip Internal ROM external bus ROM area ROM area ROM area FF bank image ROM area FF bank image FFFFFFH External ROM external bus Address #1 010000H Address #2 * Address #3 RAM Register RAM Register RAM Register 000100H 0000D0H Peripheral Peripheral Peripheral 000000H : internal : External : Access inhibited * : In models where address #3 overlaps with address #2, this external area does not exist. Model Address #1 Address #2 MB90F481 FC0000H * 001100H (access inhibited to 001FFFH) MB90F482 FC0000H 001900H (access inhibited to 001FFFH) MB90487 FD0000H MB90F488 FC0000H 002900H (access inhibited to 001FFFH) MB90V480 (FC0000H) 004000H MB90V485 (FC0000H) 004000H 004000H or 008000H, selected by the MS bit in the ROMM register Address #3 002900H (access inhibited to 001FFFH) * : No memory cells from FC0000H to FC7FFFH and FE0000H to FE7FFFH. The upper part of the 00 bank is set up to mirror the image of FF bank ROM, to enable efficient use of small model C compilers. Because the lower 16-bit address of the FF bank and the lower 16-bit address of the 00 bank is the same, enabling reference to tables in ROM without the "far" pointer declaration. For example, in accessing address 00C000H it is actually the contents of ROM at FFC000H that are accessed. If the MS bit in the ROMM register is set to "0", the ROM area in the FF bank will exceed 48 K bytes and it is not possible to reflect the entire area in the image in the 00 bank. Therefore the image from FF4000H to FFFFFFH is reflected in the 00 bank and the area from FF0000H to FF3FFFH can be seen in the FF bank only. 18 MB90480/485 Series F2MC-16L CPU PROGRAMMING MODEL * Dedicated registers AH Accumulator AL USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bit 16 bit 32 bit * General purpose registers MSB LSB 16 bit 000180H + RP x 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 * Processor status 13 12 15 PS ILM 8 7 RP 0 CCR 19 MB90480/485 Series I/O MAP Address Register name Abbreviated Read/ register name Write Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (MB90480 series) 11XXXXXXB (MB90485 series) XXXXXXXXB XXXXXXXXB - - - - XXXXB 00H 01H 02H 03H 04H 05H 06H Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 07H Port 7 data register PDR7 R/W Port 7 08H 09H 0AH Port 8 data register Port 9 data register Port A data register PDR8 PDR9 PDRA R/W R/W R/W 0BH Port 3 timer input enable register UDRE R/W Port 8 Port 9 Port A U/D timer input control 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H Interrupt/DTP enable register Interrupt/DTP enable register Request level setting register Request level setting register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register ENIR EIRR DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 17H Port 7 direction register DDR7 R/W Port 7 18H 19H 1AH 1BH 1CH 1DH Port 8 direction register Port 9 direction register Port A direction register Port 4 pin register Port 0 resistance register Port 1 resistance register DDR8 DDR9 DDRA ODR4 RDR0 RDR1 R/W R/W R/W R/W R/W R/W Port 8 Port 9 Port A Port 4 (OD control) Port 0 (Pull-up) Port 1 (Pull-up) 1EH Port 7 pin register ODR7 R/W Port 7 (OD control) 1FH Analog input enable register ADER R/W Port 5, A/D ELVR DTP/external interrupts Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (MB90480 series) XX0 0 0 0 0 0B (MB90485 series) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B (MB90480 series) XX0 0 0 0 0 0B (MB90485 series) 1 1 1 1 1 1 1 1B (Continued) 20 MB90480/485 Series Address Register name Abbreviated register name Read/ Write Resource name Initial value 20H Serial mode register 0 SMR0 R/W 0 0 0 0 0 X 0 0B 21H Serial control register 0 SCR0 R/W 0 0 0 0 0 1 0 0B 22H Serial input register/serial output register SIDR/ SODR0 R/W 23H Serial status register SSR0 R/W 24H UART0 XXXXXXXXB 0 0 0 0 1 0 0 0B (Reserved area) 25H Clock multiplier control register CDCR R/W 26H Serial mode control status register 0 SMCS0 R/W 27H Serial mode control status register 0 SMCS0 R/W 28H Serial data register SDR0 R/W 29H Clock multiplier control register SDCR0 R/W 2AH Serial mode control status register 1 SMCS1 R/W 2BH Serial mode control status register 1 SMCS1 R/W 2CH Serial data register SDR1 R/W Communication prescaler (UART) 0 0 - - 0 0 0 0B - - - - 0 0 0 0B SCI1 (ch0) 0 0 0 0 0 0 1 0B XXXXXXXXB Communication prescaler (SCI1) 0 - - - 0 0 0 0B - - - - 0 0 0 0B SCI2 (ch1) 0 0 0 0 0 0 1 0B XXXXXXXXB Communication prescaler (SCI2) 2DH Clock multiplier control register SDCR1 R/W 2EH PPG reload register L (ch0) PRLL0 R/W XXXXXXXXB 2FH PPG reload register H (ch0) PRLH0 R/W XXXXXXXXB 30H PPG reload register L (ch1) PRLL1 R/W XXXXXXXXB 31H PPG reload resister H (ch1) PRLH1 R/W XXXXXXXXB 32H PPG reload register L (ch2) PRLL2 R/W XXXXXXXXB 33H PPG reload register H (ch2) PRLH2 R/W XXXXXXXXB 34H PPG reload register L (ch3) PRLL3 R/W XXXXXXXXB 35H PPG reload register H (ch3) PRLH3 R/W XXXXXXXXB 36H PPG reload register L (ch4) PRLL4 R/W 37H PPG reload register H (ch4) PRLH4 R/W 38H PPG reload register L (ch5) PRLL5 R/W XXXXXXXXB 39H PPG reload register H (ch5) PRLH5 R/W XXXXXXXXB 3AH PPG0 operating mode control register PPGC0 R/W 0 X 0 0 0XX 1B 3BH PPG1 operating mode control register PPGC1 R/W 0 X 0 0 0 0 0 1B 3CH PPG2 operating mode control register PPGC2 R/W 0 X 0 0 0XX 1B 3DH PPG3 operating mode control register PPGC3 R/W 0 X 0 0 0 0 0 1B 3EH PPG4 operating mode control register PPGC4 R/W 0 X 0 0 0XX 1B 3FH PPG5 operating mode control register PPGC5 R/W 0 X 0 0 0 0 0 1B 40H PPG0, 1 output control register PPG01 R/W 41H 42H 43H 8/16-bit PPG (ch0 to ch5) 0 - - - 0 0 0 0B XXXXXXXXB XXXXXXXXB 8/16-bit PPG 0 0 0 0 0 0 0 0B 8/16-bit PPG 0 0 0 0 0 0 0 0B (Reserved area) PPG2, 3 output control register PPG23 R/W (Reserved area) (Continued) 21 MB90480/485 Series Address 44H Register name PPG4, 5 output control register 45H 46H 47H 48H 49H Abbreviated register name Read/ Write Resource name Initial value PPG45 R/W 8/16-bit PPG 0 0 0 0 0 0 0 0B (Reserved area) Control status register Data register ADCS1 R/W ADCS2 R/W ADCR1 R ADCR2 R OCCP0 R/W OCCP1 R/W OCCP2 R/W OCCP3 R/W OCCP4 R/W OCCP5 R/W 0 0 0 0 0 0 0 0B A/Dconverter 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 XXXB 4AH Output compare register (ch0) lower digits 4BH Output compare register (ch0) upper digits 4CH Output compare register (ch1) lower digits 4DH Output compare register (ch1) upper digits 4EH Output compare register (ch2) lower digits 4FH Output compare register (ch2) upper digits 50H Output compare register (ch3) lower digits 51H Output compare register (ch3) upper digits 52H Output compare register (ch4) lower digits 53H Output compare register (ch4) upper digits 54H Output compare register (ch5) lower digits 55H Output compare register (ch5) upper digits 56H Output compare control register (ch0) OCS0 R/W 0 0 0 0 - - 0 0B 57H Output compare control register (ch1) OCS1 R/W - - - 0 0 0 0 0B 58H Output compare control register (ch2) OCS2 R/W 0 0 0 0 - - 0 0B 59H Output compare control register (ch3) OCS3 R/W - - - 0 0 0 0 0B 5AH Output compare control register (ch4) OCS4 R/W 0 0 0 0 - - 0 0B 5BH Output compare control register (ch5) OCS5 R/W - - - 0 0 0 0 0B 5CH Input capture register (ch0) lower digits 5DH Input capture register (ch0) upper digits 5EH Input capture register (ch1) lower digits 5FH Input capture register (ch1) upper digits 60H Input capture control register 61H IPCP0 ICS01 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 16-bit output timer 0 0 0 0 0 0 0 0B output compare 0 0 0 0 0 0 0 0B (ch0 to ch5) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R XXXXXXXXB R XXXXXXXXB R IPCP1 0 0 0 0 0 0 0 0B R R/W 16-bit output timer input capture (ch0, ch1) XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B (Reserved area) 62H Timer data register lower digits TCDT R/W 0 0 0 0 0 0 0 0B 63H Timer data register upper digits TCDT R/W 0 0 0 0 0 0 0 0B 64H Timer control status register TCCS R/W 65H Timer control status register TCCS R/W 16-bit output timer 0 0 0 0 0 0 0 0B free run timer 0 - - 0 0 0 0 0B 66H Compare clear register lower digits 67H Compare clear register upper digits CPCLR R/W XXXXXXXXB XXXXXXXXB (Continued) 22 MB90480/485 Series Address Register name 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H* 77H* 78H* 79H* 7AH* 7BH* 7CH* 7DH* 7EH* 7FH* 80H* 81H* 82H* 83H 84H* 85H 86H* 87H 88H* 89H* 8AH* 8BH* 8CH* 8DH Up/down count register ch0 Up/down count register ch1 Reload compare register ch0 Reload compare register ch1 Counter control register lower digits ch0 Counter control register upper digits ch0 ROM mirror function select register Counter control register lower digits ch1 Counter control register upper digits ch1 Count status register ch0 Count status register ch1 PWC0 control status register Abbreviated Read/ register name Write Resource name UDCR0 R UDCR1 R RCR0 W 8/16-bit up/down timer counter RCR1 W CCRL0 R/W CCRH0 R/W (Reserved area) ROMM R/W ROM mirroring function CCRL1 R/W 8/16-bit up/down timer CCRH1 R/W counter CSR0 R/W (Reserved area) CSR1 R/W 8/16-bit UDC (Reserved area) PWCSR0 R/W PWCR0 R/W PWC1 control status register PWCSR1 R/W PWCR1 R/W PWCSR2 R/W PWC2 control status register PWCR2 PWC0 dividing ratio register DIVR0 R/W (Reserved area) DIVR1 R/W (Reserved area) DIVR2 R/W (Reserved area) IBSR R IBCR R/W ICCR R/W IADR R/W IDAR R/W (Reserved area) PWC1 dividing ratio control register PWC2 dividing ratio control register I2C bus status register I2C bus control register I2C bus clock select register I2C bus address register I2C bus data register 0 0 0 0 0 0 0 0B PWC (ch1) - - - - - - 0 0B PWC (ch2) - - - - - - 0 0B I2C 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - 0 X X X X XB - X X X X X X XB XXXXXXXXB PWC timer (ch2) PWC2 data buffer register ------01B 0 X 0 0 X 0 0 0B - 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B PWC (ch0) PWC timer (ch 1) PWC1 data buffer register 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 X 0 0 X 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - 0 0B PWC timer (ch0) PWC0 data buffer register Initial value R/W (Continued) 23 MB90480/485 Series Address 8EH* Register name PG control status register 8FH to 9BH Abbreviated register name Read/ Write Resource name Initial value PGCSR R/W PG 0 0 0 0 0 - - -B (Disabled) 9CH DMA status register DSRL R/W DMA 0 0 0 0 0 0 0 0B 9DH DMA status register DSRH R/W DMA 0 0 0 0 0 0 0 0B DIRR R/W Delayed interruput generator module - - - - - - - 0B 9EH (Disabled) 9FH Dilayed interrupt source general/ cancel register A0H Low-power consumption mode register LPMCR R/W Low-power operation 0 0 0 1 1 0 0 0B A1H Clock select register CKSCR R/W low-power operation 1 1 1 1 1 1 0 0B A2H, A3H (Reserved area) A4H DMA stop status register DSSR R/W DMA 0 0 0 0 0 0 0 0B A5H Automatic ready function select register ARSR W External pins 0 0 1 1 - - 0 0B A6H External address output control register HACR W External pins * * * * * * * *B A7H Bus control signal control register EPCR W External pins 1 0 0 0 * 1 0 -B A8H Watchdog control register WDTC R/W Watchdog timer XXXXX 1 1 1B A9H Timebase timer control register TBTC R/W Timebase timer 1 X X 0 0 1 0 0B AAH Watch timer control register WTC R/W Watch timer 1 0 0 0 1 0 0 0B ABH (Reserved area) ACH DMA control area DERL R/W DMA 0 0 0 0 0 0 0 0B ADH DMA control area DERH R/W DMA 0 0 0 0 0 0 0 0B AEH Flash memory control status register FMCR R/W Flash memory interface 0 0 0 X 0 0 0 0B B0H Interrupt control register 00 ICR00 W, R/W X X X X 0 1 1 1B B1H Interrupt control register 01 ICR01 W, R/W X X X X 0 1 1 1B B2H Interrupt control register 02 ICR02 W, R/W X X X X 0 1 1 1B B3H Interrupt control register 03 ICR03 W, R/W X X X X 0 1 1 1B B4H Interrupt control register 04 ICR04 W, R/W X X X X 0 1 1 1B B5H Interrupt control register 05 ICR05 W, R/W X X X X 0 1 1 1B B6H Interrupt control register 06 ICR06 W, R/W X X X X 0 1 1 1B B7H interrupt control register 07 ICR07 W, R/W X X X X 0 1 1 1B B8H Interrput control register 08 ICR08 W, R/W X X X X 0 1 1 1B B9H Interrupt control register 09 ICR09 W, R/W X X X X 0 1 1 1B BAH Interrupt control register 10 ICR10 W, R/W X X X X 0 1 1 1B BBH Interrupt control register 11 ICR11 W, R/W X X X X 0 1 1 1B AFH (Disabled) (Continued) 24 MB90480/485 Series (Continued) Address Register name Abbreviated register name Read/ Write Resource name Initial value BCH Interrupt control register 12 ICR12 W, R/ W X X X X 0 1 1 1B BDH Interrupt control register 13 ICR13 W, R/ W X X X X 0 1 1 1B BEH Interrupt control register 14 ICR14 W, R/ W X X X X 0 1 1 1B BFH Interrupt control register 15 ICR15 W, R/ W X X X X 0 1 1 1B C0H Chip select mask register 0 CMR0 R/W Chip select function 00001111B C1H Chip select area register 0 CAR0 R/W 1 1 1 1 1 1 1 1B C2H Chip select mask register 1 CMR1 R/W 00001111B C3H Chip select area register 1 CAR1 R/W 1 1 1 1 1 1 1 1B C4H Chip select mask register 2 CMR2 R/W 00001111B C5H Chip select area register 2 CAR2 R/W 1 1 1 1 1 1 1 1B C6H Chip select mask register 3 CMR3 R/W 00001111B C7H Chip select area register 3 CAR3 R/W 1 1 1 1 1 1 1 1B C8H Chip select control register CSCR R/W - - - - 0 0 0 *B C9H Chip select active level register CALR R/W CAH CBH CCH CDH Timer control status register 16-bit timer register/ 16-bit reload register CEH CFH TMCSR R/W 16-bit reload timer TMR/TMRLR - - - - 0 0 0 0B 0 0 0 0 0 0 0 0B R/W - - - - 0 0 0 0B XXXXXXXXB (Reserved area) PLL output control register PLLOS D0H to FFH (External area) 100H to #H (RAM area) W Low-power operation - - - - - - X 0B * : These registers are only for MB90485 series. They are used as the reserved area on MB90480 series. Descriptions for read/write R/W : Readable and writable R : Read only W : Write only Descriptions for initial value 0 : The initila value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. : This bit is not used. * : The initial value of this bit is "1" or "0". The value depends on the mode pin (MD2, MD1 and MD0) . 25 MB90480/485 Series INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS DMA cnannel number Number Address Number Address Reset #08 FFFFDCH INT9 instruction #09 FFFFD8H Exception #10 FFFFD4H INT0 0 #11 FFFFD0H INT1 x #12 FFFFCCH ICR00 0000B0H INT2 x #13 FFFFC8H INT3 x #14 FFFFC4H ICR01 0000B1H INT4 x #15 FFFFC0H INT5 x #16 FFFFBCH ICR02 0000B2H INT6 x #17 FFFFB8H INT7 x #18 FFFFB4H ICR03 0000B3H PWC1 (MB90485 series only) x #19 FFFFB0H PWC2 (MB90485 series only) x #20 FFFFACH ICR04 0000B4H PWC0 (MB90485 series only) 1 #21 FFFFA8H PPG0/PPG1 counter borrow 2 #22 FFFFA4H ICR05 0000B5H PPG2/PPG3 counter borrow 3 #23 FFFFA0H PPG4/PPG5 counter borrow 4 #24 FFFF9CH ICR06 0000B6H 8/16-bit up/down counter timer compare/underflow/overflow/ inversion (ch0, 1) x #25 FFFF98H ICR07 0000B7H Input capture (ch0) load 5 #26 FFFF94H Input capture (ch1) load 6 #27 FFFF90H Output compare (ch0) match 8 #28 FFFF8CH ICR08 0000B8H Output compare (ch1) match 9 #29 FFFF88H Output compare (ch2) match 10 #30 FFFF84H ICR09 0000B9H Output compare (ch3) match x #31 FFFF80H Output compare (ch4) match x #32 FFFF7CH ICR10 0000BAH Output compare (ch5) match x #33 FFFF78H UART sending completed 11 #34 FFFF74H ICR11 0000BBH 16-bit free run timer overflow, 16-bit reload timer underflow 12 #35 FFFF70H ICR12 0000BCH UART receiving compleated 7 #36 FFFF6CH SIO1 13 #37 FFFF68H SIO2 14 #38 FFFF64H ICR13 0000BDH Interrupt source Interrupt vector Interrupt control register (Continued) 26 MB90480/485 Series (Continued) Interrupt vector Interrupt source DMA channel number Number Address I2C interface (MB90485 series only) x #39 FFFF60H 15 #40 FFFF5CH FLASH write/erase, timebase timer,watch timer * x #41 FFFF58H Delay interrupt generator module x #42 FFFF54H A/D conversion Interrupt control register Number Address ICR14 0000BEH ICR15 0000BFH x: Interrupt request flag not cleared by the interrupt clear signal. If there are two interrupt sources for the same interrupt number, the resource will clear both interrupt request flags at the DMAC interrupt clear signal. Therefore if either of the two sources uses the DMAC function, the other interrupt function cannot be used. The interrupt request enable bit for the corresponding resource should be set to "0" and interrupt requests from that resource should be handled by software polling. * : Caution : The FLASH write/erase, timebase timer, and watch timer cannot be used at the same time. 27 MB90480/485 Series PERIPHERAL RESOURCES 1. I/O Ports The I/O ports perform the functions of either sending data from the CPU to the I/O pins, or loading information from the I/O into the CPU, according to the setting of the corresponding port register (PDR) . The input/output direction of each I/O pin can be set in individual bit units by the port direction register (DDR) for each port. The MB90480/485 series has 84 input/output pins. The I/O ports are port 0 through port A. (1) Port Registers PDR0 7 6 5 4 3 2 1 0 Initial value Access Address : 000000H P07 P06 P05 P04 P03 P02 P01 P00 Undefined R/W*1 PDR1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 Address : 000001H PDR2 Address : 000002H PDR3 Address : 000003H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H PDR7 Address : 000007H PDR8 Address : 000008H PDR9 Address : 000009H 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 7 6 5 4 3 2 1 0 P77 P76 P75 P74 P73 P72 P71 P70 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 PDRA 7 6 5 4 3 2 1 0 Address : 00000AH PA3 PA2 PA1 PA0 Undefined*2 R/W*1 Undefined R/W*1 Undefined R/W*1 Undefined R/W*1 *1 : The R/W indication for I/O ports is somewhat different than R/W access to memory, and involves the following operations. * Input mode Read : Reads the corresponding siganl pin level. Write : Writes to the output latch. * Output mode Read : Reads the value from the data register latch. Write : Outputs the value to the corresponding signal pin. *2 : The initial value of this bit is "11XXXXXXB" on MB90485 series. 28 MB90480/485 Series (2) Port Direction Registers DDR0 7 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR3 Address : 000013H DDR4 Address : 000014H DDR5 Address : 000015H DDR6 Address : 000016H DDR7 Address : 000017H DDR8 Address : 000018H DDR9 Address : 000019H DDRA Address : 00001AH 6 5 4 3 2 1 0 Initial value Access D07 D06 D05 D04 D03 D02 D01 D 00 00000000B R/W 7 6 5 4 3 2 1 0 D17 D16 D15 D14 D13 D12 D11 D10 00000000B R/W 7 6 5 4 3 2 1 0 D27 D26 D25 D24 D23 D22 D21 D20 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B*2 R/W 00000000B R/W 00000000B R/W - - - - 0000B R/W 7 6 5 4 3 2 1 0 D37 D36 D35 D34 D33 D32 D31 D30 7 6 5 4 3 2 1 0 D47 D46 D45 D44 D43 D42 D41 D40 7 6 5 4 3 2 1 0 D57 D56 D55 D54 D53 D52 D51 D50 7 6 5 4 3 2 1 0 D67 D66 D65 D64 D63 D62 D61 D60 7 6 5 4 3 2 1 0 D75 D74 D73 D72 D71 D70 D77*1 D76* 1 7 6 5 4 3 2 1 0 D87 D86 D85 D84 D83 D82 D81 D80 7 6 5 4 3 2 1 0 D97 D96 D95 D94 D93 D92 D91 D90 7 6 5 4 3 2 1 0 DA3 DA2 DA1 DA0 *1 : The value is set to "" on MB90485 series only. *2 : The initial value of this bit is "XX000000B" on MB90485 series only. * When a set of pins is functioning as a port, the corresponding signal pins are controlled as follows. 0 : Input mode 1 : Output mode Reset to "0". Notes : * When any of these register are accessed using a read-modify-write type instruction (such as a bit set instruction) , the bit specified in the instruction will be set to the indicated value. However, the contents of output registers corresponding to any other bits having input settings will be rewritten to the input values of those pins at that time. For this reason, when changing any pin that has been used for input to output, first write the desired value to the PDR register before setting the DDR register for output. * P76, P77 (MB90485 series only) This port has no DDR. To use P77, P76 and I2C pins, set the PDR value to "1" so that port data remains enabled (to use P77 adn P76 for general purposes, disable I2C) . The port is an open drain output (with no Pch) . To use it as an input port, therefore, set the PDR to "1" to turn off the output trangistor and add a pull-up resistor to the external output. 29 MB90480/485 Series (3) Input resistance Registers RDR0 7 6 Address : 00001CH RD07 RD06 RDR1 Address : 00001DH 5 4 3 2 1 0 RD05 RD04 RD03 RD02 RD01 RD00 7 6 5 4 3 2 1 0 RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 Initial value Access 00000000B R/W 00000000B R/W These registers control the use of pull-up resistance in input mode. 0 : No pull-up resistance in input mode. 1 : With pull-up resistance in input mode. In output mode, these registers have no significance (no pull-up resistance) . Input/output mode settings are controlled by the port direction (DDR) registers. In case of a stop (SPL = 1) , no pull-up resistance is applied (high impedance) . This function is prohibited when an external bus is used. Do not write to these registers. (4) Output Pin Registers ODR7 7 Address : 00001EH ODR4 Address : 00001BH 6 OD77*1 OD76*1 5 4 3 2 1 Initial value 0 OD75 OD74 OD73 OD72 OD71 OD70 7 6 5 4 3 2 1 0 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 B 2 Access 00000000 * R/W 00000000B R/W *1 : The value is set to "" on MB90485 series only. *2 : The initial value of this bit is "XX000000B" on MB90485 series only. These registers control open drain settings in output mode. 0 : Standard output port functions in output mode. 1 : Open drain output port in output mode. In input mode these registers have no significance (Hi-Z output) . Input/output mode settings are controlled by direction (DDR) registers. This function is prohibited when an exteral bus is used. Do not write to these registers. (5) Analog Input Enable Register ADER 7 6 Address : 00001FH ADE7 ADE6 Initial value Access 5 4 3 2 1 0 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111B R/W This resister controls the port 6 pins as follows. 0 : Port input/output mode. 1 : Analog input mode. The default value at reset is all "1". (6) Up-down Timer Input Enable Register UDER 7 6 5 Address : 00000BH UDE5 4 3 2 1 0 UDE4 UDE3 UDE2 UDE1 UDE0 Initial value Access XX000000B R/W This register controls the port 3 pins as follows. 0 : Port input mode. 1 : Up/down timer input mode.The default value at reset is "0". The MB90480/485 series uses the following setting values : UDE0 : P30/AIN0, UDE1 : P31/BIN0/UDE2 : P32/ ZIN0, UDE3 : P33/AIN1, UDE4 : P34/BIN1, UDE5 : P35/ ZIN1 30 MB90480/485 Series 2. UART The UART is a serial I/O port for asynchronous (start-stop synchronized) communication as well as CLK synchronized communication. * Full duplex double buffer * Transfer modes : asynchronous (start-stop synchronized) , or CLK synchronized (no start bit or stop bit) . * Multi-processor mode supported. * Embedded proprietary baud rate generator Asynchronous : 76923/38461/19230/9615/500 K/250 Kbps CLK synchronized : 16 M/8 M/4 M/2 M/1 M/500 Kbps * External clock setting available, allows use of any desired baud rate. * Can use internal clock feed from PPG1. * Data length : 7-bit (asynchronous normal mode only) or 8-bit. * Master/slave type communication functions (in multi-processor mode) . * Error detection functions (parity, framing, overrun) * Transmission signals are NRZ encorded. * DMAC supported (for receiving/sending) 31 MB90480/485 Series (1) Register List 8 7 15 0 CDCR SCR SMR SSR SIDR (R)/SODR (W) 8 bit 8 bit Serial mode register (SMR) 000020H 7 6 5 4 3 2 1 0 MD1 MD0 CS2 CS1 CS0 Reserved SCKE SOE R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W X Initial value Serial control register (SCR) 000021H 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 W 1 R/W 0 R/W 0 Initial value Serial I/O register (SIDR/SODR) 000022H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Initial value Serial data register (SSR) 000023H 15 14 13 12 11 10 9 8 PE ORE FRE RDRF TDRE BDS RIE TIE R 0 R 0 R 0 R 0 R 1 R/W 0 R/W 0 R/W 0 Initial value Communication prescaler control register (CDCR) 000025H 32 15 14 13 12 11 10 9 8 MD SRST DIV3 DIV2 DIV1 DIV0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Initial value MB90480/485 Series (2) Block Diagram Control signal Receiving interrupt (to CPU) Proprietary baud rate generator PPG1 (internal connection) SCK0 Clock select circuit Sending clock Sending interrupt (to CPU) Receiving control circuit External clock SIN0 Receiving control circuit Start bit detect circuit Sending control circuit Send start circuit Receive bit counter Send bit counter Receiving parity counter Send parity counter SOT0 Receiving status decision circuit DMAC receiving error generation circuit (to CPU) Receiving shifter Sending shifter Receiving control circuit Sending start SIDR SODR F2MC-16LX BUS SMR register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR register PEN P SBL CL A/D REC REX TXE SSR register PE ORE FRE RDRF TDRE BDS RIE TIE Control signal 33 MB90480/485 Series 3. Expanded I/O Serial Interface The expanded I/O serial interface is an 8-bit x 1-channel serial I/O interface for clock synchronized data transmission. A selection of LSB-first or MSB-first data transmission is provided. There are two serial I/O operation modes. * Internal shift clock mode : Data transmission is synchronized with the internal clock siganl. * External shift clock mode : Data transmission is synchronized with a clock signal input from the external clock signal pin (SCK) . In this mode the general-purpose port that shares the external clock signal pin (SCK) can be used for transmission according to CPU instructions. (1) Register List Serial mode control status register (SMCS) 000027H Address : 00002BH 000026H Address : 00002AH 15 14 13 12 11 10 9 8 Initial value SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT 00000010B R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 MODE BDS SOE SCOE R/W R/W R/W R/W ----0000B Serial data register (SDR) Address : 000028H 00002CH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W XXXXXXXXB Communication prescaler control register (SDCR0, SDCR1) 000029H Address : 00002DH 34 15 14 13 12 11 10 9 8 MD DIV3 DIV2 DIV1 DIV0 R/W R/W R/W R/W R/W 0---0000B MB90480/485 Series (2) Block Diagram Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Transfer direction selection Initial value SIN1, SIN2 SDR (Serial Data Register) Read Write SOT1, SOT2 SCK1, SCK2 Control circuit Shift clock counter Internal clock 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE Interrupt request Internal data bus 35 MB90480/485 Series 4. 8/10-bit A/D Converter The A/D converter converts analog input voltage input voltages to digital values, and provides the following features. * Conversion time : minimum 3.68 s per channel (92 machine cycles at 25 MHz machine clock, including sampling time) * Sampling time : minimum 1.92 s per channel (48 machine cycles at 25 MHz machine clock) * RC sequential comparison conversion method, with sample & hold circuit. * 8-bit or 10-bit resolution * Analog input selection of 8 channels Single conversion mode : Conversion from one selected channel. Scan conversion mode : Conversion from multiple consecutive channels, programmable selection of up to 8 channels. Continuous conversion mode : Repeated conversion of specified channels. Stop conversion mode : Conversion from one channel followed by a pause until the next activation. * At the end of A/D conversion, an A/D conversion completed interrupt request can be generated. The interrupt can be used activate the DMA in order to transfer the results of A/D conversion to memory for efficient continuous processing. * The starting factor conversion may be selected from software, external trigger (falling edge) , or timer (rising edge) . (1) Register List ADCS2, ADCS1 (Control status register) ADCS1 bit 7 6 5 Address : 000046H MD1 MD0 ANS2 ADCS2 bit Address : 000047H 36 3 2 1 0 ANS1 ANS0 ANE2 ANE1 ANE0 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 BUSY INT INTE PAUS STS1 STS0 STRT Reserved 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 W 0 R/W 6 5 4 3 2 1 0 D6 D5 D4 D3 D2 D1 D0 X R X R X R X R X R X R X R X R 15 14 13 12 11 10 9 8 S10 ST1 ST0 CT1 CT0 D9 D8 0 R/W 0 W 0 W 0 W 0 W X R X R X R ADCR2, ADCR1 (Data register) ADCR1 bit 7 Address : 000048H D7 ADCR2 bit Address : 000049H 4 Initial value Bit attributes Initial value Bit attributes Initial value Bit attributes Initial value Bit attributes MB90480/485 Series (2) Block Diagram AVCC AVRH AVSS D/A converter MP Input circuit Sequential comparison register Comparator Data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 decoder Sample & hold circuit Data registers ADCR1, ADCR2 A/D control register 1 ADTG Trigger activation Timer (PPG1 output) Timer activation A/D control register 2 ADCS1, ADCS2 Operation clock Prescaler 37 MB90480/485 Series 5. 8/16-bit PPG The 8/16-bit PPG is an 8-bit reload timer module that produces a PPG output using a pulse from the timer operation. Hardware resources include 6 x 8-bit down counters, 12 x 8-bit reload timers, 3 x 16-bit control registers, 6 external bus output pins, and 6 interrupt outputs. Note that MB90480/485 series has six channels for 8-bit PPG use, which can also be combined as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 to operate as a three-channel 16-bit PPG. The following is a summary of functions. * 8-bit PPG output 6-channel independent mode : Provides PPG output operation on six independent channels. * 16-bit PPG output operation mode : Provides 16-bit PPG output on three channels. The six original channels are used in combination as PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5. * 8 + 8-bit PPG operation mode : Output from PPG0 (PPG2/PPG4) is used as clock input to PPG1 (PPG3/ PPG5) to provide to 8-bit PPG output at any desired period length. * PPG output operation : Produces pulse waves at any desired period and duty ratio. The PPG module can also be used with external cirsuits as a D/A converter. (1) Register List PPGC0 (PPG0/2/4 operation mode control register) 00003AH 00003CH 00003EH 7 6 5 4 3 2 1 0 PEN0 PE00 PIE0 PUF0 Reserved R/W 0 X R/W 0 R/W 0 R/W 0 X X 1 Read/write Initial value PPGC1 (PPG1/3/5 operation mode control register) 00003BH 00003DH 00003FH 15 14 13 12 11 10 9 8 PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved R/W 0 X R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1 1 0 Read/write Initial value PPG01/PPG23/PPG45 (PPG0 to PPG5 output control register) 000040H 000042H 000044H 7 6 5 4 3 PCS2 PCS1 PCS0 PCM2 PCM1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 4 3 2 1 0 D04 D03 D02 D01 D00 R/W X R/W X R/W X R/W X R/W X PPLL0 to PPLL5 (Reload register L) 00002EH 7 6 5 000030H D07 D06 D05 000032H R/W R/W R/W 000034H X X X 000036H 000038H PPLH0 to PPLH5 (Reload register H) 00002FH 15 14 13 000031H D15 D14 D13 000033H R/W R/W R/W 000035H X X X 000037H 000039H 38 2 PCM0 Reserved Reserved 12 11 10 9 8 D12 D11 D10 D09 D08 R/W X R/W X R/W X R/W X R/W X Read/write Initial value Read/write Initial value Read/write Initial value MB90480/485 Series (2) Block Diagram * 8-bit PPG channel 0/2/4 block Diagram Peripheral clock x 16 Peripheral clock x 8 Peripheral clock x 4 Peripheral clock x 2 Peripheral clock PPG0/2/4 output enable PPG0/2/4 A/D converter PPG0/2/4 output latch PEN0 S R Q PCNT (down counter) Count clock select IRQ ch1/3/5 borrow L/H selector Timebase counter output main clock x 512 L/H select PUF0 PRLL PIE0 PRLBH PPGC0 (operation mode control) PRLL L data bus H data bus 39 MB90480/485 Series * 8-bit PPG ch1/3/5 Block Diagram Peripheral clock x 16 Peripheral clock x 8 Peripheral clock x 4 Peripheral clock x 2 Peripheral clock PPG1/3/5 output enable PPG1/3/5 UART0 PPG1/3/5 output latch PEN1 S R Q PCNT (down counter) IRQ Count clock select L/H selector Timebase counter output main clock x 512 PUF1 PIE1 L/H select PRLL PRLBH PPGC1 (operation mode control) PRLL L data bus H data bus 40 MB90480/485 Series 6. 8/16-bit up/down Counter/Timer 8/16-bit up/down counter/timer consists of up/down counter/timer circuits including six event input pins, two 8bit up/down counters, two 8-bit reload/compare registers, as well as the related control circuits. (1) Principal Functions * 8-bit count register enables counting in the range 0 to 256. (In 16-bit x 1 mode, counting is enabled in the range 0 to 65535) * Count clock selection provides four count modes. Count modes Timer mode Up down count mode Phase differential count mode ( x 2) Phase differential count mode ( x 8) * In timer mode, there is a choice of two internal count clock signals. Count clock 125 ns (8 MHz : x 2) (at 16 MHz operation) 0.5 s (2 MHz : x 8) * In up/down count mode there is a choice of trigger edge detection for the input signal from external pins. Edge detection Falling edge detection Rising edge detection Both rising/falling edge detection Edge detection disabled * In phase differential count mode, to handle encoder counting for mortors, the encode A-phase, B-phase, and Z-phase are each input, enabling easy and highly accurate counting of angle of rotation, speed of rotation, etc. * The ZIN pin provides a selection of two functions ZIN pin Counter clear function Gate functions * A compare function and reload function are provided, each for use separately or in combination. Both functions can be activated together for up/down counting in any desired bandwidth. Compare/reload function Compare function (output interrupt at compare events) Compare function (output interrupt and clear counter at compare events) Reload function (output interrupt and reload at underflow events) Compare/reload function (output interrupt and clear counter at compare events, output interrupt and reload at underflow events) Compare/reload disabled * Individual control over interrupts at compare, reload (underflow) and overflow events. * Count direction flag enables identification of the last previous count direction. * Interrupt generated when count direction changes. 41 MB90480/485 Series (2) Register List 8 7 15 0 UDCR1 UDCR0 RCR1 RCR0 Reserved area CSR0 CCRH0 CCRL0 Reserved area CSR1 CCRH1 CCRL1 8 bit 8 bit CCRH0 (Counter Control Register High ch.0) Address : 00006DH 15 14 13 12 11 10 9 8 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B CCRH1 (Counter Control Register High ch.1) Address : 000071H 15 14 13 12 11 10 9 8 CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W Initial value -0000000B CCRL0/1 (Counter Control Register Low ch.0/1) Address : 00006CH Address : 000070H 7 6 5 4 3 2 1 0 UDMS CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W W R/W R/W W R/W R/W R/W Initial value 0X00X000B CSR0/1 (Counter Status Register ch.0/1) Address : 000072H Address : 000074H 7 6 5 4 3 2 1 0 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 R/W R/W R/W R/W R/W R/W R R Initial value 00000000B UDCR0/1 (Up Down Count Register ch.0/1) Address : 000069H Address : 000068H 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 R R R R R R R R 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 R R R R R R R R Initial value 00000000B Initial value 00000000B RCR0/1 (Reload/Compare Register ch.0/1) Address : 00006BH Address : 00006AH 42 15 14 13 12 11 10 9 8 D17 D16 D15 D14 D13 D12 D11 D10 W W W W W W W W 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 W W W W W W W W Initial value 00000000B Initial value 00000000B MB90480/485 Series (3) Block Diagram Data bus 8 bit RCR0 (Reload/ compare register 0) CGE1 CGE0 CGSC ZIN0 Edge/level detection CTUT Reload control UCRE RLDE Counter clear UDCC 8 bit UDCR0 (Up/down count register 0) Carry CES1 CES0 CMS1 CMS0 UDFF OVFF Count clock UDMS AIN0 BIN0 Up/down count clock selection Prescaler CMPF CITE UDIE UDF1 UDF0 CDCF CFIE CSTR Interrupt output CLKS 43 MB90480/485 Series 7. DTP/External Interrupt The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the F2MC16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes the requests to the F2MC-16LX CPU to activate the extended intelligent DMA or interrupt processing. (1) Detailed Register Descriptions Interrupt/DTP Enable Register (ENIR : Enable Interrupt Request Register) ENIR 7 6 5 4 3 2 1 Address : 00000CH EN7 EN6 EN5 EN4 EN3 EN2 EN1 R/W R/W R/W R/W R/W R/W 0 EN0 R/W R/W Interrupt/DTP Source Register (EIRR : External Interrupt Request Register) EIRR 15 14 13 12 11 10 9 Address : 00000DH ER7 ER6 ER5 ER4 ER3 ER2 ER1 R/W R/W R/W R/W R/W Initial value 00000000B 8 ER0 R/W R/W R/W 2 1 0 Initial value XXXXXXXXB Interrupt Level Setting Register (ELVR : External Level Register) 7 Address : 00000EH Address : 00000FH 6 5 4 3 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B Initial value 00000000B (2) Block Diagram F2MC-16 bus 4 4 4 8 44 Interrupt/DTP enable register Gate Source F/F Interrupt/DTP source register Interrupt level setting register Edge detection circuit 4 Request input MB90480/485 Series 8. 16-bit Input/Output Timer The 16-bit input/output timer module is composed of one 16-bit free run timer, six output compare and two input capture modules. These functions can be used to output six independent waveforms based on the 16-bit free run timer, enabling input pilse width measurement and external clock frequency measurement. * Register List * 16-bit free run timer 15 0 Compare-clear register 000066/67H CPCLR 000062/63H TCDT Timer data register 000064/65H TCCS Control status register * 16-bit output compare 15 0 00004A, 4C, 4E, 50, 52, 54H 00004B, 4D, 4F, 51, 53, 55H Compare register OCCP0 to OCCP5 000056, 58, 5AH 000057, 59, 5BH OCS1/3/5 Control status registers OCS0/2/4 * 16-bit input capture 15 00005C, 5EH 00005D, 5FH 000060H 0 Compare register IPCP0, IPCP1 ICS Control status register 45 MB90480/485 Series * Block Diagram Control logic To each block Interrupt 16-bit free run timer 16-bit timer Bus Clear 46 Output compare 0 Compare register 0 TQ OUT0 Output compare 1 Compare register 1 TQ OUT1 Output compare 2 Compare register 2 TQ OUT2 Output compare 3 Compare register 3 TQ OUT3 Output compare 4 Compare register 4 TQ OUT4 Output compare 5 Compare register 5 TQ OUT5 Input capture 0 Capture register 0 Edge selection IN0 Input Capture 1 Capture register 1 Edge selection IN1 MB90480/485 Series (1) 16-bit Free Run Timer The 16-bit free run timer is composed of a 16-bit up-down counter and control status register. The counter value of this timer is used as the base timer for the input capture and output compare. * The counter operation provides a choice of eight clock types. * A counter overflow interrupt can be produced. * A mode setting is available to initialize the counter value whenever the output compare value matches the value in the compare clear register. * Register List Compare clear register (CPCLR) 000067H 000066H 15 14 13 12 11 10 9 8 CL15 CL14 CL13 CL12 CL11 CL10 CL09 CL08 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00 R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB Initial value XXXXXXXXB Timer counter data register (TCDT) 000063H 000062H 15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 T07 T06 T05 T04 T03 T02 T01 T00 R/W R/W R/W R/W R/W R/W R/W R/W 13 12 11 10 9 8 Initial value 00000000B Initial value 00000000B Timer counter control/status register (TCCS) 15 000065H 000064H 14 ECKE MSI2 MSI1 MSI0 ICLR ICRE R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0--00000B Initial value 00000000B 47 MB90480/485 Series * Block Diagram Interrupt request IVF Multiplier IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Bus Clock 16-bit free run timer Count value output T15 to T00 16-bit compare clear register Compare circuit MSI3 to MSI0 ICLR ICRE Interrupt request A/D activation 48 MB90480/485 Series (2) Output Compare The output compare module is composed of a 16-bit compare register, compare output pin group, and control register. When the value in the compare register in this module matches the 16-bit free run timer, the pin output levels can be inverted and an interrupt generated. * There are six compare registers in all, each operating independently. A setting is available to allow two compare registers to be used to control output. * Interrupts can be set in terms of compare match events. * Register List Compare registers (OCCP0 to OCCP5) 00004BH 00004DH 00004FH 000051H 000053H 000055H 00004AH 00004CH 00004EH 000050H 000052H 000054H 15 14 13 12 11 10 9 8 C15 C14 C13 C12 C11 C10 C09 C08 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 ICPIC ICP0 ICE1 ICE0 CST1 CST0 R/W R/W R/W R/W R/W R/W Initial value 00000000B Initial value 00000000B Control registers (OCS1/3/5) 000057H 000059H 00005BH Initial value ---00000B Control registers (OCS0/2/4) 000056H 000058H 00005AH Initial values 0000--00B 49 MB90480/485 Series * Block Diagram 16-bit timer counter value (T15 to T00) Compare control TQ OTE0 OUT0 (2) (4) OTE1 OUT1 (3) (5) Compare register 0 (2, 4) CMOD Bus 16-bit timer counter value (T15 to T00) Compare control TQ Compare register 1 (3, 5) ICP1 Control unit Individual control blocks 50 ICP0 ICE0 ICE0 Compare 1 (3) (5) interrupt Compare 0 (2) (4) interrupt MB90480/485 Series (3) Input Capture The input capture module performs the functions of detecting the rising edge, falling edge, or both edges of signal input from external circuits, and saving the 16-bit free run timer value at that moment to a register. An interrupt can also be generated at the instant of edge detection. The input capture module consists of input capture registers and a control register. Each input capture module has its own external input pin. * Section of three types of valid edge for external input signals. Rising edge, falling edge, both edges. * An interrupt can be generated when a valid edge is detected in the external input signal. * Register List Input capture data register (IPCP0, IPCP1) 00005DH 00005FH 00005CH 00005EH 15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R R R R R R R R 7 6 5 4 3 2 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R R R R R R R R 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB Initial value XXXXXXXXB Control status register (ICS0, ICS1) 000060H Initial value 00000000B * Block Diagram Bus Capture data register 0 Edge detection 16-bit timer counter value (T15 to T00) EG11 EG10 EG01 EG00 Capture data register 1 ICP1 Edge detection ICP0 IN0 ICE1 IN1 ICE0 Interrupt Interrupt 51 MB90480/485 Series 9. I2C Interface (MB90485 series only) The I2C interface is a serial I/O port supporting the Inter IC BUS. Serves as a master/slave device on the I2C bus. The I2C interface has the following functions. * Master/slave transmit/receive * Arbitration function * Clock synchronization * Slave address/general call address detection function * Forwarding direction ditection function * Start condition repeated generation and detection * Bus error detection function (1) Register List Bus Status Register (IBSR) 7 6 5 BB RSC AL R R R 000088H 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0B LRB TRX AAS GCA FBT R R R R R Bus control register (IBCR) 000089H 15 14 13 12 11 10 9 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W R/W R/W R/W R/W R/W Initial value 8 R/W 0 0 0 0 0 0 0 0B Clock control register (ICCR) 7 00008AH 6 5 4 3 2 1 0 EN CS4 CS3 CS2 CS1 CS0 R/W R/W R/W R/W R/W R/W Initial value - - 0 XXXXXB Address register (IADR) 00008BH 15 14 13 12 11 10 9 8 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W Initial value - XXXXXXXB Data register (IDAR) 00008CH 52 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB MB90480/485 Series (2) Block Diagram ICCR I2C enable EN Clock dividing 1 5 F2MC-16LX Bus ICCR CS4 6 7 Peripheral clock 8 Clock selection 1 CS3 Clock dividing 2 CS2 2 4 8 16 32 64 128 256 CS1 CS0 Sync Shift clock generation Clock selection 2 Change timing of shift clock edge IBSR BB RSC Bus busy Repeat start Last Bit LRB Start/stop condition detection Transmission/ Reception Error TRX First Byte FBT Arbitration lost detection AL IBCR SCL BER BEIE Interrupt request IRQ SDA INTE INT IBCR SCC MSS ACK End Start Master ACK enable Start/stop condition generatiion GC-ACK enable GCAA IDAR IBCR AAS GCA Slave Global call Slave address comparison IADR 53 MB90480/485 Series 10. 16-bit Reload Timer The 16-bit reload timer provides a choice of functions, including internal clock signals that count down in synchronization with three types of internal clock, as well as an event count mode that counts down at specified edge detection events in pulse signals input from external pins. This timer defines an underflow as a change in count value from 0000H to FFFFH.Thus an underflow will occur when counting from the value "reload register setting value + 1". The choice of counting operations includes reload mode, in which the count setting values is reload and counting continues following an underflow event, and one-shot mode, in which an underflow event causes counting to stop. An interrupt can be generated at counter underflow, and the timer is DTC compatible. (1) Register List * TMCSR (Timer control status register) Timer control status register (high) (TMCSR) 0000CBH 15 14 13 12 11 10 9 8 CSL1 CSL0 MOD2 MOD1 R/W 0 R/W 0 R/W 0 R/W 0 Read/Write Initial value Timer control status register (low) (TMCSR) 0000CAH 7 6 5 4 3 2 1 0 MOD0 OUTE OUTL RELD INTE UF CNTE TRG R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Read/Write Initial value * 16-bit timer register/16-bit reload register TMR/TMRLR (high) 0000CDH 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D09 D08 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Read/Write Initial value TMR/TMRLR (low) 0000CCH 54 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X Read/Write Initial value MB90480/485 Series (2) Block Diagram Internal data bus TMRLR 16-bit reload register Reload signal Reload control circuit TMR 16-bit timer register (down counter) UF CLK Count clock generator circuit machine clock Prescaler 3 Gate input Valid clock detection circuit Clear Wait signal CLK to A/D converter Output signal generation circuit Inverted Pin (TIN0) Input control circuit Clock selector External clock EN OUTL Function selection 3 Select signal Pin (TOT0) Output signal generation circuit 2 RELD Operation control circuit OUTE Timer control status register (TMCSR) 55 MB90480/485 Series 11. PG Timer (MB90485 only) The PG timer performs pulse output in response to the external input. (1) Register List PG control status register (PGCSR) Initial value 00008EH 7 6 5 4 3 PEN0 PE1 PE0 PMT1 PMT0 R/W R/W R/W R/W R/W 2 1 0 00000---B (2) Block Diagram MT00 MT01 MT00 Output latch Control circuit 56 MT00 Output latch Output enable EXTC MB90480/485 Series 12. PWC Timer (MB90485 only) The PWC timer is a 16-bit multifunction up-count timer capable of measuring the pulse width of the input signal. A total of three channels are provided, each consisting of a 16-bit up-count timer, an input pulse divider & divide ratio control register, a measurement input pin, and a 16-bit control register. These components provide the following functions. Timer function : * Capable of generating an interrupt request at fixed intervals specified. * The internal clock used as the reference clock can be selected from among three types. Pulse width measurement function : * Measures the time between arbitrary events based on external pulse inputs. * The internal clock used as the reference clock can be selected from among three types. * Measurement modes - H pulse width ( to ) /L pulse width ( to ) - Rising cycle ( to ) /Falling cycle ( to ) - Measurement between edges ( or to or ) * The 8-bit input divider can be used for division measurement by dividing the input pulse by 22 ns (n = 1, 2, 3, 4) . * An interrupt can be generated upon completion of measurement. * One-time measurement or fast measurement can be selected. 57 MB90480/485 Series (1) Register list PWC control status register (PWCSR0 to PWCSR2) 000077H 00007BH 00007FH 15 14 13 12 11 10 9 STRT STOP EDIR EDIE OVIR OVIE R/W R/W R R/W R/W R/W R 2 1 8 Initial value 0000000XB ERR Reserved PWC control status register (PWCSR0 to PWCSR2) 000076H 00007AH 00007EH 7 6 5 4 3 0 CKS1 CKS0 PIS1 PIS0 S/C R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B MOD2 MOD1 MOD0 PWC data buffer register (PWCR0 to PWCR2) 000079H 00007DH 000081H 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W 3 2 1 0 Initial value 00000000B PWC data buffer register (PWCR0 to PWCR2) 000078H 00007CH 000080H 7 6 5 4 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B Dividing ratio control register (DIVR0 to DIVR2) 000082H 000084H 000086H 58 7 6 5 4 3 2 1 0 - - - - - - DIV1 DIV0 - - - - - - R/W R/W Initial value ------00B MB90480/485 Series (2) Block Diagram PWCR read Error detection ERR Internal clock (machine clock/4) PWCR 16 Reload Data transfer 16 22 Clock Overflow 16-bit up count timer Clock divider 23 F2MC-16 Bus Timer clear Count enable Control bit output Flagset etc. Control circuit Start edge selection Completion edge selection Start of measurement edge CKS1/CKS0 Dividing ON/OFF Input waveform comparator Edge detection Completion of measurement edge PWC0 PWC1 PIS0/PIS1 Completion of measurement interrupt request Overflow interrupt request PWCSR ERR 8-bit divider CKS0/ CKS1 Dividing ratio selection 15 2 DIVR 59 MB90480/485 Series 13. Watch Timer The watch timer is a 15-bit timer using the sub clock. This circuit can generate interrupts at predetermined intervals. Also a setting is available to enable it to be used as the clock source for the watchdog timer. (1) Register List Watch timer control register (WTC) 0000AAH 7 6 5 4 3 2 1 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 R/W 1 R 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 WTC2 WTC1 WTC0 Read/write Initial value (2) Block Diagram Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR Clear 28 29 Sub clock Watch counter 210 211 Interval sector Interrupt generator circuit Watch timer interrupt 212 213 210 213 214 215 214 To watchdog timer 60 MB90480/485 Series 14. Watchdog timer The watchdog timer is a 2-bit counter that uses the output from the timebase timer or watch timer as acount clock signal, and will reset the CPU if not cleared within a predetermined time interval after it is activated. (1) Register List Watchdog timer control register (WDTC) 0000A8H 7 6 5 4 3 2 1 0 PONR Reserved WRST ERST SRST WTE WT1 WT0 R X X R X R X R X W 1 W 1 W 1 Read/write Initial value (2) Block Diagram Watchdog timer control register (WDTC) Re- PONR served WRST ERST SRST WTE WT1 WT0 2 Watch mode start Timebase timer mode start Sleep mode start Watchdog timer Hold status start CLR and start Count clock selector Counter clear circuit Stop mode start 2-bit counter CLR Watch timer control register (WTO) WDCS bit Clock select register (CKSCR) SCM bit CLR Watchdog reset generator circuit Internal reset generator circuit 4 4 Clear Time-base counter HCLK x 2 SCLK x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 x 21 x 2 2 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 HCLK : Oscillator clock SCLK : Sub clock 61 MB90480/485 Series 15. Timebase Timer The timebase timer is an 18-bit free run counter (timebase counter) that counts up in synchronization with the internal count clock signal (base oscillator x 2) , and functions as an interval timer with a choice of four types of time intervals. Other functions provided by this module include timer output for the oscillator stabilization wait period, and operating clock signal feed for other timer circuits such as the watchdog timer. (1) Register List Timebase timer control register (TBTC) 0000A9H 15 14 13 12 11 10 9 8 RESV TBIE TBOF TBR TBC1 TBC0 R/W 1 X X R/W 0 R/W 0 W 1 R/W 0 R/W 0 Read/write Initial value (2) Block Diagram to PPG timer To watchdog timer Timebase timer counter HCLK x 2 x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 Power-on reset Stop mode start Hold status start CKSCR : MCS = 10*1 CKSCR : SCS = 01*2 Counter clear control circuit OF OF OF OF Clock control module Oscillator stabilization wait To time selector Interval timer selector TBOF set TBOF clear Timebase timer control register (TBTC) RESV TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt signal OF HCLK *1 *2 62 : Not used : Overflow : Oscillator clock : Switch machine clock from main clock or sub clock to PLL clock. : Switch machine clock from sub clock to main clock. MB90480/485 Series 16. Clock The clock generator module controls the operation of the internal clock circuits that serve as the operating clock for the CPU and peripheral devices. This internal clock is referred to as the machine clock, and one cycle os refferd to as a machine cycle. Also, the clock signals from the base oscillator are called the oscillator clock, and those from the PLL oscillator are called the PLL clock. (1) Register List Clock select register (CKSCR) 0000A1H 15 14 13 12 11 10 9 8 SCM MCM WS1 WS0 SCS MCS CS1 CS0 R 1 R 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 0 R/W 0 Read/write Initial value PLL output select register (PLLOS) 0000CFH 15 14 13 12 11 10 9 8 PLL2 W X W 0 Read/write Initial value 63 MB90480/485 Series (2) Block Diagram Standby control circuit Low-power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin high-impedance control Pin high-impedance control circuit RST Internal reset generator circuit pin CPU internal operation selector Internal reset Intermittent cycle selection CPU clock control circuit Standby control circuit Interrupt release Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Peripheral clock Oscillator stabilization wait release Clock generator module PLL output select register (PLLOS) Clock selector Oscillator stabilization wait period selector PLL2 2 x 4 SCLK 2 PLL multiplier circuit Sub clock generator circuit X0A pin X1A pin SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) System clock generator circuit x2 HCLK X0 pin X1 pin x 1024 x2 x4 x4 x4 MCLK Timebase timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock 64 CPU clock To watchdog timer x2 MB90480/485 Series (3) Clock Feed Map 4 Peripheral functions Watchdog timer 4 Clock generator module X0A Sub clock generator circuit pin X1A pin Watch timer 8/16-bit PPG timer 0 Timebase timer 8/16-bit PPG timer 1 1 8/16-bit PPG timer 2 2 3 PLL multiplier circuit x4 SCLK X0 pin X1 pin 4 System clock x2 generator HCLK circuit MCLK Clock selector PPG0, PPG1 pins PPG2, PPG3 pins PPG4, PPG5 pins TIN0 PCLK 16-bit reload timer 0 pin TOT0 pin SCK0, SIN0 pins UART0 SOT0 pin CPU, DMAC SCK1, SCK2 SIN1, SIN2 I/O expanded serial interface, 2ch 8/16-bit U/D counter pins SOT1, SOT2 pins AIN0, AIN1 BIN0, BIN1 ZIN0, ZIN1 pins CS0, CS1, CS2, CS3 Chip select 16-bit output compare 16-bit free run timer 16-bit input capture 10-bit A/D converter pins OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 pins FRCK pin IN0, IN1 pins AN0 to AN7, ADTG pins IRQ0 to IRQ7 HCLK MCLK SCLK PCLK : Oscillator clock : Main clock : Sub clock : PLL clock : Machine clock External interrupt 3 pin Oscillator stabilization wait control 65 MB90480/485 Series 17. Low-power Consumption Mode The MB90480/485 series uses operating clock selection and clock operation controls to provide the following CPU operating modes : * Clock modes (PLL clock mode, main clock mode, sub clock mode) * CPU intermittent operating modes (PLL clock intermittent mode, main clock intermittent mode, sub clock intermittent mode) * Standby modes (Sleep mode, timebase timer mode, stop mode, watch mode) (1) Register List Low-power mode control register (LPMCR) 0000A0H 66 7 6 5 4 3 2 1 0 STP SLP SPL RST TMD CG1 CG0 Reserved W 0 W 0 R/W 0 W 1 R/W 1 R/W 0 R/W 0 R/W 0 Read/write Initial value MB90480/485 Series (2) Block Diagram Standby control circuit Low-power mode control register (LPMCR) Re- STP SLP SPL RST TMD CG1 CG0 served RST Pin high-impedance control circuit Pin high-impedance control Internal reset generator circuit pin CPU intermittent operating selector Internal reset Intermittent cycle selection CPU clock control circuit Standby control circuit Interrupt release CPU clock Stop, sleep signals Stop signal Peripheral clock control circuit Machine clock Peripheral clock Oscillator stabilization wait release Clock generator PLL output select register (PLLOS) Clock selector Oscillator stabilization wait period selector PLL2 2 x 4 SCLK 2 PLL multiplier circuit Sub clock generator circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR) System clock generator circuit X0A pin X1A pin X0 pin X1 pin x2 HCLK x 1024 x2 x4 x4 x4 x2 MCLK Timebase timer To watchdog timer HCLK : Oscillator clock MCLK : Main clock SCLK : Sub clock 67 MB90480/485 Series (3) Status Transition Chart External reset, watchdog timer reset, software reset Power-on reset Reset SCS = 0 Power-on reset SCS = 1 Main clock mode Oscillator stabilization wait ends SLP = 1 MCS = 0 PLL clock mode MCS = 1 Interrupt SLP = 1 Interrupt Timebase timer mode STP = 1 Interrupt 68 Interrupt TMD = 0 Interrupt Timebase timer mode STP = 1 Main stop mode Oscillator stabilization wait ends Sub clock mode SCS = 1 SLP = 1 PLL sleep mode Main sleep mode TMD = 0 SCS = 0 Interrupt Sub sleep mode TMD = 0 Interrupt Watch mode STP = 1 PLL stop mode Interrupt Oscillator stabilization wait ends Sub stop mode Interrupt Oscillator stabilization wait ends Main clock oscillator Main clock oscillator Sub clock oscillator stabilization wait stabilization wait stabilization wait MB90480/485 Series 18. External Bus Pin Control Circuit The external bus pin control circuit controls the external bus pins used to expand the CPU address/data bus connections to external circuits. (1) Register List * Auto ready function select register (ARSR) Address : 0000A5H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 IOR1 IOR0 HMR1 HMR0 LMR1 LMR0 W W W W W W Initial value 0011- - 00B * External address output control register (HACR) Address : 0000A6H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 E23 E22 E21 E20 E19 E18 E17 E16 W W W W W W W W Initial value ********B * Bus control signal select register (EPCR) Address : 0000A7H W - * bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 CKE RYE HDE IOBS HMBS WRE LMBS W W W W W W W Initial value 1000*10 -B : Write only : Not used : May be either "1" or "0" (2) Block Diagram P5 P0 P0 data P1 P2 P3 P4 P5 P0 P0 direction RB Data control Address control Access control Access control 69 MB90480/485 Series 19. Chip Select Function Description The chip select module generators a chip select signals, which are used to facilitate connections to external memory devices. The MB90480/485 series has four chip select output pins, each having a chip select area register setting that specifies the corresponding hardware area and select signal that is output when access to the corresponding external address is detected. * Chip select function features The chip select function uses two 8-bit registers for each output pin. One of these registers (CARx) is able to detect memory areas in 64 Kbyte units by specifying the upper 8-bit of the address for match detection. The other register (CMRx) can be used to expand the detection area beyond 64 Kbytes by masking bits for match detection. Note that during external bus holds, the CS output is set to high impedance. (1) Register List 8 7 15 0 R/W CAR0 CMR0 R/W CAR1 CMR1 R/W CAR2 CMR2 R/W CAR3 CMR3 R/W CALR CSCR R/W Chip select area mask register (CMRx) 0000C0H 0000C2H 0000C4H 0000C6H 7 6 5 4 3 2 1 0 M7 M6 M5 M4 M3 M2 M1 M0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 Read/write initial value Chip select area register (CARx) 0000C1H 0000C3H 0000C5H 0000C7H 15 14 13 12 11 10 9 8 A7 A6 A5 A4 A3 A2 A1 A0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Read/write initial value Chip select control register (CSCR) 0000C8H 7 6 5 4 3 2 1 0 OPL3 OPL2 OPL1 OPL0 R/W 0 R/W 0 R/W 0 R/W * Read/write initial value Chip select active level register (CALR) 0000C9H 15 14 13 12 11 10 9 8 ACTL3 ACTL2 ACTL1 ACTL0 R/W 0 R/W 0 R/W 0 R/W 0 * : The initial value of this bit is "1" or "0". The value depends on the mode pin (MD2, MD1 and MD0) . 70 Read/write initial value MB90480/485 Series F2MC-16LX Bus (2) Block Diagram CMRx CARx Chip select output pins A23 to A16 71 MB90480/485 Series 20. ROM Mirror Function Select Module The ROM mirror function selection module sets the data in ROM assigned to FF bank so that the data is read by access to 00 bank. (1) Register List * ROM mirror function select register (ROMM) bit 15 14 Address : 00006FH 13 12 11 10 9 8 MS MI R/W R/W Initial value - - - - - -01B - : Not used (2) Block Diagram F2MC-16LX bus ROM mirror function select Address area 00 bank FF bank ROM Note : Do not access ROM mirror function selection register (ROMM) on using the area of address 004000H to 00FFFFH (008000H to 00FFFFH) . 72 MB90480/485 Series 21. Interrupt Controller The interrupt control register is built in interrupt control, and is supported for all I/O of interrupt function. This register set corresponding peripheral interrupt level. (1) Register List Interrupt control registers Address : ICR01 ICR03 ICR05 ICR07 ICR09 ICR11 ICR13 ICR15 0000B1H 0000B3H 0000B5H 0000B7H 0000B9H 0000BBH 0000BDH 0000BFH bit Read/write Initial value 15 14 13 12 11 10 Reserved W X W X W X W X R/W 0 9 8 IL2 IL1 IL0 R/W 1 R/W 1 R/W 1 ICR01, 03, 05, 07, 09, 11, 13, 15 Interrupt control registers Address : ICR00 ICR02 ICR04 ICR06 ICR08 ICR10 ICR12 ICR14 0000B0H 0000B2H 0000B4H 0000B6H 0000B8H 0000BAH 0000BCH 0000BEH bit Read/write Initial value 7 6 5 4 3 Reserved W X W X W X W X R/W 0 2 1 0 IL2 IL1 IL0 R/W 1 R/W 1 R/W 1 ICR00, 02, 04, 06, 08, 10, 12, 14 Note : The use of access involving read-modify-write instructions may lead to abnormal operation, and should be avoided. 73 MB90480/485 Series (2) Block Diagram F2MC-16LX Bus 3 74 IL2 IL1 IL0 3 32 Interrupt requests (Peripheral resources) 3 (CPU) Interrupt level Interrupt priority setting MB90480/485 Series 22. DMAC The DMAC is a simplified DMA module with functions equivalent to EI2OS. The DMA has 16 DMA data transfer channels, and provides the following functions. * Automatic data transfer between peripheral resources (I/O) and memory. * CPU program execution stops during DMA operation. * Incremental addressing for transfer source and destination can be turned on and off. * DMA transfer control from the DMA enable register, DMA stop status register, DMA status register, and descriptor. * Stop requests from resources can stop DMA transfer. * When DMA transfer is completed, the DMA status register sets a flag in the bit for the corresponding channel on which transfer was completed, and outputs a completion interrupt to the interrupt controller. (1) Register List DMA enable register bit DERH : 0000ADH 15 14 13 12 11 10 9 8 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DE15 DE14 DE13 DE12 DE11 DE10 DE9 DE8 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B DMA enable register bit DERL : 0000ACH Initial value 00000000B DMA stop status register bit DSSR : 0000A4H Initial value 00000000B DMA status register bit DSRH : 00009DH Initial value 00000000B DMA status register bit DSRL : 00009CH Initial value 00000000B 75 MB90480/485 Series (2) Block Diagram Memory space by IOA DMA transfer request If transfer not ended DMA descriptor Read by DER DMA controller If transfer is ended by BAP Transfer Buffer by DCT CPU IOA BAP DER DCT 76 Peripheral function (I/O) : I/O address pointer : Buffer address pointer : DMA enable register (ENx selection) : Data counter Interrupt controller F2MC-16LX Bus I/O register I/O register MB90480/485 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter (VSS = AVSS = 0.0 V) Symbol Rating Unit Remarks Min Max VCC3 VSS - 0.3 VSS + 4.0 V VCC5 VSS - 0.3 VSS + 7.0 V AVCC VSS - 0.3 VSS + 4.0 V AVRH VSS - 0.3 VSS + 4.0 V VSS - 0.3 VSS + 4.0 V *2 VSS - 0.3 VSS + 7.0 V *2 VSS - 0.3 VSS + 4.0 V *2 VSS - 0.3 VSS + 7.0 V *2 ICLAMP -2.0 +2.0 mA *6 ICLAMP 20 mA *6 IOL 10 mA *3 "L" level average output current IOLAV 3 mA *4 "L" level maximum total output current IOL 60 mA "L" level total average output current IOLAV 30 mA *5 IOH -10 mA *3 "H" level average output current IOHAV -3 mA *4 "H" level maximum total output current IOH -60 mA "H" level total average output current IOHAV -30 mA Power consumption PD 320 mW Operating temperature TA -40 +85 C Tstg -55 +150 C Power supply voltage Input voltage VI Output volatage VO Maximum clamp current Total maximum clamp current "L" level maximum output current "H" level maximum output current Storage temperature *1 *5 *1 : AVCC and AVRH must not exceed VCC. Also, AVRH must not exceed AVCC. *2 : V1 and V0 must not exceed VCC + 0.3 V. However, if the maximum current to/from and input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : Maximum output current is defined as the peak value for one of the corresponding pins. *4 : Average output current is defined as the average current flow in a 100 ms interval at one of the corresponding pins. *5 : Average total output current is defined as the average current flow in a 100 ms interval at all corresponding pins. *6 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P46, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA3 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. 77 MB90480/485 Series * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits: * Input/Output Equivalent circuits Protective diode +B input (0 V to 16 V) VCC Limiting resistance P-ch N-ch R *7 : MB90485 series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 78 MB90480/485 Series 2. Recommended Operating Conditions Parameter Symbol Remarks 2.7 3.6 V During normal operation 1.8 3.6 V To maintain RAM state in stop mode 2.7 5.5 V During normal operation* 1.8 5.5 V To maintain RAM state in stop mode* VIH 0.7 VCC VCC + 0.3 V All pins other than VIHS, VIHM and VIHX VIHS 0.8 VCC VCC + 0.3 V Hysteresis input pins VIHM VCC - 0.3 VCC + 0.3 V MD pin input VIHX 0.8 VCC VCC + 0.3 V X0A pin, X1A pin VIL VSS - 0.3 0.3 VCC V All pins other than VILS, VILM and VILX VILS VSS - 0.3 0.2 VCC V Hysteresis input pins VILM VSS - 0.3 VSS + 0.3 V MD pin input VILX VSS - 0.3 0.1 V X0A pin, X1A pin TA -40 +85 C VCC5 Operating temperature Unit Max Supply voltage "L" level input voltage Value Min VCC3 "H" level input voltage (VSS = AVSS = 0.0 V) * : MB90485 series only P20 to P27, P30 to P37, P40 to P47, P70 to P77 pins can be used as 5 V I/F pin on applied 5 V to VCC5 pin. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 79 MB90480/485 Series 3. DC Characteristics (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Condition Min Value Typ VCC = 2.7 V, VCC3 - 0.3 IOH = -1.6 mA VOH All output pins VCC = 4.5 V, VCC5 - 0.5 IOH = -4.0 mA VCC = 2.7 V, IOL = 2.0 mA "L" level VOL All output pins output voltage VCC = 4.5 V, IOH = 4.0 mA VCC = 3.3 V, Input leakage All input pins -10 IIL VSS < VI < VCC current Pull-up VCC = 3.0 V, RPULL 20 at TA = +25 C resistance P40 to P47, Open drain Ileak P70 to P77 output current At VCC = 3.3 V, internal 25 MHz operation, normal operation ICC At VCC = 3.3 V, internal 25 MHz operation, FLASH programming At VCC = 3.3 V, internal 25 MHz operation, ICCS sleep mode At VCC = 3.3 V, Power supply external 32 kHz, current internal 8 kHz operation, ICCL sub clock operation (TA = +25 C) At VCC = 3.3 V, external 32 kHz, internal 8 kHz operation, ICCT watch mode (TA = +25 C) TA = +25 C, stop mode, ICCH At VCC = 3.3 V Other than Input CIN AVCC, AVSS, capacitance VCC, VSS "H" level output voltage Max Unit V V 0.4 V 0.4 V +10 A 53 200 k 0.1 10 A 45 60 mA 55 70 mA 17 35 mA 15 140 A 1.8 40 A 0.8 40 A 5 15 pF Remarks At using 5 V power supply At using 5 V power supply Notes : * Pins P40 to P47, and P70 to P77 are controlled N-ch open drain pins, and should always be used at CMOS levels. * MB90485 series only * P40 to P47 and P70 to P77 are Nch open drain pins with control, which are usually used as CMOS. * P76 and P77 are open drain pins without Pch. * For use as a single 3 V power supply products, set VCC = VCC3 = VCC5. * When the device is used with dual power supplies, P20 to P27, P30 to P37, P40 to P47 and P70 to P77 serve as 5 V pins while the other pins serve as 3 V I/O pins. 80 MB90480/485 Series 4. AC Characteristics (1) Clock Timing Standards Parameter (VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pinname FCH Clock frequency Clock cycle time Input clock pulse width Input clock rise, fall time Internal operating clock frequency Internal operating clock cycle time X0, X1 Value Condition Min Typ Max 3 25 3 50 External crystal 3 MHz oscillator* External clock input*3 Unit Remarks FCL X0A, X1A 32.768 kHz tC X0, X1 20 333 ns tCL X0A, X1A 30.5 s PWH PWL X0 5 ns PWLH PWLL X0A 15.2 s *2 tcr tcf X0 5 ns With external clock fCP 1.5 25 MHz *1 fCPL 8.192 kHz tCP 40.0 666 ns tCPL 122.1 s *1 *1 *1 : Be careful of the operating voltage. *2 : Duty raito should be 50 % 3 %. *3 : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as mentioned in "Base oscillator frequency vs. Internal operating clock frequency". * X0, X1 clock timing tC 0.8 VCC X0 0.2 VCC PWH PWL tcf tcr * X0A, X1A clock timing tCL 0.8 VCC X0A 0.1 V PWLH PWLL tcf tcr 81 MB90480/485 Series * Range of warranted PLL operation Internal operating clock frequency vs. Power supply voltage 3.6 Supply voltage VCC (V) Range of warranted PLL operation 3.0 2.7 Normal operating range 1.5 16 4.5 25 Internal clock fCP (MHz) Note: For A/D operating frequency, refer to "5. A/D Converter Electrical Characteristics" Base oscillator frequency vs. Internal operating clock frequency 25.0 Internal clock fCP (MHz) 4x 20.0 3x 2x PLL operation 1x 16.0 12.0 External clock 8.0 4.5 4.0 3.0 4.5 8.0 4.0 12.5 16.0 20.0 24.0 25.0 32.0 50.0 Base oscillator clock FC (MHz) Notes : * In the PLL operation at 20 MHz to 25 MHz, set the PLL2 bit in the PLLOS register. * When the internal clock is operating at 20 MHz to 25 MHz, the PLL clock is the clock that the following have been set. * Set CS1 (CS0) in the CKSCR register to multiplied-by-1 (multiplied-by-2) * Set PLL 2 bit in the PLLOS register to "1" * To set the internal frequency to 20 MHz using the PLL multiplier circuit, you can select either multiplication by 1/2/3/4 or multiplication by 2/4/6/8 with no problem. AC standards are set at the following measurement voltage values. * Input signal waveform Hysteresis input pins Output pins 0.8 VCC 2.4 V 0.2 VCC 0.8 V * Pins other than hysteresis input/MD input 0.7 VCC 0.3 VCC 82 * Output signal waveform MB90480/485 Series (2) Clock output timing Parameter Cycle time CLKCLK (VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name tCYC tCHCL Conditions CLK CLK Value Min Max tCP* Unit Remarks ns VCC = 3.0 V to 3.6 V tCP* / 2 - 15 tCP* / 2 + 15 ns at fcp = 25 MHz VCC = 2.7 V to 3.3 V tCP* / 2 - 20 tCP* / 2 + 20 ns at fcp = 16 MHz VCC = 2.7 V to 3.3 V tCP* / 2 - 64 tCP* / 2 + 64 ns at fcp = 5 MHz * : For tCP see " (1) Clock Timing Standards." tCYC tCHCL 2.4 V CLK 2.4 V 0.8 V 83 MB90480/485 Series (3) Reset Input Standards Parameter Reset input time Symbol (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name tRSTL Value Conditions RST Unit Remarks ns Normal operation ms Stop mode Min Max 16 tCP Oscillator oscillation time* + 4 tCP * : Oscillator oscillation time is the time to 90 % of amplitude. For a crystal oscillator this is on the order of several milliseconds to tens of milliseconds. For a FAR/ceramic oscillator, this is several hundred microseconds to several milliseconds. For an external clock signal the value is 0 ms. * In stop mode tRSTL RST 0.2 Vcc X0 0.2 Vcc 90 % of amplitude Internal operating clock Oscillator oscillation time 4 tcp Oscillator stabilization wait time Instruction execution Internal reset * Condition for measurement of AC standards CL : Load capacitance applied during testing CLK, ALE : CL = 30 pF AD15 to AD00 (address data bus) , RD, WR, A23 to A00/D15 to D00 : CL = 30 pF Pin CL 84 MB90480/485 Series (4) Power-on Reset Stanards Parameter Symbol Power rise time Power down time (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name Conditions tR VCC tOFF VCC Value Unit Remarks Min Max 30 ms * 1 ms In repeated operation * : Power rise time requires VCC < 0.2 V. Notes: * The above standards are for the application of a power-on reset. * Within the device, the power-on reset should be applied by switching the power supply off and on again. tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Rapid fluctuations in power supply voltage may trigger a power-on reset in some cases. As shown below, when changing supply voltage during operation, it is recommended that voltage changes be suppressed and a smooth restart be applied. Main power supply voltage VCC Sub power supply voltage VSS RAM data maintenance The slope of voltage increase should be kept within 50 mV/ms. 85 MB90480/485 Series (5) Bus Read Timing Parameter ALE pulse width (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 C to +70 C) Symbol Pin name tLHLL ALE Value Unit Remarks ns at fcp = 25 MHz tCP* / 2 - 20 ns at fcp = 16 MHz tCP* / 2 - 35 ns at fcp = 8 MHz tCP* / 2 - 17 ns tCP* / 2 - 40 ns Min Max tCP* / 2 - 15 Valid address ALEtime tAVLL Address, ALE ALE address valid time tLLAX ALE, Address tCP* / 2 - 12 ns Valid address RDtime tAVRL RD, address tCP* - 25 ns Valid address valid data input tAVDV Address, Data 5 tCP* / 2 - 55 ns 5 tCP* / 2 - 80 ns at fcp = 8 MHz RD pulse width tRLRH RD 3 tCP* / 2 - 25 ns at fcp = 25 MHz 3 tCP* / 2 - 20 ns at fcp = 16 MHz RD valid data input tRLDV RD, Data 3 tCP* / 2 - 55 ns 3 tCP* / 2 - 80 ns RDdata hold time tRHDX RD, Data 0 ns RDALErise time tRHLH RD, ALE tCP* / 2 - 15 ns RD address valid time tRHAX Address, RD tCP* / 2 - 10 ns Valid address CLKtime tAVCH Address, CLK tCP* / 2 - 17 ns RDCLKtime tRLCH RD, CLK tCP* / 2 - 17 ns ALERDtime tLLRL RD, ALE tCP* / 2 - 15 ns * : tCP : See " (1) Clock Timing Standards". 86 Conditions at fcp = 8 MHz at fcp = 8 MHz MB90480/485 Series tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH 2.4 V 2.4 V ALE tLHLL 2.4 V 0.8 V tRLRH 2.4 V RD tAVLL tLLAX 0.8 V tLLRL In multiplexed mode tAVRL A23 to A16 tRLDV 2.4 V 2.4 V 0.8 V 0.8 V tAVDV 2.4 V 2.4 V tRHDX 0.7 VCC 0.8 V 0.7 VCC Read data Address AD15 to AD00 0.8 V 0.3 VCC 0.3 VCC tRHAX In non-multiplexed mode A23 to A00 tRHAX 2.4 V 2.4 V 0.8 V 0.8 V tRLDV tRHDX tAVDV 0.7 VCC 0.7 VCC Read data D15 to D00 0.3 VCC 0.3 VCC 87 MB90480/485 Series (6) Bus Write Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 C to +70 C) Value Symbol Pin name Condition Min Max Valid addressWRtime tAVWL Address, WR tCP* - 15 ns WR pulse width tWLWH WRL, WRH 3 tCP* / 2 - 25 ns at fcp = 25 MHz 3 tCP* / 2 - 20 ns at fcp = 16 MHz 3 tCP* / 2 - 15 ns 10 ns at fcp = 25 MHz 20 ns at fcp = 16 MHz 30 ns at fcp = 8 MHz Parameter Valid data output WRtime tDVWH WRdata hold time Data, WR WR, Data tWHDX Unit WRaddress valid time tWHAX WR, Address tCP* / 2 - 10 ns WRALEtime tWHLH WR, ALE tCP* / 2 - 15 ns WRCLKtime tWLCH WR, CLK tCP* / 2 - 17 ns Remarks * : tCP : See " (1) Clock Timing Standards". tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH 2.4 V WR (WRL, WRH) 0.8 V In multiplexed mode tAVWL A23 to A16 tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH 2.4 V Address AD15 to AD00 0.8 V 2.4 V 0.8 V 2.4 V Write data 0.8 V tWHAX In non-multiplexed mode A23 to A00 2.4 V 2.4 V 0.8 V 0.8 V tDVWH D15 to D00 88 tWHDX 2.4 V 0.8 V tWHDX 2.4 V Write data 0.8 V MB90480/485 Series (7) Ready Input Timing Parameter (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 C to +70 C) Symbol RDY setup time tRYHS RDY hold time tRYHH Pin name Conditions RDY Value Unit Min Max 35 ns 70 ns 0 ns Remarks at fcp = 8 MHz Notes: * If the RDY setup time is insufficient, use the auto ready function. * Warning : For input from the RDY pin, if the AC ratings are not satisfied this device may unexpected operation. 2.4 V 2.4 V CLK ALE RD/WR tRYHS tRYHH RDY wait not inserted RDY wait inserted (1 cycle) 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tRYHS 89 MB90480/485 Series (8) Hold Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = 0 C to +70 C) Parameter Symbol Pin name Pin floatingHAKtime tXHAL HAK HAKpin valid time tHAHV HAK Value Conditions Unit Min Max 30 tCP* ns tCP 2 tCP* ns Remarks * : tCP : See " (1) Clock Timing Standards". Note : One or more cycles are required from the time the HRQ pin is read until the HAK signal changes. HAK 2.4 V 0.8 V tXHAL tHAHV High-Z 2.4 V Pins 0.8 V (9) UART Timing Parameter (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin Serial clock cycle time tSCYC SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX tSHSL Serial clock "L" pulse width tSLSH SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX Serial clock "H" pulse width Conditions Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL *2 : tCP : See " (1) Clock Timing Standards". Note : AC ratings are for CLK synchronized mode. Value External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Unit Min Max 8 tCP*2 ns -80 +80 ns -120 +120 ns 100 ns 200 ns tCP*2 ns CP 2 ns CP 2 4t * ns 150 ns 200 ns 60 ns 120 ns 60 ns 120 ns 4t * *1 : CL is the load capacitance applied to pins for testing. 90 2.4 V 0.8 V Remarks fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz MB90480/485 Series * Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External shift clock mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 91 MB90480/485 Series (10) I/O Expanded Serial Interface Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Serial clock cycle time tSCYC SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX tSHSL Serial clock "L" pulse width tSLSH SCKSOT delay time tSLOV Valid SINSCK tIVSH SCKvalid SIN hold time tSHIX Parameter Serial clock "H" pulse width Conditions Internal shift clock mode output pins : CL*1 = 80 pF + 1 TTL External shift clock mode output pins : CL*1 = 80 pF + 1 TTL Notes:* AC ratings are for CLK synchronized mode. * Values on this table are target values. 92 Unit Min Max 8 tCP*2 ns -80 + 80 ns -120 + 120 ns 100 ns 200 ns tCP*2 ns CP 2 ns CP 2 4t * ns 150 ns 200 ns 60 ns 120 ns 60 ns 120 ns 4t * *1 : CL is the load capacitance applied to pins for testing. *2 : tCP : See " (1) Clock Timing Standards". Value Remarks fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz fcp = 8 MHz MB90480/485 Series * Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC * External shift clock mode tSLSH tSHSL SCK 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC 93 MB90480/485 Series (11) Timer Input Timing Parameter Input pulse width (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Conditions tTIWH tTIWL TIN0, IN0, IN1, PWC0 to PWC3 Value Min Max 4 tCP* Unit Remarks ns * : tCP : See " (1) Clock Timing Standards". 0.8 VCC TIN0 IN0, IN1 0.8 VCC 0.2 VCC tTIWH (12) Timer Output Timing tTIWL (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Conditions CLKTout change time PPG0 to PPG5 change time OUT0 to OUT5 change time tTO TOT0, PPG0 to PPG5, OUT0 to OUT5 Load conditions 80 pF CLK TOUT PPG0 to PPG5 OUT0 to OUT5 0.7 VCC 0.7 VCC 0.3 VCC tTO 94 0.2 VCC Value Min Max 30 Unit Remarks ns MB90480/485 Series (13) I2C Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Value Conditions Min Max Unit SCL clock frequency fSCL 0 100 kHz Bus free time between stop and start tBUS 4.7 s Hold time (resend) start tHDSTA 4.0 s SCL clock "L" status hold time tLOW 4.7 s SCL clock "H" status hold time tHIGH 4.0 s Resend start condition setup time tSUSTA 4.7 s Data hold time tHDDAT 0 s SDA and SCL signal rise time tR 1000 ns SDA and SCL signal fall time tF 300 ns Stop condition setup time tSUSTO 4.0 s Remarks First clock pulse is generated after this interval. Note : VCC = VCC3 = VCC5 0.8VCC SDA 0.2VCC tBUS tLOW tR tHIGH tF tHDSTA 0.8VCC SCL 0.2VCC tHDSTA tHDDAT tSUSTA tSUSTO tSCL 95 MB90480/485 Series (14) Trigger Input Timing Parameter (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Symbol Pin name Conditions tTRGH tTRGL ADTG, IRQ0 to IRQ7 Input pulse width Value Unit Remarks ns Normal operation s Stop mode Min Max 5 tCP* 1 * : tCP : See " (1) Clock Timing Standards". IRQ0 to IRQ7 ADTG 0.8 VCC 0.8 VCC 0.2 VCC tTRGH (15) Up-down Counter Timing Parameter Symbol tTRGL (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Pin name Conditions Value Min Max Unit AIN input "H" pulse width tAHL 8 tCP* ns AIN input "L" pulse width tALL 8 tCP* ns BIN input "H" pulse width tBHL 8 tCP* ns BIN input "L" pulse width tBLL 8 tCP* ns AINBIN rise time tAUBU 4 tCP* ns BINAIN fall time tBUAD 4 tCP* ns AINBIN rise time tADBD 4 tCP* ns BINAIN rise tome tBDAU 4 tCP* ns BINAIN rise time tBUAU 4 tCP* ns AINBIN fall time tAUBD 4 tCP* ns BINAIN rise time tBDAD 4 tCP* ns AINBIN rise time tADBU 4 tCP* ns ZIN input "H" pulse width tZHL 4 tCP* ns ZIN input "L" pulse width tZLL 4 tCP* ns AIN0, AIN1, BIN0, BIN1 ZIN0, ZIN1 * : tCP : See " (1) Clock Timing Standards". 96 0.2 VCC Load conditions 80 pF Remarks MB90480/485 Series tAHL 0.8 VCC tALL 0.8 VCC AIN 0.2 VCC tAUBU tBUAD tADBD 0.8 VCC 0.2 VCC tBDAU 0.8 VCC BIN 0.2 VCC tBHL 0.8 VCC 0.2 VCC tBLL 0.8 VCC BIN 0.2 VCC tBUAU tAUBD tBDAD 0.2 VCC tADBU 0.8 VCC AIN 0.2 VCC 0.8 VCC ZIN 0.8 VCC tZHL tZLL 0.2 VCC 0.2 VCC 97 MB90480/485 Series (16) Chip Select Output Timing (VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = -40 C to +85 C) Value Symbol Pin name Conditions Min Max Chip select output valid time RD tSVRL CS0 to CS3, RD tCP* / 2 - 7 ns Chip select output valid timeWR tSVWL CS0 to CS3, WRH, WRL tCP* / 2 - 7 ns RDchip select output valid time tRHSV RD, CS0 to CS3 tCP* / 2 - 17 ns WRchip select output valid time tWHSV WRH, WRL, CS0 to CS3 tCP* / 2 - 17 ns Parameter Unit Remarks * : tCP : See " (1) Clock Timing Standards". tSVRL 2.4 V RD 0.8 V tRHSV A23 to A16 CS0 to CS3 2.4 V 0.8 V 2.4 V D15 to D00 Read data 0.8 V tSVWL tWHSV 2.4 V WRH, WRL 0.8 V D15 to D00 Undefined Write data Note : Due to the configuration of the internal bus, changes in the chip select output signal are clock synchronous and therefore may causes bus conflict conditions. AC cannot be warranted between the ALE output signal and the chip select output signal. 98 MB90480/485 Series 5. A/D Converter Electrical Characteristics (VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, 2.7 V AVRH, TA = -40 C to +85 C) Parameter Symbol Pin name Value Min Typ Max Unit Resolution 10 bit Total error 3.0 LSB Non-linear error 2.5 LSB Differential linearity error 1.9 LSB Zero transition voltage VOT AN0 to AN7 AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB mV Full scale transition voltage VFST AN0 to AN7 AVRH - 3.5 LSB AVRH - 1.5 LSB AVRH + 0.5 LSB mV Conversion time 3.68 *1 s Analog port input current IAIN AN0 to AN7 0.1 10 A Analog input voltage VAIN AN0 to AN7 AVSS AVRH V AVRH AVSS + 2.2 AVCC V IA AVCC 1.4 3.5 mA IAH AVCC 5 *2 A IR AVRH 94 150 A IRH AVRH 5* 2 A AN0 to AN7 4 Reference voltage Power supply current Reference voltage supply current Offset between channels Remarks LSB *1 : At machine clock frequency of 25 MHz. *2 : CPU stop mode current when A/D converter is not operating (at VCC = AVCC = AVRH = 3.0 V) . Notes : * Error increases in absolute terms as the value |AVRH - AVSS|decreases. * The external circuit output impedance for analog input channels should be set according to the following conditions. External circuit output impedance of approximately 4 k or less is recommended. If an external capacitor is used, then due to considerations of capacitance division between the external capacitor and on-chip capacitors the external capacitor should be on the order of several thousand times the level of the internal capacitors. * If the output impedance of external circuits is set too high, the analog voltage sampling time may be too short (sampling time = 1.92 s at machine clock 25 MHz) . 99 MB90480/485 Series * Concerning analog input circuits * Model analog input circuit Sample & hold circuit Analog input C0 Comparator RON1 RON2 RON3 RON4 C1 RON1 : Approx. 200 RON2 + RON3 : Approx. 2 k RON4 : Approx. 1.9 k C0 + C1 : Approx. 32.3 pF Note: Values shown here are intended as guidelines. Note : Concerning sampling time, and compare time When 3.6 V AVCC 2.7 V, then Sampling time : 1.92 s, compare time : 1.1 s Settings should ensure that actual values do not go below these values due to operating frequency changes. * Flash Memory Program/Erase Characteristics Parameter Conditions Sector erase time Chip erase time TA = + 25 C, VCC = 3.0 V Word (16-bit) programming time 100 Value Unit Remarks Min Typ Max 1 15 s Excludes 00H programming prior erasure 7 s Excludes 00H programming prior erasure 16 3,600 s Excludes system-level overhead Program/Erase cycle 10,000 cycle Data hold time 100,000 h MB90480/485 Series * Use of the X0/X1, X0A/X1A pins When used with a crystal oscillator X1 Pull-up resistance 1 X0 X0A Damping resistance 1 C2 X1A Internal damping resistance 0 Damping resistance 2 C3 C1 C4 In normal use : Internal damping resistance 1 : Typ 600 Consult with the oscillator manufacturer. Pull-up resistance 1, Damping resistance 1, 2, C1 to C4 * Sample use with external clock input X0 OPEN MB90480/485 series X1 101 MB90480/485 Series EXAMPLE CHARACTERISTICS ICC - VCC 60 50 1 MHz 2 MHz 4 MHz 10 MHz 16 MHz 20 MHz 25 MHz ICC (mA) 40 30 20 10 0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) ICCH - VCC 1.4 1.2 ICCH (A) 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) ICCT - VCC 2.0 1.8 1.6 ICCT (A) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) (Continued) 102 MB90480/485 Series IA - VCC 2.0 1.8 1.6 IA (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.4 2.7 3.0 3.3 3.6 3.9 3.6 3.9 VCC (V) R - VCC R (k) 1000 100 10 2.4 2.7 3.0 3.3 VCC (V) (Continued) 103 MB90480/485 Series (Continued) ICCS - VCC 20 18 16 ICCS (mA) 14 1 MHz 2 MHz 4 MHz 10 MHz 16 MHz 20 MHz 25 MHz 12 10 8 6 4 2 0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) ICCL - VCC 20 18 16 ICCL (A) 14 12 10 8 6 4 2 0 2.4 2.7 3.0 3.3 3.6 3.9 VCC (V) IR - VCC 250 200 IR (A) 150 100 50 0 2.4 2.7 3.0 3.3 VCC (V) 104 3.6 3.9 MB90480/485 Series ORDERING INFORMATION Model Package MB90F481PF MB90F482PF MB90487PF MB90F488PF 100-pin plastic QFP (FPT-100P-M06) MB90F481PFV MB90F482PFV MB90487PFV MB90F488PFV 100-pin plastic LQFP (FPT-100P-M05) Remarks 105 MB90480/485 Series PACKAGE DIMENSIONS Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 100-pin plastic QFP (FPT-100P-M06) 23.900.40(.941.016) * 20.000.20(.787.008) 80 51 81 50 0.10(.004) 17.900.40 (.705.016) *14.000.20 (.551.008) INDEX Details of "A" part 100 1 30 0.65(.026) "A" C 0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 31 0.320.05 (.013.002) 0.13(.005) M 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off) 2002 FUJITSU LIMITED F100008S-c-5-5 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 106 MB90480/485 Series (Continued) 100-pin plastic LQFP (FPT-100P-M05) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.000.20(.630.008)SQ * 14.000.10(.551.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 100 26 1 25 C 0.200.05 (.008.002) 0.08(.003) M 0.100.10 (.004.004) (Stand off) 0~8 "A" 0.50(.020) +.008 1.50 -0.10 .059 -.004 (Mounting height) INDEX 0.1450.055 (.0057.0022) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 2003 FUJITSU LIMITED F100007S-c-4-6 Dimensions in mm (inches) Note : The values in parentheses are reference values. 107 MB90480/485 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. 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