SST39WF800A-90-4C-M2QE - Silicon Storage Technology, Inc.

S71258-05-000 7/06

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

FEATURES:

• Organized as 512K x16

• Single Voltage Read and Write Operations

– 1.65-1.95V

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 5 mA (typical)

– Standby Current: 5 µA (typical)

• Sector-Erase Capability

– Uniform 2 KWord sectors

• Block-Erase Capability

– Uniform 32 KWord blocks

• Fast Read Access Time

– 90 ns

• Latched Address and Data

• Fast Erase and Word-Program

– Sector-Erase Time: 36 ms (typical)

– Block-Erase Time: 36 ms (typical)

– Chip-Erase Time: 140 ms (typical)

– Word-Program Time: 28 µs (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and command sets

• Packages Available

– 48-ball TFBGA (6mm x 8mm)

– 48-ball WFBGA (5mm x 6mm) Micro-Package

– 48-ball XFLGA (5mm x 6mm) Micro-Package

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST39WF800A device is a 512K x16 CMOS Multi-

Purpose Flash (MPF) manufactured with SST’s proprietary,

high performance CMOS SuperFlash technology. The

split-gate cell design and thick-oxide tunneling injector

attain better reliability and manufacturability compared with

alternate approaches. The SST39WF800A writes (Pro-

gram or Erase) with a 1.65-1.95V power supply. This

device conforms to JEDEC standard pin assignments for

x16 memories.

Featuring high-performance Word-Program, the

SST39WF800A device provides a typical Word-Program

time of 28 µsec. The device uses Toggle Bit or Data# Poll-

ing to detect the completion of the Program or Erase opera-

tion. To protect against inadvertent writes, it has on-chip

hardware and software data protection schemes.

Designed, manufactured, and tested for a wide spectrum of

applications, this device is offered with a guaranteed typical

endurance of 100,000 cycles. Data retention is rated at

greater than 100 years.

The SST39WF800A device is suited for applications that

require convenient and economical updating of program,

configuration, or data memory. For all system applications,

it significantly improves performance and reliability, while

lowering power consumption. It inherently uses less energy

during Erase and Program than alternative flash technolo-

gies. When programming a flash device, the total energy

consumed is a function of the applied voltage, current, and

time of application. Since for any given voltage range, the

SuperFlash technology uses less current to program and

has a shorter erase time, the total energy consumed during

any Erase or Program operation is less than alternative

flash technologies. These devices also improve flexibility

while lowering the cost for program, data, and configuration

storage applications.

The SuperFlash technology provides fixed Erase and Pro-

gram times, independent of the number of Erase/Program

cycles that have occurred. Therefore the system software

or hardware does not have to be modified or de-rated as is

necessary with alternative flash technologies, whose Erase

and Program times increase with accumulated Erase/Pro-

gram cycles.

To meet surface mount requirements, the SST39WF800A

is offered in a 48-ball TFBGA package and a 48-ball Micro-

Package. See Figure 3 and Figure 2 for pin assignments.

8 Mbit (x16) Multi-Purpose Flash

SST39WF800A

SST39WF800A1.8V 8Mb (x16) MPF memory

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asserting WE# low while keeping CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first.

Read

The Read operation of the SST39WF800A is controlled by

CE# and OE#, both have to be low for the system to obtain

data from the outputs. CE# is used for device selection.

When CE# is high, the chip is deselected and only standby

power is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high. Refer to

the Read cycle timing diagram for further details (Figure 4).

Word-Program Operation

The SST39WF800A is programmed on a word-by-word

basis. Before programming, the sector where the word

exists must be fully erased. The Program operation is

accomplished in three steps. The first step is the three-byte

load sequence for Software Data Protection. The second

step is to load word address and word data. During the

Word-Program operation, the addresses are latched on the

falling edge of either CE# or WE#, whichever occurs last.

The data is latched on the rising edge of either CE# or

WE#, whichever occurs first. The third step is the internal

Program operation which is initiated after the rising edge of

the fourth WE# or CE#, whichever occurs first. The Pro-

gram operation, once initiated, will be completed within 40

µs. See Figures 5 and 6 for WE# and CE# controlled Pro-

gram operation timing diagrams and Figure 15 for flow-

charts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Pro-

gram operation, the host is free to perform additional tasks.

Any commands issued during the internal Program opera-

tion are ignored.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system

to erase the device on a sector-by-sector (or block-by-

block) basis. The SST39WF800A offers both Sector-Erase

and Block-Erase mode. The sector architecture is based

on uniform sector size of 2 KWord. The Block-Erase mode

is based on uniform block size of 32 KWord. The Sector-

Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (30H) and

sector address (SA) in the last bus cycle. The Block-Erase

operation is initiated by executing a six-byte command

sequence with Block-Erase command (50H) and block

address (BA) in the last bus cycle. The sector or block

address is latched on the falling edge of the sixth WE#

pulse, while the command (30H or 50H) is latched on the

rising edge of the sixth WE# pulse. The internal Erase

operation begins after the sixth WE# pulse. The End-of-

Erase operation can be determined using either Data#

Polling or Toggle Bit methods. See Figures 9 and 10 for tim-

ing waveforms. Any commands issued during the Sector-

or Block-Erase operation are ignored.

Chip-Erase Operation

The SST39WF800A provides a Chip-Erase operation,

which allows the user to erase the entire memory array to

the ‘1’ state. This is useful when the entire device must be

quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte command sequence with Chip-Erase command (10H)

at address 5555H in the last byte sequence. The Erase

operation begins with the rising edge of the sixth WE# or

CE#, whichever occurs first. During the Erase operation,

the only valid read is Toggle Bit or Data# Polling. See Table

4 for the command sequence, Figure 8 for timing diagram,

and Figure 18 for the flowchart. Any commands issued dur-

ing the Chip-Erase operation are ignored.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

Write Operation Status Detection

The SST39WF800A provides two software means to

detect the completion of a write (Program or Erase) cycle,

in order to optimize the system write cycle time. The soft-

ware detection includes two status bits: Data# Polling

(DQ7) and Toggle Bit (DQ6). The End-of-Write detection

mode is enabled after the rising edge of WE#, which ini-

tiates the internal Program or Erase operation.

The actual completion of the nonvolatile Write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneous with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data may appear to con-

flict with either DQ7 or DQ6. In order to prevent spurious

rejection, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both Reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Data# Polling (DQ7)

When the SST39WF800A is in the internal Program oper-

ation, any attempt to read DQ7 will produce the comple-

ment of the true data. Once the Program operation is

completed, DQ7 will produce true data. Note that even

though DQ7 may have valid data immediately following the

completion of an internal Write operation, the remaining

data outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. During internal Erase oper-

ation, any attempt to read DQ7 will produce a ‘0’. Once the

internal Erase operation is completed, DQ7 will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Data# Polling is valid after the

rising edge of sixth WE# (or CE#) pulse. See Figure 7 for

Data# Polling timing diagram and Figure 16 for a flowchart.

Toggle Bit (DQ6)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ6 will produce alternating 1s

and 0s, i.e., toggling between 1 and 0. When the internal

Program or Erase operation is completed, the DQ6 bit will

stop toggling. The device is then ready for the next opera-

tion. The Toggle Bit is valid after the rising edge of fourth

WE# (or CE#) pulse for Program operation. For Sector-,

Block- or Chip-Erase, the Toggle Bit is valid after the rising

edge of sixth WE# (or CE#) pulse. See Figure 0-1 for Tog-

gle Bit timing diagram and Figure 16 for a flowchart.

Data Protection

The SST39WF800A provides both hardware and software

features to protect nonvolatile data from inadvertent writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5

ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is

inhibited when VDD is less than 1.0V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE#

high will inhibit the Write operation. This prevents inadvert-

ent writes during power-up or power-down.

Software Data Protection (SDP)

The SST39WF800A provides the JEDEC approved Soft-

ware Data Protection scheme for all data alteration opera-

tions, i.e., Program and Erase. Any Program operation

requires the inclusion of the three-byte sequence. The

three-byte load sequence is used to initiate the Program

operation, providing optimal protection from inadvertent

Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six-byte sequence. This group of devices are shipped with

the Software Data Protection permanently enabled. See

Table 4 for the specific software command codes. During

SDP command sequence, invalid commands will abort the

device to Read mode within TRC. The contents of DQ15-

DQ8 can be VIL or VIH, but no other value, during any SDP

command sequence.

Common Flash Memory Interface (CFI)

The SST39WF800A also contains the CFI information to

describe the characteristics of the device. In order to enter

the CFI Query mode, the system must write three-byte

sequence, same as Software ID Entry command with 98H

(CFI Query command) to address 5555H in the last byte

sequence. See Figure 11 for the timing diagram. Once the

device enters the CFI Query mode, the system can read

CFI data at the addresses given in Tables 5 through 7. The

system must write the CFI Exit command to return to Read

mode from the CFI Query mode.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

Product Identification

The Product Identification mode identifies the devices as

the SST39WF800A and manufacturer as SST. This mode

may be accessed by software operations. Users may use

the Software Product Identification operation to identify the

part (i.e., using the device ID) when using multiple

manufacturers in the same socket. For details, see Table 4

for software operation, Figure 0-2 for the Software ID Entry

and Read timing diagram, and Figure 17 for the Software

ID Entry command sequence flowchart.

Product Identification Mode Exit/

CFI Mode Exit

In order to return to the standard Read mode, the Software

Product Identification mode must be exited. Exit is accom-

plished by issuing the Software ID Exit command

sequence, which returns the device to the Read mode.

This command may also be used to reset the device to the

Read mode after any inadvertent transient condition that

apparently causes the device to behave abnormally, e.g.,

not read correctly. Please note that the Software ID Exit/

CFI Exit command is ignored during an internal Program or

Erase operation. See Table 4 for software command

codes, Figure 12 for timing waveform, and Figure 17 for a

flowchart.

TABLE 1: Product Identification Table

Address Data

Manufacturer’s ID 0000H 00BFH

Device ID

SST39WF800A 0001H 273FH

T1.0 1258

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 1: Functional Block Diagram

FIGURE 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA

Y-Decoder

I/O Buffers and Data Latches

1258 B1.0

Address Buffer & Latches

X-Decoder

DQ15 - DQ0

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

CE#

VSS

DQ8

OE#

DQ0

A18

DQ10

DQ9

DQ1

A17

DQ2

DQ3

VDD

WE#

DQ12

DQ13

A10

DQ4

DQ5

DQ14

A11

A13

A12

DQ11

DQ6

DQ15

A14

A15

A16

DQ7

VSS

TOP VIEW (balls facing down)

A B C D E F G H J K L

1258 48-wfbga M2Q P020

SST39WF800A

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 3: Pin Assignments for 48-ball TFBGA

TABLE 2: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS = A18 for SST39WF800A

Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the

sector. During Block-Erase AMS-A15 address lines will select the block.

DQ15-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 1.65-1.95V for SST39WF800A

VSS Ground

NC No Connection Unconnected pins.

T2.0 1258

TABLE 3: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or Block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 4

T3.0 1258

1258 48-tfb

a P01.0

SST39WF800A

TOP VIEW (balls facing down)

A B C D E F G H

A13

WE#

A12

A17

A14

A10

A18

A15

A11

A16

DQ7

DQ5

DQ2

DQ0

DQ14

DQ12

DQ10

DQ8

CE#

DQ15

DQ13

VDD

DQ11

DQ9

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

TABLE 4: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2Addr1Data2

Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3Data

Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX430H

Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX450H

Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H

Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H

CFI Query Entry55555H AAH 2AAAH 55H 5555H 98H

Software ID Exit7/

CFI Exit

XXH F0H

Software ID Exit7/

CFI Exit

5555H AAH 2AAAH 55H 5555H F0H

T4.0 1258

1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.

AMS = Most significant address

AMS = A18 for SST39WF800A

2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence

3. WA = Program word address

4. SAX for Sector-Erase; uses AMS-A11 address lines

BAX for Block-Erase; uses AMS-A15 address lines

5. The device does not remain in Software Product ID mode if powered down.

6. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,

SST39WF800A Device ID = 273FH, is read with A0 = 1.

7. Both Software ID Exit operations are equivalent

TABLE 5: CFI Query Identification String1 for SST39WF800A

1. Refer to CFI publication 100 for more details.

Address Data Data

10H 0051H Query Unique ASCII string “QRY”

11H 0052H

12H 0059H

13H 0001H Primary OEM command set

14H 0007H

15H 0000H Address for Primary Extended Table

16H 0000H

17H 0000H Alternate OEM command set (00H = none exists)

18H 0000H

19H 0000H Address for Alternate OEM extended Table (00H = none exits)

1AH 0000H

T5.0 1258

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

TABLE 6: System Interface Information for SST39WF800A

Address Data Data

1BH 0016H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 0020H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 0000H VPP min (00H = no VPP pin)

1EH 0000H VPP max (00H = no VPP pin)

1FH 0005H Typical time out for Word-Program 2N µs (25 = 32 µs)

20H 0000H Typical time out for min size buffer program 2N µs (00H = not supported)

21H 0005H Typical time out for individual Sector/Block-Erase 2N ms (25 = 32 ms)

22H 0007H Typical time out for Chip-Erase 2N ms (27 = 128 ms)

23H 0001H Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs)

24H 0000H Maximum time out for buffer program 2N times typical

25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms)

26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms)

T6.0 1258

TABLE 7: Device Geometry Information for SST39WF800A

Address Data Data

27H 0014H Device size = 2N Byte (14H = 20; 220 = 1 MByte)

28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface

29H 0000H

2AH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported)

2BH 0000H

2CH 0002H Number of Erase Sector/Block sizes supported by device

2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size)

2EH 0000H y = 255 + 1 = 256 sectors (00FFH = 255)

2FH 0010H

30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 000FH Block Information (y + 1 = Number of blocks; z x 256B = block size)

32H 0000H y = 15 + 1 = 16 blocks (000FH = 15)

33H 0000H

34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T7.0 1258

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 11V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 1.65-1.95V

Industrial -40°C to +85°C 1.65-1.95V

AC Conditions of Test

Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns

Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF

See Figures 13 and 14

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

TABLE 8: DC Operating Characteristics, VDD = 1.65-1.95V1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=5 MHz,

VDD=VDD Max

Read 15 mA CE#=VIL, OE#=WE#=VIH, all I/Os open

Program and Erase 20 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current220 µA CE#=VDD, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.2VDD VDD=VDD Min

VIH Input High Voltage 0.8VDD VV

DD=VDD Max

VOL Output Low Voltage 0.1 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.1 V IOH=-100 µA, VDD=VDD Min

T8.0 1258

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 1.8V. Not 100% tested.

2. 20 µA is the maximum ISB for all SST39WF800A commercial grade devices. 30 µA is the maximum ISB for all 39WF800A industrial

grade devices. For all SST39WF800A commercial and industrial devices, ISB typical is under 5 µA.

TABLE 9: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T9.0 1258

TABLE 10: Capacitance (TA = 25°C, f=1 MHz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T10.0 1258

TABLE 11: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a

higher minimum specification.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T11.0 1258

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

AC CHARACTERISTICS

TABLE 12: Read Cycle Timing Parameters

Symbol Parameter Min Max Units

TRC Read Cycle Time 90 ns

TCE Chip Enable Access Time 90 ns

TAA Address Access Time 90 ns

TOE Output Enable Access Time 50 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 40 ns

TOHZ1OE# High to High-Z Output 40 ns

TOH1Output Hold from Address Change 0 ns

T12.0 1258

TABLE 13: Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Word-Program Time 40 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 50 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 50 ns

TWP WE# Pulse Width 50 ns

TWPH1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 50 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 50 ms

TBE Block-Erase 50 ms

TSCE Chip-Erase 200 ms

T13.0 1258

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 4: Read Cycle Timing Diagram

FIGURE 5: WE# Controlled Program Cycle Timing Diagram

1258 F03.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z TCLZ TOH

TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most significant address

AMS = A18 for SST39WF800A

1258 F04.0

ADDRESS AMS-0

DQ15-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most significant address

AMS = A18 for SST39WF800A

X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 6: CE# Controlled Program Cycle Timing Diagram

FIGURE 7: Data# Polling Timing Diagram

1258 F05.0

ADDRESS AMS-0

DQ15-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

5555 2AAA 5555 ADDR

XXAA XX55 XXA0 DATA

INTERNAL PROGRAM OPERATION STARTS

WORD

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most significant address

AMS = A18 for SST39WF800A

X can be VIL or VIH, but no other value.

1258 F06.0

ADDRESS AMS-0

DQ7DATA DATA# DATA# DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most significant address

AMS = A18 for SST39WF800A

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 0-1: TOGGLE BIT TIMING DIAGRAM

FIGURE 8: WE# Controlled Chip-Erase Timing Diagram

1258 F07.0

ADDRESS AMS-0

DQ6

WE#

OE#

CE#

TOETOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most significant address

AMS = A18 for SST39WF800A

1258 F08.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX10XX55XXAA XX80 XXAA

5555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

TSCE

TWP

Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchange-

able as long as minimum timings are met. (See Table 13)

AMS = Most significant address

AMS = A18 for SST39WF800A

X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 9: WE# Controlled Block-Erase Timing Diagram

FIGURE 10: WE# Controlled Sector-Erase Timing Diagram

1258 F09.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX50XX55XXAA XX80 XXAA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 13)

AMS = Most significant address

AMS = A18 for SST39WF800A

X can be VIL or VIH, but no other value.

1258 F10.0

ADDRESS AMS-0

DQ15-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

5555 2AAA 2AAA5555 5555

XX55 XX30XX55XXAA XX80 XXAA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are

interchangeable as long as minimum timings are met. (See Table 13)

AMS = Most significant address

AMS = A18 for SST39WF800A

X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 0-2: SOFTWARE ID ENTRY AND READ

FIGURE 11: CFI Query Entry and Read

1258 F11.0

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

00BF

Device ID

XX55XXAA XX90

Note: Device ID = 273FH for SST39WF800A

X can be VIL or VIH, but no other value.

1258 F12.0

ADDRESS A14-0

TIDA

DQ15-0

WE#

SW0 SW1 SW2

5555 2AAA 5555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

XX55XXAA XX98

Note: X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 12: Software ID Exit/CFI Exit

1258 F13.0

ADDRESS A14-0

DQ15-0

TIDA

TWP

T WHP

WE#

SW0 SW1 SW2

5555 2AAA 5555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

XXAA XX55 XXF0

Note: X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 13: AC Input/Output Reference Waveforms

FIGURE 14: A Test Load Example

1258 F14.0

REFERENCE POINTS OUTPUTINPUT VIT

VIHT

VILT

VOT

AC test inputs are driven at VIHT (VDD) for a logic ‘1’ and VILT (VSS) for a logic ‘0’. Measurement reference points for inputs

and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times are (10% ↔ 90%) <5 ns.

Note: VIT - VINPUT Te s t

VOT - VOUTPUT Tes t

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1258 F15.0

TO TESTER

TO DUT

VDD

25KΩ

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 15: Word-Program Algorithm

1258 F16.0

Start

Load data: XXAAH

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XXA0H

Address: 5555H

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

Note: X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 16: Wait Options

1258 F17.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match?

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7 =

true data?

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 17: Software ID/CFI Command Flowcharts

1258 F18.0

Load data: XXAAH

Address: 5555H

Software ID Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: XXAAH

Address: 5555H

CFI Query Entry

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX98H

Address: 5555H

Wait TIDA

Read CFI data

Load data: XXAAH

Address: 5555H

Software ID Exit/CFI Exit

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XXF0H

Address: 5555H

Load data: XXF0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

Note: X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 18: Erase Command Sequence

1258 F19.0

Load data: XXAAH

Address: 5555H

Chip-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX10H

Address: 5555H

Load data: XXAAH

Address: 5555H

Wait TSCE

Chip erased

to FFFFH

Load data: XXAAH

Address: 5555H

Sector-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX30H

Address: SAX

Load data: XXAAH

Address: 5555H

Wait TSE

Sector erased

to FFFFH

Load data: XXAAH

Address: 5555H

Block-Erase

Command Sequence

Load data: XX55H

Address: 2AAAH

Load data: XX80H

Address: 5555H

Load data: XX55H

Address: 2AAAH

Load data: XX50H

Address: BAX

Load data: XXAAH

Address: 5555H

Wait TBE

Block erased

to FFFFH

Note: X can be VIL or VIH, but no other value.

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

PRODUCT ORDERING INFORMATION

Valid combinations for SST39WF800A

SST39WF800A-90-4C-B3KE SST39WF800A-90-4C-M2QE SST39WF800A-90-4C-C2QE

SST39WF800A-90-4I-B3KE SST39WF800A-90-4I-M2QE SST39WF800A-90-4I-C2QE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E1 = non-Pb

Package Modifier

K = 48 balls

Q = 48 balls (66 possible positions)

Package Type

B3 = TFBGA (0.8mm pitch, 6mm x 8mm)

M2 = WFBGA (0.5mm pitch, 5mm x 6mm)

C2 = XFLGA (0.5mm pitch, 5mm x 6mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

90 = 90 ns

Device Density

800 = 8 Mbit

Voltage

W = 1.65-1.95V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

SST 39 WF 800A - 90 - 4C - B3K E

XX XX XXXX-XX-XX-XXX X

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

PACKAGING DIAGRAMS

FIGURE 19: 48-Ball Thin-Profile, Fine-Pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

FIGURE 20: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 5mm x 6mm

SST Package Code: C2Q

A1 CORNER

H G F E D C B A

A B C D E F G H

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 ± 0.05

1.10 ± 0.10

0.12

6.00 ± 0.20

0.45 ± 0.05

(48X)

A1 CORNER

8.00 ± 0.20

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-4

Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm (± 0.05 mm)

1mm

L K J H G F E D C B A

ABCDEFGHJKL

0.50

BOTTOM VIEW

5.00 ± 0.08

0.29 ± 0.05

(48X)

A1 INDICATOR4

6.00 ± 0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-xflga-C2Q-5x6-29mic-NR

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-222,

this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. No bump is present in position A1; a gold-colored indicator is present.

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.04 + 0.025/ - 0.015

0.52 max.

0.473 nom.

0.08

Data Sheet

8 Mbit Multi-Purpose Flash

SST39WF800A

FIGURE 21: 48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 5mm x 6mm

SST Package Code: M2Q

TABLE 14: Revision History

Number Description Date

00 •Initial release Aug 2004

01 •Corrected Standby Current from 1 µA to 5 µA on page 1

•Added M2Q package and associated MPNs

•Clarified Surface Mount Temperatures in “Absolute Maximum Stress Ratings” on

page 9

Nov 2004

02 •Changed data sheet status from “Preliminary Specifications” to “Data Sheet”

•Added RoHS compliance information on page 1 and in the “Product Ordering Infor-

mation” on page 23

•Corrected the solder temperature profile in “Absolute Maximum Stress Ratings” on

page 9

Mar 2005

03 •Added C2Q package information and relevant marketing part numbers.

•Removed Pb-based package marketing part numbers from valid ordering list on

page 23.

•Applied new style format.

Feb 2006

04 •In Figure 20 title, changed XFBGA (6mm x 8mm) to XFLGA (5mm x 6mm) Jun 2006

05 •Changed package C2 size from 6mm x 8mm to 5mm x 6mm in Product Ordering

Information on page 23.

Jul 2006

L K J H G F E D C B A

ABCDEFGHJKL

0.50

BOTTOM VIEW

5.00 ± 0.08

0.32 ± 0.05

(48X)

A1 INDICATOR4

6.00 ± 0.08

2.50

5.00

A1 CORNER

TOP VIEW

48-wfbga-M2Q-5x6-32mic-0

Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.08 mm

4. No ball is present in position A1; a gold-colored indicator is present.

5. Ball opening size is 0.29 mm (± 0.05 mm)

1mm

DETAIL SIDE VIEW

SEATING PLANE

0.20 ± 0.06

0.63 ± 0.10

0.08

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036