 
  
FEATURES APPLICATIONS
DESCRIPTION
Single-End/
Differential
Converter BCK
VINL
Reference
Single-End/
Differential
Converter
VREF1
VREF2
VINR
5th Order
Delta-Sigma
Modulator
5th Order
Delta-Sigma
Modulator
×1/64
Decimation
and
High-Pass
Filter
Power Supply
AGNDVCC VDD
DGND
Clock/Timing Control
Serial Data
Interface LRCK
DOUT
FMT
BYPAS
SCKI
(+)
(−)
(−)
(+)
PCM1801
B0004-02
Format
Control
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
SINGLE-ENDED ANALOG-INPUT 16-BIT STEREO ANALOG-TO-DIGITAL CONVERTER
•DVD Recorders•Dual 16-Bit Monolithic Δ Σ ADC
•DVD Receivers•Single-Ended Voltage Input
•AV Amplifier Receivers•Antialiasing Filter Included
•Electric Musical Instruments•64 ×Oversampling Decimation Filter:Pass-Band Ripple: ±0.05 dBStop-Band Attenuation: –65 dB
The PCM1801 is a low-cost, single-chip stereo•Analog Performance:
analog-to-digital converter (ADC) with single-endedTHD+N: –88 dB (typical)
analog voltage inputs. The PCM1801 uses aSNR: 93 dB (typical)
delta-sigma modulator with 64 times oversampling, aDynamic Range: 93 dB (typical)
digital decimation filter, and a serial interface thatInternal High-Pass Filter
supports slave mode operation and two data formats.•PCM Audio Interface: Left-Justified, I
2
S
The PCM1801 is suitable for a wide variety ofcost-sensitive consumer applications where good•Sampling Rate: 4 kHz to 48 kHz
performance is required.•System Clock: 256 f
S
, 384 f
S
, or 512 f
S•Single 5-V Power Supply•Small SO-14 Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE PACKAGE PACKAGE ORDERING TRANSPORT QUANTITYTYPE CODE MARKING NUMBER MEDIA
PCM1801U Rails 56PCM1801U 14-pin SOIC D PCM1801U
PCM1801U/2K Tape and reel 2000
Supply voltage: V
DD
, V
CC
–0.3 V to 6.5 VSupply voltage differences: V
DD
, V
CC
±0.1 VGND voltage differences: AGND, DGND ±0.1 VDigital input voltage –0.3 V to (V
DD
+ 0.3 V), < 6.5 VAnalog input voltage –0.3 V to (V
CC
+ 0.3 V), < 6.5 VInput current (any pin except supplies) ±10 mAPower dissipation 300 mWOperating temperature range –25 °C to 85 °CStorage temperature –55 °C to 125 °CLead temperature, soldering 260 °C, 5 sPackage temperature (IR reflow, peak) 235 °C
over operating free-air temperature range
MIN NOM MAX UNIT
Analog supply voltage, V
CC
4.5 5 5.5 VDigital supply voltage, V
DD
4.5 5 5.5 VAnalog input voltage, full-scale (–0 dB) 2.828 Vp-pDigital input logic family TTLSystem clock 8.192 24.576 MHzDigital input clock frequency
Sampling clock 32 48 kHzDigital output load capacitance 10 pFOperating free-air temperature, T
A
–25 85 °C
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1
2
3
4
5
6
7
14
13
12
11
10
9
8
VREF1
VREF2
AGND
VCC
FMT
BYPAS
DOUT
PCM1801
(TOP VIEW)
P0005-01
VINL
VINR
DGND
VDD
SCKI
BCK
LRCK
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
PIN CONFIGURATION
Table 1. PIN ASSIGNMENTS
NAME PIN I/O DESCRIPTION
AGND 12 – Analog groundBCK 6 I Bit clock inputBYPAS 9 I HPF bypass control
(1)
L: HPF enabledH: HPF disabledDGND 3 – Digital groundDOUT 8 O Audio data outputFMT 10 I Audio data format
(1)
L: MSB-first, left-justifiedH: MSB-first, I
2
SLRCK 7 I Sampling clock inputSCKI 5 I System clock input; 256 f
S
, 384 f
S
, or 512 f
S
V
CC
11 – Analog power supplyV
DD
4 – Digital power supplyV
IN
L 1 I Analog input, LchV
IN
R 2 I Analog input, RchV
REF
1 14 – Reference 1 decoupling capacitorV
REF
2 13 – Reference 2 decoupling capacitor
(1) With 100-k Ωtypical pulldown resistor
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ELECTRICAL CHARACTERISTICS
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, 16-bit data, and SYSCLK = 384 f
S
, unless otherwise noted.
PCM1801UPARAMETER TEST CONDITIONS
MIN TYP MAX UNITS
RESOLUTION 16 Bits
DIGITAL INPUT/OUTPUT
V
IH
(1)
2Input logic level VDCV
IL
(1)
0.8I
IN
(2)
±10Input logic current μAI
IN
(3)
100V
OH
(4)
I
OH
= –1.6 mA 4.5Output logic level VDCV
OL
(4)
I
OL
= 3.2 mA 0.5f
S
Sampling frequency 4 44.1 48 kHz256 f
S
1.024 11.2896 12.288System clock frequency 384 f
S
1.536 16.9344 18.432 MHz512 f
S
2.048 22.5792 24.576
DC ACCURACY
Gain mismatch, channel-to-channel ±1±2.5 % of FSRGain error ±2±5 % of FSRGain drift ±20 ppm of FSR/ °CBipolar zero error High-pass filter bypassed ±2 % of FSRBipolar zero drift High-pass filter bypassed ±20 ppm of FSR/ °C
DYNAMIC PERFORMANCE
(5)
FS (–0.5 dB) –88 –80THD+N dB–60 dB –90Dynamic range A-weighted 90 93 dBSignal-to-noise ratio A-weighted 90 93 dBChannel separation 87 90 dB
ANALOG INPUT
Input range FS (V
IN
= 0 dB) 2.828 Vp-pCenter voltage 2.1 VInput impedance 30 k ΩAntialiasing filter frequency response –3 dB 150 kHz
DIGITAL FILTER PERFORMANCE
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ±0.05 dBStop-band attenuation –65 dBDelay time (latency) 17.4/f
S
sHigh-pass frequency response –3 dB 0.019 f
S
mHz
(1) Pins 5, 6, 7, 9, and 10 (SCKI, BCK, LRCK, BYPAS, and FMT)(2) Pins 5, 6, 7 (SCKI, BCK, LRCK) Schmitt-trigger input(3) Pins 9, 10 (BYPAS, FMT) Schmitt-trigger input with 100-k Ωtypical pulldown resistor(4) Pin 8 (DOUT)(5) f
IN
= 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF and 400-Hz HPFin the performance calculation.
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Single-End/
Differential
Converter BCK
VINL
Reference
Single-End/
Differential
Converter
VREF1
VREF2
VINR
5th Order
Delta-Sigma
Modulator
5th Order
Delta-Sigma
Modulator
×1/64
Decimation
and
High-Pass
Filter
Power Supply
AGNDVCC VDD
DGND
Clock/Timing Control
Serial Data
Interface LRCK
DOUT
FMT
BYPAS
SCKI
(+)
(−)
(−)
(+)
PCM1801
B0004-02
Format
Control
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, 16-bit data, and SYSCLK = 384 f
S
, unless otherwise noted.
PCM1801UPARAMETER TEST CONDITIONS
MIN TYP MAX UNITS
POWER SUPPLY REQUIREMENTS
V
CC
4.5 5 5.5Voltage range VDCV
DD
4.5 5 5.5Supply current
(6)
V
CC
= V
DD
= 5 V 18 24 mAPower dissipation V
CC
= V
DD
= 5 V 90 120 mW
TEMPERATURE RANGE
T
A
Operation –25 85 °CT
stg
Storage –55 125 °C
θ
JA
Thermal resistance 100 °C/W
(6) No load on DOUT (pin 8)
BLOCK DIAGRAM
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30 kΩ
1 kΩ
VINL
VREF1
1
14
13
Delta-Sigma
Modulator
(+)
VREF
VREF2
+
1 µF
4.7 µF
+
4.7 µF
+
+
−
(−)
+
−
1 kΩ
S0011-02
TYPICAL PERFORMANCE CURVES
ANALOG DYNAMIC PERFORMANCE
0.002
0.003
0.004
0.005
0.006
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
−0.5 dB
3.0
2.8
2.6
2.2
2.4
−60 dB
G001
THD+N − Total Harm. Dist. + Noise at −60 dB − %
92
93
94
95
96
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
Dynamic Range − dB
SNR
96
95
94
92
93
SNR − Signal-to-Noise Ratio − dB
G002
Dynamic Range
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
ANALOG FRONT-END (Single Channel)
All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, and SYSCLK = 384 f
S
, unless otherwise noted
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIOvs vsTEMPERATURE TEMPERATURE
Figure 1. Figure 2.
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0.002
0.003
0.004
0.005
0.006
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
3.0
2.8
2.6
2.2
2.4
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G003
−60 dB
−0.5 dB
92
93
94
95
96
4.25 4.50 4.75 5.00 5.25 5.50 5.75
VCC − Supply V oltage − V
Dynamic Range − dB
96
95
94
92
93
SNR − Signal-to-Noise Ratio − dB
G004
Dynamic Range
SNR
0.002
0.003
0.004
0.005
0.006
Sampling Rate − kHz
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
3.0
2.8
2.6
2.2
2.4
G005
THD+N − Total Harm. Dist. + Noise at −60 dB − %
4832 44.1
−60 dB
−0.5 dB
92
93
94
95
96
Dynamic Range − dB
96
95
94
92
93
SNR − Signal-to-Noise Ratio − dB
G006
Dynamic Range
SNR
Sampling Rate − kHz 4832 44.1
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, and SYSCLK = 384 f
S
, unless otherwise noted
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIOvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIOvs vsSAMPLING RATE SAMPLING RATE
Figure 5. Figure 6.
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SUPPLY CURRENT
0
4
8
12
16
20
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
ICC − Supply Current − mA
IDD
G007
ICC + IDD
ICC
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, and SYSCLK = 384 f
S
, unless otherwise noted
SUPPLY CURRENT SUPPLY CURRENTvs vsTEMPERATURE SUPPLY VOLTAGE
Figure 7. Figure 8.
SUPPLY CURRENT
vsSAMPLING RATE
Figure 9.
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OUTPUT SPECTRUM
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Amplitude − dB
G010
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20
Amplitude − dB
G011
Amplitude − dBV
−100 −80 −60 −40 −20 0
THD+N − Total Harmonic Distortion + Noise − %
G012
0.001
0.1
100
0.01
1
10
THD+N − Total Harmonic Distortion + Noise − %
f − Frequency − Hz
20 100 1k 20k
G013
10k
0.0001
0.01
0.1
0.001
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, and SYSCLK = 384 f
S
, unless otherwise noted
FULL-SCALE FFT –60 dBFS FFT
Figure 10. Figure 11.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISEvs vsAMPLITUDE FREQUENCY
Figure 12. Figure 13.
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DECIMATION FILTER
Normalized Frequency [× fS Hz]
−200
−150
−100
−50
0
0 8 16 24 32
Amplitude − dB
G014
Normalized Frequency [× fS Hz]
−100
−80
−60
−40
−20
0
0.00 0.25 0.50 0.75 1.00
Amplitude − dB
G015
Normalized Frequency [× fS Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G016
Normalized Frequency [× fS Hz]
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.47 0.49 0.51 0.53 0.55
Amplitude − dB
G017
−4.13 dB at 0.5 fS
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, and SYSCLK = 384 f
S
, unless otherwise noted
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS
Figure 14. Figure 15.
PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS
Figure 16. Figure 17.
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HIGH-PASS FILTER
Normalized Frequency [× fS/1000 Hz]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
Amplitude − dB
G018
Normalized Frequency [× fS/1000 Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Amplitude − dB
G019
ANTIALIASING FILTER
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Amplitude − dB
1 10 100 10M1k 10k
G020
100k 1M
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
f − Frequency − Hz
Amplitude − dB
1 10 100 100k1k 10k
G021
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 5 V, f
S
= 44.1 kHz, and SYSCLK = 384 f
S
, unless otherwise noted
HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE
Figure 18. Figure 19.
ANTIALIASING FILTER ANTIALIASING FILTERSTOP-BAND CHARACTERISTICS PASS-BAND CHARACTERISTICS
Figure 20. Figure 21.
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THEORY OF OPERATION
1st
SW-CAP
Integrator
Analog
In
X(z) +
−
+−2nd
SW-CAP
Integrator
3rd
SW-CAP
Integrator
+−4th
SW-CAP
Integrator
++++
++++
5th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function B0005-01
SYSTEM CLOCK
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
The PCM1801 consists of a band-gap reference, two channels of a single-to-differential converter, a fullydifferential 5th-order delta-sigma modulator, a decimation filter (including digital high-pass), and a serial interfacecircuit. The block diagram illustrates the total architecture of the PCM1801, and the analog front-end diagramillustrates the architecture of the single-to-differential converter and the antialiasing filter. Figure 22 illustrates thearchitecture of the 5th-order delta-sigma modulator and transfer functions.
An internal high-precision reference with two external capacitors provides all reference voltages which arerequired by the converter, and defines the full-scale voltage range of both channels. The internal single-ended todifferential voltage converter saves the design, space, and extra parts needed for external circuitry required bymany delta-sigma converters. The internal full-differential architecture provides a wide dynamic range andexcellent power-supply rejection performance.
The input signal is sampled at a 64 ×oversampling rate, eliminating the need for a sample-and-hold circuit andsimplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integratorswhich use a switched-capacitor topology, a comparator, and a feedback loop consisting of a 1-bitdigital-to-analog converter (DAC). The delta-sigma modulator shapes the quantization noise, shifting it out of theaudio band in the frequency domain. The high order of the modulator enables it to randomize the modulatoroutputs, reducing idle tone levels.
The 64-f
S
, 1-bit stream from the modulator is converted to 1-f
S
, 16-bit digital data by the decimation filter, whichalso acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by adigital high-pass filter, and the filtered output is converted to time-multiplexed serial signals through a serialinterface which provides flexible serial formats.
Figure 22. Simplified Diagram of the PCM1801 5th-Order Delta-Sigma Modulator
The system clock for the PCM1801 must be either 256 f
S
, 384 f
S,
or 512 f
S
, where f
S
is the audio samplingfrequency. The system clock must be supplied on SCKI (pin 5).
The PCM1801 also has a system clock detection circuit that automatically senses if the system clock isoperating at 256 f
S
, 384 f
S
, or 512 f
S
.
When a 384-f
S
or 512-f
S
system clock is used, the PCM1801 automatically divides the clock down to 256 f
Sinternally. This 256-f
S
clock is used to operate the digital filter and the modulator. Table 2 lists the relationship oftypical sampling frequencies and system clock frequencies. Figure 23 illustrates the system clock timing.
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SCKI 0.8 V
2 V
tCLKIL
tCLKIH
T0005-04
POWER-ON RESET
1024 System Clocks
Reset Reset Removal
4.4 V
4 V
3.6 V
VCC / VDD
Internal Reset
System Clock
3 Clocks Minimum
DOUT Zero Data Normal Data(1)
18436 / fS
T0014-02
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
Table 2. System Clock Frequencies
SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY(kHz)
256 f
s
384 f
s
512 f
s
32 8.1920 12.2880 16.384044.1 11.2896 16.9344 22.579248 12.2880 18.4320 24.5760
System clock pulse duration, HIGH t
(CLKIH)
12 ns (min)System clock pulse duration, LOW t
(CLKIL)
12 ns (min)
Figure 23. System Clock Timing
The PCM1801 has an internal power-on reset circuit, which initializes (resets) when the supply voltage(V
CC
/V
DD
) exceeds 4 V (typical). Because the system clock is used as the clock signal for the reset circuit, thesystem clock must be supplied as soon as power is applied; more specifically, the device must receive at leastthree system clock cycles before V
DD
> 4 V. While V
CC
/V
DD
< 4 V (typical) and for 1024 system clock cycles afterV
CC
/V
DD
> 4 V, the PCM1801 stays in the reset state and the digital output is forced to zero. The digital output isvalid 18,436 f
S
periods after release from the reset state. Figure 24 illustrates the internal power-on reset timingand the digital output for power-on reset.
(1) The transient response (exponentially attenuated signal from ±0.2% dc of FSR with a 200-ms time constant) appearsinitially.
Figure 24. Internal Power-On Reset Timing
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SERIAL AUDIO DATA INTERFACE
DATA FORMAT
16-Bit, MSB-First, Left-Justified
BCK
LRCK Right-ChannelLeft-Channel
DOUT 1
14 15 16321
MSB LSB MSB LSB
14 15 16321
LRCK Right-ChannelLeft-Channel
BCK
DOUT
MSB LSB MSB LSB
16-Bit, MSB-First, I2S
FMT = H
14 15 16321 14 15 16321
FMT = L
T0016-03
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
The PCM1801 interfaces the audio system through BCK (pin 6), LRCK (pin 7), and DOUT (pin 8).
The PCM1801 accepts 64-BCK/LRCK, 48-BCK/LRCK (only for a 384-f
S
system clock) or 32-BCK/LRCK formatfor the left-justified format. And the PCM1801 accepts the 64-BCK/LRCK or 48-BCK/LRCK format (only for a384-f
S
system clock) for I
2
S format.
The PCM1801 supports two audio data formats in slave mode, which are selected by the FMT control input(pin 10) as shown in Table 3 .Figure 25 illustrates the data format. If the application system cannot ensure aneffective system clock prior to power up of the PCM1801, the FMT pin must be held LOW until the power-onreset sequence is completed. In this case, if the I
2
S format (FMT = HIGH) is required in the application, FMT canbe set HIGH after the power-on reset sequence is completed.
Table 3. Data Format
FMT DATA FORMAT
0 (L) 16-bit, left-justified1 (H) 16-bit, I
2
S
Figure 25. Audio Data Format
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INTERFACE TIMING
BCK
LRCK
DOUT
t(BCKH)
t(BCKL)
t(LRHD)
t(LRCP)
t(LRSU)
t(BCKP) t(CKDO) t(LRDO)
1.4 V
1.4 V
0.5 VDD
T0017-02
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
Figure 26 illustrates the interface timing.
DESCRIPTION SYMBOL MIN TYP MAX UNITS
BCK period t
(BCKP)
300 nsBCK pulse duration, HIGH t
(BCKH)
120 nsBCK pulse duration, LOW t
(BCKL)
120 nsLRCK setup time to BCK rising edge t
(LRSU)
80 nsLRCK hold time to BCK rising edge t
(LRHD)
40 nsLRCK period t
(LRCP)
20 μsDelay time, BCK falling edge to DOUT valid t
(CKDO)
–20 40 nsDelay time, LRCK edge to DOUT valid t
(LRDO)
–20 40 nsRising time of all signals t
(RISE)
20 nsFalling time of all signals t
(FALL)
20 ns
NOTE: Timing measurement reference level is (V
IH
+ V
IL
)/2. Rising and falling time ismeasured from 10% to 90% of the I/O signal swing. Load capacitance of the DOUTsignal is 20 pF.
Figure 26. Audio Data Interface Timing
The PCM1801 operates with LRCK synchronized to the system clock (SCKI). The PCM1801 does not require aspecific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. Ifthe relationship between LRCK and SCKI changes more than 6 bit clocks (BCK) during one sample period dueto LRCK or SCKI jitter, internal operation of the ADC halts within 1/f
S
and the digital output is forced to BPZ untilresynchronization between LRCK and SCKI is completed. In case of changes less than 5 bit clocks (BCK),resynchronization does not occur and the previously described digital output control and discontinuity do notoccur. Figure 27 illustrates the ADC digital output for lost synchronization and resynchronization. Duringundefined data, some noise may be generated in the audio signal. Also, the transition of normal to undefineddata and undefined or zero data to normal makes a discontinuity of data on the digital output and may generatesome noise in the audio signal.
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1/fS32/fS
Normal Data(1)
Zero Data
Undefined
Data
Normal Data
SynchronousAsynchronousSynchronous
Resynchronization
Synchronization Lost
DOUT
State of Synchronization
T0020-02
HPF Bypass Control
APPLICATION INFORMATION
BOARD DESIGN AND LAYOUT CONSIDERATIONS
V
CC
, V
DD
PINS
AGND, DGND PINS
V
IN
PINS
V
REF
PINS
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
(1) The transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appearsinitially.
Figure 27. ADC Digital Output for Loss of Synchronization and Re-Synchronization
The built-in function for dc component rejection can be bypassed by BYPAS (pin 9) control (see Table 4 ). Inbypass mode, the dc component of the input analog signal, the internal dc offset, etc., are also converted andoutput in the digital output data.
Table 4. HPF Bypass Control
BYPAS HIGH-PASS FILTER (HPF) MODE
Low Normal (dc cut) modeHigh Bypass (through) mode
The digital and analog power supply lines to the PCM1801 should be bypassed to the corresponding groundpins with both 0.1- μF ceramic and 10- μF tantalum capacitors as close to the pins as possible to maximize thedynamic performance of the ADC. Although the PCM1801 has two power lines to maximize the potential ofdynamic performance, using one common power supply is recommended to avoid unexpected power supplyproblems, such as latch-up due to power supply sequencing.
To maximize the dynamic performance of the PCM1801, the analog and digital grounds are not internallyconnected. These points should have low impedance to avoid digital noise feedback into the analog ground.They should be connected directly to each other under the PCM1801 package to reduce potential noiseproblems.
A 1.0- μF tantalum capacitor is recommended as an ac-coupling capacitor, which establishes a 5.3-Hz cutofffrequency. If a higher full-scale input voltage is required, the input voltage range can be increased by adding aseries resistor to the V
IN
pins.
To ensure low source impedance, 4.7- μF tantalum capacitors are recommended from V
REF
1 to AGND and fromV
REF
2 to AGND. These capacitors should be located as close as possible to the V
REF
1 and V
REF
2 pins to reducedynamic errors on the ADC references.
16
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DOUT PIN
FMT PIN
SYSTEM CLOCK
TYPICAL CIRCUIT CONNECTION DIAGRAM
S0013-01
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Format
Latch Enable
Data Out
+
Pin Program
or Control
Audio
Data
Processor
Lch In
+5 V
C4(2)
VREF1
VREF2
AGND
VCC
FMT
BYPAS
DOUT
VINL
VINR
DGND
VDD
SCKI
BCK
LRCK
0 V
Bypass
+C6(3)
+C5(3)
Data Clock
System Clock
C3(2)
+
Rch In
C1(1)
C2(1)
PCM1801
SBAS131C – OCTOBER 2000 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
The DOUT pin has a large load-drive capability, but locating a buffer near the PCM1801 and minimizing loadcapacitance is recommended in order to minimize the digital-analog crosstalk and maximize the dynamicperformance of the ADC.
In general, the FMT pin is used for audio data format selection by tying up DGND or V
DD
in accordance withinterface requirements. If the application system cannot ensure an effective system clock prior to power up ofthe PCM1801 when I
2
S format is required, then the FMT pin must be set HIGH after the power-on resetsequence. This input control can be accomplished easily by connecting a C-R delay circuit with a delay timegreater than 1 ms to the FMT pin.
The quality of the system clock can influence dynamic performance in the PCM1801. The duty cycle, jitter, andthreshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part,the system clock, bit clock (BCK), and word clock (LRCK) should also be supplied simultaneously. Failure tosupply the audio clocks results in a power dissipation increase of up to three times normal dissipation and maydegrade long-term reliability if the maximum power dissipation limit is exceeded.
Figure 28 is a typical connection diagram illustrating a circuit for which the input HPF cutoff frequency is about5 Hz.
(1) C1 and C2: A 1- μF capacitor gives a 5.3-Hz ( τ= 1 μF * 30 k Ω) cutoff frequency for the input HPF in normal operationand requires a power-on setting time of 30 ms at power up.(2) C3 and C4: Bypass capacitors, 0.1- μF ceramic and 10- μF tantalum or aluminum electrolytic, depending on layoutand power supply(3) C5 and C6: 4.7- μF tantalum or aluminum electrolytic capacitors
Figure 28. Typical Circuit Connection
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PACKAGE OPTION ADDENDUM
www.ti.com 19-Feb-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
PCM1801U ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
PCM1801U/2K ACTIVE SOIC D 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
PCM1801U/2KG4 ACTIVE SOIC D 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
PCM1801UG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Add to cart
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM1801U/2K SOIC D 14 2000 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM1801U/2K SOIC D 14 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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