1
ISL62875
PWM DC/DC Controller with VID Inputs for
Portable GPU Core-Voltage Regulator
ISL62875
The ISL62875 is a Single-Phase S ynchronous-Buck
PWM volt age regulator featurin g Intersil’s R obust Ripple
Regulator (R3) Technology™. The wide 3.3V to 25V
input voltage range is ideal for systems that run on
battery or AC-adapter power sources. The ISL62875 is a
low-c ost solu tio n for app licat ion s requi rin g dyna mica lly
selected slew - r at e contr olled output v olt ages. Th e
soft-start and dynamic setpoint slew-r ates are capacitor
programmed. Voltage identification logic-inp uts selec t
four resisto r-pro gr a mme d setpoi nt re fe rence v olta ges
that directly set the output voltage of the conv erter
between 0.5V to 1.5V, and up to 3.3V using a feedback
voltage divid er. R o bust integ r at ed MOSFET driv er s and
Schottky bootstrap diode reduce the implementation
area and component cost.
Intersil’ s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The
PWM frequency is 500kHz during static operation,
becoming variable during changes in load, setpoint
voltage, and input voltage when changing between
battery and AC-adapter power. The modulators ability to
change the PWM switching frequency during these
events in conjunction with external loop compensation
produces superior transient response. For maximum
efficiency, the converter automatically enters diode-
emulation mode (DEM) during light-load conditions such
as system standby.
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Output Load up to 30A
• Extremely Flexible Output Voltage Programmability
- 2-Bit VID Selects Four Independent Setpoint
Voltages
- Simple Resistor Programming of Setpoint Voltages
- Accepts External Setpoint Reference such as DAC
• ±0.75% System Accuracy: -10°C to +100°C
• Fixed 500kHz PWM Frequency in Continuous
Conduction
• Integrated High-current MOSFET Drivers and
Schottky Boot-Strap Diode for Optimal Efficiency
Applications*(see page 21)
• Mobile PC GPU Core Power
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Tablet PCs/Slates and Netbooks
• Hand-Held Portable Instruments
Related Literature*(see page 21)
• TB389 “PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages”
Typical Application
LO
COUT
CBOOT COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
CIN
VIN
VOUT
CSOFT
RSET1 RSET2 RSET3
RSET4
CVCC
+5V
CPVCC
GPIO
GPIO
RPGOOD
VCC
ROFS
PHASE
LGATE
PVCC
VCC
BOOT
UGATE
OCSET
VO
FB
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
SET2
PGOOD
1
2
3
4
5
12
6
7
8
9
10 11
13
14
16
17
18
19
20
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a regi s tered trademark of Inters il Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
FN6905.1
September 18, 2009
2September 18, 2009
FN6905.1
ISL62875
Application Schematics
FIGURE 1. ISL62875 APPLICATION SCHEMATIC WITH FO UR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT
SENSE
FIGURE 2. ISL62875 APPLICATION SCHEMATIC WITH FOUR OUTP UT VOLTAGE SETPOINTS A ND RESISTOR
CURRENT SENSE
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
FB
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
SET2
PGOOD
LGATE
PVCC
LO
COC
CBOOT COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25 V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
RSET1 RSET2 RSET3
RSET4
CVCC
+5V
RVCC
CPVCC
GPIO
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
110
11 20
GPIO
RPGOOD
VCC
ROFS
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
FB
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
LO
COC
COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
GPIO
3.3V TO 25 V
0.5V TO 3.3V
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1LGATE
PVCC
10
11 20
SET2
PGOOD
RO
COB
CINCCINB
VIN
VOUT
CSOFT
RSET1 RSET2 RSET3
RSET4
CVCC
+5V
RVCC
CPVCC
RSNS
CBOOT
RPGOOD
VCC
GPIO
ROFS
3September 18, 2009
FN6905.1
FIGURE 3. ISL62875 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
Application Schematics (Continued)
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
FB
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
SET2
PGOOD
LGATE
PVCC
LO
COC
CBOOT COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25 V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
CVCC
+5V
RVCC
CPVCC
GPIO
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
110
11 20
GPIO
RPGOOD
VCC
ROFS
EXT_REF
ISL62875
4September 18, 2009
FN6905.1
Block Diagram
PGND
PVCC
UVP
+
−
POR
SET1
SET2
VID1
VID0
VID DECODER
SET0
SREF
BOOT
LGATE
DRIVER UGATE
DRIVER
PHASE
VO
OCSET
+
−
OCP
VSET
FB
PGOOD
SW1
SW2
SW3
SW0
100pF
SW4
VREF
FIGURE 4. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62875
100kΩ
VCC
INT
GND
IOCSET
10µA
+
−
+
−
+
−
Cr
H
L
IN
VCC
PWM
VW
EN
PWM
RUN
RUN
RUN
FAULT
EXT
500mV
gmVO
gmVIN
VR
VCOMP
+
−
EA
FB
PROTECTION
SHOOT-THROUGH
OTP
FAULT
ISL62875
5September 18, 2009
FN6905.1
Pin Configuration
ISL62875
(20 LD 3.2X1.8 µTQFN)
TOP VIEW
19
18
17
16
15
14
13
1
2
10
11
2
3
4
5
6
7
8
PGND
GND
EN
VID1
VID0
SREF
SET0
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
LGATE
PVCC
SET2
P
GOOD
9
SET1 12 FB
ISL62875 Functional Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1 LGA TE Low-side MOSFET gate driver output. Con nect to the gate terminal of t he low-side MOSFET of
the converter.
2 PGND Return current path for the LGA TE MOSFET driver. Connect to the source of the low- side MOSFET.
3 GND IC ground for bias supply and signal reference.
4 EN Enable input for th e IC. Pulling EN above the VENTHR rising threshold voltage initializes the
soft-start sequence.
5 VID1 Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four
setpoint reference voltages.
6 VID0 Logic input for setpoint v oltage selector. Use in conjunction with the VID1 pin to select among
four setpoint reference voltages. External reference input when enabled by connecting the
SET0 pin to the VCC pin.
7 SREF Soft-start and voltage slew-rate programming capacitor input. Setpoint reference voltage
programming resistor input. Connects internally to the inverting input of the VSET volta ge
setpoint amplifier.
8 SET0 Voltage set-point programming resistor input.
9 SET1 Voltage set-point programming resistor input.
10 SET2 Voltage set-point programming resistor input.
11 PGOOD Power-good open-drain indicator output. This pin changes to high impedance when the
converter is able to supply regulated voltage. The pull-down resistance between the PGOOD
pin and the GND pin identifies which protective fault has shut down the regulator.
12 FB Voltage feedback sense input. Connects internally to the inverting input of the control-loop
error amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage
on the SREF pin. The control loop compensation network connects between the FB pin and the
converter output.
13 VO Output voltage sense input for the R3 modulator. The VO pin also serves as the reference input
for the overcurrent detection circuit.
ISL62875
6September 18, 2009
FN6905.1
14 OCSET Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor
ROCSET connects from this pin to the sense node .
15 NC No internal connection. Pin 15 should be connected to the GND pin.
16 PHASE Return current path for the UGATE high-side MOSFET driver. VIN sense input for the R3
modulator. Inductor current polari ty detector input. Connect to junction of output inductor,
high-side MOSFET, and low-side MOSFET. See Figures 1 and 2 on page 2.
17 UGA TE High-s ide MOSFET gate dr iver out put. Connect to th e gate terminal of the high-side M OSFET
of the converter.
18 BOOT Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally
connected to the cathode of the Schottky boot-strap diode. Connect an MLCC between the
BOOT pin and the PHASE pin.
19 VCC Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a 1µF
MLCC to the GND pin. See “Application Schematics” (Figures 1 and 2) on page 2.
20 PVCC Input for the LGATE and UGA TE MOSFET driver circuits. The PVCC pin is internally connected
to the anode of the Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple
with a 10µF MLCC to the PGND pin. See “Application Schematics” (Figures 1 and 2) on page 2.
ISL62875 Functional Pin Descriptions (Continued)
PIN
NUMBER SYMBOL DESCRIPTION
Ordering Information
PART NUMBER
(Notes 1, 2, 3) PART MARKING TEMP RANGE
(°C) PACKAGE
(Pb-Free) PKG. DWG. #
ISL62875HRUZ-T* GAR -10 to +100 20 Ld 3.2x1.8 µTQFN (Tape and Reel) L20.3.2x1.8
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb -free plast ic packaged produ cts emplo y special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62875. For more information on MSL please
see techbrief TB363.
ISL62875
7September 18, 2009
FN6905.1
Table of Contents
Application Schematics ....................................................................................................................... 2
Block Diagram .................................................................................................................................... 4
Pin Configuration .............................................. ............. ............. ........................................................ 5
ISL62875 Functional Pin Descriptions ................................................................................................ 5
Ordering Information ......................................................................................................................... 6
Absolute Maximum Ratings ................................................................................................................ 8
Thermal Information ........................................ .................................................................................. 8
Recommended Operating Conditions .................................................................................................. 8
Electrical Specifications ...................................................................................................................... 8
Theory of Operation .......................................................................................................................... 11
Modulator ...................................................................................................................................... 11
Synchronous Rectification ................................................................................................................. 11
Diode Emulation .............................................................................................................................. 11
Power-On Reset .......... .. .. ............. ............ .. ............. ............. ............ ............. .. ............. ................... 12
VIN and PVCC Voltage Sequence ....................................................................................................... 12
Start-Up Timing .............................................................................................................................. 12
PGOOD Monitor ............................................................................................................................... 12
LGATE and UGATE MOSFET Gate-Driv ers ................ .. .. .. .. ....................................................................12
Adaptive Shoot-Through Protection .................................................................................................... 12
Setpoint Reference Voltage Programming ........................................................................................ 13
Calculating Setpoint Voltage Programming Resistor Values ................................................................... 13
External Setpoint Reference .............................................................................................................. 14
Soft-Start and Voltage-Step Delay .................................................................................................... 14
Circuit Description ........................................................................................................................... 14
Component Selection For CSOFT Capacitor ............................ ............. ..................... ............. ............... 15
Compensation Design ........................................................................................... ............. ............... 15
Fault Protection .............................................................................................................. .................. 15
Overcurrent .................................................................................................................................... 15
Component Selection for ROCSET and CSEN ......................................................................................... 16
Overvoltage .................................................................................................................................... 16
Undervoltage .................................................................................................................................. 16
Over-Tempera ture ........................................................................................................................... 16
General Application Design Guide ..................................................................................................... 16
Selecting the LC Output Filter ........................................................................................................... 17
Selection of the Input Capacitor ........................................................................................................ 17
Selecting The Bootstrap Capacitor ..................................................................................................... 17
Driver Power Dissipation .................................................................................................................. 18
MOSFET Selection and Considerations ................................................................................................ 18
PCB Layout Considerations ............................................................................................................... 19
Power and Signal Layers Placement on the PCB ...................................................................................19
Component Placement ..................................................................................................................... 19
Signal Ground and Power Ground ...................................................................................................... 19
Routing and Connection Details ......................................................................................................... 19
Copper Si ze for the Phase Node ............... ............. ..................... ....................... ............. ................... 20
Revision History ............................................................................................................................... 21
Products ........................................................................................................................................... 21
Package Outline Drawing .................... ............. ............. ................................................................... 22
ISL62875
8September 18, 2009
FN6905.1
Absolute Maximum Ratings
VCC, PVCC, PGOOD to GND. . . . . . . . . . . . . -0.3V to +7.0V
VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, SET0, SET1, SET2, VO,
VID0, VID1, FB, OCSET, SREF . . . -0.3V to GND, VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . -0.3V to 33V
BOOT To PHASE Voltage (VBOOT-PHASE) . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage. . . . . . . . . . . . . . . . . . . .GND - 0.3V to 28 V
GND -8V (<20ns Pulse Width, 10µJ)
UGATE Voltage. . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Thermal Information
Thermal Resistance (Typical) θJA (°C/W)
20 Ld µTQFN Package (Notes 4, 5). . . . . . . . 84
Junction Temp erature Range . . . . . . . . . . . -55°C to +150°C
Operating Temperature Range . . . . . . . . . . -10°C to +100°C
Storage Temperature. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . -10°C to +100°C
Converter Input Vol tage to GND . . . . . . . . . . . . 3.3V to 25V
VCC, PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications These specificatio ns apply for TA = -10°C to +100°C, unless ot herwise stated.
All typica l specifications TA = +25°C, VCC = 5V. Boldfa ce limits apply over th e operating
temperature range, -10 °C t o +10 0°C.
PARAMETER SYMBOL TEST CONDITIONS MIN
(Note 7) TYP MAX
(Note 7) UNIT
VCC and PVCC
VCC Input Bias Current IVCC EN = 5V, VCC = 5V, FB = 0.55V, SREF < FB -1.1 1.5 mA
VCC Shutdown Current IVCCoff EN = GND, VCC = 5V -0.1 1.0 µA
PVCC Shutdown Current IPVCCoff EN = GND, PVCC = 5V -0.1 1.0 µA
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage VVCC_THR 4.40 4.49 4.60 V
Falling VCC POR Threshold Voltage VVCC_THF 4.10 4.22 4.35 V
REGULATION
Reference Voltage VREF(int) -0.50 -V
System Accuracy VID0 = VID1 = GND, PWM Mode = CCM -0.75 -+0.75 %
PWM
Switching Frequency FSW PWM Mode = CCM 450 500 550 kHz
VO
VO Input Voltage Range VVO 0-3.6 V
VO Input Impedance RVO EN = 5V -600 -kΩ
VO Reference Offset Current IVOSS VENTHR < EN, SREF = Soft-Start Mode -10 -µA
VO Input Leakage Current IVOoff EN = GND, VO = 3.6V -0.1 -µA
ERROR AMPLIFIER
FB Input Bias Current IFB EN = 5V, FB = 0.50V -20 -+50 nA
SREF
SREF Operating Voltage Range VSREF Nominal SREF Setting with 1% Resistors 0.5 -1.5 V
Soft-Start Current ISS SREF = Soft-Start Mode 10 20 30 µA
ISL62875
9September 18, 2009
FN6905.1
Voltage Step Current IVS SREF = Setpoint-Stepping Mode ±60 ±100 ±140 µA
EXTERNA L REFEREN C E
EXTREF Operating Voltage Range VEXT SET0 = VCC 0-1.5 V
EXTREF Accuracy VEXT_OFS SET0 = VCC, VID0 = 0V to 1.5V -0.5 -+0.5 %
POWER GOOD
PGOOD Pull-down Impedance RPG_SS PGOOD = 5mA Sink 75 95 150 Ω
RPG_UV PGOOD = 5mA Sink 75 95 150 Ω
RPG_OV PGOOD = 5mA Sink 50 65 90 Ω
RPG_OC PGOOD = 5mA Sink 25 35 50 Ω
PGOOD Leakage Current IPG PGOOD = 5V -0.1 1.0 µA
PGOOD Maximum Sink Current
(Note 6) IPG_max -5.0 -mA
GATE DRIVER
UGATE Pull-Up Resistance (Note 6) RUGPU 200mA Source Current -1.0 1.5 Ω
UGATE Source Current (Note 6) IUGSRC UGATE - PHASE = 2.5V -2.0 -A
UGATE Sink Resistance (Note 6) RUGPD 250mA Sink Current -1.0 1.5 Ω
UGATE Sink Current (Note 6) IUGSNK UGATE - PHASE = 2.5V -2.0 -A
LGATE Pull-Up Resistance (Note 6) RLGPU 250mA Source Current -1.0 1.5 Ω
LGATE Source Current (Note 6) ILGSRC LGATE - GND = 2.5V -2.0 -A
LGATE Sink Resistance (Note 6) RLGPD 250mA Sink Current -0.5 0.9 Ω
LGATE Sink Current (Note 6) ILGSNK LGAT E - PGND = 2.5V -4.0 -A
UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load -21 -ns
LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load -21 -ns
PHASE
PHASE Input Impedance RPHASE -33 -kΩ
BOOTSTRAP DIODE
Forward Voltage VFPVCC = 5V, IF = 2mA -0.58 -V
Reverse Leakage IRVR = 25V -0.2 -µA
CONTROL INPUTS
EN High Threshold Voltage VENTHR 2.0 --V
EN Low Threshold Voltage VENTHF --1.0 V
EN Input Bias Current IEN EN = 5V 1.5 2.0 2.5 µA
EN Leakage Current IENoff EN = GND -0.1 1.0 µA
VID<0,1> High Threshold Voltage VVIDTHR 0.6 --V
VID<0,1> Low Threshold Voltage VVIDTHF --0.5 V
VID<0,1> Input Bias Current IVID EN = 5V, VVID = 1V -0.5 -µA
VID<0,1> Leakage Current IVIDoff -0-µA
Electrical Specifications These specificatio ns apply for TA = -10°C to +100°C, unless ot herwise stated.
All typica l specifications TA = +25°C, VCC = 5V. Boldfa ce limits apply over th e operating
temperature range, -10 °C t o +10 0°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN
(Note 7) TYP MAX
(Note 7) UNIT
ISL62875
10 September 18, 2009
FN6905.1
PROTECTION
OCP Threshold Voltage VOCPTH VOCSET - VO-1.75 -1.75 mV
OCP Reference Current IOCP EN = 5.0V 9.0 10 11 µA
OCSET Input Resistance ROCSET EN = 5.0V -600 -kΩ
OCSET Leakage Current IOCSET EN = GND -0-µA
UVP Threshold Voltage VUVTH VFB = %VSREF 81 84 87 %
OTP Rising Threshold Temperature
(Note 6) TOTRTH -150 -°C
OTP Hysteresis (Note 6) TOTHYS -25 -°C
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production te sted.
Electrical Specifications These specificatio ns apply for TA = -10°C to +100°C, unless ot herwise stated.
All typica l specifications TA = +25°C, VCC = 5V. Boldfa ce limits apply over th e operating
temperature range, -10 °C t o +10 0°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN
(Note 7) TYP MAX
(Note 7) UNIT
ISL62875
11 September 18, 2009
FN6905.1
Theory of Operation
The modulator features Intersil’s R3 Robust-Ripple-
Regulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic control. The
PWM frequency is maintained at 500kHz under static
continuous-conduction-mode operation within the entire
specified envelope of input voltage, output vo ltage, and
output load. If the application should experience a rising
load transient and/or a falling line tr ansient such that the
output voltage starts to fall, the modulator will extend
the on-time and/or reduce the off -time of the PWM pulse
in progress. Conversely, if the application should
experience a falling load transient and/or a rising line
transient such that the output voltage starts to rise, the
modulator will truncate the on-time and/or extend the
off-time of the PWM pulse in progress. The period and
duty cycle of the ensuing PWM pulses are optimized by
the R3 modulator for the remainder of the transient and
work in concert with the error amplifier VERR to maintain
output voltage regulation. Once the transient has
dissipated and the control loop has recovered, the PWM
frequency returns to the nominal static 500kHz.
Modulator
The R3 modulator synthesizes an AC signal VR, which is
an analog representation of the output inductor ripple
current. The duty-cycle of VR is the result of charge and
discharge current through a ripple capacitor CR. The
current through CR is provided by a transconductance
amplifier gm that measures the input voltage (VIN) at the
PHASE pin and output voltage (VOUT) at the VO pin. The
positive slope of VR can be written as Equation 1:
The negative slope of VR can be written as Equ ation 2:
Where, gm is the gain of the tr ansconductance amplifier.
A window voltage VW is referenced with respect to the
error amplifier output voltage VCOMP, creating an
envelope into which the ripple voltage VR is compared.
The amplitude of VW is controlled internally by the IC.
The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold
voltage and VW is the higher threshold voltage. Figure 5
shows PWM pulses being generated as VR tra verses the
VW and VCOMP thresholds. The PWM switching frequency
is proportional to the slew rates of th e positiv e and
negative slopes of VR; it is inversely proportional to the
voltage between VW and VCOMP.
Synchronous Rectification
A standard DC/DC buck regulator uses a free-wheeling
diode to maintain uninterrupted current conduction
through the output inductor when the high-side MOSFET
switches off for the balance of the PWM switching cycle.
Low conversion efficiency as a result of the conduction
loss of the diode makes this an unattractive option for all
but the lowest current applications. Efficiency is
dramatically improv ed when the free- wheeling diode is
replaced with a MOSFET that is turned on whenev er the
high-side MOSFET is turned off. This modification to the
standard DC/DC buck regulator is referred to as
synchronous rectification, the topology implemented by
the ISL62875 controller.
Diode Emulation
The polarity of the output inductor current is defined as
positive when conducting away from the phase node,
and defined as negative when conducting towards the
phase node. The DC component of the inductor current is
positive, but the AC component known as the ripple
current, can be either positive or negativ e. Should the
sum of the AC and DC components of the inductor
current remain positive for the entire switching period,
the converter is in continuous-conduction-mode (CCM.)
However, if the inductor current becomes negative or
zero, the con verter is in discontinuous-conduction-mode
(DCM.)
Unlike the standard DC/DC buck regulator, the
synchronous rectifier can sink current from the output
filter inductor during DCM, reducing the light-load
efficiency with unnecessary conduction loss as the low-
side MOSFET sinks the inductor current. The ISL62875
controller avoids the DCM con duction loss by making the
low-side MOSFET emulate the current-blocking behavior
of a diode. This smart -diode oper ation called diode-
emulation-mode (DEM) is triggered when the negative
inductor current produces a positive voltage drop across
the rDS(ON) of the low-side MOSFET for eight consecutive
PWM cycles while the LGATE pin is high. The converter
will exit DEM on the next PWM pulse after detecting a
negative voltage across the rDS(ON) of the low-side
MOSFET.
It is characteristic of the R3 architecture for the PWM
switching frequency to decrease while in DCM, increasing
efficiency by reducing unnecessary gate-driver switching
losses. The extent of the frequency reduction is
proportional to the reduction of load current. Upon
entering DEM, the PWM frequ ency is forced to fall
approximately 30% by forcing a similar increase of the
VRPOS gm
()VIN VOUT
–()CR
⁄⋅=(EQ. 1)
VRNEG gmVOUT CR
⁄⋅=(EQ. 2)
FIGURE 5. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
PWM
RIPPLE CAPACITOR VOLTAGE CRWINDOW VOLTAGE V
W
ERROR AMPLIFIER VOLTAGE VCOMP
ISL62875
12 September 18, 2009
FN6905.1
window voltage VW. This measure is taken to prevent
oscillating between modes at the boundary between CCM
and DCM. The 30% increase of VW is removed upon exit
of DEM, forcing the PWM sw itching frequ ency to jump
back to the nominal CCM value.
Power-On Reset
The IC is disabled until the voltage at the VCC pin has
increased above the rising power -on reset (POR)
threshold voltage VVCC_THR. The controller will become
disabled when the voltage at the VCC pin decreases below
the falling POR threshold voltage VVCC_THF. The POR
detector has a noise filter of approximately 1µs.
VIN and PVCC Voltage Sequence
Prior to pulling EN above the VENTHR rising threshold
voltage, the following criteria must be met:
-V
PVCC is at least equivalent to the VCC rising
power-on reset voltage VVCC_THR
-V
VIN must be 3.3V or the minimum required by the
application
Start-Up Timing
Once VCC has ramped above V VCC_THR, the controller
can be enabled by pulling the EN pin voltage above the
input-high threshold VENTHR. Approximately 20µs later,
the voltage at the SREF pin begins slewing to the
designated VID set-point. The converter output vo ltage
at the FB feedback pin follows the voltage at the SREF
pin. During soft-start, The regulator alwa ys oper ates in
CCM until the soft-start sequence is complete.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable
of supplying regulated voltage. Th e PGOOD pin is an
undefined impedance if the VCC pin has not reached the
rising POR threshold VVCC_THR, or if the VC C pin is below
the falling POR threshold VVCC_THF. The PGOOD
pull-down resistance corresponds to a specific protective
fault, thereby reducing troubleshooting time and effort.
Table 1 maps the pull-down resistance of the PGOOD pin
to the corresponding fault status of the controller.
LGATE and UGATE MOSFET Gate-Drivers
The LGATE pin and UGA TE pin s are MOSFET driv er
outputs. The LGATE pin drives the low-side MOSFET of
the converter while the UGATE pin drives the high-side
MOSFET of the conv erter.
The LGATE driver is optimized for low duty -cy cle
applications where the low-side MOSFET experiences
long conduction times. In this environment, the low-side
MOSFETs require exceptionally low rDS(ON) and tend to
have large par asitic charges that conduct tr ansient
currents within the devices in response to high dv/dt
switching pres ent at the ph ase node. The dr ain-gate
charge in particular can conduct sufficient current
through the driver pull-down resistance that the VGS(th)
of the device can be exceeded and turned on. For this
reason the LGATE driver has been designed with low
pull-down resistance and high sink current capability to
ensure clamping the MOSFETs gate voltage below
VGS(th).
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driv er
output has fallen below approximately 1V. The dead-time
shown in Figure 6 is extended by the additional period
that the falling gate voltage remains above the 1V
threshold. The high-side gate-driver output v oltage is
measured across the UGATE and PHASE pins while the
low-side gate-driver output voltage is measured across
the LGATE and PGND pins. The power for the LGATE
gate-driver is sourced directly from the PVCC pin. The
power for the UGATE gate-driver is supplied by a boot-
strap capacitor connected across the BOO T and PHASE
pins. The capacitor is charged each time the phase node
voltage falls a diode drop below PVCC such as when the
low-side MOSFET is turned on.
TABLE 1. PGOOD PULL-DOWN RESISTANCE
CONDITION PGOOD RESISTANCE
VCC Below POR Undefined
Soft-Start or Undervoltage 95Ω
Overcurrent 35Ω
FIGURE 6. GATE DRIVER ADAPTIVE SHOOT-THROUGH
1V
1V
UGATE
LGATE
1V
1V
ISL62875
13 September 18, 2009
FN6905.1
Setpoint Reference Voltage
Programming
V oltage identification (VID) pins select user-programmed
setpoint reference voltages that appear at the SREF pin.
The converter is in regulation when the FB pin v oltage
(VFB) equals the SREF pin voltage (VSREF.) The IC
measures VFB and VSREF relative to the GND pin, not the
PGND pin. The setpoint reference voltages use the
naming convention VSET(x) where (x) is the first, second,
third, or fourth setpoint reference voltage where:
-V
SET1 < VSET2 < VSET3 < VSET4
-V
OUT1 < VOUT2 < VOUT3 < VOUT4
The VSET1 setpoint is fixed at 500mV because it
corresponds to the closure of internal switch SW0 that
configures the V SET amplifier as a unity -gain v oltage
follower for the 500mV voltage reference VREF.
A feedback v oltage-div ider network m ay be requir ed to
achieve the desired reference v oltages. Using the
feedback voltage-divider allows the maximum output
voltage of the con verter to be higher than the 1.5V
maximum setpoint reference voltage th at can be
programmed on the SREF pin. Likewise, the feedback
voltage-divider allows the minimum output voltage of the
converter to be higher than the fix ed 500mV setpoint
reference voltage of VSET1. Scale the voltage-divider
network such that the voltage V FB equals the voltage
VSREF when the converter output voltage is at the
desired level. The voltage-divider relation is giv en in
Equation 3:
Where:
-V
FB = VSREF
-R
FB is the loop-compensation feedback resistor
that connects from the FB pin to the converter
output
-R
OFS is the voltage-scaling programming resistor
that connects from the FB pin to the GND pin
The attenuation of the feedback voltage divider is written
as:
Where:
-K is the attenuation factor
-V
SREF(lim) is the VSREF voltage setpoint of either
500mV or 1.50V
-V
OUT(lim) is the output voltage of the converter
when VSREF = VSREF(lim)
Since the voltage-divider network is in the feedback
path, all output voltage setpoints will be attenuated by K,
so it follows that all of the setpoint reference voltages will
be attenuated by K. It will be necessary then to include
the attenuation factor K in all the calculations for
selecting the RSET programming resistors.
The value of offset resistor ROFS can be calculated only
after the value of loop-compensati on re si stor R FB has
been determined. The calcul ation of R OFS is written as
Equation 5:
The setpoint reference voltages are programmed with
resistors that use the naming convention RSET(x) where
(x) is the first, second, third, or fourth progr amming
resistor connected in series starting at the SREF pin and
ending at the GND pin. When one of the internal switches
closes, it connects the inverting input of the VSET
amplifier to a specific node among the string of R SET
programming resistors. All the resistors between that
node and the SREF pin serve as the feedback impedance
RF of the VSET amplifier. Likewise, all the resistors
between that node and the GND pin serve as the input
impedance RIN of the VSET amplifier. Equation 6 gives
the general form of the gain equation for the VSET
amplifier:
Where:
-V
REF is the 500mV internal reference of the IC
-V
SET(x) is the resulting setpoint reference voltage
that appears at the SREF pin
Calculating Setpoint Voltage Programming
Resistor Values
First, determine the attenuation factor K. Next, assign an
initial value to R SET4 of approximately 100kΩ then
calculate RSET1, RSET2, and RSET3 using Equations 7, 8,
and 9 respectively. The equation for the value of RSET1 is
written as Equation 7:
The equation for the value of R SET2 is written as
Equation 8:
VFB VOUT ROFS
RFB ROFS
+
----------------------------------
⋅=(EQ. 3)
KVSREF lim()
VOUT lim()
------------------------------- ROFS
RFB ROFS
+
----------------------------------
== (EQ. 4)
TABLE 2. ISL62875 VID TRUTH TABLE
VID STATE RESULT
VID1 VID0 CLOSE VSREF VOUT
11SW0V
SET1 VOUT1
10SW1V
SET2 VOUT2
01SW2V
SET3 VOUT3
00SW3V
SET4 VOUT4
ROFS VSET x() R⋅FB
VOUT VSET x()
–
--------------------------------------------
=(EQ. 5)
VSET X)( VREF 1RF
RIN
----------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 6)
RSET1 RSET4 KVSET4 KVSET2 VREF
–()⋅⋅
VREF KVSET2
⋅
----------------------------------------------------------------------------------------------------
=(EQ. 7)
RSET2 RSET4 KVSET4 KVSET3 KVSET2
–()⋅⋅
KVSET2 KVSET3
⋅
-----------------------------------------------------------------------------------------------------------
=(EQ. 8)
ISL62875
14 September 18, 2009
FN6905.1
The equation for the value of R SET3 is written as
Equation 9:
The sum of all the progr amming resistors should be
approximately 300kΩ as shown in Equation 10 otherwise
adjust the value of RSET4 and repeat the calculations.
Equations 11, 12, 13 and 14 give the specific VSET gain
equations for the ISL62875 setpoint reference voltages.
The ISL62875 VSET1 setpoint is written as Equ ation 11:
The ISL62875 VSET2 setpoint is written as Equ ation 12:
The ISL62875 VSET3 setpoint is written as Equ ation 13:
The ISL62875 VSET4 setpoint is written as Equ ation 14:
External Setpoint Reference
The IC can use an external setpoint reference voltage as
an alternative to VID-selected, resistor-progr ammed
setpoints. This is accomplished by removing all setpoint
programming resistors, connecting the SET0 pin to the
VCC pin, and feeding the external setpoint reference
voltage to the VID0 pin. When SET0 and VCC are tied
together, the following internal recon figur ations tak e
place:
- VID0 pin opens its 500nA pull-down current sink
- R eference source selector switch SW4 mov es from
INT position (internal 500mV) to EXT position
(VID0 pin)
- VID1 pin is disabled
The converter will now be in regulation when the voltage
on the FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage
range on the VID0 pin is 500mV to 1.5V. Use Equations
3, 4, and 5 beginning on page 13 should it become
necessary to implement an output voltage-divider
network to make the external setpoint reference voltage
compatible with the 500mV to 1.5V constraint.
Soft-Start and Voltage-Step
Delay
Circuit Description
When the voltage on the VCC pin has r amped above the
rising power-on reset voltage VVCC_THR, and the voltage
on the EN pin has increased above the ri sing enable
threshold voltage VENTHR, the SREF pin releases its
discharge clamp and enables the reference amplifier
VSET. The soft-start current ISS is limited to 20µA and is
sourced out of the SREF pin into the par allel RC network
of capacitor CSOFT and resistance RT. The resistance RT
is the sum of all the series connected RSET programming
resistors and is written as Equation 15:
The voltage on the SREF pin rises as ISS charges CSOFT
to the voltage reference setpoint selected by the state of
the VID inputs at the time the EN pin is asserted. The
regulator controls the PWM such that the v oltage on the
FB pin tracks the rising vo ltage on the SREF pin. Once
CSOFT charges to the selected setpoint voltage, the ISS
current source comes out of the 20µA current limit and
decays to the static value set by VSREF ÷ RT. The elapsed
time from when the EN pin is asserted to when V SREF
has reached the voltage reference setpoint is the soft-
start delay tSS which is given by E quation 16:
Where:
-ISS is the soft-start current source at the 20µA
limit
-V
START-UP is the setpoint reference voltage
selected by the state of the VID inputs at the time
EN is asserted
-R
T is the sum of the RSET progr amming resistors
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to the designated VSET voltage
RSET3 RSET4 KVSET4 KVSET3
–()⋅
KVSET3
--------------------------------------------------------------------------------
=(EQ. 9)
RSET1 RSET2 RSET3 RSET4
+++ 300kΩ≅ (EQ. 10)
VSET1 VREF
=(EQ. 11)
VSET2 VREF 1RSET1
RSET2 RSET3 RSET4
++
---------------------------------------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 12)
VSET3 VREF 1RSET1 RSET2
+
RSET3 RSET4
+
--------------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 13)
VSET4 VREF 1RSET1 RSET2 R+SET3
+
RSET4
---------------------------------------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 14)
FIGURE 7. VOLTAGE PROGRAMMING CIRCUIT
SET2
SET0
SREF
VSET
+
-
SW0
VREF
SET1
SW1
SW2
SW3
CSOFT
RSET1
RSET2
RSET3
RSET4
EA
+
-
FB
ROFS
RFB
VOUT VCOMP
500mV RTRSET1 RSET2 …RSET n()
++=(EQ. 15)
tSS RTCSOFT
⋅()–LN 1 VSTART-UP
ISS RT
⋅
------------------------------
–()⋅=(EQ. 16)
ISL62875
15 September 18, 2009
FN6905.1
reference setpoint. The SSOK flag is set, the PGOOD pin
goes high, and the ISS current source changes over to
the voltage-step current source IVS which has a current
limit of ±100µA. Whenever the VID inputs or the
external setpoint reference, programs a different setpoint
reference voltage, the IVS current source charges or
discharges capacitor CSOFT to that new level at ±100µA.
Once CSOFT charges to the selected setpoint voltage, the
IVS current source comes out of the 100µA current limit
and decays to the static v alue set by VSREF ÷ RT. The
elapsed time to charge CSOFT to the new voltage is
called the voltage-step delay tVS and is given by
Equation 17:
Where:
-IVS is the ±100µA setpoint voltage-step current
-V
NEW is the new setpoint voltage selected by the
VID inputs
-V
OLD is the setpoint voltage that VNEW is changing
from
-R
T is the sum of the RSET programming resistors
Component Selection For CSOFT Capacitor
Choosing the CSOFT capacitor to meet the requirements
of a particular soft-start dela y t SS is calculated with
Equation 18, which is written as:
Where:
-tSS is the soft-start delay
-ISS is the soft-start current source at the 20µA
limit
-V
START-UP is the setpoint reference voltage
selected by the state of the VID inputs at the time
EN is asserted
-R
T is the sum of the RSET programming resistors
Choosing the CSOFT capacitor to meet the requirements
of a particular voltage-step delay tVS is calculated with
Equation 19, which is written as:
Where:
-tVS is the voltage-step delay
-V
NEW is the new setpoint voltage
-V
OLD is the setpoint voltage that VNEW is changing
from
-IVS is the ±100µA setpoint voltage-step current;
positive when VNEW > VOLD, negative when VNEW
< VOLD
-R
T is the sum of the RSET programming resistors
Compensation Design
Figure 8 shows the recommended T ype-II compensation
circuit. The FB pin is the in verting i nput of the error
amplifier. The COMP signal, the output of the error
amplifier, is inside the chip and unavailable to users.
CINT is a 100pF capacitor integr ated inside the IC,
connecting across the FB pin and the COMP signal. RFB,
RCOMP, CCOMP and CINT form the Type-II compensator.
The frequency domain tr ansf er function is given by
Equation 20:
The LC output filter has a double pole at its resonant
frequency that causes rapid phase change. The R3
modulator used in the IC mak es the L C output filter
resemble a first order system in which the closed loop
stability can be achieved with the recommended Type- II
compensation network. Intersil provides a PC -based tool
that can be used to calculate compensation network
component values and help simulate the loop frequency
response.
Fault Protection
Overcurrent
The overcurren t protection (OCP) setpoint is
programmed with resistor R OCSET which is connected
across the OCSET and PHASE pins. Resistor RO is
connected between the VO pin and the actual output
voltage of the converter. During normal oper ation, the
VO pin is a h igh imp edance p ath, ther efore ther e is no
voltage drop across RO. The value of resistor RO should
always match the value of resistor ROCSET.
tVS RTCSOFT
⋅()–LN 1 VNEW VOLD
–()
IVS RT
⋅
-------------------------------------------
–()⋅=(EQ. 17)
CSOFT
t
SS
–
RTLN 1 VSTART-UP
ISS RT
⋅
------------------------------
–()⋅
⎝⎠
⎜⎟
⎛⎞
---------------------------------------------------------------------
=(EQ. 18)
CSOFT tVS
–
RTLN 1 VNEW VOLD
–
I±VS RT
⋅
---------------------------------------
–()⋅
⎝⎠
⎜⎟
⎛⎞
------------------------------------------------------------------------------
=(EQ. 19)
(EQ. 20)
GCOMP s() 1sR
FB RCOMP
+()C⋅COMP
⋅+
sR
FB CINT 1sR
COMP C⋅COMP
⋅+()⋅⋅ ⋅
---------------------------------------------------------------------------------------------------------------
=
ROFS
EA
+
FB
CINT = 100pF
-
SREF
VOUT
FIGURE 8. COMPENSATION REFERENCE CIRCUIT
RFB
RCOMP CCOMP
COMP
FIGURE 9. OVERCURRENT PROGRAMMING CIRCUIT
PHASE
CO
L
VO
ROCSET CSEN
OCSET
VO
RO
DCR IL
10µA
+_
VDCR
+_
VROCSET
ISL62875
16 September 18, 2009
FN6905.1
Figure 9 shows the overcurrent set circuit. The in ductor
consists of inductance L and the DC resistance DCR. The
inductor DC current IL creates a voltage drop across
DCR, which is given by Equation 21:
The IOCSET current source sinks 10µA into the OCSET
pin, creating a DC voltage drop across the resistor
ROCSET, which is given by Equation 22:
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 23:
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10µs, an OCP
fault latches the converter off.
Component Selection for ROCSET and CSEN
The value of ROCSET is calculated with Equation 24,
which is written as:
Where:
-R
OCSET (Ω) is the resistor used to program the
overcurrent setpoint
-I
OC is the output DC load current that will activate
the OCP fault detection circuit
- DCR is the inductor DC resistance
For example, if I OC is 20A and DCR is 4.5mΩ, the choice
of ROCSET is = 20A x 4.5mΩ/10µA = 9kΩ.
Resistor ROCSET and capacitor CSEN form an R -C
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
constant ROCSET CSEN needs to match the inductor time
constant L/DCR. The value of CSEN is then written as
Equation 25:
For example, if L is 1.5µH, DCR is 4.5m Ω, and ROCSET is
9kΩ, the choice of CSEN = 1.5µH /(9k Ω x 4.5mΩ) =
0.037µF.
When an OCP fault is declared, the PGOOD pin will
pull-down to 35Ω and latch off the converter. The fault
will remain latched until the EN pin has been pulled below
the falling EN threshold voltage VENTHF or if VCC has
decayed below the falling POR threshold voltage
VVCC_THF.
Overvoltage
The ISL62875 does not feature overvoltage fault
protection.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold VUVTH for
more than 2µs. For example, if the con verter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical VUVTH threshold of
84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be
84% x 1.0V = 0.84V. When a UVP fault is declared, the
PGOOD pin will pull-down to 95Ω and latch-off the
converter. The fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
VENTHF or if VCC has decay ed below the falling POR
threshold voltage VVCC_THF.
Over-Temperature
When the temperature of the IC increases above the
rising threshold temperature TOTRTH, it will enter the OTP
state that suspends the PWM, forcing the LGATE and
UGA TE gate-driver outputs low . The status of the PGOOD
pin does not change nor does the converter latch-off . The
PWM remains suspended until the IC temperature falls
below the hysteresis temperature T OTHYS at which time
normal PWM operation resumes. The O T P state can be
reset if the EN pin is pulled below the falling EN threshold
voltage VENTHF or if VCC has decay ed below the falling
POR threshold voltage VVCC_THF. All other protection
circuits remain functional while the IC is in the O TP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage deca ys below
the undervoltage threshold VUVTH.
General Application Design
Guide
This design guide is inte nded to pro vide a high-le v el
explanation of the ste ps nece ssar y to des ign a s ingle -
phase power converter. It is assumed that the reader is
familiar with many of the basic skil ls and tec hniq ues
referenced in the following. In addition to th is gui de,
Intersil pro vide s co mplete re feren ce d esign s that
include sch ema ti cs, bills of ma ter ia ls , a n d example
board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of
the input and the output voltage. This relationship is
expressed in Equation 26:
The output inductor peak-to-peak ripple current is
expressed in Equation 27:
VDCR ILDCR⋅=(EQ. 21)
VROCSET 10μAR
OCSET
⋅=(EQ. 22)
VOCSET V–VO VDCR V–ROCSET ILDCR⋅IOCSET ROCSET
⋅–==
(EQ. 23)
(EQ. 24)
ROCSET IOC DCR⋅
IOCSET
----------------------------
=
(EQ. 25)
CSEN L
ROCSET DCR⋅
------------------------------------------
=
DVO
VIN
---------
=(EQ. 26)
(EQ. 27)
IP-P VO1D–()⋅
FSW L⋅
-------------------------------
=
ISL62875
17 September 18, 2009
FN6905.1
A typical step-down DC/DC converter will have an I P-P of
20% to 40% of the maximum DC output load current.
The value of IP-P is selected based upon several criteria,
such as MOSFET switching loss, inductor core loss, and
the resistive loss of the inductor winding. The DC copper
loss of the inductor can be estimated using Equation 28:
Where, ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider
when choosing the inductor is its saturation
characteristics at elev ated temper ature. A saturated
inductor could cause destruction of circuit components,
as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance
CO into which ripple current I P-P can flow. Current IP-P
develops a corresponding ripple voltage VP-P across CO,
which is the sum of the voltage drop across the capacitor
ESR and of the voltage change stemming from ch arge
moved in and out of the capacitor. These two voltages
are expressed in Equations 29 and 30:
If the output of the converter has to support a load with
high pulsating current, several capacitors will need to be
paralleled to reduce the total ESR until the required VP-P
is achieved. The inductance of the capacitor can cause a
brief volt age dip if the loa d tr a nsie nt ha s an extremel y
high slew rate. Low inductance capacitors should be
considered. A c apaci tor diss ipates heat a s a func tion of
RMS current and frequency. Be sure that IP-P is shared
by a sufficient quan tit y of paralleled capacitors so th at
they operate below the maximum rated RMS current at
FSW. Take into account that the rated value of a
capacitor can fade as much as 50% as the DC voltage
across it increas es.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance
are the voltage r ating and the RMS current r ating. For
reliable operation, select bulk capacitors with voltage and
current ratings abov e the maxim um input voltage and
capable of supplying the RMS current required by the
switching circuit. Their voltage r ating should be at least
1.25x greater than the maximum input v oltage, while a
voltage rating of 1.5x is a preferred rating. Figure 10 is a
graph of the input R MS ripple current, normalized
relative to output load current, as a function of duty
cycle that is adjusted for converter efficiency. The ripple
current calculation is written as Equation 31:
Where:
-I
MAX is the maximum continuous ILOAD of the
converter
- x is a multiplier (0 to 1) corresponding to the
inductor peak-to-peak ripple amplitud e expressed
as a percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into
account the efficiency of the converter
Duty cycle is written as Equation 32:
In addition to the bulk capacitance, some low ESL
ceramic capacitance is recommended to decouple
between the drain of the high-side MOSFET and the
source of the low-side MOSFET.
Selecting The Bootstrap Capacitor
Adding an external capacitor across the BOO T and
PHASE pins completes the bootstrap circuit. W e selected
the bootstr ap cap acitor breakdown v olta ge to be at
least 10V. Although the the oretical maximum vo ltage of
the capacitor is PVCC-VDIODE (voltage drop across the
boot diode), large excursio ns below ground by the
phase node requir es we sele ct a cap acito r with at least
a breakdown rating of 10V. The bootstr ap capacitor can
be chosen from Equation 33:
Where:
-Q
GATE is the amount of gate charge required to
fully charge the gate of the upper MOSFET
-ΔVBOOT is the maximum decay across the BOOT
capacitor
As an example, suppose an upper MOSFET has a gate
charge, QGATE, of 25nC at 5V and also assume the droop
in the drive voltage over a PWM cy cle is 200mV. One will
find that a bootstrap capacitance of at least 0.125µF is
required. The next larger standard value capacitance is
(EQ. 28)
PCOPPER ILOAD2DCR⋅=
ΔVESR IP-P E⋅SR=(EQ. 29)
ΔΔVCIP-P
8C
OF⋅SW
⋅
---------------------------------
=(EQ. 30)
(EQ. 31)
IIN_RMS
IMAX2DD
2
–()⋅()xI
MAX2D
12
------
⋅⋅
⎝⎠
⎛⎞
+
IMAX
-----------------------------------------------------------------------------------------------------
=
(EQ. 32)
DVO
VIN EFF⋅
--------------------------
=
FIGURE 10. NORMALIZED RMS INPUT CURRENT FOR
x = 0.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
NORMALIZED INPUT RMS RIPPLE CURRENT
DUTY CYCLE
x = 1
x = 0.75
x = 0.50
x = 0.25
x = 0
CBOOT QGATE
ΔVBOOT
------------------------
≥(EQ. 33)
ISL62875
18 September 18, 2009
FN6905.1
0.15µF. A good quality ceramic capacitor su ch as X7R or
X5R is recommended.
Driver Power Dissipation
Switching power dissipation in the driv er is mainly a
function of the switching frequency and total gate charge
of the selected MOSFETs. Calculating the power
dissipation in the driver for a desired application is critical
to ensuring safe operation. Ex ceeding the maximum
allowable power dissipation level will push the IC beyond
the maximum recommended oper ating junction
temperature of +125°C. When designing the application,
it is recommended that the following calculation be
performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power
dissipated by the drivers is approximated as
Equation 34:
Where:
-F
sw is the switching frequency of the PWM signal
-V
U is the upper gate driver bias supply voltage
-V
L is the lower gate driver bias supply voltage
-Q
U is the charge to be delivered by the upper
driver into the gate of the MOSFET and discrete
capacitors
-Q
L is the charge to be delivered by the lo wer driver
into the gate of the MOSFET and discrete
capacitors
-P
L is the quiescent power consumption of the low er
driver
-P
U is the quiescent power consumption of the upper
driver
MOSFET Selection and Considerations
T ypically, a MOSFET cannot tolerate even brief excursions
beyond their maximum dr ain to source v oltage r ating.
The MOSFETs used in the power stage of the converter
should have a maximum VDS rating that exceeds the
sum of the upper v oltage toler ance of the input power
source and the voltage spike that occurs when the
MOSFET switches off .
There are several power MOSFETs readily available that
are optimized for DC/DC converter applications. The
preferred high-side MOSFET emphasizes low switch
charge so that the device spends the least amount of
time dissipating power in the linear region. Unlike the
low-side MOSFET which has the drain-source v oltage
clamped by its body diode during turn-off, the high-side
MOSFET turns off with VIN-VOUT, plus the spike, acro ss
it. The preferred low -side MOSFET emphasizes low
rDS(ON) when fully saturated to minimize conduction
loss.
For the low -side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as
Equation 35:
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 36:
For the high-side MOSFET, its switching loss is written as
Equation 37:
Where:
-I
VALLEY is the difference of the DC component of
the inductor current minus 1/2 of the inductor
ripple current
-I
PEAK is the sum of the DC component of the
inductor current plus 1/2 of the inductor ripple
current
-t
ON is the time required to drive the device into
saturation
FIGURE 11. BOOT CAPACITANCE vs BOOT RIPPLE
VOLTAGE
20nC
ΔVBOOT_CAP (V)
CBOOT_CAP (µF)
2.0
1.6
1.4
1.0
0.8
0.6
0.4
0.2
0.0 0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
QGATE = 100nC
1.2
1.8
50nC
PF
sw 1.5VUQUVLQL
+()PLPU
++=(EQ. 34)
FIGURE 12. POWER DISSIPATION vs FREQUENCY
FREQUENCY (Hz)
0
100
200
300
400
500
600
700
800
900
1000
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
POWER (mW)
QU = 50nC
QL = 50nC
QU = 50nC
QL = 100nC
QU = 100nC
QL = 200nC
QU = 20nC
QL = 50nC
(EQ. 35)
PCON_LS ILOAD2r⋅DS ON()_LS 1D–()⋅≈
(EQ. 36)
PCON_HS ILOAD2r⋅DS ON()_HS D⋅=
(EQ. 37)
PSW_HS VIN IVALLEY tON F⋅SW
⋅⋅
2
----------------------------------------------------------------------VIN IPEAK tOFF F⋅SW
⋅⋅
2
------------------------------------------------------------------
+=
ISL62875
19 September 18, 2009
FN6905.1
-t
OFF is the time required to drive the device into
cut-off
PCB Layout Considerations
Power and Signal Layers Placement on the
PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with the weak
analog or logic signal layers on the opposite side of the
board. The ground-plane layer should be adjacent to the
signal layer to provide shielding. The ground plane lay er
should have an island located under the IC, the
compensation components, and the SREF components.
The island should be connected to the rest of the ground
plane layer at one point.
Component Placement
There are two sets of critical components in a DC/DC
converter; the power components and the small signal
components. The power components are the most critical
because they switch large amount of energy. The small
signal components connect to sensitive nodes or supply
critical bypassing current and signal coupling.
The power components should be placed first and these
include MOSFETs, input and output capacitors, and the
inductor. Keeping the distance between the power train
and the control IC short helps keep the gate drive tr aces
short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOO T.
When placing MOSFETs, try to keep the source of the
upper MOSFETs and the drain o f the lower MOSFETs as
close as thermally possible (see Figure 13). Input high-
frequency capacitors should be placed close to the dr ain
of the upper MOSFETs and the source of the lower
MOSFETs. Place the output inductor and output
capacitors between the MOSFETs and the load. High-
frequency output decoupling capacitors (cer amic) should
be placed as close as possible to the decoupling target
(GPUor CPU), making use of the shortest connection
paths to any internal planes. Place the components in
such a way that the area under the IC has less noise
traces with high dV/dt and di/dt, such as gate signals and
phase node signals.
Signal Ground and Power Ground
The GND pin is the signal-common also known as analog
ground of the IC. When laying out the PCB, it is v ery
important that the connection of the GND pin to the
bottom setpoint-reference programming-resistor, bottom
feedback voltage-divider resistor (if used), and the
CSOFT capacitor be made as close as possible to the
GND pin on a conduc tor not shared by an y other
components.
In addition to the critical single point connection
discussed in the previous paragraph, the ground plane
layer of the PCB should hav e a single-point-connected
island located under the area encompassing the IC,
setpoint reference programming components, feedback
voltage divider components, compensation components,
CSOFT capacitor, and the interconnecting tr aces among
the components and the IC. The island should be
connected using several filled vias to the rest of the
ground plane layer at one point that is not in the path of
either large static currents or high di/dt currents. The
single connection point should also be where the VCC
decoupling capacitor and the GND pin of the IC are
connected.
Anywhere not within the analog-ground island is P ower
Ground. Connect the input capacitor(s), the output
capacitor(s), and the source of the lower MOSFET(s) to
the power ground plane.
Routing and Connection Details
Specific pins (and the trace routin g from them ), require
extra attention during the la yout process. The following
sub-sections outline concerns by pin name.
VCC PIN
For best performance, place the decoupling capacitor
next to the VCC and GND pins. The VCC decoupling
capacitor should not share any vias with the PVCC
decoupling capacitor.
PVCC PIN
For best performance, place the PVCC decoupling
capacitor next to the PVCC and PGND pins, preferably on
the same side of the PCB as the ISL62875. The PVCC
decoupling capacitor should have a very short and wide
trace connection to th e PGND pin.
EN, PGOOD, VID0, AND VID1 PINS
These are logic signals that are referenced to the GND
pin. Treat as a typical logic signal.
OCSET AND VO PINS
The current-sensing network consisting of ROCSET, RO,
and CSEN must be connnected to the inductor pads for
accurate measurement of the DCR v oltage drop. These
components however, should be located physically close
to the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all the wa y to the inductor pads. The
procedure is the same for resistive current sense.
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
INDUCTOR
VIAS TO
GROUND
PLANE
VIN
VOUT
PHASE
NODE
GND OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
SCHOTTKY
DIODE
HIGH-SIDE
MOSFETS
ISL62875
20 September 18, 2009
FN6905.1
FB, SREF, SET0, SET1, AND SET2 PINS
The input impedance of these pins is high, making it
critical to place the loop compensation components,
setpoint reference programming resistors, feedback
voltage divider resistors, and CSOFT close to the IC,
keeping the length of the tr aces short.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are boht high
dv/dt and di/dt, with high peak charging and discharging
current. The PGND pin can only flow current from the
gate-source charge of the low-side MOSFETs when
LGATE goes low . Id eally, route the trace fro m the L GATE
pin in parallel with the tr ace from th e PGND pin, route
the trace from the UGATE pin in parallel with the tr ace
from the PHASE pin, and route the tr ace from th e BOOT
pin in parallel with the tr ace from th e PHASE pin. Th ese
pairs of traces should be short, wide, and aw ay from
other traces with high input impedance; weak signal
traces should not be in pro ximity with these tr aces on
any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic in ductance of the
phase node should be kept very low to minimize ringing.
It is best to limit the size of the PHASE node copper in
strict accordance with the current and thermal
management of the application. An MLCC should be
connected directly across the drain of the upper MOSFET
and the source of the lower MOSFET to suppress the
turn-off voltage.
ISL62875
21
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil produc ts are sol d by desc rip tio n o nly . Intersil Corpor ati on reserves the right to make ch ang e s in c irc uit de sign , software and/or specifications
at any time without n oti ce. Acco rdin gly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of t hird parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidi arie s .
For information regarding Intersil Corporation and its products, see www.intersil.com
September 18, 2009
FN6905.1
For additional products, see www.intersil.com/product_tree
Products
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Revision History
The revision history provided is for informational purpos es only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE REVISION CHANGE
8/09 FN6905.0 Initial Release
9/09 FN6905.1 Page 10: Removed “OVP Rising Threshold Voltage” and “OVP Falling Threshold Voltage” lines
from the “Electrical Specifications” table.
ISL62875
22 September 18, 2009
FN6905.1
ISL62875
Package Outline Drawing
L20.3.2x1.8
20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN)
Rev 0, 5/08
located within the zone indicated . Th e pin #1 identifier may be
Unless otherwise specified, tol erance : Decim al ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optio nal, but must be
between 0.15mm an d 0.3 0m m from the te rminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
(1 x 0.70)
( 19X 0 . 60 )
20
0.10
( 2. 30 )
(4X)
( 16 X 0 . 40 )
( 20X 0 . 20 ) C
MAX 0.55
3.20
12
PIN 1 ID#
6
1.80 B
A
19
16X 0.40
5
0 . 05 MAX.
0 . 00 MIN.
0 . 2 REF
BASE PLANE
SEE DETAIL "X"
C
C
0.10
SEATING PLANE
0.05 C
M
20X 0.20
M
4
19X 0.40 ± 0.10
11 10
0.10
0.05 ABC
C
9
6
PIN #1 ID
2
1
0.50±0.10
BOTTOM VIEW
VIEW “A-A”
( 1.0 )
