MOTOROLA.COM/SEMICONDUCTORS
M68HC11
Microcontrollers
MC68HC711D3/D
Re v. 2
MC68HC711D3
Data Sheet
9/2003
MC68HC11D3
MC68HC11D0
MC68L11D0
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA 3
Motorola and the Stylized M Lo go are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc. © Motorola, Inc., 2003
MC68HC711D3
Data Sheet
To provide the most up-to-date information, the revision of our documents on the
World Wide Web will be the most current. Your printed copy may be an earlier
revision. To verify you have the latest information available, refer to:
http://www.motorola.com/semiconductors/
The following revision history table summarizes changes contained in this
document. For your convenience, the page number designators have been linked
to the appropriate location.
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Revision History
Data Sheet MC68HC711D3 — Rev. 2
4 Revision History MOTOROLA
Revision History
Date Revision
Level Description Page
Number(s)
September,
2003 2
Reformatted to curent publications standards N/A
Removed references to PROG mode. Throughout
Corrected pin assignments for:
Figure 1-2. Pin Assignments for 40-Pin Plastic DIP
Figure 1-3. Pin Assignments for 44-Pin PLCC
Added Figure 1-4 . Pin Assignments for 44-Pin QFP
15
15
16
1.9 Interrupt Request (IRQ) — Reworked description for clarity. 18
2.4 Programmable Read-Only Memory (PROM) — Updated with additional
data. 31
Section 10. Ordering Information and Mechanical Specifications —
Added mechanical specificatio ns for 44-pin plastic quad flat pack (QFP). 133
Added the followi ng appendices:
Appendix A. MC68HC11D3 and MC68HC11D0
Appendix B. MC68L11D0 137
143
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA List of Sections 5
Data Sheet — MC68HC711D3
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Section 2. Operating Modes and Memory . . . . . . . . . . . . . . . . . . . . . .21
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . .35
Section 4. Resets, Interrupts, and Low-Power Modes . . . . . . . . . . . .51
Section 5. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Section 6. Serial Communications Interface (SCI). . . . . . . . . . . . . . . .73
Section 7. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . .87
Section 8. Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Section 9. Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .117
Section 10. Ordering Information and Mechanical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Appendix A. MC68HC11D3 and MC68HC11D0. . . . . . . . . . . . . . . . . .137
Appendix B. MC68L11D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
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List of Sections
Data Sheet MC68HC711D3 — Rev. 2
6 List of Sections MOTOROLA
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Table of Contents 7
Data Sheet — MC68HC711D3
Table of Contents
Section 1. General Description
1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5 Power Supply (VDD, VSS, and EVSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.7 Crystal Driver and External Clock Input (XTAL and EXTAL) . . . . . . . . . 17
1.8 E-Clock Output (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.9 Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.10 Non-Maskable Interrupt/Programming Voltage (XIRQ/VPP). . . . . . . . . . 18
1.11 MODA and MODB (MODA/LIR and MODB/VSTBY) . . . . . . . . . . . . . . . . 18
1.12 Read/Write (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.13 Port D Bit 6/Address Strobe (PD6/AS) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.14 Input/Output Lines (PA7–PA0, PB7–PB0,
PC7–PC0, and PD7–PD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Section 2. Operating Modes and Memory
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 Single-Chip Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.2 Expanded Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.3 Special Bootstrap Mode (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.4 Special Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.1 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.2 RAM and I/O Mapping Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.3 Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.4 Programmable Read-Only Memory (PROM) . . . . . . . . . . . . . . . . . . . . . 31
2.4.1 Programming an Individual EPROM Address. . . . . . . . . . . . . . . . . . 32
2.4.2 Programming the EPROM with Downloaded Data. . . . . . . . . . . . . . 32
2.4.3 PROM Programming Control Register . . . . . . . . . . . . . . . . . . . . . . . 33
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Table of Contents
Data Sheet MC68HC711D3 — Rev. 2
8 Table of Contents MOTOROLA
Section 3. Central Processor Unit (CPU)
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2.1 Accumulators A, B, and D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2.2 Index Register X (IX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.3 Index Register Y (IY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.6.1 Carry/Borrow (C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.6.2 Overflow (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.6.3 Zero (Z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.6.4 Negative (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.6.5 I-Interrupt Mask (I). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.6.6 Half Carry (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.6.7 X-Interrupt Mask (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.6.8 STOP Disable (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3 Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.1 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.2 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.3 Extended. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.4 Indexed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.5 Inherent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5.6 Relative. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.6 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Section 4. Resets, Interrupts, and Low-Power Modes
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.1 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.2 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.3 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . 52
4.2.4 Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.2.5 System Configuration Options Register . . . . . . . . . . . . . . . . . . . . . . 53
4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3.1 Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.2 Illegal Opcode Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.3 Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.4 Interrupt Mask Bits in the CCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.5 Priority Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.6 Highest Priority I Interrupt and Miscellaneous
Register (HPRIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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Table of Contents
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Table of Contents 9
4.4 Low-Power Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.2 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Section 5. Input/Output (I/O) Ports
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.1 Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.2 Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.4.1 Port C Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.4.2 Port C Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.4.3 Port C Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.5.1 Port D Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.5.2 Port D Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Section 6. Serial Communications Interface (SCI)
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3 Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.5 Wakeup Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.5.1 Idle-Line Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.5.2 Address-Mark Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.6 SCI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.7 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.7.1 SCI Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.7.2 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.7.3 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.7.4 SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.7.5 Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.8 Status Flags and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Section 7. Serial Peripheral Interface (SPI)
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
7.3 SPI Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7.4 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
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Table of Contents
Data Sheet MC68HC711D3 — Rev. 2
10 Table of Contents MOTOROLA
7.5 SPI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.5.1 Master In/Slave Out (MISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.5.2 Master Out/Slave In (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.5.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.5.4 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.6 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.7 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.7.1 SPI Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.7.2 SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.7.3 SPI Data I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Section 8. Programmable Timer
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
8.2 Timer Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3.1 Timer Control 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3.2 Timer Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
8.3.3 Timer Input Capture 4/Output Compare 5 Register . . . . . . . . . . . . 101
8.4 Output Compare (OC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
8.4.1 Timer Output Compare Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 103
8.4.2 Timer Compare Force Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
8.4.3 Output Compare 1 Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.4.4 Output Compare 1 Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.4.5 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.4.6 Timer Control 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.4.7 Timer Interrupt Mask 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.4.8 Timer Interrupt Flag 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.4.9 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.4.10 Timer Interrupt Flag 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.5 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.5.1 Timer Interrupt Mask 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.5.2 Timer Interrupt Flag 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.5.3 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . 112
8.6 Computer Operating Properly Watchdog Function. . . . . . . . . . . . . . . . 113
8.7 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.7.1 Pulse Accumulator Control Register. . . . . . . . . . . . . . . . . . . . . . . . 114
8.7.2 Pulse Accumulator Count Register. . . . . . . . . . . . . . . . . . . . . . . . . 115
8.7.3 Pulse Accumulator Status and Interrupt Bits . . . . . . . . . . . . . . . . . 115
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Table of Contents
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Table of Contents 11
Section 9. Electrical Characteristics
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.2 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.3 Functional Operating Temp erature Ran ge. . . . . . . . . . . . . . . . . . . . . . 118
9.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.7 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.8 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
9.9 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Section 10. Ordering Information and Mechanical Specifications
10.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.2 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
10.3 40-Pin DIP (Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
10.4 44-Pin PLCC (Case 777-02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10.5 44-Pin QFP (Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Appendix A. MC68HC11D3 and MC68HC11D0
A.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
A.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
A.3 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
A.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
A.5 MC68HC11D3 and MC68HC11D0 Electrical Characteristics. . . . . . . . 140
A.5.1 Functional Operating Temp erature Ran ge . . . . . . . . . . . . . . . . . . . 140
A.5.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
A.6 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Appendix B. MC68L11D0
B.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
B.2 MC68L11D0 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 143
B.2.1 Functional Operating Temp erature Ran ge . . . . . . . . . . . . . . . . . . . 143
B.2.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
B.2.3 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
B.2.4 Peripheral Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
B.2.5 Expansion Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
B.2.6 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 147
B.3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
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Table of Contents
Data Sheet MC68HC711D3 — Rev. 2
12 Table of Contents MOTOROLA
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA General Description 13
Data Sheet — MC68HC711D3
Section 1. General Description
1.1 Introduction
This section depicts the general characteristics and features of the MC68HC711D3
high-density complementary metal-oxide semiconductor (HCMOS) microcontroller
unit (MCU).
The MC68HC711D3 contains highly sophisticated on-chip peripheral functions.
This high-speed, low-power programmable read-only memory (PROM) MCU has
a nominal bus speed of 3 MHz. The fully static design allows operations at
frequencies down to dc.
The MC68HC11D3 and MC68HC11D0 are read-only memory (ROM) based
high-performance microcontrollers (MCU) based on the MC68HC11E9 design.
The MC68L11D0 is an extended-voltage version of the MC68HC11D0 that
can operate in applications that require supply voltages as low as 3.0 V. The
information in this document pertains to all the devices with the exceptions noted in
Appendix A. MC68HC11D3 and MC68HC11D0 and Appendix B. MC68L11D0.
1.2 Features
Features of the MC68HC711D3 include:
• Expanded 16-bit timer system with four-stage programmable prescaler
• Non-return-to-zero (NRZ) serial communications interface (SCI)
• Power-saving stop and wait modes
• 64 Kbytes memory addressability
• Multiplexed address/data bus
• Serial peripheral interface (SPI)
• 4 Kbytes of one-time programmable read-only memory (OTPROM)
• 8-bit pulse accumulator circuit
• 192 bytes of static random-access memory (RAM) (all saved during
standby)
• Real-time interrupt (RTI) circuit
• Computer operating properly (COP) watchdog system
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General Description
Data Sheet MC68HC711D3 — Rev. 2
14 General Description MOTOROLA
• Available in these packages:
– 40-pin plastic dual in-line package (DIP)
– 44-pin plastic leaded chip carrier (PLCC)
– 44-pin plastic quad flat pack (QFP)
1.3 Structure
Refer to Figure 1-1, which shows the structure of the MC68HC711D3 MCU.
Figure 1-1. MC68HC711D3 Block Diagram
PORT A
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
MODE CONTROL INTERRUPT CONTROL
MODA/LIR
MODB/VSTBY
RESET IRQ XIRQ/VPP XTAL EXTAL E
CLOCK LOGIC
OSCILLATOR
PAI/OC1
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC1
IC2
IC3
TIMER
PULSE ACCUMULATOR COP
PERIODIC INTERRUPT
4 KBYTES
PD7/R/W
PD6/AS
PD5
PD4
PD3
PD2
PD1
PD0
DATA DIRECTION REGISTER D
PORT D
DATA DIRECTION REGISTER C
PORT C
DATA DIRECTION REGISTER B
PORT B
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
MULTIPLEXED ADDRESS/DATA BUS
192 BYTES STATIC RAM
SERIAL
PERIPHERAL
INTERFACE
(SPI)
SERIAL
COMMUNICATIONS
INTERFACE
(SCI)
MC68HC711D3
CPU CORE
SS
SCK
MOSI
MISO
TxD RxD
VSS
VDD
EVSS
EPROM OR OTPROM
NOT BONDED IN 40-PIN PACKAGE
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General Description
Pin Descriptions
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA General Description 15
1.4 Pin Descriptions
Refer to Figure 1-2, Figure 1-3, and Figure 1-4 for pin assignments.
Figure 1-2. Pin Assignments for 40-Pin Plastic DIP
Figure 1-3. Pin Assignments for 44-Pin PLCC
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA5
PA7
VDD
PB4
PB3
PB2
PB1
PB0
MODB/VSTBY
MODA/LIR
E
EXTAL
XTAL
PC7
XIRQ/VPP
PD7/R/W
PD6/AS
RESET
IRQ
PD0
PD1
PD2
PD3
PD4
PD5
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
9
10
11
12
13
14
15
16
17
18
19
20
8
7
6
5
4
3
2
1
30
29
28
27
26
25
24
23
22
21
31
32
33
34
35
36
37
38
39
40
PC4
PC5
PC6
PC7
XIRQ/VPP
PD7/R/W
PD6/AS
RESET
IRQ
PD0
PD1
PB2
PB3
PB4
PB5
PB6
PB7
NC
PA0
PA1
PC3
PC2
PD1
PC0
VSS
EVSS
XTAL
EXTAL
E
MODA/LIR
MODB/VSTBY
PD2
PD3
PD4
PD5
VDD
PA7
PA6
PA5
PA4
PA3
PA2
7
8
9
10
11
12
13
14
15
16
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
17
PB1
38
PB0
39
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General Description
Data Sheet MC68HC711D3 — Rev. 2
16 General Description MOTOROLA
Figure 1-4. Pin Assignments for 44-Pin QFP
1.5 Power Supply (VDD, VSS, and EVSS)
Power is supplied to the MCU through VDD and VSS. VDD is the power supply
(+5 V ±10%) and VSS is ground (0 V). EVSS, available on the 44-pin PLCC and
QFP, is an additional ground pin.
1.6 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to initialize the
MCU to a known startup state. It also acts as an open-drain output to indicate that
an internal failure has been detected in either the clock monitor or computer
operating properly (COP) watchdog circuit. In addition, the state of this pin is one
of the factors governing the selection of BOOT mode.
PC4
PC5
PC6
PC7
XIRQ
PD7
PD6
RESET
IRQ
PD0
PD1
PB2
PB3
PB4
PB5
PB6
PB7
NC
PA0
PA1
PC3
PC2
PC1
PC0
EVSS
VSS
XTAL
EXTAL
E
MODA
MODB
PD2
PD3
PD4
PD5
VDD
PA7
PA6
PA5
PA4
PA3
PA2
2
3
4
5
6
7
8
9
10
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
43
42
41
40
39
38
37
36
35
34
PB1
32
PB0
1
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General Description
Crystal Driver and External Clock Input (XTAL and EXTAL)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA General Description 17
1.7 Crystal Driver and External Clock Input (XTAL and EXTAL)
These two pins provide the interface for either a crystal or a CMOS compatible
clock to control the internal clock generator circuitry. The frequency applied to
these pins is four times higher than the desired E-clock rate. Refer to Figure 1-5
for crystal and clock connections.
Figure 1-5. Oscillator Connections
10 M
* Values includes all stray capacitances.
FIRST MCU
EXTAL
XTAL
4 x E
CRYSTAL
MCU
EXTAL
XTAL
4 x E
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
NC OR
10K–100K
LOAD
25 pF *
25 pF *
SECOND MCU
EXTAL
XTAL
NC OR
10K–100K
LOAD
10 M
MCU
EXTAL
XTAL
4 x E
CRYSTAL
25 pF *
25 pF *
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General Description
Data Sheet MC68HC711D3 — Rev. 2
18 General Description MOTOROLA
1.8 E-Clock Output (E)
E is the output connection for the internally generated E clock. The signal from E
is used as a timing reference. The frequency of the E-clock output is one fourth that
of the input frequency at the XTAL an d EXTAL pins. The E clock can be turned of f
in single-chip mode for greater noise immunity if desired. See 4.3.6 Highest
Priority I Interrupt and Miscellaneous Register (HPRIO) for details.
1.9 Interrupt Request (IRQ)
The IRQ input provides a means of applying asynchronous interrupt requests to the
microcontroller unit (MCU). Either negative edge-sensitive triggering or
level-sensitive triggering is prog ram selectable by using the IRQE bit of the
OPTION register. IRQ is always configured to level-sensitive triggering at reset.
While the programmable read-only memory (PROM) is being programmed, this pin
provides the chip enable (CE) signal. To prevent accidental programming of the
PROM during reset, an external resistor is required on IRQ to pull the pin to VDD.
1.10 Non-Maskable Interrupt/Programming Voltage (XIRQ/VPP)
The XIRQ input provides the capability for asynchronously applying non -maskable
interrupts to the MCU after a power-on reset (POR). During reset, the X bit in the
condition code register (CCR) is set masking any interrupt until enabled by
software. This level-sensitive input requires an external pullup resistor to VDD.
In the programming configuration of the boot strap mode, this pin is used to supply
one-time programmable read-only memory (OTPROM) programming voltage, VPP,
to the MCU. To avoid programming accidents during reset, this pin should be equal
to VDD during normal operation unless XIRQ is active.
1.11 MODA and MODB (MODA/LIR and MODB/VSTBY)
As reset transitions, these pins are used to latch the part into one of the four central
processor unit (CPU) controlled modes of operation. The LIR output can be used
as an aid to debugging once reset is completed. The open-drain LIR pin goes to an
active low during the first E-clock cycle of each instruction and remains low for the
duration of that cycle. The VSTBY input is used to retain random-access memory
(RAM) contents during power down.
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General Description
Read/Write (R/W)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA General Description 19
1.12 Read/Write (R/W)
This pin performs either of two separate functions, depending on the operating
mode.
• In single-chip and bootstrap modes, R/W functions as input/output port D
bit 7. Refer to Section 5. Input/Output (I/O) Ports for further information.
• In expanded multiplexed and test modes, R/W performs a read/write
function. R/W controls the direction of transfers on the external data bus.
1.13 Port D Bit 6/Address Strobe (PD6/AS)
This pin performs either of two separate functions, depending on the operating
mode.
• In single-chip and bootstrap modes, the pin functions as input/outp ut port D
bit 6.
• In the expanded multiplexed and test modes, it provides an address strob e
(AS) function. AS is used to demultiplex the address and data signals at
port C.
Refer to Section 2. Operating Modes and Memory for further information.
1.14 Input/Output Lines (PA7–PA0, PB7–PB0, PC7–PC0, and PD7–PD0)
In the 44-pin PLCC package, 32 input/output lines are arranged into four 8-bit
ports: A, B, C, and D. The lines of ports B, C, and D are fully bidirectional. Port A
has two bidirectional, three input-only, and three output-only lines in the 44-pin
PLCC packaging. In the 40-pin DIP, two of the output-only lines are not bonded.
Each of these four ports serves a pu rpose other than input/output (I/O), depen ding
on the operating mode or peripheral functions selected.
NOTE: Ports B, C, and two bits of port D are available for I/O functions only in single-chip
and bootstrap modes.
Refer to Table 1-1 for details about the functions of the 32 port signals within
different operating modes.
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General Description
Data Sheet MC68HC711D3 — Rev. 2
20 General Description MOTOROLA
Table 1-1. Port Signal Functions
Port/Bit Single-Chip
and Bootstrap Mode Expanded Multiplexed
and Special Test Mode
PA0 PA0/IC3
PA1 PA1/IC2
PA2 PA2/IC1
PA3 PA3/OC5/IC4/and-or OC1
PA4(1)
1. In the 40-pin package, pins PA4 and PA6 are not bonded. Their associated I/O and output
compare functions are not available externally. They can still be used as internal software
timers, however.
PA4/OC4/and-or OC1
PA5 PA5/OC3/and-or OC1
PA6(1) PA6/OC2/and-or OC1
PA7 PA7/PAI/and-or OC1
PB0 PB0 A8
PB1 PB1 A9
PB2 PB2 A10
PB3 PB3 A11
PB4 PB4 A12
PB5 PB5 A13
PB6 PB6 A14
PB7 PB7 A15
PC0 PC0 A0/D0
PC1 PC1 A1/D1
PC2 PC2 A2/D2
PC3 PC3 A3/D3
PC4 PC4 A4/D4
PC5 PC5 A5/D5
PC6 PC6 A6/D6
PC7 PC7 A7/D7
PD0 PD0/RxD
PD1 PD1/TxD
PD2 PD2/MISO
PD3 PD3/MOSI
PD4 PD4/SCK
PD5 PD5/SS
PD6 PD6 AS
PD7 PD7 R/W
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Operating Modes and Memory 21
Data Sheet — MC68HC711D3
Section 2. Operating Modes and Memory
2.1 Introduction
This section contains information about:
• The modes that define MC68HC711D3 operating conditions
• The on-chip memory that allows the microcontroller unit (MCU) to be
configured for various applications
• The 4-Kbytes of programmable read-only memory (PROM)
2.2 Operating Modes
The MC68HC711D3 uses two d edicated pins, MODA and MODB, to select one o f
two normal operating modes or one of two special operating modes. A value
reflecting the microcontroller unit (MCU) status or mode selected is latched on bits
SMOD and MDA of the highest priority I-bit interrupt and miscellaneous register
(HPRIO) on the rising edge of reset. The normal operating modes are the
single-chip and expanded-multiplexed modes. The special operating modes are
the bootstrap and test modes. Table 2-1 shows mode selection according to the
values encoded on the MODA and MODB pins, and the value latched in the SMOD
and MDA bits.
2.2.1 Single-Chip Mode
In single-chip mode, the MCU functions as a self-contained microcontroller and has
no external address or data bus. The 4-Kbyte erasable programmable read-only
memory (EPROM) would contain all program code and is located at
$F000–$FFFF. This mode provides maximum use of the pins for on-chip peripheral
functions, and all the address and data activity occurs within the MCU.
Table 2-1. Mode Selection
RESET MODA MODB Mode Selected SMOD MDA
1 0 1 Normal — single chip 0 0
1 1 1 Normal — expanded multiplexed 0 1
1 0 0 Special — bootstrap (BOOT) 1 0
1 1 0 Special — test 1 1
0 0 0 Reserved X X
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Operating Modes and Memory
Data Sheet MC68HC711D3 — Rev. 2
22 Operating Modes and Memory MOTOROLA
2.2.2 Expanded Multiplexed Mode
In the expanded-multiplexed mode, the MCU can address up to 64 Kbytes of
address space. High-order address bits are output on the port B pins. Low-order
address bits and the bidirectional data bus are multiplexed on port C. The AS pin
provides the control output used in demultiplexing the low-order address. The R/W
pin is used to control the direction of data transfer on the port C bus.
If this mode is entered out of reset, the EPROM is located at $7000–$7FFF and
vector accesses are from external memory. To be in expanded-multiplexed mode
with EPROM located at $F000–$FFFF, it is necessary to start in single-chip mode,
executing out of EPROM, and then set the MDA bit of the HPRIO register to switch
mode.
NOTE: R/W, AS, and the high-order address bus (port B) are inputs in single-chip mode.
These inputs may need to be pulled up so that off-chip accesses cannot occur
while the MCU is in single-chip mode.
2.2.3 Special Bootstrap Mode (BOOT)
This special mode is similar to single- chip mode. The resident bootloader program
contains a 256-byte program in a special on-chip read-only memory (ROM). The
user downloads a small program into on-board RAM using the SCI port. Program
control is passed to RAM when an idle line of at least four characters occurs. In this
mode, all interrupt vectors are mapped to RAM (see Table 2-2), so that the user
can set up a jump table, if desired.
Bootstrap mode (BOOT) is entered out of reset if the voltage level on both MODA
and MODB is low. The programming aspect of bootstrap mode, used to program
the one-time programmable ROM (OTPROM) through the MCU, is entered
automatically if IRQ is low and programming voltage is available on the VPP pin.
IRQ should be pulled up while in reset with MODA and MODB configured for
bootstrap mode to prevent unintentional programming of the EPROM.
This versatile mode (BOOT) can be us ed for test and diagnostic functions on
completed modules and for progra mming the o n-board PROM. The serial rece ive
logic is initialized by software in the bootloader ROM, which provides program
control for the SCI baud rate and word format. Mode switching to other modes can
occur under program control by writing to the SMOD and MDA bits of the HPRIO
register. Two special bootloader functions allow eith er an immediate jump-to-RAM
at memory address $0000 or an immediate jump-to-EPROM at $F000.
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Operating Modes and Memory
Operating Modes
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Operating Modes and Memory 23
2.2.4 Special Test Mode
This special expanded mode is primarily intended or production testing. The user
can access a number of special test control bits in this mode. Reset and interrupt
vectors are fetched externally from locations $BFC0–$BFFF. A switch can be
made from this mode to other modes under program control.
Table 2-2. Bootstrap Mode Jump Vectors
Address Vector
00C4 SCI
00C7 SPI
00CA Pulse accumulator input edge
00CD Pulse accumulator overflow
00D0 Timer overflow
00D3 Timer output compare 5/input capture 4
00D6 Timer output compare 4
00D9 Timer output compare 3
00DC Timer output compare 2
00DF Timer output compare 1
00E3 Timer input capture 3
00E5 Timer input capture 2
00E8 Timer input capture 1
00EB Real-time interrupt
00EE IRQ
00F1 XIRQ
00F4 SWI
00F7 Illegal opcode
00FA COP fail
00FD Clock monitor
BF00 (Boot) Reset
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Operating Modes and Memory
Data Sheet MC68HC711D3 — Rev. 2
24 Operating Modes and Memory MOTOROLA
2.3 Memory Map
Figure 2-1 illustrates the memory map for both normal modes of operation
(single-chip and expanded-multiplexed), as well as for both special modes of
operation (bootstrap and test).
• In the single-chip mode, the MCU does not generate external addresses.
The internal memory locations are shown in the shaded areas, and the
contents of these shaded areas are explained on the right side of the
diagram.
• In expanded-multiplexed mode, the memory locations are basically the
same as in the single-chip mode excep t that the memory locations between
shaded areas are for externally addressed memory and I/O.
• The special bootstrap mode is similar to the single-chip mode, except that
the bootstrap program ROM is located at memory locations $BF00– $BFFF,
vectors included.
• The special test mode is similar to the expanded-multiplexed mode except
the interrupt vectors are at external memory locations.
Figure 2-1. MC68HC711D3 Memory Map
SINGLE
CHIP
SPECIAL SPECIAL
TEST
EXPANDED
192 BYTES STATIC RAM
INTERNAL REGISTERS AND I/O
SPECIAL MODES
INTERRUPT
VECTORS
4 KBYTES PROM (ROM)
256-BYTES
BOOT ROM
$BFC0
$BFFF
$BF00
$BFFF
$7000
$7FFF
$0040
$00FF
$0000
$003F
$0000
$1000
$2000
$3000
$4000
$5000
$6000
$7000
$8000
$9000
$A000
$B000
$C000
$D000
$E000
$F000
$FFFF
MULTIPLEXED BOOTSTRAP
EXTERNAL
EXTERNAL
(MAY BE MAPPED TO ANY 4-K BOUNDARY
USING INIT REGISTER)
(MAY BE MAPPED TO ANY 4-K BOUNDARY
USING THE INIT REGISTER)
PRESENT AT RESET AND MAY BE DISABLED BY
EPON (ROM ON) BIT IN CONFIG REGISTER.
INTERRUPT VECTORS ARE EXTERNAL.
NORMAL MODES
INTERRUPT
VECTORS
4-KBYTES
PROM (ROM)
$BFC0
$BFFF
$BF00
$BFFF
MODB MODA Mode Selected
1
1
0
0
0
1
0
1
Single-chip (mode 0)
Expanded multiplexed (mode 1)
Special bootstrap
Special test
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Operating Modes and Memory
Memory Map
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Operating Modes and Memory 25
2.3.1 Control and Status Registers
Figure 2-2 is a representation of all 64 bytes of control and status registers, I/O and
data registers, and reserved locations that make up the internal register block. This
block may be mapped to any 4-K boundary in memory, but reset locates it at
$0000–$003F. This mappability factor and the default starting addresses are
indicated by the use of a bold 0 as the starting character of a register’s address.
Addr. Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PORTA)
See page 68.
Read:
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Hi-Z 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
$0001 Reserved RRRRRRRR
$0002
Port C Control Register
(PIOC)
See page 70.
Read:
00CWOM00000
Write:
Reset:00000000
$0003
Port C Data Register
(PORTC)
See page 70.
Read:
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Write:
Reset: Reset configures pins as Hi-Z inputs
$0004
Port B Data Register
(PORTB)
See page 69.
Read:
PB7 PB6 PB5 PB4 PB3 BP2 BP1 PB0
Write:
Reset: Reset configures pins as Hi-Z inputs
$0005 Reserved RRRRRRRR
$0006
Data Direction Register
for Port B (DDRB)
See page 69.
Read:
DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0
Write:
Reset:00000000
$0007
Data Direction Register
for Port C (DDRC)
See page 71.
Read:
DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0
Write:
Reset:00000000
$0008
Port D Data Register
(PORTD)
See page 71.
Read:
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Write:
Reset:00000000
$0009
Data Direction Register
for Port D (DDRD)
See page 72.
Read:
DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
Write:
Reset:00000000
$000A Reserved RRRRRRRR
= Unimplemented R= Reserved U = Unaffected
Figure 2-2. Register and Control Bit Assignments (Sheet 1 of 5)
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Operating Modes and Memory
Data Sheet MC68HC711D3 — Rev. 2
26 Operating Modes and Memory MOTOROLA
$000B
Timer Compare Force Register
(CFORC)
See page 104.
Read:
FOC1 FOC2 FOC3 FOC4 FOC5 0 0 0
Write:
Reset:00000000
$000C
Output Compare 1 Mask Register
(OC1M)
See page 105.
Read:
OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 0 0 0
Write:
Reset:00000000
$000D
Output Compare 1 Data Register
(OC1D)
See page 105.
Read:
OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 0 0 0
Write:
Reset:00000000
$000E
Timer Counter Register High
(TCNT)
See page 106.
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:00000000
$000F
Timer Counter Register Low
(TCNT)
See page 106.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
$0010
Timer Input Capture Register 1
High (TIC1)
See page 100.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
$0011
Timer Input Capture Register 1
Low (TIC1)
See page 100.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
$0012
Timer Input Capture Register 2
High (TIC2)
See page 100.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
$0013
Timer Input Capture Register 2
Low (TIC2)
See page 100.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
$0014
Timer Input Capture Register 3
High (TIC3)
See page 100.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
$0015
Timer Input Capture Register 3
Low (TIC3)
See page 100.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
$0016
Timer Output Compare Register 1
High (TOC1)
See page 103.
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 15
Write:
Reset:11111111
Addr. Register Name Bit 7654321Bit 0
= Unimplemented R= Reserved U = Unaffected
Figure 2-2. Register and Control Bit Assignments (Sheet 2 of 5)
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Operating Modes and Memory
Memory Map
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Operating Modes and Memory 27
$0017
Timer Output Compare Register 1
Low (TOC1)
See page 103.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:11111111
$0018
Timer Output Compare Register 2
High (TOC2)
See page 103.
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
$0019
Timer Output Compare Register 2
Low (TOC2)
See page 103.
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:11111111
$001A
Timer Output Compare Register 3
High (TOC3)
See page 103.
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
$001B
Timer Output Compare Register 3
Low (TOC3)
See page 103.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:11111111
$001C
Timer Output Compare Register 4
High (TOC4)
See page 103.
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
$001D
Timer Output Compare Register 4
Low (TOC4)
See page 103.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:11111111
$001E
Timer Input Capture 4/
Output Compare 5 Register High
(TI4/O5)
See page 101.
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
$001F
Timer Input Capture 4/
Output Compare 5 Register Low
(TI4/O5)
See page 101.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:11111111
$0020
Timer Control 1 Register
(TCTL1)
See page 106.
Read:
OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5
Write:
Reset:00000000
$0021
Timer Control Register 2
(TCTL2)
See page 99.
Read:
EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A
Write:
Reset:00000000
Addr. Register Name Bit 7654321Bit 0
= Unimplemented R= Reserved U = Unaffected
Figure 2-2. Register and Control Bit Assignments (Sheet 3 of 5)
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Operating Modes and Memory
Data Sheet MC68HC711D3 — Rev. 2
28 Operating Modes and Memory MOTOROLA
$0022
Timer Interrupt Mask 1 Register
(TMSK1)
See page 107.
Read:
OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I
Write:
Reset:00000000
$0023
Timer Interrupt Flag 1 Register
(TFLG1)
See page 108.
Read:
OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F
Write:
Reset:00000000
$0024
Timer Interrupt Mask 2 Register
(TMSK2)
See page 108.
Read:
TOI RTII PAOVI PAII 0 0 PR1 PR0
Write:
Reset:00000000
$0025
Timer Interrupt Flag 2 Register
(TFLG2)
See page 109.
Read:
TOF RTIF PAOVF PAIF 0 0 0 0
Write:
Reset:00000000
$0026
Pulse Accumulator Control
Register (PACTL)
See pages 112 and 114.
Read:
DDRA7 PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0
Write:
Reset:00000000
$0027
Pulse Accumulator Count Register
(PACNT)
See page 115.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Unaffected by reset
$0028
SPI Control Register
(SPCR)
See page 92.
Read:
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
Write:
Reset:000001UU
$0029
SPI Status Register
(SPSR)
See page 93.
Read:
SPIFWCOL0MODF0000
Write:
Reset:00000000
$002A
SPI Data I/O Register
(SPDR)
See page 94.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Unaffected by reset
$002B
Baud Rate Register
(BAUD)
See page 81.
Read:
TCLR 0 SCP1 SCP0 RCKB SCR2 SCR1 SCR0
Write:
Reset:00000UUU
$002C
SCI Control Register 1
(SCCR1)
See page 78.
Read:
R8 T8 0 M WAKE 0 0 0
Write:
Reset:UU000000
$002D
SCI Control Register 2
(SCCR2)
See page 79.
Read:
TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset:00000000
Addr. Register Name Bit 7654321Bit 0
= Unimplemented R= Reserved U = Unaffected
Figure 2-2. Register and Control Bit Assignments (Sheet 4 of 5)
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Operating Modes and Memory
Memory Map
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Operating Modes and Memory 29
$002E
SCI Status Register
(SCSR)
See page 80.
Read:
TDRE TC RDRF IDLE OR NF FE 0
Write:
Reset:11000000
$002F
SCI Data Register
(SCDR)
See page 78.
Read:
R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
Write:
Reset: Unaffected by reset
$0030
↓
$0038
Reserved RRRRRRRR
$0039
System Configuration Options
Register (OPTION)
See page 53.
Read:
0 0 IRQE DLY CME 0 CR1 CR0
Write:
Reset:00010000
$003A
Arm/Reset COP Timer Circuitry
Register (COPRST)
See page 52.
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
$003B
PROM Programming Control
Register (PPROG)
See page 33.
Read:
MBE 0 ELAT EXCOL EXROW 0 0 PGM
Write:
Reset:00000000
$003C
Highest Priority I-Bit Interrupt and
Miscellaneous Register (HPRIO)
See page 63.
Read:
RBOOT
SMOD
MDA IRVNE PSEL3 PSEL2 PSEL1 PSEL0
Write:
Reset: Note 1 0 1 0 1
1. The values of the RBOOT, SMOD, IRVNE, and MDA bits at reset depend
on the mode during initialization. Refer to Table 4-3. Hardware Mode
Select Summary.
$003D
RAM and I/O Mapping Register
(INIT)
See page 30.
Read:
RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0
Write:
Reset:00000001
$003E Test 1 Register
(TEST)
Read:
TILOP 0 OCC4 CBYP DISR FCM FCOP 0
Write:
Reset:00000000
$003F
System Configuration Register
(CONFIG)
See page 31.
Read:
00000NOCOPROMON0
Write:
Reset:00000UU0
Addr. Register Name Bit 7654321Bit 0
= Unimplemented R= Reserved U = Unaffected
Figure 2-2. Register and Control Bit Assignments (Sheet 5 of 5)
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Operating Modes and Memory
Data Sheet MC68HC711D3 — Rev. 2
30 Operating Modes and Memory MOTOROLA
2.3.2 RAM and I/O Mapping Register
The random-access memory (RAM) and input/output (I/O) mapping register (INIT)
is a special-purpose 8-bit register that is used during initialization to change the
default locations of RAM and control registers within the MCU memory map. It can
be written to only once within the first 64 E-clock cycles after a reset in normal
modes. Thereafter, it becomes a read-only register.
RAM2–RAM0 (INIT bits 7–4) specify the starting address for the 192 bytes of static
RAM. REG3–REG0 (INIT bits 3–0) specify the starting addre ss for the control and
status register block. In each case, the four RAM or REG bits become the four
upper bits of the 16-bit address of the RAM or register. Since the INIT register is
set to $00 by reset, the internal registers begin at $0000 and RAM begins at $0040.
Throughout this document, control and status register addresses are displayed
with the high-order digit shown as a bold 0. This convention indicates that the
register block may be relocated to any 4-K memory page, but that its default
location is $0000.
RAM and the control and status registers can be relocated independently. If the
control and status registers are relocated in such a way as to conflict with PROM,
then the register block takes priority, and the EPROM or OTPROM at those
locations becomes inaccessible. No harmful conflicts result. Lower priority
resources simply become inaccessible. Similarly, if an internal resource conflicts
with an external device, no harmful conflict results, since data from the external
device is not applied to the internal data bus. Thus, it cannot interfere with the
internal read.
NOTE: There are unused register locations in the 64-byte control and status register block.
Reads of these unused registers return data from the undriven internal data bus,
not from another source that happens to be located at the same address.
2.3.3 Configuration Control Register
The configuration control register (CONFIG) controls the presence of OTPROM or
EPROM in the memory map and enables the computer operating properly (COP)
watchdog system.
This register is writable only once in expanded and single-chip modes (SMOD = 0).
In these mode, the COP watchdog timer is enabled out of reset. In all modes,
except normal expanded, EPROM is enabled and located at $F000–$FFFF. In
Address: $003D
Bit 7654321Bit 0
Read:
RAM3 RAM2 RAM1 RAM0 REG3 REG2 REG1 REG0
Write:
Reset:00000000
Figure 2-3. RAM and I/O Mapping Register (INIT)
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Operating Modes and Memory
Programmable Read-Only Memory (PROM)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Operating Modes and Memory 31
normal expanded mode, EPROM is enabled and located at $7000–$7FFF. Should
the user wish to be in expanded mode, but with EPROM mapped at $F000–$FFFF,
he must reset in single-chip mode, and write a 1 to the MDA bit in the HPRIO
register.
Bits 7–3 and 0 — Not implemented
Always read 0.
NOCOP — Computer Operating Properly System Disable Bit
This bit is cleared out of reset in normal modes (single chip and expanded),
enabling the COP system. It is writable only once after reset in these modes
(SMOD = 0). In the special modes (test and bootstrap) (SMOD = 1), this bit
comes out of reset set, and is writable any time.
1 = COP system is disabled.
0 = COP system is enabled, reset forced on timeout.
ROMON — PROM Enable Bit
This bit is set out of reset, enabling the EPROM or OTPROM in all modes. This
bit is writable once in normal modes (SMOD = 0), but is writable at any time in
special modes (SMOD = 1).
1 = PROM is present in the memory map.
0 = PROM is disabled from the memory map.
NOTE: In expanded mode out of reset, the EPROM or OTPROM is located at
$7000–$7FFF. In all other modes, the PROM resides at $F000–$FFFF.
2.4 Programmable Read-Only Memory (PROM)
The MC68HC711D3 has 4-Kbytes of one-time programmable read-only memory
(OTPROM). The PROM address is $F000–$FFFF in all modes except expanded
multiplexed. In expanded- multiplexed mode, the PROM is located at
$7000–$7FFF after reset.
The on-chip read-only memory (ROM) of an MC68HC711D3 is programmed in
MCU mode. In this mode, the PROM is programmed through the MCU in the
bootstrap or test modes. The erased state of a PROM byte is $FF.
Using the on-chip OTPROM programming feature requires an external 12-volt
nominal power supply (VPP). Normal programming is accomplished using the
OTPROM programming register (PPROG).
Address: $003F
Bit 7654321Bit 0
Read:
00000NOCOPROMON0
Write:
Reset:00000UU0
U = Unaffected
Figure 2-4. Configuration Control Register (CONFIG)
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Operating Modes and Memory
Data Sheet MC68HC711D3 — Rev. 2
32 Operating Modes and Memory MOTOROLA
As described in the following subsections, these two methods of programming and
verifying EPROM are possible:
1. Programming an individual EPROM address
2. Programming the EPROM with downloaded data
2.4.1 Programming an Individual EPROM Address
In this method, the MCU programs its own EPROM by controlling the PPROG
register. Use these procedures to program the EPROM through the MCU with:
• The ROMON bit set in the CONFIG register
• The 12-volt nominal programming voltage present on the XIRQ/VPP pin
• The IRQ pin must be pulled high.
EPROG LDAB #$20
STAB $003B Set ELAT bit (PGM = 0) to enable
EPROM latches.
STAA $0,X Store data to EPROM address
LDAB #$21
STAB $003B Set PGM bit with ELAT = 1 to enable
EPROM programming voltage
JSR DLYEP Delay 2–4 ms
CLR $003B Turn off programming voltage and set
to READ mode
2.4.2 Programming the EPROM with Downloaded Data
When using this method, the EPROM is programmed by software while in the
special test or bootstrap modes. User-developed software can be uploaded
through the SCI or a ROM-resident EPROM programmin g utility can be used. The
12-volt nominal programming voltage must be present on the XIRQ/VPP pin. To
use the resident utility, bootload a 3-byte program consisting of a single jump
instruction to $BF00. $BF00 is the starting address of a resident EPROM
programming utility. The utility program sets the X and Y index reg isters to default
values, then receives programming data from an external host, and puts it in
EPROM. The value in IX determines programmin g delay time. The value in IY is a
pointer to the first address in EPROM to be programmed (default = $F000).
When the utility program is ready to receive programming data, it sends the host
the $FF character. Then it waits. When the host sees the $FF character, the
EPROM programming data is sent, starting with the first location in the EPROM
array. After the last byte to be programmed is sent and the corresponding
verification data is returned, the programmi ng operation is terminated by resetting
the MCU.
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Operating Modes and Memory
Programmable Read-Only Memory (PROM)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Operating Modes and Memory 33
2.4.3 PROM Programming Control Register
The PROM programming control register (PPROG) is used to control the
programming of the OTPROM or EPROM. PPROG is cleared on reset so that the
PROM is configured for normal read.
MBE — Multiple Byte Program Enable Bit
This bit is reserved for testing.
Bit 6, 2, and 1 — Not implemented
Always read 0.
ELAT — EPROM (OTPROM) Latch Control Bit
1 = PROM address and data bus are configured for programming. Writes to
PROM cause address and data to be latched. The PROM cannot be
read.
0 = PROM address and data bus are configured for normal reads. PROM
cannot be programmed.
EXCOL — Select Extra Columns Bit
This bit is reserved for testing.
EXROW — Select Extra Row Bit
This bit is reserved for testing.
PGM — EPROM (OTPROM) Program Command Bit
This bit may be written only when ELAT = 1.
1 = Programming power is switched on to PROM array.
0 = Programming power is switched off.
Address: $003B
Bit 7654321Bit 0
Read:
MBE 0 ELAT EXCOL EXROW 0 0 PGM
Write:
Reset:00000000
Figure 2-5. PROM Programming Control Register (PPROG)
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Operating Modes and Memory
Data Sheet MC68HC711D3 — Rev. 2
34 Operating Modes and Memory MOTOROLA
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 35
Data Sheet — MC68HC711D3
Section 3. Central Processor Unit (CPU)
3.1 Introduction
This section presents information on M68HC11 central processor unit (CPU):
•Architecture
• Data types
• Addressing modes
• Instruction set
• Special operations such as subroutine calls and interrupts
The CPU is designed to treat all peripheral, input/output (I/O), and memory
locations identically as addresses in the 64-Kbyte memory map. This is referred to
as memory-mapped I/O. I/O has no instructions separate from those used by
memory. This architecture also allows accessing an operand from an external
memory location with no execution time penalty.
3.2 CPU Registers
M68HC11 CPU registers are an integral part of the CPU and are not addressed as
if they were memory locations. The seven registers, discussed in the following
paragraphs, are shown in Figure 3-1.
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
36 Central Processor Unit (CPU) MOTOROLA
Figure 3-1. Programming Model
3.2.1 Accumulators A, B, and D
Accumulators A and B are general-purpose 8-bit registers that hold operands and
results of arithmetic calculations or data manipulations. For some instructions,
these two accumulators are treated as a single double-byte (16-bit) accumulator
called accumulator D. Although most instructions can use accumulators A or B
interchangeably, these exceptions apply:
• The ABX and ABY instructions add the contents of 8-bit accumulator B to
the contents of 16-bit register X or Y, but there are no equivalent instructions
that use A instead of B.
• The TAP and TPA instructions transfer data from accumulator A to the
condition code register or from the condition code register to accumulator A.
However, there are no equivalent instructions that use B rather than A.
• The decimal adjust accumulator A (DAA) instruction is used after
binary-coded decimal (BCD) arithmetic operations, but there is no
equivalent BCD instruction to adjust accumulator B.
• The add, subtract, and compare instructions associated with both A and B
(ABA, SBA, and CBA) only operate in one direction, making it important to
plan ahead to ensure that the correct operand is in the correct accumulator.
A:B
7070
15 0
ACCUMULATOR A ACCUMULATOR B
DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
70
CVZNIHXS
D
IX
IY
SP
PC
CARRY
OVERFLOW
ZERO
NEGATIVE
I INTERRUPT MASK
HALF CARRY (FROM BIT 3)
X INTERRUPT MASK
STOP DISABLE
CCR
15
15
15
15
0
0
0
0
CONDITION CODE REGISTER
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Central Processor Unit (CPU)
CPU Registers
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 37
3.2.2 Index Register X (IX)
The IX register provides a 16-bit indexing value that can be added to the 8-bit offset
provided in an instruction to create an effective address. The IX register can also
be used as a counter or as a temporary storage register.
3.2.3 Index Register Y (IY)
The 16-bit IY register performs an indexed mode function similar to that of the IX
register. However, most instructions using the IY register require an extra byte of
machine code and an extra cycle of execution time because of the way the opcode
map is implemented. Refer to 3.4 Opcodes and Operands for further information.
3.2.4 Stack Pointer (SP)
The M68HC11 CPU has an automatic program stack. This stack can be located
anywhere in the address space and can be any size up to the amount of memory
available in the system. Normally, the SP is initialized by one of the first instructions
in an application program. The stack is configured as a data structure that grows
downward from high memory to low memory. Each time a new byte is pushed onto
the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP
is incremented. At any given time, the SP ho lds the 16-bit address of the next free
location in the stack. Figure 3-2 is a summary of SP operations.
When a subroutine is called by a jump-to-subroutine (JSR) or branch-to-
subroutine (BSR) instruction, the address of the instruction after the JSR or BSR is
automatically pushed onto the stack, least significant byte first. When the
subroutine is finished, a return-from-subroutine (RTS) instruction is executed. The
RTS pulls the previously stacked return address from the stack and loads it into the
program counter. Execution then continues at this recovered return address.
When an interrupt is recognized, the current instruction finishes normally, the
return address (the current value in the program counter) is pushed onto the stack,
all of the CPU registers are pushed onto th e stack, and execution contin ues at the
address specified by the vector for the interrupt.
At the end of the interrupt service routine, a return-from interrupt (RTI) instruction
is executed. The RTI instruction causes the saved registers to be pulled off the
stack in reverse order. Program execution resumes at the return address.
Certain instructions push and pull the A and B accumulators and the X and Y index
registers and are often used to preserve program context. For example, pushing
accumulator A onto the stack when entering a subroutine that use s accumulator A
and then pulling accumulator A off the stack just before leaving the subroutine
ensures that the contents of a register will be the same after returning from the
subroutine as it was before starting the subroutine.
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
38 Central Processor Unit (CPU) MOTOROLA
Figure 3-2. Stacking Operations
SP-9
STACK
SP-1
ACMLTR A
ACMLTR B
CONDITION CODE
SP-2
SP-3
SP-4
SP-5
SP-6
SP-7
SP-8
INDEX REGISTER (YL)
INDEX REGISTER (YH)
INDEX REGISTER (XL)
INDEX REGISTER (XH)
RTNL
RTNH
STACK
SP-2
SP-1
SP
RTNL
RTNH
STACK
SP-2
SP-1
SP
RTNL
RTNH
$9D = JSR
dd
NEXT MAIN INSTR
DIRECT
MAIN PROGRAM
$AD = JSR
ff
NEXT MAIN INSTR
INDXD,X
MAIN PROGRAM
PC
RTN
PC
RTN
$18 = PRE
ff
NEXT MAIN INSTR
INDXD,Y
MAIN PROGRAM
PC
RTN
$AD = JSR
$BD = JSR
ll
NEXT MAIN INSTR
EXTEND
MAIN PROGRAM
PC
RTN
hh
$8D = BSR
rr
NEXT MAIN INSTR
MAIN PROGRAM
$39 = RTS
SUBROUTINE
PC
RTN
PC
BSR, BRANCH TO SUBROUTINE
STACK
SP
SP+1
SP+2
RTS, RETURN FROM SUBROUTINE
$3F = SWI
MAIN PROGRAM
PC
SWI, SOFTWARE INTERRUPT
RTN
$3E = WAI
MAIN PROGRAM
PC
WAI, WAIT FOR INTERRUPT
RTN
$3B = RTI
INTERRUPT PROGRAM
PC
STACK
SP+1
SP
RTI, RETURN FROM INTERRUPT
ACMLTR A
ACMLTR B
CONDITION CODE
SP+2
SP+3
SP+4
SP+5
SP+6
SP+7
SP+8
SP+9
LEGEND:
RTN
RTNH
RTNL
dd
ff
hh
ll
rr
Address of next instruction in main program to be
executed upon return from subroutine
Most significant byte of return address
Least significant byte of return address
8-bit direct address ($0000–$00FF) (high byte
assumed to be $00).
8-bit positive offset $00 (0) to $FF (256) is add ed
to index.
High-order byte of 16-bit ext ended address.
Low-order byte of 16-bit extended addre ss.
Signed-relative offset $80 (–128) to $7F (+127)
(offset relative to the addre ss fo llowing the
machine code offset byte).
JSR, JUMP TO SUBROUTINE
Shaded cells show stack pointer positi on after
operation is complete.
RTNL
RTNH
INDEX REGISTER (YL)
INDEX REGISTER (YH)
INDEX REGISTER (XL)
INDEX REGISTER (XH)
RTNL
RTNH
SP
$6E = JMP
ff
MAIN PROGRAM
NEXT INSTRUCTION
INDXD,X
PC
X + ff
$18 = PRE
ff
MAIN PROGRAM
PC
$6E = JMP
JMP, JUMP
NEXT INSTRUCTIONX + ff
INDXD,Y
$7E = JMP
ll
MAIN PROGRAM
PC
hh
NEXT INSTRUCTIONhh ll
EXTND
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Central Processor Unit (CPU)
CPU Registers
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 39
3.2.5 Program Counter (PC)
The program counter, a 16-bit register, contains the address of the next instructio n
to be executed. After reset, the program counter is initialized from one of six
possible vectors, depending on operating mode and the cause of reset.
See Table 3-1.
3.2.6 Condition Code Register (CCR)
This 8-bit register contains:
• Five condition code indicators (C, V, Z, N, and H)
• Two interrupt masking bits (IRQ and XIRQ)
• One stop disable bit (S)
In the M68HC11 CPU, condition codes are updated automatically by most
instructions. For example, load accumulator A (LDAA) and store accumulator A
(STAA) instructions automatically set or clear the N, Z, and V condition code flags.
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to Table 3-2, which shows
what condition codes are affected by a particular instruction.
3.2.6.1 Carry/Borrow (C)
The C bit is set if the arithmetic logic unit (AL U) performs a carry or borr ow during
an arithmetic operation. The C bit also acts as an error flag for multiply and divide
operations. Shift and rotate instructions operate with and through the carry bit to
facilitate multiple-word shift operations.
3.2.6.2 Overflow (V)
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the
V bit is cleared.
3.2.6.3 Zero (Z)
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation
is 0. Otherwise, the Z bit is cleared. Compare instructions do an internal implied
subtraction and the condition codes, including Z, reflect the results of that
subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no
other condition flags. For these operations, only = and ≠ conditions can be
determined.
Table 3-1. Reset Vector Comparison
Mode POR or RESET Pin Clock Monitor COP Watchdog
Normal $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB
Test or boot $BFFE, $BFFF $BFFC, $FFFD $BFFA, $FFFB
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
40 Central Processor Unit (CPU) MOTOROLA
3.2.6.4 Negative (N)
The N bit is set if the result of an arithmetic, logic, or data manipulation operation
is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative
if its most significant bit (MSB) is a 1. A quick way to test wh ether the contents of a
memory location has the MSB set is to load it into an accumulator and then check
the status of the N bit.
3.2.6.5 I-Interrupt Mask (I)
The interrupt request (IRQ) mask (I bit) is a global mask that disable s all maskable
interrupt sources. While the I bit is set, interrupts can become pending, but the
operation of the CPU continues uninterrupted until the I bit is cleared. After any
reset, the I bit is set by default and can be cleared only by a software instruction.
When an interrupt is recognized, the I bit is set after the registers are stacked, but
before the interrupt vector is fetched. After the interrupt has been serviced, a
return-from-interrupt instruction is normally executed, restoring the registers to the
values that were present before the interrupt occurred. Normally, the I bit is 0 after
a return from interrupt is executed. Although the I bit can be cleared within an
interrupt service routine, "nesting" interrupts in this way sho uld be done only when
there is a clear understanding of latency and of the arbitration mechanism. Refer
to Section 4. Resets, Interrupts, and Low-Power Modes.
3.2.6.6 Half Carry (H)
The H bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic
unit during an ADD, ABA, or ADC instruction. Otherwise, the H bit is cleared. Half
carry is used during BCD operations.
3.2.6.7 X-Interrupt Mask (X)
The XIRQ mask (X) bit disables interrupts from the XI RQ pin. After any reset, X is
set by default and must be cleared by a software instruction. When an XIRQ
interrupt is recognize d, the X a nd I bits ar e set after the registers are stacked, b ut
before the interrupt vector is f etched. After the interrupt has be en serviced, an RTI
instruction is normally executed, causing t he registers to be restored to the values
that were present before the interrupt occurred. The X interrupt mask bit is set only
by hardware (RESET or XIRQ acknowledge). X is cleared only by program
instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value
loaded into the CCR from the stack has been cleared). There is no hardware action
for clearing X.
3.2.6.8 STOP Disable (S)
Setting the STOP disable (S) bit prevents the STOP instruction from putting the
M68HC11 into a low-power stop con dition. If the STOP instruction is encountere d
by the CPU while the S bit is set, it is treated a s a no-opera tion (NOP) in struction,
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Central Processor Unit (CPU)
Data Types
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 41
and processing continues to the next instruction. S is set by reset; STOP is
disabled by default.
3.3 Data Types
The M68HC11 CPU supports four data types:
1. Bit data
2. 8-bit and 16-bit signed and unsigned integers
3. 16-bit unsigned fractions
4. 16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A word is
composed of two consecutive bytes with the most significant byte at the lower
value address. Because the M68HC11 is an 8-bit CPU, there are no special
requirements for alignment of instructions or operands.
3.4 Opcodes and Operands
The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode
identifies a particular instruction and associated addressing mode to the CPU.
Several opcodes are required to provide each instruction with a range of
addressing capabilities. Only 256 opcodes would be available if the range of values
were restricted to the number able to be expressed in 8-bit binary numbers.
A 4-page opcode map has been implemented to expand the number of
instructions. An additional byte, called a prebyte, directs the processor from page 0
of the opcode map to one of the other three pages. As its name implies, the
additional byte precedes the opcode.
A complete instruction consists of a p rebyte, if any, an opcode, and zero, one, two,
or three operands. The operands contain information the CPU needs for executing
the instruction. Complete instructions can be from one to five bytes long.
3.5 Addressing Modes
Six addressing modes can be used to access memory:
1. Immediate
2. Direct
3. Extended
4. Indexed
5. Inherent
6. Relative
These modes are de tailed in th e following paragraphs. All modes except inherent
mode use an effective address. The eff ective address is the memory address from
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
42 Central Processor Unit (CPU) MOTOROLA
which the argument is fetched or stored or the address from which execution is to
proceed. The effective address can be specified within an instruction, or it can be
calculated.
3.5.1 Immediate
In the immediate addressing mode, an argument is contained in the byte(s)
immediately following the opcode. The number of bytes following the opcode
matches the size of the register or memory location being operated on. There are
2-, 3-, and 4- (if prebyte is required) byte immediate instructions. The effective
address is the address of the byte following the instruction.
3.5.2 Direct In the direct addressing mode, the low-order byte of the operand address is
contained in a single byte following the opcode, and the high-order byte of the
address is assumed to be $00. Addresses $00–$FF are thus accessed directly,
using 2-byte instructions. Execution time is reduced by eliminating the additiona l
memory access required for the high-order address byte. In most applications, this
256-byte area is reserved f or frequently refe renced data . In M68HC11 MCUs, the
memory map can be configured for combinations of internal registers, RAM, or
external memory to occupy these addresses.
3.5.3 Extended
In the extended addressing mode, the effective address of the argument is
contained in two bytes following the opcode byte. These are 3-byte instructions (or
4-byte instructions if a prebyte is required). One or two bytes are needed for the
opcode and two for the effective address.
3.5.4 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in the
instruction is added to the valu e contained in an index reg ister (IX or IY). The sum
is the effective address. This addressing mode allows referencing any memory
location in the 64-Kbyte address space. These are 2- to 5-byte instructions,
depending on whether a prebyte is required.
3.5.5 Inherent
In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opcode. Operations that use only t he index registers
or accumulators, as well as control instructions with no arguments, are included in
this addressing mode. These are 1- or 2-byte instructions.
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Central Processor Unit (CPU)
Instruction Set
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 43
3.5.6 Relative
The relative addressing mode is used only for branch instructions. If the branch
condition is true, an 8-bit signed offset included in the instruction is added to the
contents of the program counter to form the effective branch address. Otherwise,
control proceeds to the next instruction. These are usually 2-byte instructions.
3.6 Instruction Set
Refer to Table 3-2, which shows all the M68HC11 instructions in all possible
addressing modes. For each instruction, the table shows the operand construction,
the number of machine code bytes, and execution time in CPU E-clock cycles.
Table 3-2. Instruction Set (Sheet 1 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
ABA Add
Accumulators A + B ⇒ AINH1B—2——∆—∆∆∆∆
ABX Add B to X IX + (00 : B) ⇒ IX INH 3A — 3 ————————
ABY Add B to Y IY + (00 : B) ⇒ IY INH 18 3A — 4 —————— ——
ADCA (opr) Add with Carry
to A A + M + C ⇒ AA IMM
ADIR
AEXT
AIND,X
AIND,Y
89
99
B9
A9
18 A9
ii
dd
hh ll
ff
ff
2
3
4
4
5
——∆—∆∆∆∆
ADCB (opr) Add with Carry
to B B + M + C ⇒ BB IMM
BDIR
BEXT
BIND,X
BIND,Y
C9
D9
F9
E9
18 E9
ii
dd
hh ll
ff
ff
2
3
4
4
5
——∆—∆∆∆∆
ADDA (opr) Add Memory to
AA + M ⇒ A A IMM
ADIR
AEXT
AIND,X
AIND,Y
8B
9B
BB
AB
18 AB
ii
dd
hh ll
ff
ff
2
3
4
4
5
——∆—∆∆∆∆
ADDB (opr) Add Memory to
BB + M ⇒ BBIMM
BDIR
BEXT
BIND,X
BIND,Y
CB
DB
FB
EB
18 EB
ii
dd
hh ll
ff
ff
2
3
4
4
5
——∆—∆∆∆∆
ADDD (opr) Add 16-Bit to D D + (M : M + 1) ⇒ DIMM
DIR
EXT
IND,X
IND,Y
C3
D3
F3
E3
18 E3
jj kk
dd
hh ll
ff
ff
4
5
6
6
7
————∆∆∆∆
ANDA (opr) AND A with
Memory A • M ⇒ AA IMM
A DIR
A EXT
AIND,X
AIND,Y
84
94
B4
A4
18 A4
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
ANDB (opr) AND B with
Memory B • M ⇒ BBIMM
BDIR
BEXT
BIND,X
BIND,Y
C4
D4
F4
E4
18 E4
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
ASL (opr) Arithmetic Shift
Left EXT
IND,X
IND,Y
78
68
18 68
hh ll
ff
ff
6
6
7
————∆∆∆∆
C
0
b7 b0
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
44 Central Processor Unit (CPU) MOTOROLA
ASLA Arithmetic Shift
Left A A INH 48 — 2 ————∆∆∆∆
ASLB Arithmetic Shift
Left B B INH 58 — 2 ————∆∆∆∆
ASLD Arith metic Shift
Left D INH 05 — 3 — — — — ∆∆∆∆
ASR Arithmetic Shift
Right EXT
IND,X
IND,Y
77
67
18 67
hh ll
ff
ff
6
6
7
————∆∆∆∆
ASRA Arithmetic Shift
Right A A INH 47 — 2 ————∆∆∆∆
ASRB Arithmetic Shift
Right B B INH 57 — 2 ————∆∆∆∆
BCC (rel) Branch if Carry
Clear ? C = 0 R EL 24 rr 3 ————————
BCLR (opr)
(msk) Clear Bit(s) M • (mm) ⇒ M DIR
IND,X
IND,Y
15
1D
18 1D
dd mm
ff mm
ff mm
6
7
8
————∆∆0—
BCS (rel) Branch if Carry
Set ? C = 1 R EL 25 rr 3 ————————
BEQ (rel) Branch if = Zero ? Z = 1 REL 27 rr 3 — — — — — — — —
BGE (rel) Branch if ∆ Zero ? N ⊕ V = 0 REL 2C rr 3 ————————
BGT (rel) Branch if > Zero ? Z + (N ⊕ V) = 0 REL 2 E rr 3 ————————
BHI (rel) Branch if
Higher ? C + Z = 0 REL 22 rr 3 ————————
BHS (rel) Branch if
Higher or Same ? C = 0 REL 24 rr 3 ————————
BITA (opr) Bit(s) Test A
with Memory A • M A IMM
ADIR
AEXT
AIND,X
AIND,Y
85
95
B5
A5
18 A5
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
BITB (opr) Bit(s) Test B
with Memory B • M B IMM
BDIR
BEXT
BIND,X
BIND,Y
C5
D5
F5
E5
18 E5
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
BLE (rel) Branch if ∆ Zero ? Z + (N ⊕ V) = 1 REL 2F rr 3 ————————
BLO (rel) Branch if Lower ? C = 1 REL 25 rr 3 ————————
BLS (rel) Branch if Lower
or Same ? C + Z = 1 REL 23 rr 3 ————————
BLT (rel) Branch if < Zero ? N ⊕ V = 1 R E L 2 D rr 3 ————————
BMI (rel) Branch if Minus ? N = 1 REL 2B rr 3 ————————
BNE (rel) Branch if not =
Zero ? Z = 0 REL 26 rr 3 ————————
BPL (rel) Branch if Plus ? N = 0 REL 2A rr 3 ————————
BRA (rel) Branch Always ? 1 = 1 REL 20 rr 3 ————————
BRCLR(opr)
(msk)
(rel)
Branch if
Bit(s) Clear ? M • mm = 0 DIR
IND,X
IND,Y
13
1F
18 1F
dd mm
rr
ff mm
rr
ff mm
rr
6
7
8
————————
BRN (rel) Branch Never ? 1 = 0 REL 21 rr 3 ————————
Table 3-2. Instruction Set (Sheet 2 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
C
0
b7 b0
C
0
b7 b0
C
0
b7 b0
AB
b7
b0
C
b7 b0
C
b7 b0
C
b7 b0
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Central Processor Unit (CPU)
Instruction Set
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 45
BRSET(opr)
(msk)
(rel)
Branch if Bit(s)
Set ? (M) • mm = 0 DIR
IND,X
IND,Y
12
1E
18 1E
dd mm
rr
ff mm
rr
ff mm
rr
6
7
8
————————
BSET (opr)
(msk) Set Bit(s) M + mm ⇒ MDIR
IND,X
IND,Y
14
1C
18 1C
dd mm
ff mm
ff mm
6
7
8
————∆∆0—
BSR (rel) Branch to
Subroutine See Figure 3-2 REL 8D rr 6 ————————
BVC (rel) Branch if
Overflow Clear ? V = 0 REL 28 rr 3 ————————
BVS (rel) Branch if
Overflow Set ? V = 1 REL 29 rr 3 ————————
CBA Compare A to B A – B INH 11 — 2 — — — — ∆∆∆∆
CLC Clear Carry Bit 0 ⇒ C INH 0C — 2 ——————— 0
CLI Clear Interrupt
Mask 0 ⇒ I INH 0E — 2 ——— 0 ————
CLR (opr) Clear Memory
Byte 0 ⇒ MEXT
IND,X
IND,Y
7F
6F
18 6F
hh ll
ff
ff
6
6
7
————0 1 0 0
CLRA Clear
Accumulator A 0 ⇒ A A INH 4F — 2 — — — — 0 1 0 0
CLRB Clear
Accumulator B 0 ⇒ B B INH 5F — 2 — — — — 0 1 0 0
CLV Clear Overflow
Flag 0 ⇒ V INH 0A — 2 ——————0—
CMPA (opr) Compare A to
Memory A – M A IMM
ADIR
AEXT
AIND,X
AIND,Y
81
91
B1
A1
18 A1
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆∆∆
CMPB (opr) Compare B to
Memory B – M B IMM
BDIR
BEXT
BIND,X
BIND,Y
C1
D1
F1
E1
18 E1
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆∆∆
COM (opr) Ones
Complement
Memory Byte
$FF – M ⇒ MEXT
IND,X
IND,Y
73
63
18 63
hh ll
ff
ff
6
6
7
————∆∆01
COMA Ones
Complement
A
$FF – A ⇒ AA INH 43 — 2————∆∆01
COMB Ones
Complement
B
$FF – B ⇒ BB INH 53 — 2————∆∆01
CPD (opr) Compare D to
Memory 16-Bit D – M : M + 1 IMM
DIR
EXT
IND,X
IND,Y
1A 83
1A 93
1A B3
1A A3
CD A3
jj kk
dd
hh ll
ff
ff
5
6
7
7
7
————∆∆∆∆
CPX (opr) Compare X to
Memory 16-Bit IX – M : M + 1 IMM
DIR
EXT
IND,X
IND,Y
8C
9C
BC
AC
CD AC
jj kk
dd
hh ll
ff
ff
4
5
6
6
7
————∆∆∆∆
CPY (opr) Compare Y to
Memory 16-Bit IY – M : M + 1 IMM
DIR
EXT
IND,X
IND,Y
18 8C
18 9C
18 BC
1A AC
18 AC
jj kk
dd
hh ll
ff
ff
5
6
7
7
7
————∆∆∆∆
Table 3-2. Instruction Set (Sheet 3 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
46 Central Processor Unit (CPU) MOTOROLA
DAA Decimal Adjust
AAdjust Sum to BCD INH 19 — 2 — — — — ∆∆∆∆
DEC (opr) Decrement
Memory Byte M – 1 ⇒ MEXT
IND,X
IND,Y
7A
6A
18 6A
hh ll
ff
ff
6
6
7
————∆∆∆—
DECA Decrement
Accumulator
A
A – 1 ⇒ AAINH 4A — 2————∆∆∆—
DECB Decrement
Accumulator
B
B – 1 ⇒ BBINH 5A — 2————∆∆∆—
DES Decrement
Stack Pointer SP – 1 ⇒ SP INH 34 — 3 ————————
DEX Decrement
Index Register
X
IX – 1 ⇒ IX INH 09 — 3 — — — — — ∆——
DEY Decrement
Index Register
Y
IY – 1 ⇒ IY INH 18 09 — 4 — — — — — ∆——
EORA (opr) Exclusive OR A
with Memory A ⊕ M ⇒ A A IMM
ADIR
AEXT
AIND,X
AIND,Y
88
98
B8
A8
18 A8
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
EORB (opr) Exclusive OR B
with Memory B ⊕ M ⇒ B B IMM
BDIR
BEXT
BIND,X
BIND,Y
C8
D8
F8
E8
18 E8
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
FDIV Fractional
Divide 16 by 16 D / IX ⇒ IX; r ⇒ D INH 03 — 41 ————— ∆∆∆
IDIV Integer Divide
16 by 16 D / IX ⇒ IX; r ⇒ D INH 02 — 41 —————∆0∆
INC (opr) Increment
Memory Byte M + 1 ⇒ MEXT
IND,X
IND,Y
7C
6C
18 6C
hh ll
ff
ff
6
6
7
————∆∆∆—
INCA Increment
Accumulator
A
A + 1 ⇒ A A INH 4C — 2 — — — — ∆∆∆—
INCB Increment
Accumulator
B
B + 1 ⇒ B B INH 5C — 2 — — — — ∆∆∆—
INS Increment
Stack Pointer SP + 1 ⇒ SP INH 31 — 3 ————————
INX Increment
Index Register
X
IX + 1 ⇒ IX INH 08 — 3 ————— ∆——
INY Increment
Index Register
Y
IY + 1 ⇒ IY INH 18 08 — 4 ————— ∆——
JMP (opr) Jump See Figure 3-2 EXT
IND,X
IND,Y
7E
6E
18 6E
hh ll
ff
ff
3
3
4
————————
JSR (opr) J ump to
Subroutine See Figure 3-2 DIR
EXT
IND,X
IND,Y
9D
BD
AD
18 AD
dd
hh ll
ff
ff
5
6
6
7
————————
LDAA (opr) Load
Accumulator
A
M ⇒ A A IMM
A DIR
A EXT
A IND,X
A IND,Y
86
96
B6
A6
18 A6
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
Table 3-2. Instruction Set (Sheet 4 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
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Central Processor Unit (CPU)
Instruction Set
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 47
LDAB (opr) Load
Accumulator
B
M ⇒ B B IMM
B DIR
B EXT
B IND,X
B IND,Y
C6
D6
F6
E6
18 E6
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
LDD (opr) Load Double
Accumulator
D
M ⇒ A,M + 1 ⇒ BIMM
DIR
EXT
IND,X
IND,Y
CC
DC
FC
EC
18 EC
jj kk
dd
hh ll
ff
ff
3
4
5
5
6
————∆∆0—
LDS (opr) Load Stack
Pointer M : M + 1 ⇒ SP IMM
DIR
EXT
IND,X
IND,Y
8E
9E
BE
AE
18 AE
jj kk
dd
hh ll
ff
ff
3
4
5
5
6
————∆∆0—
LDX (opr) Load Index
Register
X
M : M + 1 ⇒ IX IMM
DIR
EXT
IND,X
IND,Y
CE
DE
FE
EE
CD EE
jj kk
dd
hh ll
ff
ff
3
4
5
5
6
————∆∆0—
LDY (opr) Load Index
Register
Y
M : M + 1 ⇒ IY IMM
DIR
EXT
IND,X
IND,Y
18 CE
18 DE
18 FE
1A EE
18 EE
jj kk
dd
hh ll
ff
ff
4
5
6
6
6
————∆∆0—
LSL (opr) Logical Shift
Left EXT
IND,X
IND,Y
78
68
18 68
hh ll
ff
ff
6
6
7
————∆∆∆∆
LSLA Logical Shift
Left A A INH 48 — 2 ————∆∆∆∆
LSLB Logical Shift
Left B B INH 58 — 2 ————∆∆∆∆
LSLD Logical Shift
Left Double INH 05 — 3 — — — — ∆∆∆∆
LSR (opr) Logical Shift
Right EXT
IND,X
IND,Y
74
64
18 64
hh ll
ff
ff
6
6
7
———— 0 ∆∆∆
LSRA Logical Shift
Right A A INH 44 — 2 ———— 0 ∆∆∆
LSRB Logical Shift
Right B B INH 54 — 2 ———— 0 ∆∆∆
LSRD Logical Shift
Right Double INH 04 — 3 — — — — 0 ∆∆∆
MUL Multiply 8 by 8 A ∗ B ⇒ D INH 3D — 10 ———————∆
NEG (opr) Two’s
Complement
Memory Byte
0 – M ⇒ MEXT
IND,X
IND,Y
70
60
18 60
hh ll
ff
ff
6
6
7
————∆∆∆∆
NEGA Two’s
Complement
A
0 – A ⇒ AAINH 40 — 2————∆∆∆∆
NEGB Two’s
Complement
B
0 – B ⇒ BBINH 50 — 2————∆∆∆∆
NOP No operation No Operation INH 01 — 2 — — — — — — — —
Table 3-2. Instruction Set (Sheet 5 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
C0
b7 b0
C0
b7 b0
C0
b7 b0
C
0
b7 b0AB
b7
b0
C
0
b7 b0
C
0
b7 b0
C
0
b7 b0
C
0
b7 b0AB
b7
b0
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
48 Central Processor Unit (CPU) MOTOROLA
ORAA (opr) OR
Accumulator
A (Inclusive)
A + M ⇒ A A IMM
ADIR
AEXT
AIND,X
AIND,Y
8A
9A
BA
AA
18 AA
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
ORAB (opr) OR
Accumulator
B (Inclusive)
B + M ⇒ B B IMM
BDIR
BEXT
BIND,X
BIND,Y
CA
DA
FA
EA
18 EA
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆0—
PSHA Push A onto
Stack A ⇒ Stk,SP = SP – 1 A INH 36 — 3 — — — — — — — —
PSHB Push B onto
Stack B ⇒ Stk,SP = SP – 1 B INH 37 — 3 — — — — — — — —
PSHX Push X onto
Stack (Lo
First)
IX ⇒ Stk,SP = SP – 2 INH 3C — 4 ————————
PSHY Push Y onto
Stack (Lo
First)
IY ⇒ Stk,SP = SP – 2 INH 18 3C — 5 ————————
PULA Pull A from
Stack SP = SP + 1, A ⇐ StkA INH 32 — 4 ————————
PULB Pull B from
Stack SP = SP + 1, B ⇐ StkB INH 33 — 4 ————————
PULX Pull X From
Stack (Hi
First)
SP = SP + 2, IX ⇐ Stk INH 38 — 5 ————————
PULY Pull Y from
Stack (Hi
First)
SP = SP + 2, IY ⇐ Stk INH 18 38 — 6 ————————
ROL (opr) Rotate Left EXT
IND,X
IND,Y
79
69
18 69
hh ll
ff
ff
6
6
7
————∆∆∆∆
ROLA Rotate Left A A INH 49 — 2 — — — — ∆∆∆∆
ROLB Rotate Left B B INH 59 — 2 — — — — ∆∆∆∆
ROR (opr) Rotate Right EXT
IND,X
IND,Y
76
66
18 66
hh ll
ff
ff
6
6
7
————∆∆∆∆
RORA Rotate Right A A INH 46 — 2 — — — — ∆∆∆∆
RORB Rotate Right B B INH 56 — 2 — — — — ∆∆∆∆
RTI Return from
Interrupt See Figure 3-2 INH 3B — 12 ∆↓∆∆∆∆∆∆
RTS Return from
Subroutine See Figure 3-2 INH 39 — 5 ————————
SBA Subtract B from
AA – B ⇒ A INH 10 — 2 ————∆∆∆∆
SBCA (opr) Subtract with
Carry from A A – M – C ⇒ AA IMM
ADIR
AEXT
AIND,X
AIND,Y
82
92
B2
A2
18 A2
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆∆∆
Table 3-2. Instruction Set (Sheet 6 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
Cb7 b0
Cb7 b0
Cb7 b0
C
b7 b0
C
b7 b0
C
b7 b0
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Central Processor Unit (CPU)
Instruction Set
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Central Processor Unit (CPU) 49
SBCB (opr) Subtract with
Carry from B B – M – C ⇒ BB IMM
BDIR
BEXT
BIND,X
BIND,Y
C2
D2
F2
E2
18 E2
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆∆∆
SEC Set Carry 1 ⇒ C INH 0D — 2 ——————— 1
SEI Set Interrupt
Mask 1 ⇒ I INH 0F — 2 ——— 1 ————
SEV Set Overflow
Flag 1 ⇒ V INH 0B — 2 ——————1—
STAA (opr) Store
Accumulator
A
A ⇒ MADIR
AEXT
AIND,X
AIND,Y
97
B7
A7
18 A7
dd
hh ll
ff
ff
3
4
4
5
————∆∆0—
STAB (opr) Store
Accumulator
B
B ⇒ MBDIR
BEXT
BIND,X
BIND,Y
D7
F7
E7
18 E7
dd
hh ll
ff
ff
3
4
4
5
————∆∆0—
STD (opr) Store
Accumulator
D
A ⇒ M, B ⇒ M + 1 DIR
EXT
IND,X
IND,Y
DD
FD
ED
18 ED
dd
hh ll
ff
ff
4
5
5
6
————∆∆0—
STOP Stop Internal
Clocks — INH CF — 2 ————————
STS (opr) Store Stack
Pointer SP ⇒ M : M + 1 DIR
EXT
IND,X
IND,Y
9F
BF
AF
18 AF
dd
hh ll
ff
ff
4
5
5
6
————∆∆0—
STX (opr) Store Index
Register X IX ⇒ M : M + 1 DIR
EXT
IND,X
IND,Y
DF
FF
EF
CD EF
dd
hh ll
ff
ff
4
5
5
6
————∆∆0—
STY (opr) Store Index
Register Y IY ⇒ M : M + 1 DIR
EXT
IND,X
IND,Y
18 DF
18 FF
1A EF
18 EF
dd
hh ll
ff
ff
5
6
6
6
————∆∆0—
SUBA (opr) Subtract
Memory from
A
A – M ⇒ AAIMM
ADIR
AEXT
AIND,X
AIND,Y
80
90
B0
A0
18 A0
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆∆∆
SUBB (opr) Subtract
Memory from
B
B – M ⇒ BAIMM
ADIR
AEXT
AIND,X
AIND,Y
C0
D0
F0
E0
18 E0
ii
dd
hh ll
ff
ff
2
3
4
4
5
————∆∆∆∆
SUBD (opr) Subtract
Memory from
D
D – M : M + 1 ⇒ DIMM
DIR
EXT
IND,X
IND,Y
83
93
B3
A3
18 A3
jj kk
dd
hh ll
ff
ff
4
5
6
6
7
————∆∆∆∆
SWI Software
Interrupt See Figure 3-2 INH 3F — 14 ——— 1 ————
TAB Transfer A to B A ⇒ B INH 16 — 2 ————∆∆0—
TAP Transfer A to
CC Register A ⇒ CCR INH 06 — 2 ∆↓∆∆∆∆∆∆
TBA Transfer B to A B ⇒ A INH 17 — 2 ————∆∆0—
TEST TEST (Only in
Test Modes) Address Bus Counts INH 00 — * — — — — — — — —
TPA Transfer CC
Register to A CCR ⇒ A INH 07 — 2 ————————
Table 3-2. Instruction Set (Sheet 7 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
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Central Processor Unit (CPU)
Data Sheet MC68HC711D3 — Rev. 2
50 Central Processor Unit (CPU) MOTOROLA
TST (opr) Test for Zero or
Minus M – 0 EXT
IND,X
IND,Y
7D
6D
18 6D
hh ll
ff
ff
6
6
7
————∆∆00
TSTA Test A for Zer o
or Minus A – 0 A INH 4 D — 2 — — — — ∆∆00
TSTB Test B for Zer o
or Minus B – 0 B INH 5 D — 2 — — — — ∆∆00
TSX Transfer Stack
Point er to X SP + 1 ⇒ IX INH 30 — 3 ————————
TSY Transfer Stack
Point er to Y SP + 1 ⇒ IY INH 18 30 — 4 ————————
TXS Transfer X to
Stack Pointer IX – 1 ⇒ SP INH 35 — 3 ————————
TYS Transfer Y to
Stack Pointer IY – 1 ⇒ SP INH 18 35 — 4 ————————
WAI Wait for
Interrupt Stack Regs & WAIT INH 3E — ** — — — — — — — —
XGDX Exchange D
with X IX ⇒ D, D ⇒ IX INH 8F — 3 ————————
XGDY Exchange D
with Y IY ⇒ D, D ⇒ IY INH 18 8F — 4 ————————
Table 3-2. Instruction Set (Sheet 8 of 8)
Mnemonic Operation Description Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
Cycle
* Infinity or until reset occurs
** 12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an integer number of MPU E-clock
cycles (n) until an interrupt is recognized. Finally, two additional cycles are used to fetch the appropriate interrupt vector (14 + n total).
Operands
dd = 8-bit direct address ($0000–$00FF) (high byte assumed to be $00)
ff = 8-bit positive offset $00 (0) to $FF (255) (is added to index)
hh = High-order byte of 16-bit extende d address
ii = One byte of immediate data
jj = High-order byte of 16-bit immediate data
kk = Low-order byte of 16-bit immediate data
ll = Low-order byte of 16-bit extended address
mm = 8-bit mask (set bits to be affected)
rr = Signed relative offset $80 (–128) to $7F (+127)
(offset relative to address fo llowing machine code offset byte)
Operators
( ) Contents of register shown inside parentheses
⇐Is transferred t o
⇑Is pulled from stack
⇓Is pushed onto stack
• Boolean AND
+ Arithmetic addition symbol except where used as inclusive-OR symbol
in Boolean formula
⊕Exclusive-OR
∗Multiply
: Concatenation
– Arithmetic subtraction symbol or negation symbol (two’s complement)
Condition Codes
— Bit not changed
0 Bit always cleared
1 Bit always set
∆Bit cleared or set, depending on opera tion
↓Bit can be cleared, cannot become set
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 51
Data Sheet — MC68HC711D3
Section 4. Resets, Interrupts, and Low-Power Modes
4.1 Introduction
This section describes the internal and external resets and interrupts of the
MC68HC711D3 and its two low power-consumption modes.
4.2 Resets
The microcontroller unit (MCU) can be reset in any of these four ways:
1. An active-low input to the RESET pin
2. A power-on reset (POR) function
3. A clock monitor failure
4. A computer operating properly (COP) watchdog timer timeout
The RESET input consists mainly of a Schmitt trigger that senses the RESET line
logic level.
4.2.1 RESET Pin
To request an external reset, the RESET pin must be held low for at least eight
E-clock cycles, or for one E-clock cycle if no distinction is needed between int ernal
and external resets.
4.2.2 Power-On Reset (POR)
Power-on reset occurs when a positive transition is detected on V DD. This reset is
used strictly for power turn on conditions and should not be used to detect any drop
in the power supply voltage. If the external RESET pin is low at the end of the
power-on delay time, the processor remains in the reset condition until RESET
goes high.
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
52 Resets, Interrupts , and Low-Power Modes MOTOROLA
4.2.3 Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out unless it is
serviced within a specific time by a progra m reset sequence. If the COP watchdog
timer is allowed to timeout, a reset is generated, which drives the RESET pin low
to reset the MCU and the external system.
In the MC68HC711D3, the COP reset function is enabled out of reset in normal
modes. If the user does not want the COP enabled, he must write a 1 to the
NOCOP bit of the configuration control register (CONFIG) after reset. This bit is
writable only once after reset in normal mod es (see 2.3.3 Co nfiguration Contro l
Register for more information). Protected control bits (CR1 and CR0) in the
configuration options register (OPTION) allow the user to select one of the four
COP timeout rates. Table 4-1 shows the relationship between CR1 and CR0 and
the COP timeout period for various system clock frequencies.
The sequence for resetting the watchdog timer is:
1. Write $55 to the COP reset register (COPRST) to arm the COP timer
clearing mechanism.
2. Write $AA to the COPRST register to clear the COP timer
Both writes must occur in this sequence prior to the timeout, but any number of
instructions can be executed between the two writes.
Table 4-1. COP Time Out Periods
CR0 CR1 E ÷ 215
Divided
By
XTAL = 223
Time Out
–0/+15.6 ms
XTAL =
8.0 MHz
Time Out
–0/+16.4 ms
XTAL =
4.9152 MHz
Time Out
–0/+26.7 ms
XTAL =
4.0 MHz
Time Out
–0/+32.8 ms
XTAL =
3.6864 MHz
Time Out
–0/+35.6 ms
0 0 1 15.625 ms 16.384 ms 26.667 ms 32.768 ms 35.556 ms
0 1 4 62.5 ms 65.536 ms 106.67 ms 131.07 ms 142.22 ms
1 0 16 250 ms 262.14 ms 426.67 ms 524.29 ms 568.89 ms
1 1 64 1 sec 1.049 sec 1.707 sec 2.1 sec 2.276 ms
E = 2.1 MHz 2.0 MHz 1.2288 MHz 1.0 MHz 921.6 kHz
Address: $003A
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:00000000
Figure 4-1. Arm/Reset COP Timer Circuitry Register (COPRST)
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Resets, Interrupts, and Low-Power Modes
Resets
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 53
4.2.4 Clock Mo nitor Reset
The MCU contains a clock monitor circuit that measures the E-clock freque ncy. If
the E-clock input rate is above approximately 200 kHz, then the clock monitor does
not generate an MCU reset. If the E-clock signal is lost or its frequency falls b elow
10 kHz, then an MCU reset can be generate d, and the RESET pin is driven low to
reset the external system.
4.2.5 System Configuration Options Register
The system configuration options register (OPTION) is a specia l-purpose register
with several time-protected bits. OPTION is used during initialization to configure
internal system options.
Bits 5, 4, 2, 1, and 0 can be written only once during the first 64 E-clock cycles after
reset in normal modes (where the HPRIO register bit (SMOD) is cleared). In special
modes (where SMOD = 1), the bits can be written at an y time. Bit 3 can be written
at anytime.
Bits 7, 6, and 2 — Not implemented
Always read 0.
IRQE — IRQ Edge/Level Sensitivity Select
This bit can be written only once during the first 64 E-clock cycles after reset in
normal modes.
1 = IRQ is configured to respond only to falling edges.
0 = IRQ is configured for low-level wired-OR operation.
DLY — Stop Mode Exit Turnon Delay
This bit is set during reset and can be written only once during the first 64
E-clock cycles after reset in normal modes. If an external clock source rather
than a crystal is used, the stabilization delay can be inhibited because the clock
source is assumed to be stable.
1 = A stabilization delay of 4064 E-clock cycles is imposed before processing
resumes after a stop mode wakeup.
0 = No stabilization delay is imposed after story recovery.
CME — Clock Monitor Enable
1 = Clock monitor circuit is enabled.
0 = Clock monitor circuit is disabled.
Address: $0039
Bit 7654321Bit 0
Read:
0 0 IRQE DLY CME 0 CR1 CR0
Write:
Reset:00010000
Figure 4-2. System Configuration Options Register (OPTION)
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
54 Resets, Interrupts , and Low-Power Modes MOTOROLA
CR1 and CR0 — COP Timer Rate Selects
The COP system is driven by a constant frequency of E ÷ 215. These two bits
specify an additional divide-by value to arrive at the COP timeout rate. These
bits are cleared during reset and can be written only once during the first 64
E-clock cycles after reset in normal modes. The value of these bits is:
4.3 Interrupts
Excluding reset-type interrupts, there are 17 hardware interrupts and one software
interrupt that can be g enerated from all the possible sources. These interrupts can
be divided into two categories: maskable and non-maskable. Fifteen of the
interrupts can be masked using the I bit of the condition code register (CCR). All
the on-chip (hardware) interrupts are individually maskable by local control bits.
The software interrupt is non-maskable. The external input to the XIRQ pin is
considered a non-maskable interrupt because it cannot be masked by software
once it is enabled. However, it is masked during reset and upon receipt of an
interrupt at the XIRQ pin. Illegal opcode is also a non-maskable interrupt.
Table 4-2 provides a list of the interrupts with a vector location in memory for each,
as well as the actual condition code and control bits that mask each interrupt.
Figure 4-3 shows the interrupt stacking order.
CR1 CR0 E ÷ 215
Divided By
00 1
01 4
10 16
11 64
Table 4-2. Interrupt and Reset Vector Assignments
Vector
Address Interrupt Source CCR
Mask Local
Mask
$FFC0, $FFC1
↓
$FFD4, $FFD5 Reserved — —
$FFD6, $FFD7
SCI serial system:
• SCI transmit complete
• SCI transmit data register empty
• SCI idle line detect
• SCI receiver overrun
• SCI receive data register full
I bit
TCIE
TIE
ILIE
RIE
RIE
$FFD8, $FFD9 SPI serial transfer complete I bit SPIE
$FFDA, $FFDB Pulse accumulator input edge I bit PAII
$FFDC, $FFDD Pulse accumulator overflow I bit PAOVI
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Resets, Interrupts, and Low-Power Modes
Interrupts
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 55
Figure 4-3. Interrupt Stacking Order
$FFDE, $FFDF Timer overflow I bit TOI
$FFE0, $FFE1 Timer input capture 4/output compare 5 I bit I4/O5I
$FFE2, $FFE3 Timer output compare 4 I bit O C4I
$FFE4, $FFE5 Timer output compare 3 I bit O C3I
$FFE6, $FFE7 Timer output compare 2 I bit O C2I
$FFE8, $FFE9 Timer output compare 1 I bit O C1I
$FFEA, $FFEB Timer in put capture 3 I bit IC3I
$FFEC, $FFED Timer input capture 2 I bit IC2I
$FFEE, $FFEF Timer input capture 1 I bit IC1I
$FFF0, $FFF1 Real time interrupt I bit RTII
$FFF2, $FFF3 IRQ (external pin) I bit None
$FFF4, $FFF5 XIRQ pin (pseudo non-maskable) X bit None
$FFF6, $FFF7 Softw are interrupt None None
$FFF8, $FFF9 Illegal opcode trap None None
$FFFA, $FFFB COP failure (reset) None NOCOP
$FFFC, $FFFD Clock monitor fail (reset) None CME
$FFFE, $FFFF RESET None None
STACK
SP PCL — SP BEFORE INTERRUPT
SP – 1 PCH
SP – 2 IYL
SP – 3 IYH
SP – 4 IXL
SP – 5 IXH
SP – 6 ACCA
SP – 7 ACCB
SP – 8 CCR
SP – 9 — SP AFTER INTERRUPT
Table 4-2. Interrupt and Reset Vector Assignments (Continued)
Vector
Address Interrupt Source CCR
Mask Local
Mask
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
56 Resets, Interrupts , and Low-Power Modes MOTOROLA
4.3.1 Software Interrupt (SWI)
The SWI is executed the same as any other instruction and takes precedence over
interrupts only if the other interrupts are masked (with I and X bits in the CCR set).
SWI execution is similar to that of the maskable interrupts in that it sets the I bit,
stacks the central processor unit (CPU) registers, etc.
NOTE: The SWI instruction cannot be executed as long as another interrupt is pending.
However, once the SWI instruction has begun, no other interrupt can be honored
until the first instruction in the SWI service routine is completed.
4.3.2 Illegal Opcode Trap
Since not all possible opcodes or opcode sequences are defined, an illegal opcode
detection circuit has been included in the MCU. When an illegal opcode is
detected, an interrupt is required to the illegal opcode vector. The illegal opcode
vector should never be left uninitialized.
4.3.3 Real-Time Interrupt (RTI)
The real-time interrupt (RTI) provides a programmable periodic interrupt. This
interrupt is maskable by either the I bit in the CCR or the RTI enable (RTII) bit of
the timer interrupt mask register 2 (TMSK2). The rate is based on the MCU E clock
and is software selectable to the E ÷ 213, E ÷214, E ÷ 215, or E ÷ 216. See PACTL,
TMSK2, and TFLG2 register description s in Section 8. Programmable Timer for
control and status bit information.
4.3.4 Interrupt Mask Bits in the CCR
Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable
interrupts and XIRQ. After minimum system initia lization, software may clear the X
bit by a TAP instruction, thus enabling XIRQ interrupts. Thereafter software cannot
set the X bit. So, an XIRQ interrupt is effectively a non-maskable interrupt. Since
the operation of the I bit related interrupt structure has no effect on the X bit, the
internal XIRQ pin remains effectively non-masked. In the interrupt priority logic, the
XIRQ interrupt is a higher priority than any source that is maskable by the I bit. All
I bit related interrupts operate normally with their own priority relationship.
When an I bit related interrupt occurs, the I bit is automatically set by hardware after
stacking the CCR byte. The X bit is not affected. When an X bit related interrupt
occurs, both the X and the I bit are automatically set by hardware after stacking the
CCR. A return-from-interrupt (RTI) instruction restores the X and I bits to their
preinterrupt request state.
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Resets, Interrupts, and Low-Power Modes
Interrupts
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 57
4.3.5 Priority Structure
Interrupts obey a fixed hardware priority circuit to resolve simultaneous requests.
However one I bit related interrupt source may be elevated to the highest I bit
priority in the resolution circuit.
Six interrupt sources are not maske d by t he I bit in the CCR and have these fixed
priority relationships:
1. Reset
2. Clock monitor failure
3. COP failure
4. Illegal opcode
5. SWI
6. XIRQ
SWI is actually an instruction and has highest priority, other than resets, in that
once the SWI opcode is fetched, no other interrupt can be honored until the SWI
vector has been fetched.
Each of the previous sources is an input to the priority resolution circuit. The
highest I bit masked priority input to the resolution circuit is assigned to be
connected to any one of the remaining I bit related interrupt sources. This
assignment is made under the software control of the HPRIO register. To avoid
timing races, the HPRIO register can be written only while the I bit related interrupts
are inhibited (I bit of CCR is logic 1). An interrupt that is assigned to this higher
priority position is still subject to masking by any associated control bits or by the I
bit in the CCR. The interrupt vector address is not affected by assigning a source
to the higher priority position.
Figure 4-4, Figure 4-5, and Figure 4-6 illustrate the interrupt process as it relates
to normal processing. Figure 4-4 shows how the CPU begins from a reset, and
how interrupt detection relates to normal opcode fetches. Figure 4-5 is an
expansion of a block in Figure 4-4 and shows how interrupt priority is resolved.
Figure 4-6 is a n expansion of the SCI interrupt block of Figure 4-4 and shows the
resolution of interrupt sources within the SCI subsystem.
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
58 Resets, Interrupts , and Low-Power Modes MOTOROLA
Figure 4-4. Processing Flow Out of Reset (Sheet 1 of 2)
2A
BIT X IN
Y
N
XIRQ Y
N
PIN LOW?
CCR = 1?
BEGIN INSTRUCTION
SEQUENCE
1A
STACK CPU
REGISTERS
SET BITS I AND X
FETCH VECTOR
$FFF4, $FFF5
SET BITS S, I, AND X
RESET MCU
HARDWARE
POWER-ON RESET
(POR)
EXTERNAL RESET
CLOCK MONITOR FAIL
(WITH CME = 1)
COP WATCHDOG
TIMEOUT
(WITH NOCOP = 0)
DELAY 4064 E CYCLES
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFE, $FFFF
(VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFC, $FFFD
(VECTOR FETCH)
LOAD PROGRAM COUNTER
WITH CONTENTS OF
$FFFA, $FFFB
(VECTOR FETCH)
HIGHEST
PRIORITY
LOWEST
PRIORITY
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Resets, Interrupts, and Low-Power Modes
Interrupts
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 59
Figure 6-3. Processing Flow Out of Reset (Sheet 2 of 2)
I BIT IN
CCR SET?
2A
Y
N
ANY I-BIT
INTERRUPT Y
N
PENDING?
FETCH OPCODE
ILLEGAL
OPCODE?
N
Y
WAI Y
N
INSTRUCTION?
SWI
INSTRUCTION?
Y
N
RTI
INSTRUCTION?
Y
N
EXECUTE THIS
INSTRUCTION
STACK CPU
REGISTERS
N
Y
INTERRUPT
YET?
SET I BIT
STACK CPU
REGISTERS
SET I BIT
FETCH VECTOR
$FFF8, $FFF9
STACK CPU
REGISTERS
FETCH VECTOR
$FFF6, $FFF7
RESTORE CPU
REGISTERS
FROM STACK
1A
STACK CPU
REGISTERS
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
SEE Figure 4-5
SET I BIT
START NEXT
INSTRUCTION
SEQUENCE
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
60 Resets, Interrupts , and Low-Power Modes MOTOROLA
Figure 4-5. Interrupt Priority Resolution (Sheet 1 of 2)
2A
BEGIN
SET X BIT
FETCH VECTOR
$FFF4, $FFF5
X BIT
IN CCR
SET ?
Y
N
XIRQ PIN
LOW ?
Y
N
HIGHEST
PRIORITY
INTERRUPT
?
Y
N
IRQ ? Y
N
FETCH VECTOR
$FFF2, $FFF3
FETCH VECTOR
$FFF0, $FFF1
RTII = 1 ? Y
N
REAL-TIME
INTERRUPT
?
Y
N
FETCH VECTOR
$FFEE, $FFEF
IC1I = 1 ?
Y
N
TIMER
IC1F ?
Y
N
FETCH VECTOR
$FFEC, $FFED
IC2I = 1 ?
Y
N
TIMER
IC2F ?
Y
N
FETCH VECTOR
$FFEA, $FFEB
IC3I = 1 ?
Y
N
TIMER
IC3F ?
Y
N
FETCH VECTOR
$FFE8, $FFE9
OC1I = 1 ?
Y
N
TIMER
OC1F ?
Y
N
2B
FETCH VECTOR
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Resets, Interrupts, and Low-Power Modes
Interrupts
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 61
Figure 5-6. Interrupt Priority Resolution (Sheet 2 of 2)
TOI = 1?
Y
N
Y
N
PAOVI = 1?
PAII = 1?
Y
N
SPIE = 1?
Y
N
Y
N
FLAG Y
N
Y
N
FLAG
FLAG Y
N
FLAGS Y
N
PAIF = 1?
SPIF = 1? OR
TOF = 1?
PAOVF = 1
FETCH VECTOR
$FFDE, $FFDF
FETCH VECTOR
$FFDC, $FFDD
FETCH VECTOR
$FFDA, $FFDB
FETCH VECTOR
$FFD6, $FFD7
FETCH VECTOR
$FFD8, $FFD9
OC2I = 1?
Y
N
Y
N
OC3I = 1?
OC4I = 1?
Y
N
OC5I = 1?
Y
N
FLAG Y
N
Y
N
FLAG
FLAG Y
N
FLAG Y
N
OC4F = 1?
OC5F = 1?
OC2F = 1?
OC3F = 1
FETCH VECTOR
$FFE6, $FFE7
FETCH VECTOR
$FFE4, $FFE5
FETCH VECTOR
$FFE2, $FFE3
FETCH VECTOR
$FFE0, $FFE1
MODF = 1?
2A 2B
END
FETCH VECTOR
$FFF2, $FFF3
SCI
INTERRUPT?
SEE Figure 4-6
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
62 Resets, Interrupts , and Low-Power Modes MOTOROLA
Figure 4-6. Interrupt Source Resolution within SCI
FLAG Y
N
OR = 1? Y
N
Y
N
TDRE = 1?
TC = 1?
Y
N
IDLE = 1?
Y
N
Y
N
Y
N
Y
N
ILIE = 1?
RIE = 1?
TIE = 1?
BEGIN
RE = 1? Y
N
Y
N
TE = 1?
TCIE = 1?
Y
N
RE = 1?
Y
N
RDRF = 1?
NO
VALID SCI REQUEST
YES
VALID SCI REQUEST
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Resets, Interrupts, and Low-Power Modes
Interrupts
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 63
4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO)
Four bits of this register (PSEL3–PSEL0) are used to select one of the I bit related
interrupt sources and to elevate it to the highest I bit masked position of the priority
resolution circuit. In addition, four miscellaneous system control bits are included
in this register.
RBOOT — Read Bootstrap ROM
This bit can be read at any ti me. It can be written only in special modes
(SMOD = 1). In special bootstrap mode, it is set during reset. Reset clears it in
all other modes.
1 = Bootloader ROM is enabled in the memory map at $BF00–$BFFF.
0 = Bootloader ROM is disabled and is not in the memory map.
SMOD and MDA — Special Mode Select and Mode Select A
These two bits can be read at any time.These bits reflect the status of the MODA
and MODB input pins at the rising edge of reset. SMOD may be written only in
special modes. It cannot be written to a 1 after bein g cleared without an interim
reset. MDA may be written at any time in special modes, but only once in normal
modes. An interpretation of the values of these two bits is shown in Table 4-3.
Address: $003C
Bit 7654321Bit 0
Read:
RBOOT
SMOD
MDA IRVNE PSEL3 PSEL2 PSEL1 PSEL0
Write:
Reset: Note 1 0101
1. The values of the RBOOT, SMOD, IRVNE, and MDA bits at reset depend on the
mode during initialization. Refer to Table 4-3.
Figure 4-7. Highest Priority I-Bit Interrupt
and Miscellaneous Register (HPRIO)
Table 4-3. Hardware Mode Select Summary
Inputs Mode Latched at Reset
MODB MODA SMOD MDA
10 Single chip 00
1 1 Expanded multiplexed 0 1
0 0 Special bootstrap 1 0
0 1 Special test 1 1
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
64 Resets, Interrupts , and Low-Power Modes MOTOROLA
IRVNE — Internal Read Visibility/Not E
This bit may be read at any time. It may be written once in any mode. IRVNE is
set during reset in special test mode only, and cleared by reset in the other
modes.
1 = Data from internal reads is driven out on the external data bus in
expanded modes.
0 = Data from internal reads is not visible on the external data bus.
As shown in the table, in single-chip and bootstrap modes IRVNE determines
whether the E clock is driven out or forced low.
1 = E pin driven low
0 = E clock driven out of the chip
NOTE: To prevent bus conflicts, when using internal read visibility, the user must disable
all external devices from driving the data bus during any internal access.
PSEL3–PSEL0 — Priority Selects
These four bits are used to specify one I bit related interrupt source, which then
becomes the highest priority I bit related interrupt source. These bits may be
written only while the I bit in the CCR is set, inhibiting I bit related interrupts. An
interpretation of the value of these bits is shown in Table 4-4.
During reset, PSEL3–PSEL0 are initialized to 0101, which corresponds to
reserved (default to IRQ). IRQ becomes the highest priority I bit related interrupt
source.
Mode IRVNE
Out
of Reset
E Clock
Out
of Reset
IRV
Out
of Reset
IRVNE
Affects
Only
IRVNE
May
be Written
Single chip 0 On Off E Once
Expanded multiplexed 0 On Off IR V Once
Bootstrap 0 On Off E Once
Special test 1 On On IRV Once
Table 4-4. Highest Priority Interrupt Selection
PSEL3–PSEL0 Interrupt Source Promoted
0 0 0 0 Timer overflow
0 0 0 1 Pulse accumulator overflow
0 0 1 0 Pulse accumulator input edge
0 0 1 1 SPI serial transfer complete
0 1 0 0 SCI serial system
0 1 0 1 Reserved (default to IRQ)
0 1 1 0 IRQ (external pin)
0 1 1 1 Real-time interrupt
1 0 0 0 Timer input capture 1
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Resets, Interrupts, and Low-Power Modes
Low-Power Operation
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Resets, Interrupts, and Low-Power Modes 65
4.4 Low-Power Operation
The M68HC11 Family of microcontroller units (MCU) has two programmable low
power-consumption modes: stop and wait. In the wait mode, the on-chip oscillator
remains active. In the stop mode, the oscillator is stopped. This subsection
describes these two low power-consumption modes.
4.4.1 Stop Mode
The STOP instruction places the MCU in its lowest power-consumption mode,
provided the S bit in the CCR is cleared. In this mode, all clocks are stopped,
thereby halting all internal processing.
To exit the stop mode, a low level must be applied to either the IRQ, XIRQ, or
RESET pin. An external interrupt used at IRQ is only effective if the I bit in the CCR
is cleared. An external interrupt applied at the XIRQ input is effective, regardless
of the setting of the X bit of the CCR. However, the actual recovery sequence
differs, depending on the X bit setting. If the X bit is cleared, the MCU starts with
the stacking sequence leading to the normal service of th e XIRQ re quest. If the X
bit is set, the processing always continues with the instruction immediately
following the STOP instruction. A low input to the RESET pin a lways results in a n
exit from the stop mode, and the start of MCU operations is determined by the reset
vector.
The CPU will not exit stop mode correctly when interrupted by IRQ or XIRQ if the
instruction preceding STOP is a column 4 or 5 accumulator inherent (opcodes $4X
and $5X) instruction, such as NEGA, NEGB, COMA, COMB, etc. These
single-byte, two-cycle instructions must be followed by an NOP, then the STOP
command. If reset is used to exit stop mode, the CPU will respond properly.
A restart delay is required if the internal oscillator is being used. The delay allows
the oscillator to stabilize wh en exiting the stop mode . If a stable external oscillato r
is being used, the delay (DLY) bit in the OPTION register can be cleared to bypass
the delay. If the DLY bit is clear, the RESET pin would not normally be used to exit
the stop mode. The reset sequence sets the DLY bit, and the restart delay would
be reimposed.
1 0 0 1 Timer input capture 2
1 0 1 0 Timer input capture 3
1 0 1 1 Timer output compare 1
1 1 0 0 Timer output compare 2
1 1 0 1 Timer output compare 3
1 1 1 0 Timer output compare 4
1 1 1 1 Timer input capture 4/output compare 5
Table 4-4. Highest Priority Interrupt Selection (Continued)
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Resets, Interrupts, and Low-Power Modes
Data Sheet MC68HC711D3 — Rev. 2
66 Resets, Interrupts , and Low-Power Modes MOTOROLA
4.4.2 Wait Mode
The wait (WAI) instruction places the MCU in a low power-consumption mode. The
wait mode consumes more power than the stop mode since the oscillator is kept
running. Upon execution of the WAI instruction, the machine state is stacked and
program execution stops.
The wait state can be exited only by an unmasked interrupt or RESET. If the I bit
of the CCR is set and the COP is disabled, the timer system is turned off by WAI
to further reduce power consumption. Th e amount of power savings is application
dependent. It also depends upon the circuitry connected to the MCU pins, and
upon subsystems such as the timer, serial peripheral interface (SPI), or serial
communications interface (SCI) that were or were not active when the wait mode
was entered.
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Input/Output (I/O) Ports 67
Data Sheet — MC68HC711D3
Section 5. Input/Output (I/O) Ports
5.1 Introduction
The MC68HC711D3 has four 8-bit input/output (I/O) ports; A, B, C, and D. In the
40-pin version, port A bits 4 and 6 are n ot bonded. Port functions are controlled by
the particular mode of operation selected, as shown in Table 1-1. Port Signal
Functions.
In the single-chip and bootstrap modes, all the ports are configured as parallel
input/output (I/O) data ports. In expanded multiplexed and t est modes, ports B, C,
and lines D6 (AS) and D7 ( R/W) are configured as a memory expansion bus, with:
• Port B as the high-order address bus
• Port C as the multiplexed address and data bus
• AS as the demultiplexing signal
•R/W
as data bus direction control
The remaining ports are unaffected by mode changes.
• Ports A and D can be used as gene ral-pu rpose I/O ports, th ough each has
an alternate function.
• Port A bits handle the timer functions.
• Port D handles serial peripheral interface (SPI) and serial communications
interface (SCI) functions in addition to its bus direction control functions.
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Input/Output (I/O) Port s
Data Sheet MC68HC711D3 — Rev. 2
68 Input/Output (I/O) Ports MOTOROLA
5.2 Port A
Port A shares functions with the timer system and has:
• Three input only pins
• Three output only pins
• Two bidirectional I/O pins
Pins PA6 and PA4 are not bonded in the 40-pin dual in-line package (DIP), and
their OC output functions are unavailable, but their software interrupts are
available.
PORTA can be read any time. Inputs return the pin level, whereas outputs return
the pin driver input level. If written, PORTA stores the data in an internal latch. It
drives the pins only if they are configured as outputs. Writes to PORTA do not
change the pin state when the pins are configured for timer output compares.
Out of reset, port A bits 7 and 3–0 are general high-impedance inputs, while
bits 6–4 are outputs, driving low. On bidirectional lines PA7 and PA3, the timer
forces the I/O state to be an output if the associated output compare is enabled. In
this case, the data direction bits DDRA7 and DDRA3 in PACTL will not be changed
or have any effect on those bits. When the output compare functions associated
with these pins are disabled, the DDR bits in PACTL govern the I/O state.
Address: $0000
Bit 7654321Bit 0
Read:
PA7 PA6(1) PA5 PA4(1) PA3 PA2 PA1 PA0
Write:
Reset: Hi-Z 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z
Alt. Func.:
And/Or:
PAI
OC1
OC2
OC1
OC3
OC1
OC4
OC1
IC4/OC5
OC1
IC1
—
IC2
—
IC3
—
1. This pin is not bonded in the 40-pin version.
Figure 5-1. Port A Data Register (PORTA)
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Input/Output (I/O) Ports
Port B
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Input/Output (I/O) Ports 69
5.3 Port B Port B is an 8-bit, general-purpose I/O port with a data register (PORTB) and a data
direction register (DDRB).
• In the single-chip mode, port B pins are general-purpose I/O pins
(PB7–PB0).
• In the expanded-multiplexed mode, all of the port B pins act as the
high-order address bits (A15–A8) of the address bus.
5.3.1 Port B Data Register
PORTB can be read at any time. Inputs return the sensed levels at the pin, while
outputs return the input le vel of the port B pin drivers. If PORTB is written, the data
is stored in an internal latch and can be driven only if port B is configured for
general-purpose outputs in single-chip or bootstrap mode.
Port B pins are general--purpose inputs out of reset in single-chip and bootstrap
modes. These pins are outputs (the high-order address bits) out of reset in
expanded multiplexed and test modes.
5.3.2 Port B Data Direction Register
DDB7–DDB0 — Data Direction Bits for Port B
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured for input only
Address: $0004
Bit 7654321Bit 0
Read:
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset:00000000
Alt. Func.: A15 A14 A13 A12 A11 A10 A9 A8
Figure 5-2. Port B Data Register (PORTB)
Address: $0006
Bit 7654321Bit 0
Read:
DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0
Write:
Reset:00000000
Figure 5-3. Data Direction Register for Port B (DDRB)
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Input/Output (I/O) Port s
Data Sheet MC68HC711D3 — Rev. 2
70 Input/Output (I/O) Ports MOTOROLA
5.4 Port C
Port C is an 8-bit, general-purpose I/O port with a data register (PORTC) and a data
direction register (DDRC). In the single-chip mode, port C pins are general-purpose
I/O pins (PC7–PC0). In the expanded-multiplexed mode, port C pins are configured
as multiplexed address/data pins. During the address cycle, bits 7–0 of the address
are output on PC7–PC0. During the data cycle, bits 7–0 (PC7–PC0) are
bidirectional data pins controlled by the R/W signal.
5.4.1 Port C Control Register
CWOM — Port C Wire-OR Mode Bit
1 = Port C outputs are open drain (to facilitate testing)
0 = Port C operates normally
5.4.2 Port C Data Register
PORTC can be read at any time. Inputs return the sensed levels at the pin, while
outputs return the input level of the port C pin drivers. If PORTC is written, the data
is stored in an internal latch and can be driven only if port C is configured for
general-purpose outputs in single-chip or bootstrap mode.
Port C pins are general-purpose inputs out of reset in single-chip and bootstrap
modes. These pins are multiplexed low-order address and data bus lines out of
reset in expanded-multiplexed and test modes.
Address: $0002
Bit 7654321Bit 0
Read:
00CWOM00000
Write:
Reset:00000000
Figure 5-4. Port C Control Register (PIOC)
Address: $0003
Bit 7654321Bit 0
Read:
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Write:
Reset:00000000
Figure 5-5. Port C Data Register (PORTC)
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Input/Output (I/O) Ports
Port D
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Input/Output (I/O) Ports 71
5.4.3 Port C Data Direction Register
DDC7–DDC0 — Data Direction Bits for Port C
1 = Corresponding port C pin is configured as output
0 = Corresponding port C pin is configured for input only
5.5 Port D
Port D is an 8-bit, general-purpose I/O port with a data register (PORTD) and a data
direction register (DDRD). The eight port D bits (D7–D0) can be used for
general-purpose I/O, for the serial communications interface (SCI) and serial
peripheral interface (SPI) subsystems, or for bus data direction control
5.5.1 Port D Data Register
PORTD can be read at any time and inputs return the sensed levels at the pin;
whereas, outputs return the input level of the port D pin drivers. If PORTD is written,
the data is stored in an internal latch, and can be driven only if port D is configured
as general-purpose output. This port shares functions with the on-chip SCI and SPI
subsystems, while bits 6 and 7 control the direction of data flow on the bus in
expanded and special test modes.
Address: $0007
Bit 7654321Bit 0
Read:
DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0
Write:
Reset:00000000
Figure 5-6. Data Direction Register for Port C (DDRC)
Address: $0008
Bit 7654321Bit 0
Read:
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Write:
Reset:00000000
Figure 5-7. Port D Data Register (PORTD)
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Input/Output (I/O) Port s
Data Sheet MC68HC711D3 — Rev. 2
72 Input/Output (I/O) Ports MOTOROLA
5.5.2 Port D Data Direction Register
DDD7–DDD0 — Data Direction for Port D
When port D is a general-purpose I/O port, the DDRD register controls the
direction of the I/O pins as follows:
0 = Configures the corresponding port D pin for input only
1 = Configures the corresponding port D pin for output
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as
the slave select (SS) input. In SPI slave mode, DDD5 has no meaning or effect.
In SPI master mode, DDD5 affects port D bit 5 as follows:
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK)
to be inputs, then they are inputs, regardless of the state of DDRD bits 2, 3,
and 4. If the SPI expects port D bits 2, 3, and 4 to be outputs, they are outputs
only if DDRD bits 2, 3, and 4 are set.
Address: $0009
Bit 7654321Bit 0
Read:
DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
Write:
Reset:00000000
Figure 5-8. Data Direction Register for Port D (DDRD)
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Communications Interface (SCI) 73
Data Sheet — MC68HC711D3
Section 6. Serial Communications Interface (SCI)
6.1 Introduction
The serial communications interface (SCI) is a universal asynchronous receiver
transmitter (UART), one of two independent serial input/output (I/O) subsystems in
the MC68HC711D3. It has a sta ndard non-return to zero (NRZ) format (one start,
eight or nine data, and one stop bit). Several baud rates are available. The SCI
transmitter and receiver are independent, but us e the same data format and bit
rate.
6.2 Data Format
The serial data format requires these conditions:
• An idle line in the high state before transmission or reception of a message
• A start bit, logic 0, transmitted or received, that indicates the start of each
character
• Data that is transmitted and received least significant bit (LSB) first
• A stop bit, logic 1, used to indicate the end of a frame. A frame consists of a
start bit, a character of eight or nine data bits, and a stop bit.
• A break, defined as the transmission or reception of a logic 0 for some
multiple number of frames
Selection of the word length is controlled by the M bit in the SCI control register 1
(SCCR1).
6.3 Transmit Operation
The SCI transmitter includes a parallel transmit data register (SCDR) and a serial
shift register that puts data from the SCDR into serial form. The contents of the
serial shift register can only be written through the SCDR. This double-buffered
operation allows a character to be shifted out serially while another character is
waiting in the SCDR to be transferred into the serial shift register. The output of the
serial shift register is applied to PD1 as long as transmission is in progress or the
transmit enable (TE) bit of serial communication control register 2 (SCCR2) is set.
The block diagram, Figure 6-1, shows the transmit serial shift register and the
buffer logic at the top of the figure.
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Serial Communications Interface (SCI)
Data Sheet MC68HC711D3 — Rev. 2
74 Serial Communications Interface (SCI) MOTOROLA
Figure 6-1. SCI Transmitter Block Diagram
FE
NF
OR
IDLE
RDRF
TC
TDRE
SCSR INTERRUPT STATUS
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
SCCR2 SCI CONTROL 2
TRANSMITTER
CONTROL LOGIC
TCIE
TC
TIE
TDRE
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
PIN BUFFER
AND CONTROL
H(8)76543210L
10 (11) - BIT Tx SHIFT REGISTER
DDD1
PD1
TxD
SCDR Tx BUFFER
TRANSFER Tx BUFFER
SHIFT ENABLE
JAM ENABLE
PREAMBLE—JAM 1s
BREAK—JAM 0s
(WRITE ONLY)
FORCE PIN
DIRECTION (OUT)
SIZE 8/9
WAKE
M
T8
R8
SCCR1 SCI CONTROL 1
TRANSMITTER
BAUD RATE
CLOCK
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Serial Communications Interface (SCI)
Receive Operation
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Communications Interface (SCI) 75
6.4 Receive Operation
During receive operations, the transmit sequence is reversed. The serial shift
register receives data and transfers it to a parallel receive dat a register (SCDR) as
a complete word. Refer to Figure 6-2. This double-buffered operation allows a
character to be shifted in serially while another character is already in the SCDR.
An advanced data recovery scheme distinguishes valid data from noise in the
serial data stream. The data input is selectively sampled to detect receive data, and
a majority voting circuit determines the value and integrity of each bit.
6.5 Wakeup Feature
The wakeup feature reduces SCI service overhead in multiple receiver systems.
Software for each receiver evaluates the first character of each message. The
receiver is placed in wakeup mode by writing a 1 to the RWU bit in the SCCR2
register. While RWU is 1, all of the receiver-related status flags (RDRF, IDLE, OR,
NF, and FE) are inhibited (cannot become set). Although RWU ca n be cleared by
a software write to SCCR2, to do so would be unusual. Normally, RWU is set by
software and is cleared automatically with hardware. Whenever a new message
begins, logic alerts the sleeping receivers to wake up and evaluate the initial
character of the new message.
Two methods of wakeup are available:
• Idle line wakeup
• Address mark wakeup
During idle line wakeup, a sleeping receiver awakens as soon as the RxD line
becomes idle. In the address mark wakeup, logic 1 in the most significant bit (MSB)
of a character wakes up all sleeping receivers.
6.5.1 Idle-Line Wakeup
To use the receiver wakeup method, establish a software addressing scheme to
allow the transmitting devices to direct a message to individual receivers or to
groups of receivers. This addressing scheme can take any form as long as all
transmitting and receiving devices are programmed to understand the same
scheme. Because the addressing information is usually the first frame(s) in a
message, receivers that are not part of the current task do not become burdened
with the entire set of addressing frames. All receivers are awake (RWU = 0) when
each message begins. As soon as a receiver determines that the message is not
intended for it, software sets the RWU bit (RWU = 1), which inhibits further flag
setting until the RxD line goes idle at the end of the message. As soon as an idle
line is detected by receiver logic, hardware automatically clears the RWU bit so that
the first frame of the next message can be rece ived. This type of rece iver wakeup
requires a minimum of one idle-line frame time between messages and no idle time
between frames in a message.
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Serial Communications Interface (SCI)
Data Sheet MC68HC711D3 — Rev. 2
76 Serial Communications Interface (SCI) MOTOROLA
Figure 6-2. SCI Receiver Block Diagram
FE
NF
OR
IDLE
RDRF
TC
TDRE
SCSR SCI STATUS 1
SBK
RWU
RE
TE
ILIE
RIE
TCIE
TIE
SCCR2 SCI CONTROL 2
WAKE
M
T8
R8
WAKEUP
LOGIC
RIE
OR
ILIE
IDLE
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST INTERNAL
DATA BUS
PIN BUFFER
AND CONTROL
DDD0
PD0
RxD
SCDR Rx BUFFER
STOP
(8)76543210
10 (11) - BIT
Rx SHIFT REGISTER
(READ ONLY)
SCCR1 SCI CONTROL 1
RIE
RDRF
START
MSB ALL 1s
DATA
RECOVERY
÷16
RWU
RE
M
DISABLE
DRIVER
16X
BAUD RATE
CLOCK
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Serial Communications Interface (SCI)
SCI Error Detection
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Communications Interface (SCI) 77
6.5.2 Address-Mark Wakeup
The serial characters in this type of wakeup consist of seven (eight if M = 1)
information bits and an MSB, which indicates an address character (when set
to 1 — mark). The first character of each message is an addressing character
(MSB = 1). All receivers in the system evaluate this character to determine if the
remainder of the message is directed toward this particular receiver. As soon as a
receiver determines that a message is not intended for it, the receiver activates the
RWU function by using a software write to set t he RWU bit. Because setting RWU
inhibits receiver-related flags, there is no further software overhead for the rest of
this message. When the next message begin s, its f irst chara cter has its MSB se t,
which automatically clears the RWU bit and enables normal character reception.
The first character whose MSB is set is also the first character to be received after
wakeup because RWU gets cleared before the stop bit for that frame is serially
received. This type of wakeup allows messages t o include gaps of idle time, unlike
the idle-line method, but there is a loss of efficiency because of the extra bit time
for each character (address bi t) required for all characters.
6.6 SCI Error Detection
Three error conditions can occur during generation of SCI system interrupts:
• Serial communications data register (SCDR) overrun
• Received bit noise
•Framing
Three bits (OR, NF, and FE ) in the serial communications status register (SCSR)
indicate if one of these error conditions exists. The overrun error (OR) bit is set
when the next byte is ready to be transferred from the receive shift register to the
SCDR and the SCDR is already full (RDRF bit is set). When an overrun error
occurs, the data that caused the overrun is lost and the data that was already in
SCDR is not disturbed. The OR is cleared when the SCSR is read (with OR set),
followed by a read of the SCDR.
The noise flag (NF) bit is set if there is noise on any of the received bits, including
the start and stop bits. The NF bit is not set until the RDRF flag is set. The NF bit
is cleared when the SCSR is read (with FE equal to 1) followed by a read of the
SCDR.
When no stop bit is detected in the received data character, the framing error (FE)
bit is set. FE is set at the same time as the RDRF. If the byte received causes both
framing and overrun errors, the processor only recognizes the overrun error. The
framing error flag inhibits further transfer of data into the SCDR until it is cleared.
The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read
of the SCDR.
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Serial Communications Interface (SCI)
Data Sheet MC68HC711D3 — Rev. 2
78 Serial Communications Interface (SCI) MOTOROLA
6.7 SCI Registers
This subsection describes the five addressable registers in the SCI.
6.7.1 SCI Data Register
The SCI data register (SCDR) is a parallel register that performs two functions. It
is the receive data reg ister when it is read, and the transmit data register when it is
written. Reads access the receive data buffer a nd writes a ccess the transmit d ata
buffer. Receive and transmit are double buffered.
6.7.2 SCI Control Register 1
The SCI control register 1 (SCCR1) provides the control bits that determine word
length and select the method used for the wakeup feature.
R8 — Receive Data Bit 8
If M bit is set, R8 stores the ninth bit in the receive data character.
T8 — Transmit Data Bit 8
If M bit is set, T8 stores ninth bit in transmit data character.
M — Mode Bit
The mode bit selects character format
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wakeup by Address Mark/Idle Bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
Address: $002F
Bit 7654321Bit 0
Read:
R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
Write:
Reset: Unaffected by reset
Figure 6-3. SCI Data Register (SCDR)
Address: $002C
Bit 7654321Bit 0
Read:
R8 T8 0 M WAKE 0 0 0
Write:
Reset:UU000000
U = Unaffected
Figure 6-4. SCI Control Register 1 (SCCR1)
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Serial Communications Interface (SCI)
SCI Registers
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Communications Interface (SCI) 79
6.7.3 SCI Control Register 2
The SCI control register 2 (SCCR2) provides the control bits that enable or disable
individual SCI functions.
TIE — Transmit Interrupt Enable Bit
1 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE — Transmit Complete Interrupt Enable Bit
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE — Receiver Interrupt Enable Bit
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
ILIE — Idle Line Interrupt Enable Bit
1 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE — Transmitter Enable Bit
When TE goes from 0 to 1, one unit of idle character time (logic 1) is qu eued as
a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
RE — Receiver Enable Bit
0 = Receiver disabled
1 = Receiver enabled
RWU — Receiver Wakeup Control Bit
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
SBK — Send Break Bit
At least one character time of break is queued and sent each time SBK is written
to 1. More than one break may be sent if the transmitter is idle at the time the
SBK bit is toggled on and off, as the baud rate clock edge could occur between
writing the 1 and writing the 0 to SBK.
0 = Break generator off
1 = Break codes generated as long as SBK = 1
Address: $002D
Bit 7654321Bit 0
Read:
TIE TCIE RIE ILIE TE RE RWU SBK
Write:
Reset:00000000
Figure 6-5. SCI Control Register 2 (SCCR2)
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Serial Communications Interface (SCI)
Data Sheet MC68HC711D3 — Rev. 2
80 Serial Communications Interface (SCI) MOTOROLA
6.7.4 SCI Status Register
The SCI status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt.
TDRE — Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with
TDRE set and then writing to SCDR.
0 = SCDR busy
1 = SCDR empty
TC — Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break
transmission in progress). Clear the TC flag by reading SCSR with TC set and
then writing to SCDR.
0 = Transmitter busy
1 = Transmitter idle
RDRF — Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR. Clear the
RDRF flag by reading SCSR with RDRF set and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE — Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until
the RxD line has been active and becomes idle again. The IDLE flag is inhibited
when RWU = 1. Clear IDLE by reading SCSR with IDLE set and then reading
SCDR.
0 = RxD line active
1 = RxD line idle
OR — Overrun Error Flag
OR is set if a new character is rece ive d before a previously received chara cter
is read from SCDR. Clear the OR flag by reading SCSR with OR set and then
reading SCDR.
0 = No overrun
1 = Overrun detected
Address: $002E
Bit 7654321Bit 0
Read:
TDRE TC RDRF IDLE OR NF FE 0
Write:
Reset:11000000
Figure 6-6. SCI Status Register (SCSR)
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Serial Communications Interface (SCI)
SCI Registers
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Communications Interface (SCI) 81
NF — Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous
decision. Clear NF by reading SCSR with NF set and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE — Framing Error Bit
FE is set when a 0 is detected where a stop bit was expected. Clear the FE flag
by reading SCSR with FE set and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
6.7.5 Baud Rate Register
The baud rate register (BAUD) is used to select different baud rates for the SCI
system. The SCP1 and SCP0 bits function as a prescaler for the SCR2–SCR0 bits.
Together, these five bits provide multiple baud rate combinations for a given crystal
frequency. Normally, this register is written once during initialization. The prescaler
is set to its fastest rate by default out of reset and can be changed at any time.
Refer to Table 6-1 and Table 6-2 for normal baud rate selections.
TCLR — Clear Baud Rate Counters (Test)
RCKB — SCI Baud Rate Clock Check (Test)
SCP1 and SCP0 — SCI Baud Rate Prescaler Select Bits
These two bits select a prescale factor for the SCI baud rate generator that
determines the highest possible baud rate.
Address: $002B
Bit 7654321Bit 0
Read:
TCLR 0 SCP1 SCP0 RCKB SCR2 SCR1 SCR0
Write:
Reset:00000UUU
U = Unaffected
Figure 6-7. Baud Rate Register (BAUD)
Table 6-1. Baud Rate Prescale Selects
SCP1
and SCP0
Divide
Internal Clock
By
Crystal Frequency in MHz
4.0 MHz
(Baud) 8.0 MHz
(Baud) 10.0 MHz
(Baud) 12.0 MHz
(Baud)
0 0 1 62.50 K 125.0 K 156.25 K 187.5 K
0 1 3 20.83 K 41.67 K 52.08 K 62.5 K
1 0 4 15.625 K 31.25 K 38.4 K 46.88 K
1 1 13 4800 9600 12.02 K 14.42 K
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Serial Communications Interface (SCI)
Data Sheet MC68HC711D3 — Rev. 2
82 Serial Communications Interface (SCI) MOTOROLA
SCR2–SCR0 — SCI Baud Rate Select Bits
These three bits select receiver and transmitter bit rate based on output from
baud rate prescaler stage.
The prescale bits, SCP1 and SCP0, determine the highest baud rate and
the SCR2–SCR0 bits select an additional binary submultiple (÷1, ÷2, ÷4,
through ÷128) of this highest baud rate. The result of these two dividers in series
is the 16 X receiver baud rate clock. The SCR2–SCR0 bits are not affected by
reset and can be changed at any time, although they should not be changed
when any SCI transfer is in progress.
Figure 6-8 illustrates the SCI baud rate timing chain. The prescale select bits
determine the highest baud rate. The rate select bits determine additional divide
by two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock
is the result of dividing the RT clock by 16.
Table 6-2. Baud Rate Selects
SCR2–SCR0 Divide
Prescaler
By
Highest Baud Rate
(Prescaler Output from Table 6-1)
4800 9600 38.4 K
0 0 0 1 4800 9600 38.4 K
0 0 1 2 2400 4800 19.2 K
0 1 0 4 1200 2400 9600
0 1 1 8 600 1200 4800
1 0 0 16 300 600 2400
1 0 1 32 150 300 1200
1 1 0 64 — 150 600
1 1 1 128 — — 300
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Serial Communications Interface (SCI)
Status Flags and In terrupts
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Communications Interface (SCI) 83
Figure 6-8. SCI Baud Rate Diagram
6.8 Status Flags and Interrupts
The SCI transmitter has two status flags. These status flags can be read by
software (polled) to tell when the corresponding condition ex ists. Alternatively, a
local interrupt enable bit can be set to enable each of these status conditions to
generate interrupt requests when the corresponding condition is present. Status
flags are automatically set by hardware logic conditions, but must be cleared by
software, which provides a n interlock mechanism that enables logic to know when
software has noticed the status indication. The software clearing sequence for
these flags is automatic — functions that are normally performed in response to the
status flags also satisfy the conditions of the clearing sequence.
÷3 ÷4 ÷13
OSCILLATOR
AND
CLOCK GENERATOR
(÷ 4)
XTAL
EXTAL
E
AS
INTERNAL BUS CLOCK (PH2)
1:1
SCP1 AND SCP0
1:00:10:0
÷2
0:0:0
÷2
0:0:1
÷2
0:1:0
÷2
0:1:1
÷2
1:0:0
÷2
1:0:1
÷2
1:1:0
1:1:1
÷16
SCI
RECEIVE
BAUD RATE
(16X)
SCR2–SCR0
SCI
TRANSMIT
BAUD RATE
(1X)
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Serial Communications Interface (SCI)
Data Sheet MC68HC711D3 — Rev. 2
84 Serial Communications Interface (SCI) MOTOROLA
TDRE and TC flags are normally set when the transmitter is first enabled (TE set
to 1). The TDRE flag indicates there is room in the transmit queue to store a nother
data character in the TDR. Th e TIE bit is the local interrupt mask for TDRE. When
TIE is 0, TDRE must be polled. When TIE and TDRE are 1, an interrupt is
requested.
The TC flag indicates the transmitter has completed the queue. The TCIE bit is the
local interrupt mask for TC. When TCIE is 0, TC must be polled; when TCIE is 1
and TC is 1, an interrupt is requested.
Writing a 0 to TE requests that the transmitter stop when it can. The transmitter
completes any transmission in progress before actually shutting down. Only an
MCU reset can cause the transmitter to stop and shut down immediately. If TE is
written to 0 when the transmitter is already idle, the pin reverts to its
general-purpose I/O function (synchronized to the bit-rate clock). If anything is
being transmitted when TE is written to 0, that character is completed before the
pin reverts to general-purpose I/O, but any other ch aracters waiting in the transmit
queue are lost. The TC and TDRE flags are set at the completion of this last
character, even though TE has been disabled.
The SCI receiver has five status flags, three of which can generate interrupt
requests. The status flags are set by the SCI logic in response to specific conditions
in the receiver. These flags can be read (pol led) at a ny time by software. Refe r to
Figure 6-9, which shows SCI interrupt arbitration.
When an overrun takes place, the new character is lost, and the character that was
in its way in the parallel RDR is undisturbed. RDRF is set when a character has
been received and transferred into the parallel RDR. The OR flag is set instead of
RDRF if overrun occurs. A new character is ready to be transferred into RDR
before a previous character is read from RDR.
The NF and FE flags provide additional information about the character in the RDR,
but do not generate interrupt requests.
The last receiver status flag and interrupt source come from the IDLE flag. The RxD
line is idle if it has constantly been at logic 1 for a full character time. The IDLE flag
is set only after the RxD line has been busy and becomes idle, which prevents
repeated interrupts for the whole time RxD remains idle.
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Serial Communications Interface (SCI)
Status Flags and In terrupts
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Communications Interface (SCI) 85
Figure 6-9. Interrupt Source Resolution within SCI
FLAG Y
N
OR = 1? Y
N
Y
N
TDRE = 1?
TC = 1?
Y
N
IDLE = 1?
Y
N
Y
N
Y
N
Y
N
ILIE = 1?
RIE = 1?
TIE = 1?
BEGIN
RE = 1? Y
N
Y
N
TE = 1?
TCIE = 1?
Y
N
RE = 1?
Y
N
RDRF = 1?
VALID SCI REQUEST
NO
VALID SCI REQUEST
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Serial Communications Interface (SCI)
Data Sheet MC68HC711D3 — Rev. 2
86 Serial Communications Interface (SCI) MOTOROLA
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Peripheral Interface (SPI) 87
Data Sheet — MC68HC711D3
Section 7. Serial Peripheral Interface (SPI)
7.1 Introduction
The serial peripheral interface (SPI), an independent serial communications
subsystem, allows the microcontroller unit (MCU) to communicate synchronously
with peripheral devices, such as:
• Transistor-transistor logic (TTL) shift registers
• Liquid crystal diode (LCD) display drivers
• Analog-to-digital converter (ADC) subsystems
• Other microprocessors (MCUs)
The SPI is also capable of inter-processor communication in a multiple master
system. The SPI system can be configured as either a master or a slave device
with data rates as high as one half of the E-clock rate when configur ed as master,
and as fast as the E-clock rate when configured as slave.
7.2 Functional Description
The central element in the SPI syste m is the block containing the shift register and
the read data buffer. The system is single buffered in the transmit direction and
double buffered in the receive direction. This means that new data for transmission
cannot be written to the shifter until the previous transfer is complete; however,
received data is transferred into a parallel read data buffer so the shifter is free to
accept a second serial character. As long as the first character is read out of the
read data buffer before the next serial character is ready to be transferred, no
overrun condition occurs. A single MCU register address is used for reading data
from the read data buffer, and for writing data to the shifter.
The SPI status block represents the SPI status functions (transfer complete, write
collision, and mode fault) performed by the serial peripheral status register (SPSR).
The SPI control block represents those functions that control the SPI system
through the serial peripheral control register (SPCR).
Refer to Figure 7-1, which shows the SPI block diagram.
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Serial Peripheral Interface (SPI)
Data Sheet MC68HC711D3 — Rev. 2
88 Serial Peripheral Interface (SPI) MOTOROLA
Figure 7-1. SPI Block Diagram
7.3 SPI Transfer Formats
During an SPI transfer, data is simultaneously transmitted and received. A serial
clock line synchronizes shifting and sampling of the information on the two serial
data lines. A slave select line allows individual selection of a slave SPI device;
slave devices that are not selected do not interfere with SPI bus activities. On a
master SPI device, the select line can optionally be used to indicate a multiple
master bus contention. Refer to Figure 7-2.
SPR0
SPR1
CPOL
CPHA
MSTR
DWOM
SPE
SPIE
SPI CONTROL REGISTER
MODF
WCOL
SPIF
SPI STATUS REGISTER
8-BIT SHIFT REGISTER
READ DATA BUFFER
MSB LSB
INTERNAL
DATA BUS
SPI INTERRUPT
REQUEST
MSTR
SPE
MSTR
DWOM
SPE
SPR0
SPI CLOCK (MASTER)
SPI CONTROL
SELECT
DIVIDER
PH2
(INTERNAL)
CLOCK
LOGIC
CLOCK
PIN CONTROL LOGIC
S
M
M
S
S
M
MISO
PD2
MOSI
PD3
SCK
PD4
SS
PD5
SPR1
÷2 ÷4 ÷16 ÷32
8
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Serial Peripheral Interface (SPI)
Clock Phase and Polarity Controls
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Peripheral Interface (SPI) 89
Figure 7-2. SPI Transfer Format
7.4 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity
using two bits in the SPI control register (SPCR). The clock polarity is specified by
the CPOL control bit, which selects an active high or active low clock, and has n o
significant effect on the transfer format. The clock phase (CPHA) control bit selects
one of two different transfer formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device. In some
cases, the phase and polarity are changed between transfers to allow a master
device to communicate with peripheral slaves having different requirements.
When CPHA equals 0, the slave select (SS) line must be ne gated and reasserted
between each successive serial byte. Also, if the slave writes data to the SPI data
register (SPDR) while SS is active low, a write collision error results.
When CPHA equals 1, the SS line can remain low between successive transfers.
23456781
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK CYCLE #
SS (TO SLAVE)
654321 LSBMSB
MSB654321LSB
1
2
3
5
4
SLAVE CPHA=1 TRANSFER IN PROGRESS
MASTER TRANSFER IN PROGRESS
SLAVE CPHA=0 TRANSFER IN PROGRESS
1. SS ASSERTED
2. MASTER WRITES TO SPDR
3. FIRST SCK EDGE
4. SPIF SET
5. SS NEGATED
SAMPLE INPUT
DATA OUT
(CPHA = 0)
SAMPLE INPUT
DATA OUT
(CPHA = 1)
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Serial Peripheral Interface (SPI)
Data Sheet MC68HC711D3 — Rev. 2
90 Serial Peripheral Interface (SPI) MOTOROLA
7.5 SPI Signals
This subsection contains description of the four SPI signals:
• Master in/slave out (MISO)
• Master out/slave in (MOSI)
• Serial clock (SCK)
• Slave select (SS)
7.5.1 Master In/Slave Out (MISO)
MISO is one of two unidirectional serial data signals. It is an input to a master
device and an output from a slave device. The MISO line of a slave device is placed
in the high-impedance state if the slave device is not selected.
7.5.2 Master Out/Slave In (MOSI)
The MOSI line is the second of the two unidirectional serial data signals. It is an
output from a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge that the slave
device uses to latch the data.
7.5.3 Serial Clock (SCK)
SCK, an input to a slave device, is generated by the master device and
synchronizes data movement in and out of the device through the MOSI and MISO
lines. Master and slave devices are capable of exchanging a byte of information
during a sequence of eight clock cycles.
Four possible timing relationships can be chosen by using control bits CPOL and
CPHA in the serial peripheral control register (SPCR). Both master and slave
devices must operate with the same timing. The SPI clock rate select bits, SPR1
and SPR0, in the SPCR of the master device, select the clock rate. In a slave
device, SPR1 and SPR0 have no effect on the operation of the SPI.
7.5.4 Slave Select (SS)
The SS input of a slave device must be externally asserted before a master device
can exchange data with the slave device. SS must be low before data transactions
and must stay low for the duration of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag
(MODF) is set in the serial peripheral status register (SPSR). To disable the mode
fault circuit, write a 1 in bit 5 of the port D data direction register. This sets the SS
pin to act as a general-purpose output. The other three lines are dedicated to the
SPI whenever the serial peripheral interface is on.
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Serial Peripheral Interface (SPI)
SPI System Errors
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Peripheral Interface (SPI) 91
The state of the master and slave CPHA bits affects the operation of SS. CPHA
settings should be identical for master and slave. When CPHA = 0, the shift clock
is the OR of SS with SCK. In this clock phase mode, SS must go high between
successive characters in an SPI message. When CPHA = 1, SS can be left low
between successive SPI characters. In cases where there is only one SPI slave
MCU, its SS line can be tied to VSS as long as only CPHA = 1 clock mode is used.
7.6 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises
in a multiple-master system when more than one SPI device simultaneously tries
to be a master. This error is called a mode fault. The second type of error, write
collision, indicates that an attempt was made to write data to the SPDR while a
transfer was in progress.
When the SPI system is configured as a master and the SS input line goes to active
low, a mode fault error has occurred — usually because two devices have
attempted to act as master at the same time. In cases where more than one device
is concurrently configured as a master, there is a chance of contention between
two pin drivers. For push-pull CMOS drivers, this contention can cause permanent
damage. The mode fault attempts to protect the device by disabling the drivers.
The MSTR control bit in the SPCR and all four DDRD co ntrol bits associated with
the SPI are cleared. An interrupt is generated subject to masking by the SPIE
control bit and the I bit in the CCR.
Other precautions may need to be ta ken to pre vent driver damage. If two d evices
are made masters at the same time, mode fault does not help protect either one
unless one of them selects the other as slave. The amount of damage possible
depends on the length of time both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in progress.
Because the SPDR is not double buffered in the transmit direction, writes to SPDR
cause data to be written directly into the SPI shift register. Because this write
corrupts any transfer in progress, a write collision error is generated. The t ransfe r
continues undisturbed, and the write data that caused the error is not written to the
shifter.
A write collision is normally a slave error because a slave has no control over when
a master initiates a transfer. A master knows when a transfer is in progress, so
there is no reason for a master to generat e a write-collision error, although the SPI
logic can detect write collisions in both master and slave devices.
The SPI configuration determines the chara cteristics of a transfer in progress. For
a master, a transfer begins when data is written to SPDR and ends when SPIF is
set. For a slave with CPHA equal to zero, a transfer starts when SS g oes low an d
ends when SS returns high. In this case, SPIF is set at the middle of the eighth SCK
cycle when data is transferred from the shifter to the parallel data register, but the
transfer is still in progress until SS goes high. For a slave with CPHA equal to one,
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Serial Peripheral Interface (SPI)
Data Sheet MC68HC711D3 — Rev. 2
92 Serial Peripheral Interface (SPI) MOTOROLA
transfer begins when the SCK line goes to its active level, which is the edge at the
beginning of the first SCK cycle. The transfer ends in a slave in which CPHA equals
one when SPIF is set. For a slave, after a byte transfer, SCK must be in inactive
state for at least 2 E-clock cycles before the next byte transfer begins.
7.7 SPI Registers
The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and
data storage functions. This sub-section provides a description of how these
registers are organized.
7.7.1 SPI Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode Bit
DWOM affects all six port D pins.
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, the SCK
pin of the master device has a steady state low value. When CPOL is set, SCK
idles high. Refer to Figure 7-2 and 7.4 Clock Phase and Polarity Controls.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data
relationship between master and slave. The CPHA bit selects one of two
different clocking protocols. Refer to Figure 7-2 and 7.4 Clock Phase and
Polarity Controls.
Address: $0028
Bit 7654321Bit 0
Read:
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0
Write:
Reset:000001UU
U = Unaffected
Figure 7-3. SPI Control Register (SPCR)
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Serial Peripheral Interface (SPI)
SPI Registers
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Serial Peripheral Interface (SPI) 93
SPR1 and SPR0 — SPI Clock Rate Select Bits
These two serial peripheral ra te bits select one of four baud rates to be used as
SCK if the device is a ma ster; however, th ey have no effect in the slave mode.
7.7.2 SPI Status Register
SPIF — SPI Transfer Complete Flag
SPIF is set upon completion of data transfer between the processor and the
external device. If SPIF goes high, and if SPIE is set, a serial peripheral interrupt
is generated. To clear the SPIF bit, read the SPSR with SPIF set, then access
the SPDR. Unless SPSR is read (with SPIF set) first, attempts to write SPDR
are inhibited.
WCOL — Write Collision Bit
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set)
followed by an access of SPDR. Refer to 7.5.4 Slave Select (SS) and 7.6 SPI
System Errors.
0 = No write collision
1 = Write collision
Bit 5 — Not implemented
Always reads 0.
MODF — Mode Fault Bit
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR.
Refer to 7.5.4 Slave Select (SS) and 7.6 SPI System Errors.
0 = No mode fault
1 = Mode fault
Bits 3–0 — Not implemented
Always reads 0
Table 7-1. SPI Clock Rates
SPR1
and SPR0 E Clock
Divide By Frequency at
E = 2 MHz (Baud)
0 0 2 1.0 MHz
0 1 4 500 kHz
1 0 16 125 kHz
1 1 32 62.5 kHz
Address: $0029
Bit 7654321Bit 0
Read:
SPIFWCOL0MODF0000
Write:
Reset:00000000
Figure 7-4. SPI Status Register (SPSR)
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Serial Peripheral Interface (SPI)
Data Sheet MC68HC711D3 — Rev. 2
94 Serial Peripheral Interface (SPI) MOTOROLA
7.7.3 SPI Data I/O Register
The SPI data I/O register (SPDR) is used when transmitting or receiving data on
the serial bus. Only a write to this register initiate s transmission or reception of a
byte, and this only occurs in the master device. At the completion of transferring a
byte of data, the SPIF status bit is set in both the master and slave devices.
A read of the SPDR is actually a read of a buffe r. To prevent an overrun and the
loss of the byte that caused the ove rrun, the first SPIF must be cleared by the time
a second transfer of data from the shift register to the read buffer is initiated.
NOTE: SPI is double buffered in and single buffered out.
Address: $002A
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Unaffected by reset
Figure 7-5. SPI Data I/O Register (SPDR)
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 95
Data Sheet — MC68HC711D3
Section 8. Programmable Timer
8.1 Introduction
The M68HC11 timing system is composed of five clock divider chains. The main
clock divider chain includes a 16-bit free-running counter, which is driven by a
programmable prescaler. The main timer's prog rammable prescaler provide s one
of the four clocking rates to drive the 16-bit counter. Two prescaler control bits
select the prescale rate.
The prescaler output divides the system clock by 1, 4, 8, or 16. Taps off of this main
clocking chain drive circuitry that generates the slower clocks used by the pulse
accumulator, the real-time interrupt (RTI), and the computer operating properly
(COP) watchdog subsystems. Refer to Figure 8-1.
All main timer system activities are referenced to this free-running counter. The
counter begins incrementing from $0000 as the microcon troller unit (MCU) comes
out of reset, and continues to the maximum count, $FFFF. At the maximum count,
the counter rolls over to $0000, sets an overflow flag, and continues to increment.
As long as the MCU is running in a normal operating mode, there is no way to reset,
change, or interrupt the counting. The c apture/compare subsystem features three
input capture channels, four output compare channels, and one channel that can
be selected to perform either input capture or output compare. Each of the three
input capture functions has its own 16-bit input capture register (time capture latch)
and each of the output compar e functions has its own 16-bit comp are register. All
timer functions, including the timer overflow and RTI have their own interrupt
controls and separate interrupt vectors.
The pulse accumulator contains an 8-bit counter and edge select log ic. The pulse
accumulator can operate in either event counting or gated time accumulation
modes. During event counting mode , the pulse accumulator's 8-bit counter
increments when a specified edge is detected on an input signal. During gated time
accumulation mode, an internal clock source increments the 8-bit counter while an
input signal has a predetermined logic level.
RTI is a programmable periodic interrupt circuit that permits pacing the execution
of software routines by selecting one of four interrupt rates.
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
96 Programmable Timer MOTOROLA
Figure 8-1. Timer Clock Divider Chains
OSCILLATOR AND
CLOCK GENERATOR AS
E CLOCK
SPI
SCI RECEIVER CLOCK
SCI TRANSMIT CLOCK
E ÷ 26PULSE ACCUMULATOR
TCNT
TOF
REAL-TIME INTERRUPT
E ÷ 213
÷4
E÷215
RQ
Q
S
RQ
Q
S
FORCE
COP
RESET
SYSTEM
RESET
CLEAR COP
TIMER
FF2
FF1
(DIVIDE BY FOUR)
INTERNAL BUS CLOCK (PH2)
IC/OC
÷16
CR1 AND CR0
PRESCALER
(÷1, 4, 16, 64)
PRESCALER
(÷ 2, 4, 16, 32)
SPR1 AND SPR0
PRESCALER
(÷ 1, 3, 4, 13)
SCP1 AND SCP0
PRESCALER
(÷ 1, 2, 4, 8)
RTR1 AND RTR0
PRESCALER
(÷ 1, 2, 4,....128)
SCR2–SCR0
PRESCALER
(÷ 1, 4, 8, 16)
PR1 AND PR0
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Programmable Timer
Timer Structure
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 97
The COP watchdog clock input (E÷215) is tapped off of the free-running counter
chain. The COP automatically times out un less it is serviced within a specific time
by a program reset sequence. If the COP is allowed to time out, a reset is
generated, which drives the RESET pin low to reset the MCU and the external
system. Refer to Table 8-1 for crystal related frequencies and periods.
8.2 Timer Structure
Figure 8-2 shows the capture/compare system block diagram. The port A pin
control block includes logic for timer functions and for general-purpose input/output
(I/O). For pins PA2, PA1, and PA0, this block contains both the edge-detection
logic and the control logic that enables the selection of which edge triggers an input
capture. The digital level on PA2–PA0 can be read at any time (read PORTA
register), even if the pin is being used for the input capture function. Pins PA6–PA4
are used for either general-purpose output or as output compare pins. Pin PA3 can
be used for general-purpose I/O, input capture 4, output compare 5, or output
compare 1. When one of these pins is being used for an output compare function,
it cannot be written directly as if it were a general-purpose output. Each of the
output compare functions (OC5–OC2) is related to one of the port A output pins.
Output compare 1 (OC1) has extra control logic, allowing it optional control of any
combination of the PA7–PA3 pins. The PA7 pin can be used as a general-purpose
I/O pin, as an input to the pulse accumulator, or as an OC1 output pin.
Table 8-1. Timer Summary
Control
Bits
XTAL Frequencies
4.0 MHz 8.0 MHz 12.0 MHz Other Rates
1.0 MHz 2.0 MHz 3.0 MHz (E)
1000 ns 500 ns 333 ns (1/E)
PR1 and PR0 Main Timer Count Rates
0 0
1 count —
overflow — 1.0 µs
65.536 ms 500 ns
32.768 ms 333 ns
21.845 ms (E/1)
(E/216)
0 1
1 count —
overflow — 4.0 µs
262.14 ms 2.0 µs
131.07 ms 1.33 3 µs
87.381 ms (E/4)
(E/218)
1 0
1 count —
overflow — 8.0 µs
524.29 ms 4.0 µs
262.14 ms 2.66 7 µs
174.76 ms (E/8)
(E/219)
1 1
1 count —
overflow — 16.0 µs
1.049 s 8.0 µs
524.29 ms 5.33 3 µs
349.52 ms (E/16)
(E/220)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
98 Programmable Timer MOTOROLA
Figure 8-2. Capture/Compare Block Diagram
8.3 Input Capture
The input capture function records the time an external event occurs by latching
the value of the free-running counter when a selected edge is detected at the
associated timer input pin. Software can store latched values and use them to
compute the periodicity and duration of events. For example, by storing the times
MCU E
16-BIT LATCH CLK
4
5
6
7
8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
OC1I
OC2I
OC3I
OC4I
I4/O5I
TFLG 1
STATUS
FLAGS
FOC1
FOC2
FOC3
FOC4
FOC5
OC1F
OC2F
OC3F
OC4F
I4/O5F PA3/IC4/
PA4/OC4/
PA5/OC3/
PA6/OC2/
PA7/OC1/
I4/O5
16-BIT COMPARATOR =
TOC1 (HI) TOC1 (LO)
16-BIT COMPARATOR =
TOC2 (HI) TOC2 (LO)
16-BIT COMPARATOR =
TOC3 (HI) TOC3 (LO)
16-BIT COMPARATOR =
TOC4 (HI) TOC4 (LO)
16-BIT COMPARATOR =
TI4/O5 (HI) TI4/O5 (LO)
16-BIT FREE RUNNING
COUNTER
TCNT (HI) TCNT (LO) 9
TOI
TOF
PRESCALER — DIVIDE BY
1, 4, 8, 16
PR1
16-BIT TIMER BUS
OC5
IC4
TMSK 1
INTERRUPT
ENABLES
CFORC
PORT A
PINS
PA0/IC3
3
2
1
BIT 2
BIT 1
BIT 0
IC1I
IC2I
IC3I
IC1F
IC2F
IC3F
PA1/IC2
PA2/IC1
16-BIT LATCH
TIC1 (HI) TIC1 (LO)
CLK
16-BIT LATCH
TIC2 (HI) TIC2 (LO)
CLK
16-BIT LATCH
TIC3 (HI) TIC3 (LO)
CLK
PR0
CLOCK
PAI
OC1
OC1
OC1
OC5/OC1
PORT A
PIN
CONTROL
TO PULSE
ACCUMULATOR
INTERRUPT REQUESTS
(FURTHER QUALIFIED
BY I BIT IN CCR)
FORCE
OUTPUT
COMPARE
TAPS FOR RTL,
COP WATCHDOG,
AND PULSE ACCUMULATOR
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Programmable Timer
Input Capture
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 99
of successive edges of an incoming signal, soft ware can determine the period and
pulse width of a signal. To measure period, two successive edges of the same
polarity are captured. To measure pulse width, two alternate polarity edges are
captured.
In most cases, input capture edges are asynchronous to the internal timer counter,
which is clocked relative to the PH2 clock. Th ese asynch ronous capture reque sts
are synchronized to PH2 so that the latching occurs on the opposite half cycle of
PH2 from when the timer counter is being incremented. This synchronization
process introduces a delay from when the edge occurs to when the counter va lue
is detected. Because these delays offset each other when the time between two
edges is being measured, the delay can be ignored. When an input capture is
being used with an output compare, there is a similar delay between the actual
compare point and when the output pin changes state.
The control and status bits that implement the input capture functions are
contained in the PACTL, TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL
register. Note that this bit is cleared out of re set. To enable PA3 as the fourth input
capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a
fifth output compare out of reset, with bit I4/O5 being cleared. If the DDRA3 bit is
set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause
edges on the pin to result in input captures. Writing to TI4/O5 has no effect when
the TI4/O5 register is acting as IC4.
8.3.1 Timer Control 2 Register
Use the control bits of timer control 2 register (TCTL2) to program input capture
functions to detect a par ticu lar e dge p olarity on the corresponding timer input pin.
Each of the input capture functions can be independently configured to detect
rising edges only, falling edges only, any edge (rising or falling), or to disable the
input capture function. The input capture functio ns operat e independently of each
other and can capture the same TCNT value if the input edges are detecte d within
the same timer count cycle.
EDGxB and EDGxA — Input Capture Edge Control
There are four pairs of the se bits. Each pair is cleared to 0 by reset and must be
encoded to configure the corresponding input capture edge detector circuit. IC4
Address: $0021
Bit 7654321Bit 0
Read:
EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A
Write:
Reset:00000000
Figure 8-3. Timer Control 2 Register (TCTL2)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
100 Programmable Timer MOTOROLA
functions only if the I4/O5 bit in PACTL is set. Refer to Table 8-2 for timer control
configuration.
8.3.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit free-running
counter value is transferred into the input capture register pair as a single 16-bit
parallel transfer. Timer counter value captures and timer counter incrementing
occur on opposite half-cycles of the phase two clock so that the count value is
stable whenever a capture occu rs. The timer input capture (TICx) registers a re not
affected by reset. Input capture values can be read from a pair of 8-bit read-only
registers. A read of the high-order byte of an input capture register pair inhibits a
new capture transfer for one bus cycle. If a double-byte read instruction, such as
LDD, is used to read the captured value, coherency is assured. When a new input
capture occurs immediately after a high-order byte read, transfer is delayed for an
additional cycle but the value is not lost.
Table 8-2. Timer Control Configuration
EDGxB EDGxA Configuration
0 0 Capture disa bled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge
Address: $0010 — TIC1 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
Address: $0011 — TIC1 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
Address: $0012 — TIC2 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 8-4. Timer Input Capture Registers (TICx)
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Programmable Timer
Input Capture
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 101
8.3.3 Timer Input Capture 4/Output Compare 5 Register
Use timer input capture 4/output compare 5 (TI4/O5) as either an input capture
register or an output compare register, depending on the function chosen for the
I4/O5 pin. To enable it as an input capture pin, set the I4/O5 bit in the pulse
accumulator control register (PACTL) to logic level 1. To use it as an output
compare register, set the I4/O5 bit to a logic level 0. Refer to 8.7 Pulse
Accumulator.
Address: $0013 — TIC2 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
Address: $0014 — TIC3 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
Address: $0015 — TIC3 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 8-4. Timer Input Capture Registers (TICx) (Continued)
Address: $001E — TI4/O5 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
Address: $001F — TI4/O5 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:11111111
= Unimplemented
Figure 8-5. Timer Input Capture 4/Output
Compare 5 Register (TI4/O5)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
102 Programmable Timer MOTOROLA
8.4 Output Compare (OC)
Use the output compare (OC) function to program an action to occur at a specific
time — when the 16-bit counter reaches a specified value. For each of the five
output compare functions, there is a separate 16-bit compare register and a
dedicated 16-bit comparator. The value in the compare register is compared to the
value of the free-running counter on ev ery bus cycle. When the compare register
matches the counter value, an output compare status flag is set. The flag can be
used to initiate the automatic actions for that output compare function.
To produce a pulse of a specific duration, write to the output compare register a
value representing the time the leading edge of the pulse is to occur. The output
compare circuit is configured to set the appropriate output either high or low,
depending on the polarity of the pulse being produced. After a match occurs, the
output compare register is reprogrammed to change the output pin back to its
inactive level at the next match. A value representing the width of the pulse is
added to the original value, and then is written to the output compare register.
Because the pin state changes occur at specific values of the free-running counter,
the pulse width can be controlled accurately at the resolution of the free-running
counter, independent of software latencies. To generate an output signal of a
specific frequency and duty cycle, repeat this pulse-generating procedure.
There are four 16-bit read/write ou tput compare registers: TOC1, TOC2, TOC3,
and TOC4, and the TI4/O5 register, which functions under software control as
either IC4 or OC5. Each of the OC registers is set to $FFFF on reset. A value
written to an OC register is compared to the free-running counter value during each
E-clock cycle. If a match is found, the particular output compare flag is set in timer
interrupt flag register 1 (TFLG1). If that particular interrupt is enabled in the timer
interrupt mask register 1 (TMSK1), an interrupt is generated. In addition to an
interrupt, a specified action can be initiated at one or more timer output pins. For
OC5–OC2, the pin action is controlled by pairs of bits (OMx and OLx) in the TCTL1
register. The output action is taken on each successful compare, regardless of
whether the OCxF flag in the TFLG1 register was previously cleared.
OC1 is different from the other output compares in that a successful OC1 compare
can affect any or all five of the OC pins. The OC1 output action taken when a match
is found is controlled by two 8-bit registers with three bits unimplemented: the
output compare 1 mask register, OC1M, and the output compare 1 data register,
OC1D. OC1M specifies which port A o utputs are to be used , and OC1D specifies
what data is placed on these port pins.
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Programmable Timer
Output Compare (OC)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 103
8.4.1 Timer Output Compare Registers
All output compare registers are 16-bit read-write. Each is initialized to $FFFF at
reset. If an output compare register is not used for an output compare function, it
can be used as a storage location. A write to the high-order byte of an output
compare register pair inhibits the output compare function for one bus cycle. This
inhibition prevents inappropriate subsequent comparisons. Coherency requires a
complete 16-bit read or write. However, if coherency is n ot needed, byte accesses
can be used.
For output compare functions, write a comparison value to output compare
registers TOC1–TOC4 and TI4/O5. When TCNT value matches the comparison
value, specified pin actions occur.
Address: $0016 — TOC1 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
Address: $0017 — TOC1 (Low)
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:11111111
Address: $0018 — TOC2 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
Address: $0019 — TOC2 (Low)
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:11111111
Address: $001A — TOC3 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
Figure 8-6. Timer Output Capture Registers (TOCx)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
104 Programmable Timer MOTOROLA
8.4.2 Timer Compare Force Register
The timer compare force register (CFORC) allows forced early compares.
FOC1–FOC5 correspond to the five output compares. These bits are set f or each
output compare that is to be forced. The action taken as a result of a forced
compare is the same as if there were a match between the OCx register and the
free-running counter, except that the corresponding interrupt status flag bits are not
set. The forced channels trigger their pro grammed pin actions to occur at the next
timer count transition after the write to CFORC.
The CFORC bits should not be used on an output compare function that is
programmed to toggle its output on a successful compare because a normal
compare that occurs immediately before or after the force can result in an
undesirable operation.
FOC1–FOC5 — Write 1s to Force Compare Bits
0 = Not affected
1 = Output x action occurs
Bits 2–0 — Not implemented, always read 0.
Address: $001B — TOC3 (Low)
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:11111111
Address: $001C — TOC4 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
Address: $001D — TOC4 (Low)
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset:11111111
Figure 8-6. Timer Output Capture Registers (TOCx) (Continued)
Address: $000B
Bit 7654321Bit 0
Read:
FOC1 FOC2 FOC3 FOC4 FOC5 0 0 0
Write:
Reset:00000000
Figure 8-7. Timer Compare Force Register (CFORC)
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Programmable Timer
Output Compare (OC)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 105
8.4.3 Output Compare 1 Mask Register
Use OC1M with OC1 to specify the bits of port A that are affected by a successf ul
OC1 compare. The bits of the OC1M register correspond to PA7–PA3.
OC1M7–OC1M3 — Output Compare Masks
0 = OC1 disabled
1 = OC1 enabled to control the corresponding pin of port A
Bits 2–0 — Not implemented; always read 0.
Set bit(s) to enable OC1 to control corresponding pin(s) of port A.
8.4.4 Output Compare 1 Data Registe r
Use this register with OC1 to specify the data that is to be stored on the affected
pin of port A after a successful OC1 compare. When a successful OC1 compare
occurs, a data bit in OC1D is stored in the corresponding bit of port A for each bit
that is set in OC1M.
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1
compares.
Bits 2–0 — Not implemented; always read 0.
Address: $000C
Bit 7654321Bit 0
Read:
OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 0 0 0
Write:
Reset:00000000
Figure 8-8. Output Compare 1 Mask Register (OC1M)
Address: $000D
Bit 7654321Bit 0
Read:
OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 0 0 0
Write:
Reset:00000000
Figure 8-9. Output Compare 1 Data Register (OC1D)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
106 Programmable Timer MOTOROLA
8.4.5 Timer Counter Register
The 16-bit read-only timer count register (TCNT) contains the prescaled value of
the 16-bit timer. A full counter read addresses the most significant byte (MSB) first.
A read of this address causes the least significant byte (LSB) to be latched into a
buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state
of the counter at the time of the MSB read cycle.
In normal modes, TCNT is read-only.
8.4.6 Timer Control 1 Register
The bits of the timer control 1 register (TCTL 1) specify the action taken as a result
of a successful OCx compare.
OM2–OM5 — Output Mode Bits
OL2–OL5 — Output Level Bits
These control bit pairs are encoded to specify the action taken after a successful
OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear.
Refer to Table 8-3 for the coding.
Address: $000E — TCNT High
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 08
Write:
Reset:00000000
Address: $000F — TCNT Low
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:00000000
= Unimplemented
Figure 8-10. Timer Counter Registers (TCNT)
Address: $0020
Bit 7654321Bit 0
Read:
OM2OL2OM3OL3OM4OL4OM5OL5
Write:
Reset:00000000
Figure 8-11. Timer Control 1 Register (TCTL1)
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Programmable Timer
Output Compare (OC)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 107
8.4.7 Timer Interrupt Mask 1 Register
The timer interrupt mask 1 register (TMSK1) is an 8-bit register used to enable or
inhibit the timer input capture and output compare interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
If the OCxI enable bit is set when the OCxF flag b it is set, a hardwa re interrupt
sequence is requested.
I4/O5I — Input Capture 4 or Output Compare 5 Interrupt Enable Bit
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 in terrupt en able bit.
When I4/O5 in PACTL is 0, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input Capture x Interrupt Enable Bits
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt
sequence is requested.
NOTE: Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable
the corresponding interrupt sources.
Table 8-3. Timer Output Compare Actions
OMx OLx Action Taken on Successful Compare
0 0 Timer disconnected from output pin logic
0 1 Toggle OCx output line
1 0 Clear OCx output line to 0
1 1 Set OCx output line to 1
Address: $0022
Bit 7654321Bit 0
Read:
OC1I OC2I OC3I OC4I I4/O5I IC1I IC2I IC3I
Write:
Reset:00000000
Figure 8-12. Timer Interrupt Mask 1 Register (TMSK1)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
108 Programmable Timer MOTOROLA
8.4.8 Timer Interrupt Flag 1 Register
The timer interrupt flag 1 register (TFL G1) bits indica te when timer system events
have occurred. Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer
subsystem to operate in either a polled or interrupt driven system. Each bit of
TFLG1 corresponds to a bit in TMSK1 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
OC1F–OC5F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
8.4.9 Timer Interrupt Mask 2 Register
The timer interrupt mask 1 register (TMSK2) is an 8-bit register used to enable or
inhibit timer overflow and real-time interrupts. The timer prescaler control bits are
included in this register.
TOI — Timer Overflow Interrupt Enable Bit
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
RTII — Real-Time Interrupt Enable Bit
Refer to 8.5 Real-Time Interrupt.
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 8.7 Pulse Accumulator.
Address: $0023
Bit 7654321Bit 0
Read:
OC1F OC2F OC3F OC4F I4/O5F IC1F IC2F IC3F
Write:
Reset:00000000
Figure 8-13. Timer Interrupt Flag 1 Register (TFLG1)
Address: $0024
Bit 7654321Bit 0
Read:
TOI RTII PAOVI PAII 0 0 PR1 PR0
Write:
Reset:00000000
Figure 8-14. Timer Interrupt Mask 2 Register (TMSK2)
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Programmable Timer
Output Compare (OC)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 109
PAII — Pulse Accumulator Input Edge Interrupt Enable Bit
Refer to 8.7 Pulse Accumulator.
NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable
the corresponding interrupt sources.
PR1 and PR0 — Timer Prescaler Select Bits
These bits are used to select the prescaler divide-by ratio. In normal modes,
PR1 and PR0 can be written once only, and the write must be within 64 cycles
after reset. Refer to Table 8-4 for specific timing values.
8.4.10 Timer Interrupt Flag 2 Register
The timer interrupt flag 2 register (TFLG2) bits indicate when certain timer system
events have occurred. Coupled with the four high-order bits of TMSK2, t he bits o f
TFLG2 allow the timer subsystem to operate in either a polled or interrupt driven
system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time (Periodic) Interrupt Flag
Refer to 8.5 Real-Time Interrupt.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 8.7 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 8.7 Pulse Accumulator.
Bits 3–0 — Not implemented
Always read 0.
Table 8-4. Timer Prescale
PR1 and PR0 Prescaler
0 0 1
0 1 4
1 0 8
1 1 16
Address: $0025
Bit 7654321Bit 0
Read:
TOFRTIFPAOVFPAIF0000
Write:
Reset:00000000
Figure 8-15. Timer Interrupt Flag 2 Register (TFLG2)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
110 Programmable Timer MOTOROLA
8.5 Real-Time Interrupt
The real-time interrupt feature, used to generate hardware interrupts at a fixed
periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the
pulse accumulator control (PACTL) register. The RTII bit in the TMSK2 register
enables the interrupt capability. The four different rates available are a product
of the MCU oscillator frequency and the value of bits RTR1 and RTR0. Refer to
Table 8-5 for the periodic real-time interrupt rates.
The clock source for the RTI function is a free-running clock that cannot be stopped
or interrupted except by reset. This clock causes the time between successive RTI
timeouts to be a constant that is independent of the softwa re latencies associated
with flag clearing and service. For this reason, an RTI period starts from the
previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire real-time interrupt period elapses
before the RTIF flag is set for the first time. Refer to the TMSK2, TFLG2, and
PACTL registers.
8.5.1 Timer Interrupt Mask 2 Register
The timer interrupt mask 2 register (TMSK2) contains the real-time interrupt enable
bits.
TOI — Timer Overflow Interrupt Enable Bit
Refer to 8.4 Output Compare (OC).
Table 8-5. Periodic Real-Time Interrupt Rates
RTR1
and RTR0 E = 1 MHz E = 2 MHz E = 3 MHz E = X MHz
0 0
0 1
1 0
1 1
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
8.192 ms
16.384 ms
32.768 ms
65.536 ms
(E/213)
(E/214)
(E/215)
(E/216)
Address: $0024
Bit 7654321Bit 0
Read:
TOI RTII PAOVI PAII 0 0 PR1 PR0
Write:
Reset:00000000
Figure 8-16. Timer Interrupt Mask 2 Register (TMSK2)
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Programmable Timer
Real-Time Inte rr up t
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 111
RTII — Real-Time Interrupt Enable Bit
0 = RTIF interrupts disabled
1 = Interrupt requested
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
Refer to 8.7 Pulse Accumulator.
PAII — Pulse Accumulator Input Edge Bit
Refer to 8.7 Pulse Accumulator.
Bits 3–2 — Unimplemented
Always read 0.
PR1 and PR0 — Timer Prescaler Select Bits
Refer to Table 8-4.
NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable
the corresponding interrupt sources.
8.5.2 Timer Interrupt Flag 2 Register
Bits of the timer interrupt flag 2 register (TFLG2) indicate the occurrence of timer
system events. Coupled with the four high-order b its of TMSK2, the bits of TFLG2
allow the timer subsystem to operate in either a polled or interrupt driven system.
Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to 1 at the end of every RTI period. To
clear RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to 8.7 Pulse Accumulator.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to 8.7 Pulse Accumulator.
Bits 3–0 — Not implemented
Always read 0.
Address: $0025
Bit 7654321Bit 0
Read:
TOFRTIFPAOVFPAIF0000
Write:
Reset:00000000
Figure 8-17. Timer Interrupt Flag 2 Register (TFLG2)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
112 Programmable Timer MOTOROLA
8.5.3 Pulse Accumulator Control Register
Bits RTR1 and RTR0 of the pulse accumulator control register (PACTL) select the
rate for the real-time interrupt system. Bit DDRA3 determines whether port A bit
three is an input or an output when used for general-purpose I/O. The remaining
bits control the pulse accumulator.
DDRA7 — Data Direction Control for Port A Bit 7
Refer to 8.7 Pulse Accumulator.
PAEN — Pulse Accumulator System Enable Bit
Refer to 8.7 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode Bit
Refer to 8.7 Pulse Accumulator.
PEDGE — Pulse Accumulator Edge Control Bit
Refer to 8.7 Pulse Accumulator.
DDRA3 — Data Direction Register for Port A Bit 3
Refer to Section 5. Input/Output (I/O) Ports.
I4/O5 — Input Capture 4/Output Compare 5 Bit
Refer to 8.3 Input Capture.
RTR1 and RTR0 — RTI Interrupt Rate Select Bits
These two bits determin e the rate at which th e RTI system re quests interru pts.
The RTI system is driven by an E divided by 213 rate clock that is compensated
so it is independent of the timer prescaler. These two control bits select an
additional division factor. See Table 8-6.
Address: $0026
Bit 7654321Bit 0
Read:
DDRA7 PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0
Write:
Reset:00000000
Figure 8-18. Pulse Accumulator Control Register (PACTL)
Table 8-6. Real-Time Interrupt Rates
RTR1
and RTR0 E = 1 MHz E = 2 MHz E = 3 MHz E = X MHz
0 0
0 1
1 0
1 1
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
8.192 ms
16.384 ms
32.768 ms
65.536 ms
(E/213)
(E/214)
(E/215)
(E/216)
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Programmable Timer
Computer Operating Properly Watchdog Function
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 113
8.6 Computer Operating Properly Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain,
is only superficially related to the main timer system. The CR1 and CR0 bits in the
OPTION register and the NOCOP bit in the CONFIG register determine the status
of the COP function. Refer to Section 4. Resets, Interrupts, and Low-Power
Modes for a more detailed discussion of the COP function.
8.7 Pulse Accumulator
The MC68HC711D3 has an 8-bit counter tha t can be config ured to operat e either
as a simple event counter or for g ated time accumulation, depending on the state
of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block
diagram, Figure 8-19.
Figure 8-19. Pulse Accumulator
PACNT
8-BIT COUNTER
2:1
MUX
PA7/
ENABLE
OVERFLOW
1
2
INTERRUPT
REQUESTS
INTERNAL
DATA BUS
INPUT BUFFER
AND
EDGE DETECTION
PACTL CONTROL
TFLG2 INTERRUPT STATUSTMSK2 INT ENABLES
PAOVI
PAII
DDRA7
PAEN
PAMOD
PEDGE
PAOVF
PAIF
OUTPUT
BUFFER
PAI EDGE
PAEN
E ÷ 64 CLOCK
(FROM MAIN TIMER)
PAI/OC1
FROM
MAIN TIMER
OC1
DISABLE
FLAG SETTING
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
114 Programmable Timer MOTOROLA
In the event counting mode, the 8-bit counter is clocke d to increasing values by an
external pin. The maximum clocking rate for the external event counting mode is
the E clock divided by two. In gated time accumulation mode, a free-running
E-clock ÷ 64 signal drives the 8-bit counter, but only while the external PAI pin is
activated. Refer to Table 8-7. The pulse accumulator counter can be read or
written at any time.
Pulse accumulator control bits are a lso located within two timer registers, TMSK2
and TFLG2, as described here.
8.7.1 Pulse Accumulator Control Register
Four of the pulse accumulator control register (PACTL) bits control an 8-bit pulse
accumulator system. Another bit enables either the OC5 function or the IC4
function, while two other bits select the rate for the real-time interrupt system.
DDRA7 — Data Direction Control for Port A Bit 7
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also
be used as general-purpose I/O or as an output compare.
NOTE: Even when port A bit 7 is configured as an output, the pin still drives the input to
the pulse accumulator.
Refer to Section 5. Input/Output (I/O) Ports for more information.
PAEN — Pulse Accumulator System Enable Bit
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode Bit
0 = Event counter
1 = Gated time accumulation
Table 8-7. Pulse Accumulator Timing in Gated Mode
Selected
Crystal Common XTAL Fre quencies
4.0 MHz 8.0 MHz 12.0 MHz
CPU Clock (E) 1.0 MHz 2.0 MHz 3.0 MHz
Cycle Time (1/E) 1000 ns 500 ns 333 ns
(E/26)
(E/214)1 count -
overflow - 64.0 µs
16.384 ms 32.0 µs
8.192 ms 21.33 µs
5.461 ms
Address: $0026
Bit 7654321Bit 0
Read:
DDRA7 PAEN PAMOD PEDGE DDRA3 I4/O5 RTR1 RTR0
Write:
Reset:00000000
Figure 8-20. Pulse Accumulator Control Register (PACTL)
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Programmable Timer
Pulse Accumulator
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Programmable Timer 115
PEDGE — Pulse Accumulator Edge Control Bit
This bit has different meanings depending on the state of the PAMOD bit, as
shown in Table 8-8.
DDRA3 — Data Direction Register for Port A Bit 3
Refer to Section 5. Input/Output (I/O) Ports.
I4/O5 — Input Capture 4/Output Compare 5 Bit
Refer to 8.3 Input Capture.
RTR1 and RTR0 — RTI Interrupt Rate Select Bits
Refer to 8.5 Real-Time Interrupt.
8.7.2 Pulse Accumulator Count Register
The 8-bit read/write pulse accumulator count register (PACNT) contains the coun t
of external input events at the PAI input or the accumulated count. The counter is
not affected by reset and can be read or written at any time. Counting is
synchronized to the internal PH2 clock so that incrementing and reading occur
during opposite half cycles.
8.7.3 Pulse Accumulator Status and Interrupt Bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located
within timer registers TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
The PAOVF status bit is set each time the pulse accumulator count rolls over
from $FF to $00. To clear this status bit, write a 1 in the correspo nding data b it
position (bit 5) of the TFLG2 register. The PAOVI control bit a llows configuring
the pulse accumulator overflow for polled or interrupt-driven operation and does
Table 8-8. Pulse Accumulator Edge Control
PAMOD PEDGE Action on Clock
0 0 PAI falling edge increments the counter.
0 1 PAI rising edge increments the counter.
1 0 A 0 on PAI inhibits counting.
1 1 A 1 on PAI inhibits counting.
Address: $0027
Bit 7654321Bit 0
Read:
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Write:
Reset: Unaffected by reset
Figure 8-21. Pulse Accumulator Count Register (PACNT)
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Programmable Timer
Data Sheet MC68HC711D3 — Rev. 2
116 Programmable Timer MOTOROLA
not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow
interrupts are inhibited, and the system operates in a polled mode, which
requires PAOVF to be polled by user software to determine when an overflow
has occurred. When the PAOVI control bit is set, a hardware interrupt request
is generated each time PAOVF is set. Before leaving the interrupt service
routine, software must clear PAOVF by writing to the TFLG2 register.
PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and Flag
The PAIF status bit is automatically set each time a selected edge is detected
at the PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with
a 1 in the corresponding data bit position (bit 4). The PAII control bit allows
configuring the pulse accumulator input edge detect for polled or
interrupt-driven operation but does not affect setting or clearing the PAIF bit.
When PAII is 0, pulse accumulator input interrupts are inhibited, and the system
operates in a polled mode. In this mode, the PAIF bit must be polled by user
software to determine when an ed ge has occurred. When th e PAII control bit is
set, a hardware interrupt request is generated each time PAIF is set. Before
leaving the interrupt service routine, software must clear PAIF by writing to the
TFLG register.
Address: $0024
Bit 7654321Bit 0
Read:
TOI RTII PAOVI PAII 0 0 PR1 PR0
Write:
Reset:00000000
Figure 8-22. Timer Interrupt Mask 2 Register (TMSK2)
Address: $0025
Bit 7654321Bit 0
Read:
TOFRTIFPAOVFPAIF0000
Write:
Reset:00000000
Figure 8-23. Timer Interrupt Flag 2 Register (TFLG2)
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 117
Data Sheet — MC68HC711D3
Section 9. Electrical Characteristics
9.1 Introduction
This section contains electrical specifications.
9.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without
permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to
9.5 DC Electrical Characteristics for guaranteed operating conditions.
NOTE: This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum-rated voltages to
this high-impedance circuit. For proper operation, it is recommended that VIn and
VOut be constrained to the r ange VSS ≤ (VIn or VOut) ≤ VDD. Reliability of operation
is enhanced if unused inputs are connected to an appropriate logic voltage level
(for example, either VSS or VDD).
Rating Symbol Value Unit
Supply voltage VDD –0.3 to +7.0 V
Input voltage VIn –0.3 to +7.0 V
Current drain per pin(1)
Excluding VDD, VSS, VRH , and VRL
1. One pin at a time, observing maximum power dissipation limits
ID25 mA
Storage temperature TSTG –55 to +150 °C
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Electrical Characteristics
Data Sheet MC68HC711D3 — Rev. 2
118 Electrical Characteristics MOTOROLA
9.3 Functional Operating Temperature Range
9.4 Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range
MC68HC711D3
MC68HC711D3V TA
TL to TH
–40 to +85
–40 to +105 °C
Characteristic Symbol Value Unit
Average junction temperature TJTA + (PD × ΘJA)°C
Ambient temperature TAUser-determined °C
Package thermal resistance (junction-to-ambient)
40-pin plastic dual in-line package (DIP)
44-pin plastic leaded chip carrier (PLCC)
44-pin plastic quad flat pack (QFP)
ΘJA 50
50
85
°C/W
Total power dissipation(1) PDPINT + PI/O
K / TJ + 273°CW
Device internal power dissipation PINT IDD × VDD W
I/O pin power dissipation(2) PI/O User-determined W
A constant(3) KPD × (TA + 273°C)
+ ΘJA × PD2 W/°C
1. This is an approximate value, neglecting PI/O.
2. For most applications, PI/O ≤ PINT and can be neglected.
3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value
of K to solve for PD and TJ, iteratively, for any value of TA.
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Electrical Charac ter istics
DC Electrical Characteristics
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 119
9.5 DC Electrical Characteristics
Characteristic(1) Symbol Min Max Unit
Output voltage(2) All outputs
ILoad = ± 10.0 µAAll outputs except RESET and MODA VOL
VOH
—
VDD – 0.1 0.1
— V
Output high vo ltage(1) All outputs except
ILoad = – 0.8 mA, VDD = 4.5 V RESET, EXTAL, and MODA VOH VDD – 0.8 — V
Output low voltage All outputs except XTAL
ILoad = 1.6 mA VOL — 0.4 V
Input high voltage All inputs except RESET
RESET VIH 0.7 x VDD
0.8 x VDD
VDD + 0.3
VDD + 0.3 V
Input low vo ltage All inputs VIL VSS – 0.3 0 .2 x VDD V
I/O po rts, three-state leakage PA7, PA3, PC7–PC0, PD7–PD0, VIn = VIH
or VIL MODA/LIR, RESET IOZ — ±10 µA
Input leakage current
VIn = VDD or VSS IRQ, XIRQ
VIn = VDD or VSS MODB/VSTBY
IIn —
— ±1
±10 µA
RAM standby voltagePower dow n VSB 4.0 VDD V
RAM standby currentPower down ISB — 20 µA
Total supply current(3)
RUN:
Single-chip mode
dc — 2 MHz
dc — 3 MHz
Expanded multiplexed mode
dc — 2 MHz
dc — 3 MHz
WAIT — All peripheral functions shut down:
Single-chip mode
dc — 2 MHz
dc — 3 MHz
Expanded multiplexed mode
dc — 2 MHz
dc — 3 MHz
STOP — No clocks, single-chip mode:
dc — 2 MHz
dc — 3 MHz
IDD
WIDD
SIDD
—
—
—
—
—
—
—
—
—
—
15
27
27
35
6
15
10
20
100
150
mA
mA
µA
The dc electri c al table continues on next page.
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Electrical Characteristics
Data Sheet MC68HC711D3 — Rev. 2
120 Electrical Characteristics MOTOROLA
Figure 9-1. Equivalent Test Load
Input capacitancePA3–PA0, IRQ, XIRQ, EXTAL
PA7, PC7–PC0, PD7–PD0, MODA/LIR, RESET CIn —
— 8
12 pF
Power di ssip at i on
Single-chip mode
dc — 2 MHz
dc — 3 MHz
Expanded multiplexed mode
dc — 2 MHz
dc — 3 MHz
PD—
—
—
—
85
150
150
195
mW
EPROM programming voltage VPP 11.75 12.75 V
EPROM prog ramming time tPP 24ms
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. VOH specification for RESET and MODA is not applicable because they are open-drain pins. VOH specification is not
applicable to ports C and D in wired-OR mode.
3. All ports configured as inputs: VIL ≤ 0.2 V, VIH ≤ VDD –0.2 V; no dc loads; EXTAL is driven with a square wave;
tcyc = 476.5 ns.
Characteristic(1) Symbol Min Max Unit
Pins R1 R2 C1
PA3–PA7
PB0–PB7
PC0–PC7
PD0, PD5–PD7
E
3.26 K 2.38 K 90 pF
PD1—PD4 3.26 K 2.38 K 200 pF
VDD
C1
R2
R1
TEST
POINT
1. Full test loads are applied during all ac electrical timing measurements.
EQUIVALENT TEST LOAD(1)
Note:
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Electrical Charac ter istics
DC Electrical Characteristics
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 121
Figure 9-2. Test Methods
CLOCKS,
STROBES
INPUTS
0.4 V
NOMINAL TIMING
NOM
20% of VDD
70% of VDD
0.4 V
VSS
~
NOM
OUTPUTS
0.4 V
DC TESTING
CLOCKS,
STROBES
INPUTS
SPEC TIMING
0.4 V
SPEC
OUTPUTS
AC TESTING
(NOTE 1)
SPEC
~ VDD
~ VSS
~ VDD
~ VDD
~ VDD
~ VSS
VDD – 0.8 V
VDD – 0.8 V
20% of VDD ~ VSS 20% of VDD
70% of VDD
VDD – 0.8 V
20% of VDD
70% of VDD
70% of VDD
20% of VDD
Note:
1. During ac timing measurements, inputs are driven to 0.4 volts and VDD – 0.8 volts while timing measurements are taken
at the 20% and 70% of VDD points.
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Electrical Characteristics
Data Sheet MC68HC711D3 — Rev. 2
122 Electrical Characteristics MOTOROLA
9.6 Control Timing
Figure 9-3. Timer Inputs
Characteristic(1) Symbol 1.0 MHz 2.0 MHz 3.0 MHz Unit
Min Max Min Max Min Max
Frequen cy of operation fOdc 1.0 dc 2.0 dc 3.0 MHz
E-clock period tcyc 1000 — 500 — 333 — ns
Crystal frequency fXTAL —4.0—8.0—12.0MHz
External oscillator frequency 4 fOdc 4.0 dc 8.0 dc 12.0 MHz
Processor control setup timetPCSU = 1/4 tcyc + 50 ns tPCSU 300 — 175 — 133 — ns
Reset input pulse width(2)
To guarantee external reset vector
Minimum input time can be preempted by internal reset PWRSTL 8
1—
—8
1—
—8
1—
—tcyc
Mode programming setup time tMPS 2—2—2—
tcyc
Mode programming hold time tMPH 10 — 10 — 10 — ns
Interrupt pulse width, PWIRQ = tcyc + 20 ns
IRQ edge-sensitive mode PWIRQ 1020 — 520 — 353 — ns
Wait recovery startup time tWRS — 4—4—4tcyc
Timer pulse width PWTIM = tcyc + 20 ns
Input capture pulse
Accumulator input PWTIM 1020 — 520 — 353 — ns
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Section 5.
Input/Output (I/O) Ports for further details.
Notes:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
PA7(2) (3)
PA7(1) (3)
PA0–PA3(2)
PA0–PA3(1)
PWTIM
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 123
Electrical Charac te rist ics
Control Timing
Figure 9-4. POR and External Reset Timing Diagram
tPCSU
ADDRESS
MODA, MODB
E
EXTAL
VDD
RESET
4064 tcyc
FFFEFFFEFFFE NEW
PC
FFFE FFFF FFFEFFFEFFFE NEW
PC
FFFE FFFFFFFE
tMPH
PWRSTL
tMPS
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Data Sheet MC68HC711D3 — Rev. 2
124 Electrical Characteristics MOTOROLA
Electrical Characteristics
Figure 9-5. STOP Recovery Timing Diagram
PWIRQ
tSTOPDELAY
(3)
IRQ(1)
IRQ(2)
or XIRQ
E
SP – 8SP – 8 FFF2
(FFF4) NEW
PC
STOP
ADDR
STOP
ADDR + 1
ADDRESS(4) STOP
ADDR STOP
ADDR + 1
STOP
ADDR + 1
STOP
ADDR + 1
STOP
ADDR + 2 SP…SP–7
FFF3
(FFF5)
OPCODE
Resume program with instruction which follows the STOP instruction.
Notes:
ADDRESS(5)
RESET
1. Edge sensitive IRQ pin (IRQE bit = 1)
2. Edge sensitive IRQ pin (IRQE bit = 0)
3. tSTOPDELAY = 4064 tcyc if DLY bit = 1 or 4 tcyc if DLY = 0.
4. XIRQ with X bit in CCR = 1.
5. IRQ or (XIRQ with X bit in CCR = 0)
AS
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 125
Electrical Charac te rist ics
Control Timing
Figure 9-6. WAIT Recovery Timing Diagram
tPCSU
PCL PCH, YL, YH, XL, XH, A, B, CCR
STACK REGISTERS
E
R/W
ADDRESS WAIT
ADDR WAIT
ADDR + 1
IRQ, XIRQ,
OR INTERNAL
INTERRUPTS
Note: RESET also causes recovery from WAIT.
SP SP – 1 SP – 2…SP – 8 SP – 8 SP – 8…SP – 8 SP – 8 SP – 8 SP – 8
VECTOR
ADDR + 1
NEW
PC
tWRS
VECTOR
ADDR
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Data Sheet MC68HC711D3 — Rev. 2
126 Electrical Characteristics MOTOROLA
Electrical Characteristics
Figure 9-7. Interrupt Timing Diagram
E
PWIRQ
IRQ(1)
IRQ(2), XIRQ
tPCSU
OR INTERNAL
INTERRUPT
ADDRESS SP SP – 3 SP – 6 SP – 8 SP – 8 NEW
PC
NEXT
OPCODE
NEXT
OP + 1
VECTOR
ADDR + 1
VECTOR
ADDR
SP – 7
SP – 4 SP – 5
SP – 1 SP – 2
OP
CODE — — PCL PCH IYL IYH IXL IXH B A CCR — — VECT
MSB
VECT
LSB
OP
CODE
AS
ADDRESS
R/W
Notes:
1. Edge sensitive IRQ pin (IRQE bit = 1)
2. Level sensitive IRQ pin (IRQE bit = 0)
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Electrical Charac ter istics
Peripheral Port Timing
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 127
9.7 Peripheral Port Timing
Figure 9-8. Port Write Timing Diagram
Figure 9-9. Port Read Timing Diagram
Characteristic(1) Symbol 1.0 MHz 2.0 MHz 3.0 MHz Unit
Min Max Min Max Min Max
Frequency of operation (E-clock frequency) fO1.0 1.0 2.0 2.0 3.0 3.0 MHz
E-clock period tCYC 1000 — 500 — 333 — ns
Peripheral data setup time(2)
MCU read of ports A, B, C, and D tPDSU 100 — 100 — 100 — ns
Peripheral data hold time(2)
MCU read of ports A, B, C, and D tPDH 50 — 50 — 50 — ns
Dela y time, peripheral data write
MCU write to port A
MCU writes to ports B, C, and D
tPWD = 1/4 tcyc + 150 ns
tPWD —
—
200
350
—
—
200
225
—
—
200
183 ns
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).
tPWD
E
MCU WRITE TO PORT
PREVIOUS PORT DATA
PREVIOUS PORT DATA
NEW DATA VALID
NEW DATA VALID
PORTS
B, C, D
PORT A
tPWD
tPDH
E
MCU READ OF PORT
tPDSU
PORTS
A, B, C, D
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Electrical Characteristics
Data Sheet MC68HC711D3 — Rev. 2
128 Electrical Characteristics MOTOROLA
9.8 Expansion Bus Timing
Num Characteristic(1) Symbol 1.0 MHz 2.0 MHz 3.0 MHz Unit
Min Max Min Max Min Max
Frequency of operation (E-clock frequency) fOdc 1.0 dc 2.0 dc 3.0 MHz
1 Cycle time tcyc 1000 — 500 — 333 — ns
2Pulse width, E low, PWEL = 1/2 tcyc — 23 ns PWEL 477 — 227 — 146 — ns
3Pulse width, E high, PWEH = 1/2 tcyc – 28 ns PWEH 472 — 222 — 141 — ns
4A E and AS rise time tr—20—20—20ns
4B E and AS fall time tf—20—20—15ns
9Address hold time(2)a, tAH = 1/8 tcyc – 29.5 ns tAH 95.5 — 33 — 26 — ns
12 Non-muxed address valid time to E rise
tAV = PWEL – (tASD + 80 ns)(2)a tAV 281.5 — 94 — 54 — ns
17 Read data setup time tDSR 30 — 30 — 30 — ns
18 Read data hold time (max = tMAD)t
DHR 0 145.5 0 83 0 51 ns
19 Write data delay time, tDDW = 1/8 tcyc + 65.5 ns(2)a tDDW — 190.5 — 128 — 71 ns
21 Write data hold time, tDHW = 1/8 tcyc – 29.5 ns(2)a tDHW 95.5 — 33 — 26 — ns
22 Muxed address valid time to E rise
tAVM = PWEL – (tASD + 90 ns)(2)a tAVM 271.5 — 84 — 54 — ns
24 Muxed ad dress valid time to AS fall
tASL = PWASH – 70 ns tASL 151 — 26 — 13 — ns
25 Muxed address hold time, tAHL = 1/8 tcyc – 29.5 ns(2)b tAHL 95.5 — 33 — 31 — ns
26 Delay time, E to AS rise, tASD = 1/8 tcyc – 9.5 ns(2)a tASD 115.5 — 53 — 31 — ns
27 Pulse width, AS high, PWASH = 1/4 tcyc – 29 ns PWASH 221 — 96 — 63 — ns
28 Delay time, AS to E rise, tASED = 1/8 tcyc – 9.5 ns(2)b tASED 115.5 — 53 — 31 — ns
29 MPU address access time(2)a
tACCA = tcyc – (PWEL– tAVM) – tDSR – tftACCA 744.5 — 307 — 196 — ns
35 MPU access time , tACCE = PWEH – tDSR tACCE — 442 — 192 — 111 ns
36 Muxed address delay (previous cycle MPU read)
tMAD = tASD + 30 ns(2)a(3) tMAD 145.5 — 83 — 51 — ns
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tCYC in the above formulas, where applicable:
(a) (1-dc) × 1/4 tCYC
(b) dc × 1/4 tCYC
Where:
DC is the decimal value of duty cycle percentage (high time).
3. Formula only for dc to 2 MHz.
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Electrical Charac ter istics
Expansion Bus Timing
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 129
Figure 9-10. Multiplexed Expansion Bus Timing Diagram
E
AS
1
4
9
ADDRESS/DATA
(MULTIPLEXED)
READ
WRITE
12
2 3
4
44
29
35 17
18
19 21
25
24
27
36
22
26 28
ADDRESS
ADDRESS
DATA
DATA
R/W, ADDRESS
(NON-MUX)
Note: Measurement points shown are 20% and 70% of VDD.
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Electrical Characteristics
Data Sheet MC68HC711D3 — Rev. 2
130 Electrical Characteristics MOTOROLA
9.9 Serial Peripheral Interface Timing
Num Characteristic(1) Symbol 2.0 MHz 3.0 MHz Unit
Min Max Min Max
Operating frequency
Master
Slave fop(m)
fop(s)
dc
dc 0.5
2.0 dc
dc 0.5
3.0 fop
MHz
1Cycle time
Master
Slave tcyc(m)
tCYC(s)
2.0
500 —
—2.0
333 —
—tcyc
ns
2Enable lead time
Master(2)
Slave tlead(m)
tlead(s)
—
250 —
——
240 —
—ns
3Enable lag time
Master(2)
Slave tlag(m)
tlag(s)
—
250 —
——
240 —
—ns
4Clock (SCK) high time
Master
Slave tw(SCKH)m
tw(SCKH)s
340
190 —
—227
127 —
—ns
5Clock (SCK) low time
Master
Slave tw(SCKL)m
tw(SCKL)s
340
190 —
—227
127 —
—ns
6Data setup time (inputs)
Master
Slave tsu(m)
tsu(s)
100
100 —
—100
100 —
—ns
7Data hold time (inputs)
Master
Slave th(m)
th(s)
100
100 —
—100
100 —
—ns
8Access time (time to data active from high-impedance state)
Slave ta0 120 0 120 ns
9Disable time (hold time to high-impedance state)
Slave tdis — 240 — 167 ns
10 Data valid (after enable edge)(3) tv(s) — 240 — 167 ns
11 Da ta hold time (outputs) (after enable edge) tho 0—0—ns
12 Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)trm
trs
—
—100
2.0 —
—100
2.0 ns
µs
13 Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)tfm
tfs
—
—100
2.0 —
—100
2.0 ns
µs
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins.
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Electrical Charac ter istics
Serial Peripheral Interface Timing
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Electrical Characteristics 131
Figure 9-11. SPI Master Timing (CPHA = 0)
Figure 9-12. SPI Master Timing (CPHA = 1)
SEE
NOTE
Note: This first clock edge is generated internally but is not seen at the SCK pin.
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
(INPUT)
1
SEE
NOTE
11
MSB IN
BIT 6 - - - -1
LSB IN
MASTER MSB OUT MASTER LSB OUT
BIT 6 - - - -1
10
12
13
SS IS HELD HIGH ON MASTER
5
4
13
12
11 (REF)10 (REF)
13
4
512
Note: This last clock edge is generated internally but is not seen at the SCK pin.
4
5
5
4
1
SEE
NOTE
11
67
MSB IN LSB IN
MASTER MSB OUT MASTER LSB OUTBIT 6 - - - -1
10
13
12
12
13
SCK (CPOL = 0)
(OUTPUT)
SCK (CPOL = 1)
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
(INPUT) SS IS HELD HIGH ON MASTER
SEE
NOTE
12
13
BIT 6 - - - -1
11 (REF)10 (REF)
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Electrical Characteristics
Data Sheet MC68HC711D3 — Rev. 2
132 Electrical Characteristics MOTOROLA
Figure 9-13. SPI Slave Timing (CPHA = 0)
Figure 9-14. SPI Slave Timing (CPHA = 1)
Note: Not defined but normally MSB of character just received
4
2
5
5
4
1
8
SEE
NOTE
MSB OUT
SLAVE SLAVE LSB OUT
6 7
MSB IN
10
BIT 6 - - - -1 LSB IN
11
1213 3
9
SCK (CPOL = 0)
(INPUT)
SCK (CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
SS
(INPUT)
11
12 13
BIT 6 - - - -1
Note: Not defined but normally LSB of character previously transmitted
4
2
10
6 7
5
5
4
1
8
MSB IN
SEE
NOTE MSB OUT
10
SLAVE
BIT 6 - - - -1 LSB IN
SLAVE LSB OUT
11
13 12
12 13
3
9
SCK (CPOL = 0)
(INPUT)
SCK (CPOL = 1)
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
SS
(INPUT)
BIT 6 - - - -1
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Ordering Information and Mechanical Specifications 133
Data Sheet — MC68HC711D3
Section 10. Ordering Information and Mechanical Specifications
10.1 Introduction
This section provides ordering information for the MC68HC711D3. In addition,
mechanical specifications are provided for the following packaging options:
• 40-pin plastic dual in-line package (DIP)
• 44-pin plastic leaded chip carrier (PLCC)
• 44-pin plastic quad flat pack (QFP)
10.2 Ordering Information
Table 10-1. MC Order Numbers
Package Type Temperature MC Order Number
2 MHz 3 MHz
40-pin DIP –40 to +85°C MC68HC711D3CP2 MC68 HC711D3CP3
44-pin PLCC –40 to +85°C MC68HC711D3CFN2 MC68HC711D3CFN3
–40 to +105°C MC68H C711D3VFN2 MC68HC711D3VFN3
44-pin QFP –40 to +85°C MC68HC711D3CFB2 MC68HC711D3CFB3
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Ordering Information and Mechanical Specifications
Data Sheet MC68HC711D3 — Rev. 2
134 Ordering Information and Mechanical Specifications MOTOROLA
10.3 40-Pin DIP (Case 711-03)
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 ( 0.010 ) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
120
40 21
B
AC
SEATING
PLANE
DFGH K
N
M
J
LDIM MIN MAX MIN MAX
INCHESMILLIMETERS
A51.69 52.45 2.035 2.065
B13.72 14.22 0.540 0.560
C3.94 5.08 0.155 0.200
D0.36 0.56 0.014 0.022
F1.02 1.52 0.040 0.060
G2.54 BSC 0.100 BSC
H1.65 2.16 0.065 0.085
J0.20 0.38 0.008 0.015
K2.92 3.43 0.115 0.135
L15.24 BSC 0.600 BSC
M0 15 0 15
N0.51 1.02 0.020 0.040
°° °°
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Ordering Inform a tio n an d M ech a nic al S pe cific at ion s
44-Pin PLCC (Case 777-02)
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA Ordering Information and Mechanical Specifications 135
10.4 44-Pin PLCC (Case 777-02)
-N-
-L- -M-
D
Y
D
K
VW
144
BRK
B
Z
U
X
VIEW D-D
S
L-M
M
0.007(0.180) N S
T
S
L-M
M
0.007(0.180) N S
T
G1
S
L-M
S
0.010 (0.25) N S
T
K1
F
H
S
L-M
M
0.007(0.180) N S
T
Z
G
G1
R
A
EJ
VIEW S
C
S
L-M
M
0.007(0.180) N S
T
S
L-M
M
0.007(0.180) N S
T
0.004 (0.10)
-T- SEATING
PLANE
VIEW S
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.685 0.695 17.40 17.65
B0.685 0.695 17.40 17.65
C0.165 0.180 4.20 4.57
E0.090 0.110 2.29 2.79
F0.013 0.019 0.33 0.48
G0.050 BSC 1.27 BSC
H0.026 0.032 0.66 0.81
J0.020 0.51
K0.025 0.64
R0.650 0.656 16.51 16.66
U0.650 0.656 16.51 16.66
V0.042 0.048 1.07 1.21
W0.042 0.048 1.07 1.21
X0.042 0.056 1.07 1.42
Y0.020 0.50
Z2°10°
G1 0.610 0.630 15.50 16.00
K1 0.040 1.02
S
L-M
S
0.010 (0.25) N S
T
S
L-M
M
0.007(0.180) N S
T
2°10°
NOTES:
1. DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETERMINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7. DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940136). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
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Ordering Information and Mechanical Specifications
Data Sheet MC68HC711D3 — Rev. 2
136 Ordering Information and Mechanical Specifications MOTOROLA
10.5 44-Pin QFP (Case 824A-01)
NOTES:
1. 1. DIMENSIONING AND TO LERANCING PER ANSI
Y14.5M, 1982.
2. 2. CONTROLLING DIMENSION: MILLIMETER.
3. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT
D ATUM PLANE -H-.
5. 5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -C-.
6. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMA TCH AND ARE DETERMINED
AT DATUM PLANE -H-.
7. 7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) T O TAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
L
33
34
23
22
44
111
12
DETAIL A
-D-
-A-
A
S
A-B
M
0.20 (0.008) D S
C
S
A-B
M
0.20 (0.008) D S
H
0.05 (0.002) A-B
S
B
S
A-B
M
0.20 (0.008) D S
C
S
A-B
M
0.20 (0.008) D S
H
0.05 (0.002) A-B
V
L
-B-
-C-
SEATING
PLANE
M
M
E
HG
C-H- DATUM
PLANE
DETAIL C
0.01 (0.004)
M
-H-
DATUM
PLANE
T
R
KQ
WX
DETAIL C
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.90 10.10 0.390 0.398
B9.90 10.10 0.390 0.398
C2.10 2.45 0.083 0.096
D0.30 0.45 0.012 0.018
E2.00 2.10 0.079 0.083
F0.30 0.40 0.012 0.016
G0.80 BSC 0.031 BSC
H--- 0.25 --- 0.010
J0.13 0.23 0.005 0.009
K0.65 0.95 0.026 0.037
L8.00 REF 0.315 REF
M5 10 5 10
N0.13 0.17 0.005 0.007
Q0 7 0 7
R0.13 0.30 0.005 0.012
S12.95 13.45 0.510 0.530
T0.13 --- 0.005 ---
U0 --- 0 ---
V12.95 13.45 0.510 0.530
W0.40 --- 0.016 ---
X1.6 REF 0.063 REF
DETAIL A
B
B
-A-, -B-, -D-
S
A-B
M
0.20 (0.008) D S
C
F
N
SECTION B-B
J
D
BA SE ME TAL
°°°°
°°°°
°°
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA MC68HC11D3 and MC68HC11D0 137
Data Sheet — MC68HC711D3
Appendix A. MC68HC11D3 and MC68HC11D0
A.1 Introduction
The MC68HC11D3 and MC68HC11D0 are read-only memory (ROM) based
high-performance microcontrollers (MCU) based on the MC68HC11E9 design.
Members of the Dx series are derived from the same mask and feature a
high-speed multiplexed bus capable of running at up to 3 MHz and a fully static
design that allows operations at frequencies to dc. The only difference between the
MCUs in the Dx series is whether the ROM has been tested and guaran teed.
The information contained in this document applies to both the MC68HC11D3 and
MC68HC11D0 with the differences given in this appendix.
Features of the MC68HC11D3 and MC68HC11D0 include:
• 4 Kbytes of on-chip ROM (MC68HC11D3)
• 0 bytes of on-chip ROM (MC68HC11D0)
• 192 bytes of on-chip random-access memory (RAM) all saved during
standby
• 16-bit timer system:
– Three input capture (IC) channels
– Four output compare (OC) channels
– One IC or OC software-selectable channel
• 32 input/output (I/O) pins:
– 26 bidirectional I/O pins
– 3 input-only pins
– 3 output-only pins
• Available in these packages:
– 44-pin plastic leaded chip carrier (PLCC)
– 44-pin quad flat pack (QFP)
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MC68HC11D3 and MC68HC11D0
Data Sheet MC68HC711D3 — Rev. 2
138 MC68HC11D3 and MC68HC11D0 MOTOROLA
A.2 Block Diagram
Figure A-1. MC68HC11D3 Block Diagram
PORT A
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
MODE CONTROL INTERRUPT CONTROL
MODA/LIR
MODB/VSTBY
RESET IRQ XIRQ XTAL EXTAL E
CLOCK LOGIC
OSCILLATOR
PAI/OC1
OC2/OC1
OC3/OC1
OC4/OC1
IC4/OC5/OC1
IC1
IC2
IC3
TIMER
PULSE ACCUMULATOR COP
PERIODIC INTERRUPT
MC68HC11D3 — 4 KBYTES ROM
PD7/R/W
PD6/AS
PD5
PD4
PD3
PD2
PD1
PD0
DATA DIRECTION REGISTER D
PORT D
DATA DIRECTION REGISTER C
PORT C
DATA DIRECTION REGISTER B
PORT B
A15
A14
A13
A12
A11
A10
A9
A8
A7/D7
A6/D6
A5/D5
A4/D4
A3/D3
A2/D2
A1/D1
A0/D0
MULTIPLEXED ADDRESS/DATA BUS
192 BYTES RAM
SERIAL
PERIPHERAL
INTERFACE
(SPI)
SERIAL
COMMUNICATIONS
INTERFACE
(SCI)
MC68HC11D3
CPU CORE
SS
SCK
MOSI
MISO
TxD RxD
VSS
VDD
EVSS
MC68HC11D0 — 0 BYTES ROM
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MC68HC11D3 and MC68HC11D0
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA MC68HC11D3 and MC68HC11D0 139
A.3 Pin Assignments
Figure A-2. Pin Assignments for 44-Pin PLCC
Figure A-3. Pin Assignments for 44-Pin QFP
PC4/A4/D4
PC5/A5/D5
PC6/A6/D6
PC7/A7/D7
XIRQ
PD7/R/W
PD6/AS
RESET
IRQ
PD0/RxD
PD1/TxD
PB2/A10
PB3/A11
PB4/A12
PB5/A13
PB6/A14
PB7
NC
PA0/IC3
PA1/IC2
PC3
PC2
PC1
PC0
VSS
EVSS
XTAL
EXTAL
E
MODA/LIR
MODB/VSTBY
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
VDD
PA7/PAI
PA6/OC2
PA5/OC3
PA4/OC4
PA3/IC4/OC5/OC1
PA2/IC1
7
8
9
10
11
12
13
14
15
16
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
6
5
4
3
2
1
44
43
42
41
40
17
PB1/A9
38
PB0/A8
39
PC4
PC5
PC6
PC7
XIRQ
PD7
PD6
RESET
IRQ
PD0
PD1
PB2
PB3
PB4
PB5
PB6
PB7
NC
PA0
PA1
PC3
PC2
PC1
PC0
EVSS
VSS
XTAL
EXTAL
E
MODA
MODB
PD2
PD3
PD4
PD5
VDD
PA7
PA6
PA5
PA4
PA3
PA2
2
3
4
5
6
7
8
9
10
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
43
42
41
40
39
38
37
36
35
34
PB1
32
PB0
1
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MC68HC11D3 and MC68HC11D0
Data Sheet MC68HC711D3 — Rev. 2
140 MC68HC11D3 and MC68HC11D0 MOTOROLA
A.4 Memory Map
Figure A-4. MC68HC11Dx(1) Memory Map
A.5 MC68HC11D3 and MC68HC11D0 Electrical Characteristics
The parameters given in Section 9. Electrical Characteristics apply to the
MC68HC11D3 and MC68HC11D0 with the exceptions given here.
A.5.1 Functional Operating Temperature Range
A.5.2 Thermal Characteristics
1. MC68HC11D0 only operates in expanded multi plexed mode and bootstrap mo de.
SINGLE
CHIP
SPECIAL SPECIAL
TEST
EXPANDED
192 BYTES STATIC RAM
INTERNAL REGISTERS AND I/O
SPECIAL MODES
INTERRUPT
VECTORS
4 KBYTES ROM (MC68HC11D3)
BOOT
ROM $BFC0
$BFFF
$BF00
$BFFF
$7000
$7FFF
$0040
$00FF
$0000
$003F
$0000
$7000
$8000
$B000
$FFFF
MULTIPLEXED BOOTSTRAP
EXTERNAL
EXTERNAL
(CAN BE MAPPED TO ANY 4-K BOUNDARY
USING INIT REGISTER)
(CAN BE MAPPED TO ANY 4-K BOUNDARY
USING THE INIT REGISTER)
PRESENT AT RESET AND CAN BE DISABLED BY
ROM ON BIT IN CONFIG REGISTER.
INTERRUPT VECTORS ARE EXTERNAL.
NORMAL MODES
INTERRUPT
VECTORS
4-KBYTES
ROM $FFC0
$FFFF
$FF00
$FFFF
Rating Symbol Value Unit
Operating temperature range
MC68HC11D0C TATL to TH
–40 to +85 °C
Characteristic Symbol Value Unit
Package thermal resistance (junction-to-ambient)
44-pin plastic leaded chip carrier (PLCC)
44-pin plastic quad flat pack (QFP ΘJA 50
85 °C/W
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MC68HC11D3 and MC68HC11D0
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA MC68HC11D3 and MC68HC11D0 141
A.6 Ordering Information
MCU Package Temperature MC Order Number
2 MHz 3 MHz
MC68HC11D3
(Custom ROM) 44-pin PLCC –40 to +85°C MC68HC11D3CFN2 MC68HC11D3CFN3
MC68HC11D0
(No ROM) 44-pin PLCC –40 to +85°C MC68HC11D0CFN2 MC68HC11D0CFN3
44-pin QFP –40 to +85°C MC68HC11D0CFB2 MC68HC11D0CFB3
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MC68HC11D3 and MC68HC11D0
Data Sheet MC68HC711D3 — Rev. 2
142 MC68HC11D3 and MC68HC11D0 MOTOROLA
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MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA MC68L11D0 143
Data Sheet — MC68HC711D3
Appendix B. MC68L11D0
B.1 Introduction
The MC68L11D0 is an extended-voltage version of the MC68HC11D0
microcontroller that can operate in applications that require supply voltages as low
as 3.0 volts. Operation is identical to that of the MC68HC11D0 (see App endix A.
MC68HC11D3 and MC68HC11D0) in all aspects other than electrical parameters,
as shown in this appendix.
Features of the MC68HC11D0 include:
• Suitable for battery-powered portable and hand-held applications
• Excellent for use in devices such as remote sensors and actuators
• Operating performance is same at 5 V and 3 V
B.2 MC68L11D0 Electrical Characteristics
The parameters given in Section 9. Electrical Characteristics apply to the
MC68L11D0 with the exceptions given here.
B.2.1 Functional Operating Temperature Range
B.2.2 DC Electrical Characteristics
Rating Symbol Value Unit
Operating temperature range TATL to TH
–20 to +70 °C
Characteristic(1) Symbol Min Max Unit
Output voltage(2) All outputs except XTAL
ILoad = ± 10.0 µA All outputs except XTAL, RESET, and MODA VOL
VOH
—
VDD – 0.1 0.1
— V
Output high vo ltage(1) All outputs except XTAL, R E SET, and MODA
ILoad = – 0.5 mA, VDD = 3.0 V
ILoad = – 0.8 mA, VDD = 4.5 V VOH VDD – 0.8 — V
Output low voltage All outputs except XTAL
ILoad = 1.6 mA, VDD = 5.0 V
ILoad = 1.0 mA, VDD = 3.0 V VOL — 0.4 V
The dc electri c al table continues on next page.
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MC68L11D0
Data Sheet MC68HC711D3 — Rev. 2
144 MC68L11D0 MOTOROLA
Input high v oltage All inputs except RESET
RESET VIH 0.7 x VDD
0.8 x VDD
VDD + 0.3
VDD + 0.3 V
Input low vo ltage All inputs VIL VSS – 0.3 0 .2 x VDD V
I/O ports, three-state leakage PA7, PA3, PC7–PC0,
VIn = VIH or VIL PD7–PD0, MODA/LIR, RESET IOZ — ±10 µA
Input leakage current
VIn = VDD or VSS PA2–PA0, IRQ, XIRQ
VIn = VDD or VSS MODB/VSTBY
IIn —
— ±1
±10 µA
RAM standby voltage Power down VSB 2.0 VDD V
RAM standby current Power down ISB — 10 µA
Input capacitance PA2–PA0, IRQ, XIRQ, EXTAL
PA3, PA7, PC7–PC0, PD7–PD0, MODA/LIR, RESET CIn —
— 8
12 pF
Output load capacitance All outputs exce pt PD4–PD1
PD4–PD1 CL—
—90
100 pF
Total supply current(3)
RUN:
Single-chip mode
VDD = 5.5 V
VDD = 3.0 V
Expanded multiplexed mode
VDD = 5.5 V
VDD = 3.0 V
WAIT — All peripheral functions shut down:
Single-chip mode
VDD = 5.5 V
VDD = 3.0 V
Expanded multiplexed mode
VDD = 5.5 V
VDD = 3.0 V
STOP — No clocks, single-chip mode:
VDD = 5.5 V
VDD = 3.0 V
IDD
WIDD
SIDD
8
4
14
7
3
1.5
5
2.5
50
25
15
8
27
14
6
3
10
5
50
25
mA
mA
µA
Power di ssip at i on
Single-chip mode
VDD = 5.5 V
VDD = 3.0 V
Expanded multiplexed mode
VDD = 5.5 V
VDD = 3.0 V
PD44
12
77
21
85
24
150
42
mW
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. VOH specification for RESET and MODA is not applicable because they are open-drain pins. VOH specification is not
applicable to ports C and D in wired-OR mode.
3. EXTAL is driven with a square wave, and
tcyc = 1000 ns for 1 MHz rating;
tcyc = 500 ns for 2 MHz rating;
VIL ≤ 0.2 V;
VIH ≥ VDD – 0.2 V;
No dc loads
Characteristic(1) Symbol Min Max Unit
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MC68L11D0
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA MC68L11D0 145
B.2.3 Control Timing
B.2.4 Peripheral Port Timing
Characteristic(1) Symbol 1.0 MHz 2.0 MHz Unit
Min Max Min Max
Frequen cy of operation fOdc 1.0 dc 2.0 MHz
E-clock period tcyc 1000 — 500 — ns
Crystal frequency fXTAL — 4.0 — 8.0 MHz
External oscillator frequency 4 fOdc 4.0 dc 8.0 MHz
Processor control setup time
tPCSU = 1/4 tcyc + 50 ns tPCSU 325 — 200 — ns
Reset input pulse width(2)
To guarantee exter nal reset vector
Minimum input time can be preempted by internal reset PWRSTL 8
1—
—8
1—
—tcyc
Interrupt pulse width, PWIRQ = tcyc + 20 ns
IRQ edge-sensitive mode PWIRQ 1020 — 520 — ns
Wait recovery startup time tWRS —4—4
tcyc
Timer pulse width PWTIM = tcyc + 20 ns
Input capture pulse accumula tor input PWTIM 1020 — 520 — ns
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Section 4.
Resets, Interrupts, and Low-Power Modes for further details.
Characteristic(1) Symbol 1.0 MHz 2.0 MHz Unit
Min Max Min Max
Frequency of operation (E-clock frequency) fOdc 1.0 dc 2.0 MHz
E-clock period tcyc 1000 — 500 — ns
Peripheral data setup time(2)
MCU read of ports A, B, C, and D tPDSU 100 — 100 — ns
Peripheral data hold time(2)
MCU read of ports A, B, C, and D tPDH 50 — 50 — ns
Dela y time, peripheral data write
MCU write to port A
MCU writes to ports B, C, and D
tPWD = 1/4 tcyc + 150 ns
tPWD —
—
200
350
—
—
200
225 ns
1. VDD = 3.0 Vd to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).
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MC68L11D0
Data Sheet MC68HC711D3 — Rev. 2
146 MC68L11D0 MOTOROLA
B.2.5 Expansion Bus Timing
Num Characteristic(1) Symbol 1.0 MHz 2.0 MHz Unit
Min Max Min Max
Frequency of op eration (E-clock fr equency) fOdc 1.0 dc 2.0 MHz
1 Cycle time tcyc 1000 — 500 — ns
2Pulse width, E low, PWEL = 1/2 tcyc — 23 ns PWEL 475 — 225 — ns
3Pulse width, E high, PWEH = 1/2 tcyc – 28 ns PWEH 470 — 220 — ns
4A E and AS rise time tr—25—25ns
4B E and AS fall time tf—25—25ns
9Address hold time(2)a, tAH = 1/8 tcyc – 29.5 ns tAH 95 — 33 — ns
12 Non-muxed address valid time to E rise
tAV = PWEL – (tASD + 80 ns)(2)a tAV 275 — 88 — ns
17 Read data setup time tDSR 30 — 30 — ns
18 Read data hold time (max = tMAD)t
DHR 0 150 0 88 ns
19 Write data delay time, tDDW = 1/8 tcyc + 65.5 ns(2)a tDDW — 195 — 133 ns
21 Write data hold time, tDHW = 1/8 tcyc – 29.5 ns(2)a tDHW 95 — 33 — ns
22 Muxe d address valid time to E rise
tAVM = PWEL – (tASD + 90 ns)(2)a tAVM 265 — 78 — ns
24 Muxe d address valid time to AS fall
tASL = PWASH – 70 ns tASL 150 — 25 — ns
25 Muxed address hold time, tAHL = 1/8 tcyc – 29.5 ns(2)b tAHL 95 — 33 — ns
26 Delay time, E to AS rise, tASD = 1/8 tcyc – 9.5 ns(2)a tASD 120 — 58 — ns
27 Pulse width, AS high, PWASH = 1/4 tcyc – 29 ns PWASH 220 — 95 — ns
28 Delay time, AS to E rise, tASED = 1/8 tcyc – 9.5 ns(2)b tASED 120 — 58 — ns
29 MPU address access time(2)a
tACCA = tcyc – (PWEL– tAVM) – tDSR – tftACCA 735 — 298 — ns
35 MPU access time , tACCE = PWEH – tDSR tACCE — 440 — 190 ns
36 Muxed address delay (pr evious cycle MPU read)
tMAD = tASD + 30 ns(2)a tMAD 150 — 88 — ns
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Input clocks with duty cycles other than 50% affect bus performance. Timing parameters affected by input clock duty cycle
are identified by (a) and (b). To recalculate the approximate bus timing values, substitute the following expressions in place
of 1/8 tCYC in the above formulas, where applicable:
(a) (1-dc) × 1/4 tCYC
(b) dc × 1/4 tCYC
Where:
DC is the decimal value of duty cycle percentage (high time).
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MC68L11D0
MC68HC711D3 — Rev. 2 Data Sheet
MOTOROLA MC68L11D0 147
B.2.6 Serial Peripheral Interface Timing
Num Characteristic(1) Symbol 1.0 MHz 2.0 MHz Unit
Min Max Min Max
Operating frequency
Master
Slave fop(m)
fop(s)
dc
dc 0.5
1.0 dc
dc 0.5
2.0 fop
MHz
1Cycle time
Master
Slave tcyc(m)
tCYC(s)
2.0
1000 —
—2.0
500 —
—tcyc
ns
2Enable lead time
Master(2)
Slave tlead(m)
tlead(s)
—
500 —
——
250 —
—ns
3Enable lag time
Master(2)
Slave tlag(m)
tlag(s)
—
500 —
——
250 —
—ns
4Clock (SCK) high time
Master
Slave tw(SCKH)m
tw(SCKH)s
680
380 —
—340
190 —
—ns
5Clock (SCK) low time
Master
Slave tw(SCKL)m
tw(SCKL)s
680
380 —
—340
190 —
—ns
6Data setup time (inputs)
Master
Slave tsu(m)
tsu(s)
100
100 —
—100
100 —
—ns
7Data hold time (inputs)
Master
Slave th(m)
th(s)
100
100 —
—100
100 —
—ns
8Access time (time to data active from high-impedance state)
Slave ta0 120 0 120 ns
9Disable time (hold time to high-impedance state)
Slave tdis — 240 — 240 ns
10 Data valid (after enable edge)(3) tv(s) — 240 — 240 ns
11 Data hold time (outputs) (after ena ble edge) tho 0—0—ns
12 Rise time (20% VDD to 70% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)trm
trs
—
—100
2.0 —
—100
2.0 ns
µs
13 Fall time (70% VDD to 20% VDD, CL = 200 pF)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)tfm
tfs
—
—100
2.0 —
—100
2.0 ns
µs
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
2. Signal production depends on software.
3. Assumes 100 pF load on all SPI pins.
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MC68L11D0
Data Sheet MC68HC711D3 — Rev. 2
148 MC68L11D0 MOTOROLA
B.3 Ordering Information
Package Frequency Features MC Order Number
44-pin PLCC 2 MHz No ROM MC68L11D0FN2
44-pin QFP 2 MHz No ROM MC68L11D0FB2
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MC68HC711D3/D
Rev. 2
9/2003
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