Philips Semiconductors Product specification Dual N-channel enhancement mode TrenchMOSTM transistor FEATURES PHN203 SYMBOL * Dual device * Low threshold voltage * Fast switching * Logic level compatible * Surface mount package QUICK REFERENCE DATA d1 d1 VDS = 25 V d2 d2 ID = 6.3 A RDS(ON) 30 m (VGS = 10 V) RDS(ON) 55 m (VGS = 4.5 V) s1 GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHN203 is supplied in the SOT96-1 (SO8) surface mounting package. s2 g2 g1 PINNING PIN SOT96-1 DESCRIPTION 1 source 1 2 gate 1 3 source 2 4 gate 2 5,6 drain 2 7,8 drain 1 pin 1 index 8 7 6 5 1 2 3 4 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS VDS Repetitive peak drain-source voltage Continuous drain-source voltage Drain-gate voltage Gate-source voltage Drain current per MOSFET1 Tj = 25 C to 150C VDS VDGR VGS ID ID IDM Ptot Tstg, Tj Drain current per MOSFET (both MOSFETs conducting)1 Drain current per MOSFET (pulse peak value) Total power dissipation (either or both MOSFETs conducting)1 Storage & operating temperature RGS = 20 k Ta = 25 C Ta = 70 C Ta = 25 C Ta = 70 C Ta = 25 C Ta = 25 C Ta = 70 C MIN. MAX. UNIT - 25 V - 25 25 20 6.3 5 4.4 3.5 25 V V V A A A A A - 55 2 1.3 150 W W C 1 Surface mounted on FR4 board, t 10 sec January 1999 1 Rev 1.000 Philips Semiconductors Product specification Dual N-channel enhancement mode TrenchMOSTM transistor PHN203 THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-a Surface mounted on FR4 board, t 10 sec; either or both MOSFETs conducting Surface mounted on FR4 board; either or both MOSFETs conducting Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient TYP. MAX. UNIT - 62.5 K/W 150 - K/W MIN. MAX. UNIT - 20 mJ - 6.3 A AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS EAS Non-repetitive avalanche energy (per MOSFET) Unclamped inductive load, IAS = 6.3 A; tp = 0.2 ms; Tj prior to avalanche = 25C; VDD 15 V; RGS = 50 ; VGS = 10 V IAS Non-repetitive avalanche current (per MOSFET) ELECTRICAL CHARACTERISTICS Tj= 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS VGS = 0 V; ID = 10 A; VGS(TO) Drain-source breakdown voltage Gate threshold voltage MIN. Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C 2 27 40 43 9.7 60 0.1 10 2.8 3.2 30 55 51 100 10 100 V V V V V m m m S nA A nA IGSS VGS = 10 V; ID = 4 A VGS = 4.5 V; ID = 2 A VGS = 10 V; ID = 4 A; Tj = 150C Forward transconductance VDS = 20 V; ID = 4 A Zero gate voltage drain VDS = 20 V; VGS = 0 V; current VDS = 20 V; VGS = 0 V; Tj = 150C Gate source leakage current VGS = 20 V; VDS = 0 V Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 4 A; VDD = 20 V; VGS = 10 V - 20 1.9 6.1 - nC nC nC td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 20 V; RD = 18 ; VGS = 10 V; RG = 6 Resistive load - 8 11 31 17 - ns ns ns ns Ld Ls Internal drain inductance Internal source inductance Measured from drain lead to centre of die Measured from source lead to source bond pad - 2.5 5 - nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 611 260 137 - pF pF pF RDS(ON) gfs IDSS Drain-source on-state resistance 25 22.5 1 0.4 5 - TYP. MAX. UNIT January 1999 2 Rev 1.000 Philips Semiconductors Product specification Dual N-channel enhancement mode TrenchMOSTM transistor PHN203 REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER CONDITIONS Ta = 25 C VSD Continuous source diode current (per MOSFET) Pulsed source diode current (per MOSFET) Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge IS ISM MIN. TYP. MAX. UNIT - - 2.85 A - - 25 A IF = 1.25 A; VGS = 0 V - 0.75 1 V IF = 1.25 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V - 35 24 - ns nC Normalised Power Dissipation, PD (%) 100 120 PHN203 Peak Pulsed Drain Current, IDM (A) tp = 10 us RDS(on) = VDS/ ID 100 100 us 10 1 ms 80 10 ms 60 1 100 ms 40 0.1 20 10 s 0 0 25 50 75 100 125 0.01 150 0.1 Ambient Temperature, Ta (C) Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ta) 1 10 Drain-Source Voltage, VDS (V) 100 Fig.3. Safe operating area. Ta = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Drain Current, ID (%) 100 120 PHN203 Peak Pulsed Drain Current, IDM (A) D = 0.5 100 10 80 0.2 0.1 0.05 0.02 1 60 P D single pulse 40 tp D = tp/T 0.1 20 T 0.01 1E-06 0 0 25 50 75 100 125 150 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ta); conditions: VGS 4.5 V January 1999 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 Pulse width, tp (s) Ambient Temperature, Ta (C) Fig.4. Transient thermal impedance; Zth j-a = f(t); parameter D = tp/T 3 Rev 1.000 Philips Semiconductors Product specification Dual N-channel enhancement mode TrenchMOSTM transistor Drain Current, ID (A) 10 10V 9 PHN203 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHN203 Tj = 25 C VGS = 5 V 3.6 V 8 7 3.4 V 6 5 3.2 V 4 3 3V 2 2.8 V 1 2.6 V 0 VDS > ID X RDS(ON) Tj = 25 C 150 C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Drain-Source Voltage, VDS (V) 1.8 2.6V 2.8V 3V 3.2 V 0.4 2 3 4 5 6 7 Drain current, ID (A) 8 9 10 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID) PHN203 Drain-Source On Resistance, RDS(on) (Ohms) 0.5 1 2 Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS PHN203 Transconductance, gfs (S) 2 a SOT223 30V Trench Normalised RDS(ON) = f(Tj) Tj = 25 C 1.5 3.4V 0.3 3.6V 1 0.2 0.5 0.1 VGS =5 V 10V 0 0 1 2 3 4 5 6 Drain Current, ID (A) 7 8 9 0 -50 10 Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS 50 Tj / C 100 150 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj) VGS(TO) / V PHN203 Drain current, ID (A) 0 10 4 VDS > ID X RDS(ON) 9 8 7 3 max. 6 5 4 typ. 2 150 C Tj = 25 C 3 2 min. 1 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 -60 -40 -20 Gate-source voltage, VGS (V) Fig.7. Typical transfer characteristics. ID = f(VGS) January 1999 0 20 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 4 Rev 1.000 Philips Semiconductors Product specification Dual N-channel enhancement mode TrenchMOSTM transistor PHN203 Sub-Threshold Conduction 1E-01 Source-Drain Diode Current, IF (A) PHN203 10 VGS = 0 V 9 1E-02 8 7 min 1E-03 typ 6 max 5 4 1E-04 150 C 3 Tj = 25 C 2 1 1E-05 0 0 1E-06 0 1 2 3 4 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C Non-repetitive Avalanche current, IAS (A) PHN203 10 PHN203 Capacitances, Ciss, Coss, Crss (pF) 0.9 Drain-Source Voltage, VSDS (V) 5 10000 25 C Tj prior to avalanche =125 C VDS 1000 Ciss tp ID Coss Crss 1 1E-06 100 0.1 1 10 Drain-Source Voltage, VDS (V) 100 Gate-source voltage, VGS (V) 1E-04 1E-03 1E-02 Avalanche time, tp (s) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1E-05 Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load PHN203 ID = 4A Tj = 25 C VDD = 20 V 0 5 10 15 20 Gate charge, QG (nC) 25 30 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) January 1999 5 Rev 1.000 Philips Semiconductors Product specification Dual N-channel enhancement mode TrenchMOSTM transistor PHN203 MECHANICAL DATA SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A max. A1 A2 mm inches UNIT A3 bp c D (1) E (2) 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 e HE 4.0 3.8 1.27 6.2 5.8 0.16 0.15 0.050 L Lp Q 1.05 1.0 0.4 0.7 0.6 0.244 0.039 0.028 0.041 0.228 0.016 0.024 v w y Z (1) 0.25 0.25 0.1 0.7 0.3 0.01 0.01 0.004 0.028 0.012 o 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03S MS-012AA EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-05-22 Fig.16. SOT96 surface mounting package. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8". January 1999 6 Rev 1.000 Philips Semiconductors Product specification Dual N-channel enhancement mode TrenchMOSTM transistor PHN203 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. January 1999 7 Rev 1.000 1 of 2 Select & Go... Go to Philips Semiconductors' home page Start part Catalog & Datasheets Information as of 2000-08-26 Catalog by Function Discrete semiconductors Audio Clocks and Watches Data communications Microcontrollers Peripherals Standard analog Video Wired communications Wireless communications Catalog by System Automotive Consumer Multimedia Systems Communications PC/PC-peripherals Cross reference PHN203; Dual N-channel enhancement mode TrenchMOS transistor * Description * Features * Datasheet * Products, packages, availability and ordering * Find similar products * Support & tools Subscribe to eNews To be kept informed on PHN203, subscribe to eNews. * Description N-channel enhancement mode field-effect power transistor in a plastic envelope using 'trench' technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHN203 is supplied in the SOT96-1 (SO8) surface mounting package. Models Packages Application notes Features Selection guides Other technical documentation l End of Life information l Datahandbook system l l Relevant Links About catalog tree About search About this site Subscribe to eNews Catalog & Datasheets Search PHN203 PHN203 l Dual device Low threshold voltage Fast switching Logic level compatible Surface mount package Datasheet Type nr. Title Publication release date Datasheet status Page count File size (kB) Datasheet 2 of 2 Type nr. Title PHN203 Dual N-channel enhancement mode TrenchMOS transistor release date 01-Jan-99 Datasheet status Product Specification count 7 (kB) 98 Datasheet Download Products, packages, availability and ordering Partnumber North American Partnumber Order code (12nc) marking/packing package device status PHN203 PHN203 /T3 9340 554 42118 Standard Marking * Reel Pack, SMD, 13" SOT96 buy online Full production Find similar products: PHN203 links to the similar products page containing an overview of products that are similar in function or related to the part number(s) as listed on this page. The similar products page includes products from the same catalog tree(s) , relevant selection guides and products from the same functional category. Support &tools Spice model of PHN203 Copyright (c) 2000 Royal Philips Electronics All rights reserved. Terms and conditions.