Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN203
TrenchMOSTM transistor
FEATURES SYMBOL QUICK REFERENCE DATA
• Dual device VDS = 25 V
• Low threshold voltage
• Fast switching ID = 6.3 A
• Logic level compatible
• Surface mount package RDS(ON) ≤ 30 mΩ (VGS = 10 V)
RDS(ON) ≤ 55 mΩ (VGS = 4.5 V)
GENERAL DESCRIPTION PINNING SOT96-1
N-channel enhancement mode PIN DESCRIPTION
field-effect power transistor in a
plastic envelope using ’trench’ 1 source 1
technology. The device has very
low on-state resistance. It is 2 gate 1
intended for use in dc to dc
converters and general purpose 3 source 2
switching applications. 4 gate 2
The PHN203 is supplied in the
SOT96-1 (SO8) surface mounting 5,6 drain 2
package. 7,8 drain 1
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS Repetitive peak drain-source Tj = 25 ˚C to 150˚C - 25 V
voltage
VDS Continuous drain-source voltage - 25 V
VDGR Drain-gate voltage RGS = 20 kΩ-25V
VGS Gate-source voltage - ± 20 V
IDDrain current per MOSFET1Ta = 25 ˚C - 6.3 A
Ta = 70 ˚C - 5 A
IDDrain current per MOSFET (both Ta = 25 ˚C - 4.4 A
MOSFETs conducting)1Ta = 70 ˚C - 3.5 A
IDM Drain current per MOSFET (pulse Ta = 25 ˚C - 25 A
peak value)
Ptot Total power dissipation (either or Ta = 25 ˚C - 2 W
both MOSFETs conducting)1Ta = 70 ˚C - 1.3 W
Tstg, TjStorage & operating temperature - 55 150 ˚C
d1
g1
s1
d1 d2
g2
d2
s2
1234
5678
pin 1 index
1 Surface mounted on FR4 board, t ≤ 10 sec
January 1999 1 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN203
TrenchMOSTM transistor
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
Rth j-a Thermal resistance junction Surface mounted on FR4 board, t ≤ 10 - 62.5 K/W
to ambient sec; either or both MOSFETs conducting
Rth j-a Thermal resistance junction Surface mounted on FR4 board; either or 150 - K/W
to ambient both MOSFETs conducting
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 6.3 A; - 20 mJ
energy (per MOSFET) tp = 0.2 ms; Tj prior to avalanche = 25˚C;
VDD ≤ 15 V; RGS = 50 Ω; VGS = 10 V
IAS Non-repetitive avalanche - 6.3 A
current (per MOSFET)
ELECTRICAL CHARACTERISTICS
Tj= 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 10 µA; 25 - - V
voltage Tj = -55˚C 22.5 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 1 2 2.8 V
Tj = 150˚C 0.4 - - V
Tj = -55˚C - 3.2 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 4 A - 27 30 mΩ
resistance VGS = 4.5 V; ID = 2 A - 40 55 mΩ
VGS = 10 V; ID = 4 A; Tj = 150˚C - 43 51 mΩ
gfs Forward transconductance VDS = 20 V; ID = 4 A 5 9.7 - S
IDSS Zero gate voltage drain VDS = 20 V; VGS = 0 V; - 60 100 nA
current VDS = 20 V; VGS = 0 V; Tj = 150˚C - 0.1 10 µA
IGSS Gate source leakage current VGS = ±20 V; VDS = 0 V - 10 100 nA
Qg(tot) Total gate charge ID = 4 A; VDD = 20 V; VGS = 10 V - 20 - nC
Qgs Gate-source charge - 1.9 - nC
Qgd Gate-drain (Miller) charge - 6.1 - nC
td on Turn-on delay time VDD = 20 V; RD = 18 Ω;-8-ns
trTurn-on rise time VGS = 10 V; RG = 6 Ω-11-ns
td off Turn-off delay time Resistive load - 31 - ns
tfTurn-off fall time - 17 - ns
LdInternal drain inductance Measured from drain lead to centre of die - 2.5 - nH
LsInternal source inductance Measured from source lead to source - 5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 20 V; f = 1 MHz - 611 - pF
Coss Output capacitance - 260 - pF
Crss Feedback capacitance - 137 - pF
January 1999 2 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN203
TrenchMOSTM transistor
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C, per MOSFET unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ISContinuous source diode Ta = 25 ˚C - - 2.85 A
current (per MOSFET)
ISM Pulsed source diode current - - 25 A
(per MOSFET)
VSD Diode forward voltage IF = 1.25 A; VGS = 0 V - 0.75 1 V
trr Reverse recovery time IF = 1.25 A; -dIF/dt = 100 A/µs; - 35 - ns
Qrr Reverse recovery charge VGS = 0 V; VR = 25 V - 24 - nC
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
a
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
a
); conditions: V
GS
≥
4.5 V
Fig.3. Safe operating area. T
a
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance;
Z
th j-a
= f(t); parameter D = t
p
/T
Normalised Power Dissipation, PD (%)
0
20
40
60
80
100
120
0 25 50 75 100 125 150
Ambient Temperature, Ta (C)
PHN203
0.01
0.1
1
10
100
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
10 s
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
Normalised Drain Current, ID (%)
0
20
40
60
80
100
120
0 25 50 75 100 125 150
Ambient Temperature, Ta (C)
PHN203
0.01
0.1
1
10
100
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Peak Pulsed Drain Current, IDM (A)
single pulse
D = 0.5
0.2 0.1
0.05 0.02
tp D = tp/T
D
P
T
January 1999 3 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN203
TrenchMOSTM transistor
Fig.5. Typical output characteristics, T
j
= 25 ˚C
.
I
D
= f(V
DS
); parameter V
GS
Fig.6. Typical on-state resistance, T
j
= 25 ˚C
.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.8. Typical transconductance, T
j
= 25 ˚C
.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
PHN203
0
1
2
3
4
5
6
7
8
9
10
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
2.6 V
2.8 V
3 V
3.6 V
Tj = 25 C
VGS = 5 V
3.2 V
3.4 V
10V
PHN203
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
012345678910
Drain current, ID (A)
Transconductance, gfs (S)
VDS > ID X RDS(ON)
Tj = 25 C
150 C
PHN203
0
0.1
0.2
0.3
0.4
0.5
012345678910
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS =5 V
2.6V 2.8V
3.4V
10V
Tj = 25 C
3.6V
3.2 V
3 V
-50 0 50 100 150
0
0.5
1
1.5
2SOT223 30V Trench
Tj / C
aNormalised RDS(ON) = f(Tj)
PHN203
0
1
2
3
4
5
6
7
8
9
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
150 C
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
VGS(TO) / V
4
3
2
1
0
max.
typ.
min.
January 1999 4 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN203
TrenchMOSTM transistor
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
p
);
unclamped inductive load
012345
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01 Sub-Threshold Conduction
typmin max
PHN203
0
1
2
3
4
5
6
7
8
9
10
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Drain-Source Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
150 C
VGS = 0 V
PHN203
100
1000
10000
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
PHN203
1
10
1E-06 1E-05 1E-04 1E-03 1E-02
Avalanche time, tp (s)
Non-repetitive Avalanche current, IAS (A)
25 C
VDS
ID tp
Tj prior to avalanche =125 C
PHN203
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0 5 10 15 20 25 30
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 4A
Tj = 25 C
VDD = 20 V
January 1999 5 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN203
TrenchMOSTM transistor
MECHANICAL DATA
Fig.16. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
UNIT A
max. A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 5.0
4.8 4.0
3.8 1.27 6.2
5.8 1.05 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
1.0
0.4
SOT96-1
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
4
5
pin 1 index
1
8
y
076E03S MS-012AA
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.20
0.19 0.16
0.15 0.050 0.244
0.228 0.028
0.024 0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
95-02-04
97-05-22
January 1999 6 Rev 1.000
Philips Semiconductors Product specification
Dual N-channel enhancement mode PHN203
TrenchMOSTM transistor
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
January 1999 7 Rev 1.000
1 of 2
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PHN203
Information as of 2000-08-26
PHN203; Dual N-channel enhancement mode TrenchMOS transistor
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Description
N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. The device has
very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.
The PHN203 is supplied in the SOT96-1 (SO8) surface mounting package.
Features
lDual device
lLow threshold voltage
lFast switching
lLogic level compatible
lSurface mount package
Datasheet
Type nr.
Title
Publication
release date
Datasheet status
Page
count
File
size
(kB)
Datasheet
2 of 2
Type nr.
Title
release date
Datasheet status
count
(kB)
Datasheet
PHN203 Dual N-channel enhancement mode
TrenchMOS transistor 01-Jan-99 Product
Specification 7 98 Download
Products, packages, availability and ordering
Partnumber North American
Partnumber Order code
(12nc) marking/packing package device status buy online
PHN203 PHN203 /T3 9340 554 42118 Standard Marking * Reel
Pack, SMD, 13" SOT96 Full production
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