DS04-28310-2E FUJITSU SEMICONDUCTOR DATA SHEET MB40730 is a low-power consumption, high-speed 10-bit D/A converter. The MB40730 is characterized by ECL (10 kH) compatible digital inputs, an analog output voltage from -2 to 0 V, and a maximum conversion rate of 60 MHz. It provides a reference voltage from a potential divider and band-gap reference, and can also use an external reference voltage. The MB40730 D/A converter is suitable for high-resolution TVs or VTRs. 20-PIN PLASTIC DIP e Resolution: 10 bits e Conversion characteristics: -Maximum conversion rate: 60 MHz (Minimum) -Linearity error: +0.1 % (Maximum) -Differential linearity error: +0.1 % (Maximum) @ Input and output: -Digital input voltage: ECL (10 kh) levels -Analog output voltage: 2 Vp-p (-2 V to 0 V) e Reference voltage: -VrouT1: Potential divider circuit (Vee 2/5.2) -Vrout2: Band-gap reference circuit (-2 V) (DIP-20P-M01) 20-PIN PLASTIC SOP Others: - Supply voltage: -5.2 V single power supply - Power dissipation: 180mW_ (Typical value at analog output voltage 2 Vp-p) 140 mW (Typical value at analog output voltage 1 Vp-p) ABSOLUTE MAXIMUM RATINGS (See NOTE) (Veca=Vecb=0 V, Ta=+25C) Parameter Symbol Value Unit Analog power supply voltage VEEA -7.0to0 Vv Digital power supply voltage VEED -7.0to 0 Vv Power supply voltage difference VEED-VEEA 1.0 Vv (FPT-20P-M01) Digital signal input voltage VID 0 to VEE Vv Storage Temperature Tstg -55 to +125 C NOTE: Permanent device damage may occur if the above Absolute Maximum Rat- ing are exceeded. Functional operation should be restricted to the condi- tions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device contains circuitry to protect the inputs against damage dueto high static voltages or electric fields. However, itis advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.MB40730 m PIN ASSIGNMENT (TOP VIEW) (MSB) Di Cyl 20 [CLK De cy2 19 [4 Vecp Ds [3 18 [ Veca Da [cy/4 17 [5] A.OUT Ds (5 16 [2 Vrout2 De C6 15 (TZ Vain D7 C7 14 [ Vrouti Ds [18 13 [5] COMP Des C9 12 [5 Veea (LSB) Dio E410 11 [2 Veep (DIP-20P-M01) (FPT-20P-M01) mg PIN DESCRIPTIONS Pin No. Symbol VO Description 1 to 10 D1 to Dio I Data signal input pin (D1: MSB, D10: LSB) 20 CLK I Clock signal input pin 19 VecbD - Digital ground pin (0 V) 18 VCcCA - Analog ground pin (0 V) 11 VEED - Digital power pin (-5.2 V) 12 VEEA - Analog ground pin (-5.2 V) Reference voltage input pin Analog output dynamic range setup pin 15 VRIN Connect to pin 14 or 16 to use the built-in reference voltage When using an external reference voltage, the voltage on this pin must be from -2.20 V to -0.70 V Reference voltage output pin 1 14 VROUT1 0 The output voltage of the potential divider reference is fixed at VEEA 2/5.2. When this pin is connected to pin 15, the analog output voltage ranges from VEEA 2/5.2 toO0 V Reference voltage output pin 2 16 VROUT2 0 The output voltage of the band-gap reference is fixed at -2.0 V. When the pin is connected to pin 15, the analog output voltage ranges from -2 V toO V Phase compensation capacitor pin 13 COMP - Insert a capacitor of 0.1 uF or greater between VEEA and COMP for phase compensation 17 A. OUT 0 Analog signal output pinm BLOCK DIAGRAM MB40730 CLK D4 Ds De D7 Ds Dg Dio (LSB) +) A.OUT R AAA yy < sR 2R AAA Wey R 2R AAA Fey R 2R went 10 | Master- 40 Buffer 40 Current AMA uimer . vV , slave , , Switch Sp OR , Flip Flop [7 7 > AAA Fey = $R 2R AAA Wey = SR 2R AAA . Fey =RR T AAA ev VCCA VecbD Reference Resistor VCcCA Reference Voltage 1 Reference Voltage 2 (potential divider (band-gap VEED reference) reference) VEEA \/ \/ \/ \/ VROUT1 VROUT2 VRIN COMPMB40730 m DIGITAL INPUT EQUIVALENT CIRCUIT Veep O AAA AAA D1 to Dio CLK Threshold voltage = -1.3 V VEED O m ANALOG OUTPUT EQUIVALENT CIRCUIT Voca a = Ro = 2400 AAA _______{) A.OUT q lo VEEA m REFERENCE VOLTAGE OUTPUT EQUIVALENT CIRCUIT Veca Q-- Veca 4AkQ = # vaours 6kQ = AAA vvv W VEEA O_-- Vroute2 *: Overcurrent-prevention resistor (2 kQ) for a short to GND.TYPICAL CONNECTION EXAMPLE MB40730 Al DATA Input Q CLK Input C(J Connect to Vrout1, VRouT2 or external reference voltage. 0.01 u T Tu Voccp Voca D1 A. OUT -- to Vrout2 lL D10 VRIN VrRouTt COMP CLK VEED VEEA T 0.1m 2.2y 22u 52V 0 I. od TH 70.01 uu RECOMMENDED OPERATING CONDITIONS (Veca=Vecb=0 V, Ta=-20C to +75C) Standard value Parameter Symbol Unit Min. Typ. Max. Analog power supply voltage VEEA -5.46 -5.20 -4.94 Vv Power supply Digital power supply voltage VEED -5.46 -5.20 -4.94 Vv voltage : Power supply voltage difference VEEA-VEED -0.2 - 0.2 Vv Analog reference voltage VRIN -2.20 -2.00 -0.70 Vv -20C - - -0.88 Vv Digital input high voltage VIHD 25C -1.13 - -0.81 Vv 75C - - -0.735 Vv -20C -1.95 - - Vv Digital input low voltage VILD 25C -1.95 - -1.48 Vv 75C -1.95 - - Vv Clock frequency fcLk - - 60 MHz Setup time tsu 8 - - ns Hold time th 2 - - ns Clock minimum pulse width high twH 6.5 - - ns Clock minimum pulse width low tw 6.5 - - ns Phase compensation capacitor Ccompe 0.1 - - uF Operating temperature Top -20 - 75 cMB40730 m DC CHARACTERISTICS (VEEA=VEED=-5.46 to -4.94 V, Ta=-20C to +75C) Standard values Parameter Symbol Condition Unit Min. Typ. Max. Resolution - - - - 10 bit Linearity error LE - - +0.1 % - _ , DC accuracy Differential linearity error DLE - - +0.1 % Digital input current high IHD - - - 5 HA Digital input current low liLD - -0.1 - - LA Reference input current IRIN VRIN=-2.000V - - 10 LA Potential _ VEEA = -5.20 V divider Reference voltage VROUT1 VEED = -5.20 V -2.100 -2.000 -1.900 Vv reference Reference voltage VROUT2 - -2.100 -2.000 -1.900 Vv Band-gap 7 t reference emperature - . - - coefficient 100 ppm/*C Full-scale output voltage VoFs - -20 0 - mV VEEA = -5.20 V Zero-scale output voltage Vozs VEED = -5.20 V -2.068 -1.998 -1.928 Vv VRIN = -2.000 V Output resistance Ro Ta=+25C 192 240 288 Q VEEA = -5.46 V Power dissipation IEE VEED = -5.46 V -59 -34* - mA VRIN = VROUT * + VEEA = VEED = -5.20 V m AC CHARACTERISTICS (VEEA= VEED=-5.46 to -4.94 V, Ta=-20C to +75C) Standard values Parameter Symbol Conditions Unit Min. Typ. Max. Maximum conversion rate Fs 60 - - MSPS Output propagation delay time ted CL = 15 pF - 7 - ns Output rise time tr A.OUT pin terminating - 5 - ns Output fall time tf resistance = 240 2 - 5 - ns Settling time tset - -17.5 - nsMB40730 mg TIMING CHART ViHD I 7 I -0.9V : | I I Data input ! 43V ViLD ! 417V i . I I ViHD -0.9V Clock input 1 I ! -1.7V ViLD I I I I I I I I I +'/2LSB ; ; Vors 7 \ I I I I I Analog output +'/LSB Vozs re toot He-+ tsetHL I I I l 1 tPLH 1 1 tPHL 4MB40730 m DAC OUTPUT VOLTAGE CHARACTERISTICS m DAC OUTPUT VOLTAGE FORMULA IN IDEAL CONDITIONS Input D1 to Dio 1023 Output A.OUT 0.000 V 0.000 V -1.998 V -2.000 V 1LSB=2mvV A.OUT = Veca - A023 = N vycca - VRin) 1024 (N : Digital input code from 0 to 1023) Vors = Vceca 1023 1024 Vozs = Vcca - (Vcca - VRiN) NOTES 1. Preventing Switching Noise To prevent switching noise in the analog output signal, connect noise limiting capacitors to the Veea and Veep pins as close to the Vcca and Veco pins as possible. Power Pattern To reduce parasitic impedance, the PC board pattern to the Vcca, Vccp, Veea and Veep pins should be as wide as possible.TYPICAL CHARACTERISTICS CURVES MB40730 1. Power Supply Current v.s. Ambient Temperature lEE, Power supply current (mA) 3. Differential Linearity Error v.s. Ambient Temperature | DLEM| , Differential linearity error (%) VeE=-5.46 V Varin = Vroutt -204 4S -604 -80 -100 -25 0.1 T I I I 0 25 50 75 100 Ambient temperature Ta (C) VeE=-5.20 V Varin = -2.000 V 0.08= 0.06 0.04 0.02 4 lJ Il -25 0 25 50 75 100 Ambient temperature Ta ( C) 2. Linearity Error v.s. Ambient Temperature | LEMI , Linearity error (%) Ro, Output resistance (Q) Vee = -5.20 V Varin = -2.000 V 0.1 0.084 0.064 0.044 0.024 0 I I I I -25 0 25 50 75 100 300 Ambient temperature Ta (C) 4. Output Resistance v.s. Ambient Temperature 280 260 oof 22044 200 -25 I I I I 0 25 50 75 Ambient temperature Ta (C) 10010 MB40730 5. Full-Scale Output Voltage v.s. Ambient Temperature Vee = -5.20 V VRIN = -2.000 V Veco (Reference) -{o4 Voes, Full-scale -2044 output voltage -30-4 (mV) -404 -50 I lJ I -25 0 25 50 7. Vrouti Reference Output Voltage v.s. Ambient Temperature VeE=-5.20 V -1.900 Ambient temperature Ta (C) -1.950 VrouT1, Reference _9 990_] output voltage (V) -2.050_] -2.100 I I I -25 0 25 50 Ambient temperature Ta (C) 6. Zero-Scale Output Voltage v.s. Ambient Temperature Vee = -5.20 V Vain = -2.000 V -1.900 -1.9504 Vozs, Zero-scale -2.000 77-7 output voltage (V) -2.050_] -2.100 I lJ I -25 0 25 50 I 75 100 Ambient temperature Ta ( C) 8. Vrout2 Reference Output Voltage v.s. Ambient Temperature Vee = -5.20 V -1.900 -1.9504 VRoutT2, Reference output -2.000-] en voltage (V) -2.050_] -2.100 I I I -25 0 25 50 I 75 100 Ambient temperature Ta ( C)MB40730 9. VRout2 Reference Output Voltage v.s. Power Supply Voltage Reference output voltage Vroutz (V) tsu, Setup time (ns) Ta= 25C -1.900 -1.950- -2.0004 oe -2.050_] -2.100 I l l 65 -60 -55 -5.0 -45 -4.0 Power supply voltage Vcc (V) 11. Setup Time v.s. Power Supply Voltage Ta = 25C 10 84 64 24 0 I l l 65 -60 -55 -5.0 -45 -4.0 Power supply voltage Vee (V) 10. Setup Time v.s. Ambient Temperature tsu, Setup time (ns) VeE=-5.20 V 10 l i l -25 0 25 50 75 100 Ambient temperature Ta (C) 12. Hold Time v.s. Ambient Temperature tn, Hold time (ns) VeE=-5.20 V T I I I -25 0 25 50 75 100 Ambient temperature Ta (C) 14MB40730 13. Hold Time v.s. Power Supply Voltage Ta = 25 C tn, Holdtime 27 (ns) -4 I I T T 65 -60 -55 -5.0 -4.5 Power supply voltage Vee (V) -4.0 Power supply voltage Vee (V) 15. Minimum Clock Pulse Width v.s. Power Supply Voltage Ta= 25C 10 8 twL/twH, 65 Minimum clock pulse 4 width (ns) twL 2- twH 0 l l l 65 -60 -55 -5.0 -45 -40 14. Minimum Clock Pulse Width v.s. Ambient Temperature twL/twH, Minimum clock pulse width (ns) Vee = -5.20 V 10 eT 24 twH 0 l J l -25 0 25 50 75 100 Ambient temperature Ta (C) 16. Rise Time / Fall Time v.s. Ambient Temperature t/t, Rise time and fall time (ns) Vee = -5.20 V Varin = -2.000 V Ci = 15 pF Analog output 240 termination (1 V amplitude) 10 T I -25 0 25 I 50 I 75 Ambient temperature Ta (C) 100 12MB40730 17. Rise Time / Fall Time v.s. Power Supply Voltage ttt, Rise time and fall time (ns) Ta = 25C VRIN = -2.000 V CL = 15 pF Analog output 240 termination (1 V amplitude) 10 0 I I T T 65 60 -55 -5.0 -4.5 Power supply voltage Vee (V) -4.0 18. Quantization Noise v.s. Analog Output Frequency 70 66 S/Na, 50- Quantization fcLK = 15 MHz noise (dB) 494 folk = 30 MHz fcLkK = 60 MHz 304 20 T T T T 0 5 10 15 20 25 Analog output frequency fout (MHz) 13MB40730 m PACKAGE DIMENSIONS 20-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-20P-M01) +.008 +0.20 15MAX 970.912 (24.649 39 ) I I I I I I I I i rir piri ri ri Pirie <=} INDEX-1 f \Y 260+.010 ) (6.6040.25) 300(7.62) RS) O TYP LA | Ioexxe | J LD LS Ld oe bd bd bd Ld +.012 +.012 010.002 034% 050 * (0.25+0.05) 0.30 0.30 (0.864039 ) (1.27 +0:30) A | | 172(4.36) MAX J - ty oq a) 118(3.00) MIN \ AL Y 100(2.54 018+.003 020(0 51) MIN 4640.08 020(0. oso1.27) TYP (0,460.08) MAX Dimensions in 1991 FUJITSU LIMITED D200058-3C inches (millimeters) 14MB40730 PACKAGE DIMENSIONS (Continued) 20-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-20P-M01) +.01 I< .B00_ ggg (12.70-9.20 ) HHH HOH HOH HH Hi (MOUNTING HEIGHT) .002(0.05) MIN (STAND OFF HEIGHT) A +0.25 - L__.089(2.25) MAX | .307+.016 (7.80-0.40) +.016 +0.40 INDEX s0etote 268. og (6.80.0 20 ) OC) (5.30-40.30) TLECLLLe + st S| ; (0.50+0.20) .050(1.27 .018+.004 +.002 +0.05 WE tte tte +B} @.005(0.13)(M) 008_g97 (0-159 92 } (0.45+40.10) FO | | Details of A part | 5 \ A | .008(0.20) | o ~ py | i \ | r | nh = Shea ar | f | | | co L t+ ff fj) ff jf jt pity .020(0.50) ~ | .007(0.18) | || .004(0.10) | MAX | \> 027(0.68) | t<_ 450(11.43) REF_ MAK Dimensions in 1991 FUJITSU LIMITED F20003S-5C inches (millimeters) 1516 MB40730 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609 F9601 FUJITSU LIMITED Printed in Japan All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Com- plete information sufficient for construction purposes is not nec- essarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu as- sumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. 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