2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Features DDR2 SDRAM SODIMM MT16HTS25664H - 2GB1 MT16HTS51264H - 4GB For component specifications, refer to Micron's Web site: www.micron.com Features Figure 1: * 200-pin, small outline dual in-line memory module (SODIMM) * Fast data transfer rates: PC2-3200, PC2-4200, or PC2-5300 * 2GB (256 Meg x 64) and 4GB (512 Meg x 64) * VDD = VDDQ = +1.8V * VDDSPD = +1.7V to +3.6V * JEDEC standard 1.8V I/O (SSTL_18-compatible) * Differential data strobe (DQS, DQS#) option * 4n-bit prefetch architecture * Multiple internal device banks for concurrent operation * Programmable CAS latency (CL) * Posted CAS additive latency (AL) * WRITE latency = READ latency - 1 tCK * Programmable burst lengths (BL) 4 or 8 * Adjustable data-output drive strength * 64ms, 8192-cycle refresh * On-die termination (ODT) * Serial presence-detect (SPD) with EEPROM * Gold edge contacts * Dual rank, TwinDieTM (2COB) DRAM devices 200-Pin SODIMM (MO-224 R/C D) PCB height: 30mm (1.18in) Options * Marking Operating temperature2 - Commercial (0C TA +70C) - Industrial (-40C TA +85C) * Package - 200-pin DIMM (Pb-free) * Frequency/CAS latency - 2.5ns @ CL 6 (DDR2-800) - 3.0ns @ CL = 5 (DDR2-667) - 3.75ns @ CL = 4 (DDR2-533) - 5.0ns @ CL = 3 (DDR2-400)3 None I Y -800 -667 -53E -40E Notes: 1. End of life. 2. Contact Micron for industrial temperature module offerings. 3. Not recommended for new designs. Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 (ns) tRP (ns) tRC (ns) -800 -667 -53E -40E PC2-6400 PC2-5300 PC2-4200 PC2-3200 800 667 - - 667 667 - - 533 533 533 400 - 400 400 400 15 15 15 15 15 15 15 15 55 55 55 55 PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 1 tRCD Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Features Table 2: Addressing Parameter Refresh count Row address Device bank address Device configuration Column address Module rank address Table 3: 2GB 4GB 8K 16K (A0-A13) 8 (BA0-BA2) 2Gb TwinDie (128 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) 8K 32K (A0-A14) 8 (BA0-BA2) 4Gb TwinDie (256 Meg x 8) 1K (A0-A9) 2 (S0#, S1#) Part Numbers and Timing Parameters - 2GB Base device: MT47H256M8THJ,1 2Gb TwinDie DDR2 SDRAM Part Number2 MT16HTS25664HY-800__ MT16HTS25664HY-667__ MT16HTS25664HY-53E__ MT16HTS25664HY-40E__ Table 4: Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 2GB 2GB 2GB 2GB 256 Meg x 64 256 Meg x 64 256 Meg x 64 256 Meg x 64 6.4 GB/s 5.3 GB/s 4.3 GB/s 3.2 GB/s 2.5ns/800MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 5.0ns/400 MT/s 6-6-6 5-5-5 4-4-4 3-3-3 Part Numbers and Timing Parameters - 4GB Base device: MT47H512M8THM,1 4Gb TwinDie DDR2 SDRAM Part Number2 MT16HTS51264HY-800__ MT16HTS51264HY-667__ MT16HTS51264HY-53E__ Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) 4GB 4GB 4GB 512 Meg x 64 512 Meg x 64 512 Meg x 64 6.4 GB/s 5.3 GB/s 4.3 GB/s 2.5ns/800MT/s 3.0ns/667 MT/s 3.75ns/533 MT/s 6-6-6 5-5-5 4-4-4 Notes: 1. Data sheets for the base devices can be found on Micron's Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT16HTS51264HY-667A1. PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 5: Pin Assignments 200-Pin SODIMM Front 200-Pin SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 A1 VDD A10 BA0 WE# VDD CAS# S1# VDD ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DQ42 DQ43 VSS DQ48 DQ49 VSS NC VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC 52 DM2 54 VSS 56 DQ22 58 DQ23 60 VSS 62 DQ28 64 DQ29 66 VSS 68 DQS3# 70 DQS3 72 VSS 74 DQ30 76 DQ31 78 VSS 80 CKE1 82 VDD 84 NC 861 NC/A14 88 VDD 90 A11 92 A7 94 A6 96 VDD 98 A4 100 A2 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A0 VDD BA1 RAS# S0# VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 Notes: 1. Pin 86 is NC for 2GB and A14 for 4GB. PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Pin Assignments and Descriptions Table 6: Symbol Pin Descriptions Type Description A0-A14 Input Address inputs: Provide the row address for ACTIVE commands and the column address, and (SSTL_18) auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0-BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. A0-A13 (2GB) and A0-A14 (4GB). BA0-BA2 Input Bank address inputs: BA0-BA2 define to which device bank an ACTIVE, READ, WRITE, or (SSTL_18) PRECHARGE command is being applied. BA0-BA2 define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. CK0, CK0# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are CK1, CK1# (SSTL_18) sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#. CKE0, CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking (SSTL_18) circuitry on the DDR2 SDRAM. DM0-DM7 Input Data input mask: DM is an input mask signal for write data. Input data is masked when DM is (SSTL_18) sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. ODT0, ODT1 Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the (SSTL_18) DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. RAS#, CAS#, Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. WE# (SSTL_18) S0#, S1# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command (SSTL_18) decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. SA0-SA1 Input Presence-detect address inputs: These pins are used to configure the presence-detect (SSTL_18) devices. SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data (SSTL_18) transfer to and from the module. DQ0-DQ63 I/O Data input/output: Bidirectional data bus. (SSTL_18) DQS0-DQS7, I/O Data strobe: Output with read data, input with write data for source synchronous operation. DQS0#-DQS7# (SSTL_18) Edge-aligned with read data, center-aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data (SSTL_18) into and out of the presence-detect portion of the module. Supply Power supply: +1.8 0.1V. VDD Supply Serial EEPROM positive power supply: +1.7V to +3.6V. VDDSPD Supply SSTL_18 reference voltage (VDD/2). VREF VSS Supply Ground. NC - No connect: These pins are not connected on the module. PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0# DQS4# DQS4 DQS0 DM0 DM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U1b CS# DQ DM DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1t DQS1# DQS5# DQS1 DM1 DQS5 DM5 DM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U9b CS# DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U9t DQS# DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DM DQ DQ DQ DQ DQ DQ DQ DQ DQS# DQ DQS# U7t DM DQ DQ DQ DQ DQ DQ DQ DQ U3b CS# CS# DQ DQS# U3t DQS6 DM6 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U8b CS# DQ DM DQS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U8t DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ U4b CS# DQ DQS# U4t DQS7# DQS3# DQS3 DQS7 DM7 DM3 DM BA0-BA2 A0-A13/A14 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 DQ DQS6# DM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS# U7b DM DQS# DQS2# DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ U2b DQS# DM DQ DQ DQ DQ DQ DQ DQ DQ BA0-BA2: DDR2 SDRAM A0-A13/A14: DDR2 SDRAM RAS#: DDR2 SDRAM CAS#: DDR2 SDRAM WE#: DDR2 SDRAM CKE0: Rank 0 CKE1: Rank 1 ODT0: Rank 0 ODT1: Rank 1 PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN CS# DQ DM DQS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U2t U5 SPD EEPROM SCL WP A0 DQ DQ DQ DQ DQ DQ DQ DQ CS# SDA VDD DDR2 SDRAM VREF DDR2 SDRAM DDR2 SDRAM, EEPROM 5 DM DQ DQ DQ DQ DQ DQ DQ DQ CS# DQ DQS# U6t Rank 0 = U1b-U4b, U6b-U9b Rank 1 = U1t-U4t, U6t-U9t A1 A2 SPD EEPROM VSS DQS# U6b VSS SA0 SA1 SA2 VDDSPD DQ CK0 CK0# U1, U2, U9, U8 CK1 CK1# U3, U4, U6, U7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM General Description General Description The MT16HTS25664H and MT16HTS51264H DDR2 SDRAM modules are high-speed, CMOS, dynamic random access 2GB and 4GB memory modules organized in a x64 configuration. These modules use 2Gb and 4Gb TwinDie DDR2 SDRAM devices with eight internal banks. DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA (1:0), which provide four unique DIMM/EEPROM addresses. Write protect (WP) is pulled down to VSS on the module, permanently disabling hardware write protect. PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VIN, VOUT II VDD supply voltage relative to VSS Voltage on any pin relative to VSS Address inputs Input leakage current; Any input 0V VIN VDD; VREF input 0V VIN 0.95V (All other pins not under RAS#, CAS#, WE# test = 0V) S#, CKE, ODT, CK, CK# DM Output leakage current; 0V VOUT; DQ and ODT are DQ, DQS, DQS# disabled VREF leakage current; VREF = valid VREF level Module ambient operating temperature Commercial Industrial DDR2 SDRAM component case operating Commercial temperature2 Industrial -1.0 -0.5 -80 +2.3 +2.3 +80 V V A -40 -10 -10 +40 +10 +10 A -32 0 -40 0 -40 +32 +70 +85 +85 +95 A C C C C Ioz IVREF TA TC1 Notes: 1. The refresh rate is required to double when 85C < TC 95C. 2. For further information, refer to technical note TN-00-08: "Thermal Applications," available on Micron's Web site. Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades, as shown in Table 8. Table 8: Module and Component Speed Grades Module Speed Grade Component Speed Grade -800 -667 -53E -40E -25 -3 -37E -53E PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Table 9: DDR2 IDD Specifications and Conditions - 2GB Values are shown for the MT47H256M8THJ DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie (256 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), RC = tRC (IDD), tRAS = tRASmin (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRASmin (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between DD DD valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (I ); CKE is HIGH, S# is HIGH; Other control and address bus DD inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (I ); CKE is LOW; Other control and address MR[12] = 0 DD bus inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRASmax (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between DD DD valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRASmax (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between DD DD valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst read; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), t RAS = tRASmax (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); REFRESH command at every t RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - = 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between DD DD valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching t PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 8 Symbol -800 -667 -53E -40E Units IDD0 816 776 656 656 mA IDD1 976 896 856 816 mA IDD2P 112 112 112 112 mA IDD2Q 456 376 376 336 mA IDD2N 496 416 416 376 mA IDD3PF 296 296 296 296 mA IDD3PS 136 136 136 136 mA IDD3N 576 536 456 416 mA IDD4W 1376 1176 1096 936 mA IDD4R 1376 1176 1096 936 mA IDD5 1976 1816 1776 1736 mA IDD6 112 112 112 112 mA IDD7 2776 2336 2256 2176 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Electrical Specifications Table 10: DDR2 IDD Specifications and Conditions - 4GB Values are shown for the MT47H512M8THM DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie (512 Meg x 8) component data sheet Parameter/Condition t t Operating one bank active-precharge current: CK = CK (IDD), RC = tRC (IDD), tRAS = tRASmin (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRASmin (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between DD DD valid commands; Address bus inputs are switching; Data pattern is same as IDD4W Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Precharge quiet standby current: All device banks idle; tCK = tCK (I ); CKE is HIGH, S# is HIGH; Other control and address bus DD inputs are stable; Data bus inputs are floating Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching Active power-down current: All device banks open; Fast PDN exit tCK = tCK (I ); CKE is LOW; Other control and address MR[12] = 0 DD bus inputs are stable; Data bus inputs are floating Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRASmax (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between DD DD valid commands; Other control and address bus inputs are switching; Data bus inputs are switching Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRASmax (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRASmax (I ), tRP = tRP (I ); CKE is HIGH, S# is HIGH between DD DD valid commands; Address bus inputs are switching; Data bus inputs are switching Burst refresh current: tCK = tCK (IDD); Refresh command at every tRFC (I ) interval; CKE is HIGH, S# is HIGH between valid commands; DD Other control and address bus inputs are switching; Data bus inputs are switching Self refresh current: CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = t RRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching t PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 9 Symbol -800 -667 -53E Units IDD0 TBD 904 824 mA IDD1 TBD 1264 944 mA IDD2P TBD 128 128 mA IDD2Q TBD 504 424 mA IDD2N TBD 584 504 mA IDD3PF TBD 384 344 mA IDD3PS TBD 144 144 mA IDD3N TBD 544 464 mA IDD4W TBD 1304 1144 mA IDD4R TBD 1464 1304 mA IDD5 TBD 2344 2184 mA IDD6 TBD 128 128 mA IDD7 TBD 2824 2464 mA Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Serial Presence-Detect Serial Presence-Detect Table 11: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT= 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current Power supply current, READ: SCL clock frequency = 100 kHz Power supply current, WRITE: SCL clock frequency = 100 kHz Table 12: Symbol Min Max Units VDDSPD VIH VIL VOL ILI ILO ISB ICCR ICCW 1.7 VDDSPD x 0.7 -0.6 - 0.10 0.05 1.6 0.4 2.0 3.6 VDDSPD + 0.5 VDDSPD x 0.3 0.4 3.0 3.0 4.0 1.0 3.0 V V V V A A A mA mA Serial Presence-Detect EEPROM AC Operating Conditions Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Symbol Min Max Units Notes tAA 0.2 1.3 200 - 0 0.6 0.6 - 1.3 - - 100 0.6 0.6 - 0.9 - - 300 - - - 50 - 0.3 400 - - - 10 s s ns ns s s s ns s s kHz ns s s ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR fSCL tSU:DAT t SU:STA tSU:STO tWRC 2 2 3 4 Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pullup resistance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron's SPD page: www.micron.com/SPD. PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Module Dimensions Module Dimensions Figure 3: 200-Pin DDR2 SODIMM Front view 3.8 (0.15) MAX 67.75 (2.667) 67.45 (2.656) 2.0 (0.079) R (2X) U1 1.8 (0.071) (2X) U2 U3 U4 30.15 (1.187) 29.85 (1.175) 20.0 (0.787) TYP U5 6.0 (0.236) TYP 2.55 (0.10) TYP 0.45 (0.018) TYP 0.99 (0.039) TYP Pin 1 2.0 (0.079) TYP 1.1 (0.043) 0.9 (0.035) 0.60 (0.024) TYP Pin 199 63.60 (2.504) TYP Back view U6 Pin 200 U7 47.4 (1.87) TYP U8 U9 4.2 (0.165) TYP Pin 2 11.4 (0.45) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or TYP where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM Revision History Revision History Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/09 * "Features" on page 1: Added PC2-6400 to data transfer rates. * Published externally. Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/09 * Added -800 speed grade. * Not published externally -- customer draft only. Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/07 * Updated file name from HTS16C256x64H.fm to HTS16C256_512x64H.fm. * Added 4GB - MT16HTS51264H. * Updated to latest format and data diet. * Added note "Not recommended for new designs" for MT16HTS25664H - 2GB. * Updated the IDD tables. * Removed the SPD matrices and replaced them with a link to the online SPD Web site. * Referenced PCB 0402 in this revision. * Removed part number MT16HTS51264HY-40E from Table 4 on page 2. Rev. A, Released (No Mark) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 04/06 * Initial release. PDF: 09005aef821e5bf3/Source: 09005aef82198d54 HTS16C256_512x64H.fm - Rev. D 5/09 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.