MT16HTS25664HY-800A1 - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Features

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

DDR2 SDRAM SODIMM

MT16HTS25664H – 2GB1

MT16HTS51264H – 4GB

For component specifications, refer to Micron’s Web site: www.micron.com

Features

• 200-pin, small outline dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC2-3200, PC2-4200, or

PC2-5300

• 2GB (256 Meg x 64) and 4GB (512 Meg x 64)

•VDD = VDDQ = +1.8V

•VDDSPD = +1.7V to +3.6V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

•4n-bit prefetch architecture

• Multiple internal device banks for concurre nt

operation

• Programmable CAS latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths (BL) 4 or 8

• Adjustable data-output drive strength

• 64ms, 8192-cycle refresh

• On-die termination (ODT)

• Serial presence-detect (SPD) with EEPROM

• Gold edge contacts

• Dual rank, TwinDie™ (2COB) DRAM devices

Figure 1: 200-Pin SODIMM (MO-224 R/C D)

Notes: 1. End of life.

2. Contact Micron for industrial temperature

module offerings.

3. Not recommended for new designs.

Options Marking

• Operating temperature2

–Commercial (0°C ≤ TA ≤ +70°C) None

–Industrial (–40°C ≤ TA ≤ +85°C) I

•Package

–200-pin DIMM (Pb-free) Y

• Frequency/CAS latency

–2.5ns @ CL 6 (DDR2-800) -800

–3.0ns @ CL = 5 (DDR2-667) -667

–3.75ns @ CL = 4 (DDR2-533) -53E

–5.0ns @ CL = 3 (DDR2-400)3-40E

PCB height: 30mm (1.18in)

Table 1: Key Timing Parameters

Speed Grade Industry

Nomenclature

Data Rate (MT/s) tRCD

(ns) tRP

(ns) tRC

(ns)CL = 6 CL = 5 CL = 4 CL = 3

-800 PC2-6400 800 667 533 – 15 15 55

-667 PC2-5300 667 667 533 400 15 15 55

-53E PC2-4200 – – 533 400 15 15 55

-40E PC2-3200 – – 400 400 15 15 55

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Features

Notes: 1. Data sheets for the base devices can be found on Micron ’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and

PCB revisions. Consult factory for current revision codes.

Example: MT16HTS51264HY-667A1.

Table 2: Addressing

Parameter 2GB 4GB

Refresh count 8K 8K

Row address 16K (A0–A13) 32K (A0–A14)

Device bank address 8 (BA0–BA2) 8 (BA0–BA2)

Device configuration 2Gb TwinDie (128 Meg x 8) 4Gb TwinDie (256 Meg x 8)

Column address 1K (A0–A9) 1K (A0–A9)

Module rank address 2 (S0#, S1#) 2 (S0#, S1#)

Table 3: Part Numbers and Timing Parameters – 2GB

Base device: MT47H256 M8THJ,1 2Gb TwinDie DDR2 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory Clock/

Data Rate Clock Cycles

(CL-tRCD-tRP)

MT16HTS25664HY-800__ 2G B 256 Meg x 64 6.4 GB/s 2.5ns/800MT/s 6-6-6

MT16HTS25664HY-667__ 2G B 256 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

MT16HTS25664HY-53E__ 2G B 256 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

MT16HTS25664HY-40E__ 2G B 256 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

Table 4: Part Numbers and Timing Parameters – 4GB

Base device: MT47H512 M8THM,1 4Gb TwinDie DDR2 SDRAM

Part Number2Module

Density Configuration Module

Bandwidth Memory Clock/

Data Rate Clock Cycles

(CL-tRCD-tRP)

MT16HTS51264HY-800__ 4G B 512 Meg x 64 6.4 GB/s 2.5ns/800MT/s 6-6-6

MT16HTS51264HY-667__ 4G B 512 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

MT16HTS51264HY-53E__ 4G B 512 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Pin Assignments and Descriptions

Notes: 1. Pin 86 is NC for 2GB and A14 for 4GB.

Table 5: Pin Assignments

200-Pin SODIMM Front 200-Pin SODIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

REF 51 DQS2 101 A1 151 DQ42 2 VSS 52 DM2 102 A0 152 DQ46

SS 53 VSS 103 VDD 153 DQ43 4 DQ4 54 VSS 104 VDD 154 DQ47

5 DQ0 55 DQ18 105 A10 155 VSS 6 DQ5 56 DQ22 106 BA1 156 VSS

7 DQ1 57 DQ19 107 BA0 157 DQ48 8 VSS 58 DQ23 108 RAS# 158 DQ52

SS 59 VSS 109 WE# 159 DQ49 10 DM0 60 VSS 110 S0# 160 DQ53

11 DQS0# 61 DQ24 111 VDD 161 VSS 12 VSS 62 DQ28 112 VDD 162 VSS

13 DQS0 63 DQ25 113 CAS# 163 NC 14 DQ6 64 DQ29 114 ODT0 164 CK1

15 VSS 65 VSS 115 S1# 165 VSS 16 DQ7 66 VSS 116 A13 166 CK1#

17 DQ2 67 DM3 117 VDD 167 DQS6# 18 VSS 68 DQS3# 118 VDD 168 VSS

19 DQ3 69 NC 119 ODT1 169 DQS6 20 DQ12 70 DQS3 120 NC 170 DM6

21 VSS 71 VSS 121 VSS 171 VSS 22 DQ13 72 VSS 122 VSS 172 VSS

23 DQ8 73 DQ26 123 DQ32 173 DQ50 24 VSS 74 DQ30 124 DQ36 174 DQ54

25 DQ9 75 DQ27 125 DQ33 175 DQ51 26 DM1 76 DQ31 126 DQ37 176 DQ55

27 VSS 77 VSS 127 VSS 177 VSS 28 VSS 78 VSS 128 VSS 178 VSS

29 DQS1# 79 CKE0 129 DQS4# 179 DQ56 30 CK0 80 CKE1 130 DM4 180 DQ60

31 DQS1 81 VDD 131 DQS4 181 DQ57 32 CK0# 82 VDD 132 VSS 182 DQ61

33 VSS 83 NC 133 VSS 183 VSS 34 VSS 84 NC 134 DQ38 184 VSS

35 DQ10 85 BA2 135 DQ34 185 DM7 36 DQ14 861NC/A14 136 DQ39 186 DQS7#

37 DQ11 87 VDD 137 DQ35 187 VSS 38 DQ15 88 VDD 138 VSS 188 DQS7

39 VSS 89 A12 139 VSS 189 DQ58 40 VSS 90 A11 140 DQ44 190 VSS

41 VSS 91 A9 141 DQ40 191 DQ59 42 VSS 92 A7 142 DQ45 192 DQ62

43 DQ16 93 A8 143 DQ41 193 VSS 44 DQ20 94 A6 144 VSS 194 DQ63

45 DQ17 95 VDD 145 VSS 195SDA 46DQ2196 V

DD 146 DQS5# 196 VSS

47 VSS 97 A5 147 DM5 197 SCL 48 VSS 98 A4 148 DQS5 198 SA0

49 DQS2# 99 A3 149 VSS 199 VDDSPD 50 NC 100 A2 150 VSS 200 SA1

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Pin Assignments and Descriptions

Table 6: Pin Descriptions

Symbol Type Description

A0–A14 Input

(SSTL_18) Address inputs: Provide the row address for ACTIVE commands and the column address, and

auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory

array in the respective bank. A10 sampled during a PRECHARGE command determines whether

the PRECHARGE applies to one device bank (A10 LOW , device bank selected by BA0–BA2) or all

device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE

command. A0–A13 (2GB) and A0–A14 (4GB).

BA0–BA2 Input

(SSTL_18) Bank address inputs: BA0–BA2 define to which device bank an ACTIVE, READ, WRITE, or

PRECHARGE comman d is being applie d. BA0–BA2 define which mode register, including MR ,

EMR, EMR(2) , an d EMR(3), is load ed during the LOAD MO D E com m a nd.

CK0, CK0#

CK1, CK1# Input

(SSTL_18) Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data

(DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE0, CKE1 Input

(SSTL_18) Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking

circuitry on the DDR2 SDRAM.

DM0–DM7 Input

(SSTL_18) Data input mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges

of DQS. Although DM pins are input-only , the DM loading is designed to match that of DQ and

DQS pins.

ODT0, ODT1 Input

(SSTL_18) On-die termination: ODT (registered HIGH) enables termination resistance internal to the

DDR2 SDRAM. When enabled, ODT is only ap plied to each of the following pins : DQ, DQS,

DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command.

RAS#, CAS#,

WE# Input

(SSTL_18) Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.

S0#, S1# Input

(SSTL_18) Chip select: S# enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when S# is registered HIGH. S# provides for external rank

selection on systems with multiple ranks. S# is considered part of the command code.

SA0–SA1 Input

(SSTL_18) Presence-detect address inputs: These pins are used to configure the presence-det ect

devices.

SCL Input

(SSTL_18) Serial clock for prese nce- d etec t: SCL is used to synchronize the presence-detect data

transfer to and from the module.

DQ0–DQ63 I/O

(SSTL_18) Data input/output: Bidirectional data bus.

DQS0–DQS7,

DQS0#–DQS7# I/O

(SSTL_18) Data strobe: Output with read data, input with write data for source sync hronou s operation.

Edge-aligned with read data, center-aligned with write data. DQS# is on ly used when

differential data strobe mode is enabled via the LOAD MODE command.

SDA I/O

(SSTL_18) Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data

into and out of the presence-detect portion of the module.

VDD Supply Power supply: +1.8 ±0.1V.

VDDSPD Supply Serial EEPROM positive power supply: +1.7V to +3.6V.

VREF Supply SSTL_18 reference voltage (VDD/2).

VSS Supply Ground.

NC – No connect: These pins are not connected on the module.

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1b

DM CS# DQ DQS#

U1t

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U7b

U7t

DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U9b

DM CS# DQ DQS#

U9t

DM CS# DQ DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

U8b

DM CS# DQ DQS#

U8t

DM CS# DQ DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

U2b

DM CS# DQ DQS#

U2t

DM CS# DQ DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

U3b

U3t

DM CS# DQ DQS# DM CS# DQ DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

U4b

U4t

DM CS# DQ DQS# DM CS# DQ DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

U6b

U6t

DM CS# DQ DQS# DM CS# DQ DQS#

DQS0#

DQS0

DM0

S0#

S1#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

U1, U2, U9, U8

CK0

CK0#

U3, U4, U6, U7

CK1

CK1#

SPD EEPROM

A1 A2

SA0 SA1 SA2

SDA

SCL WP

VDDSPD

VDD

VREF

VSS

SPD EEPROM

DDR2 SDRAM

DDR2 SDRAM, EEPROM

BA0–BA2

A0–A13/A14

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

BA0–BA2: DDR2 SDRAM

A0–A13/A14: DDR2 SDRAM

RAS#: DDR2 SDRAM

CAS#: DDR2 SDRAM

WE#: DDR2 SDRAM

CKE0: Rank 0

CKE1: Rank 1

ODT0: Rank 0

ODT1: Rank 1

Rank 0 = U1b–U4b, U6b–U9b

Rank 1 = U1t–U4t, U6t–U9t

VSS

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

General Description

The MT16HTS25664H and MT16HTS51264H DDR2 SDRAM modules are high-speed,

CMOS, dynamic random access 2GB and 4GB memory modules organized in a x64 con-

figuration. These modules use 2Gb and 4Gb TwinDie DDR2 SDRAM devices with eight

internal ban ks.

DDR2 SDRAM modules use double data ra te architecture to achieve high-speed opera-

tion. The double data rate archi t ecture is essentially a 4n-prefetch architecture with an

interface designed to transfer two data words per clock cycle at the I/O pins. A single

read or write access for the DDR2 SDRAM module effectively consis ts of a single 4n-bit-

wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding

n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS, DQS#) i s transmitted externally, along with data, for

use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM

device during READs and by the memory controller during WRITEs. DQS is edge-

aligned with data for READs and center-aligned with data for WRITEs.

DDR2 SDRAM modul es operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands are registered at every positive edge of CK . Input data is registered on both edges

of DQS, and output data is referenced to both edges of DQS, as well as to both edges of

CK.

Serial Presence-Detect Operation

DDR2 SDRAM modules incorporate seri al presence-d etect (SPD). The SPD functio n is

implemented using a 2048-bit EEPROM. This nonvolatile storage device contains

256 bytes . The first 128 b ytes are pr ogrammed b y Micron to identify the module type and

various SDRAM organizations and timing parameters. The remaining 128 bytes of stor-

age are available for use by the customer. System READ/WRITE operations between the

master (system logic) and the slave EEPROM device occur via a standard I2C bus using

the DIMM’s SCL (clock) and SDA (data) signals, together with SA (1:0), which provide

four unique DIMM/EEPROM addresses. Write protect (WP) is pulled down to VSS on the

module, permanently disabling hardware write protect.

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Electrical Specifications

S tresses greater than those listed in Table 7 may cause permanent damage to the mod-

ule. This is a stress rating only, and functional operation of the module at these or any

other conditions outside those ind icated on the device data shee t is not impl ie d . Expo -

sure to absolute maximum rating conditions for extended periods may adversely affect

reliability.

Notes: 1. The refresh rate is required to double when 85°C < TC ≤ 95°C.

2. For fur th e r informatio n, r ef er to technical note TN-00-08: “Thermal Applications,” avail-

able on Micron’s W eb site.

Input Capacitance

Micron encourages designers to simulate the performance of the module to achieve

optimum values. Simulations are sign ificantly mor e accurate and realistic than a gr oss

estimation of module capacitance when inductance and delay parameters associated

with trace lengths are used in simulations. JEDEC modules are currently designed using

simulations to cl ose timing budget s.

AC Timing and Operating Conditions

Re commended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron’s Web site. Module speed grades

correlate with component speed grades, as shown in Table 8.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –1.0 +2.3 V

VIN, VOUT Voltage on any pin relative to VSS –0.5 +2.3 V

IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;

VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under

test = 0V)

Address inputs

RAS#, CAS#, WE# –80 +80 µA

S#, CKE, ODT, CK, CK# –40 +40

DM –10 +10

Ioz Output leakage current; 0V ≤ VOUT; DQ a nd OD T ar e

disabled DQ, DQS, DQS# –10 +10 µA

IVREF VREF leakage current; VREF = valid VREF level –32 +32 µA

TAModule ambient operating temperature Commercial 0+70°C

Industrial –40 +85 °C

TC1DDR2 SDRAM component case operating

temperature2Commercial 0+85°C

Industrial –40 +95 °C

Table 8: Module and Component Speed Grades

Module Speed Grade Component Speed Grade

-800 -25

-667 -3

-53E -37E

-40E -53E

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Electrical Specifications

Table 9: DDR2 IDD Specifications and Conditions – 2GB

V alues are shown for the MT47H256M8THJ DDR2 SDRAM only and are computed from values specified in the

2Gb TwinDie (256 Meg x 8) component data sheet

Parameter/Condition Symbol -800 -667 -53E -40E Units

Operating one bank active-precharge current: tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRASmin (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

IDD0 816 776 656 656 mA

Operating one bank active-read-precharge current: IOUT = 0mA;

BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRASmin (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data pattern is same

as IDD4W

IDD1 976 896 856 816 mA

Precha rge power-down current : All device banks idle; tCK = tCK (IDD);

CKE is LOW; Other control and address bus inputs are stable; Data bus

inputs are floating

IDD2P 112 112 112 112 mA

Precharge quiet standby current: All device banks idle;

tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Othe r control and address bus

inputs are stable; Data bus inputs are floating

IDD2Q 456 376 376 336 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD);

CKE is HIGH, S# is HIGH; Other control and address bus inputs are

switching; Data bus inputs are switching

IDD2N 496 416 416 376 mA

Active power-down current: All device banks open;

tCK = tCK (IDD); CKE is LOW; Other control and address

bus inputs are stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0 IDD3PF 296 296 296 296 mA

Slow PDN exit

MR[12] = 1 IDD3PS 136 136 136 136 mA

Active standby current: All device banks open; tCK = tCK (IDD),

tRAS = tRASmax (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Other control and address bus inputs are switching;

Data bus inputs are switching

IDD3N 576 536 456 416 mA

Operating burst write current: All device banks open; Continuous

burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRAS = tRASmax (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

IDD4W 1376 1176 1096 936 mA

Operating burst read current: All device banks open; Continuous

burst read; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRAS = tRASmax (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

IDD4R 1376 1176 1096 936 mA

Burst refresh current: tCK = tCK (IDD); REFRESH command at every

tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are

switching

IDD5 1976 1816 1776 1736 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Othe r control and

address bus inputs are floating; Data bus inputs are floating IDD6 112 112 112 112 mA

Operating bank interleave read current: All devic e banks

interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD),

AL = tRCD (IDD)-=1×tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),

tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are stable during deselects; Data

bus inputs are switching

IDD7 2776 2336 2256 2176 mA

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Electrical Specifications

Table 10: DDR2 IDD Specifications and Conditions – 4GB

Values are shown for the MT47H512M8THM DDR2 SDRAM only and are computed from values specified in

the 4Gb TwinDie (512 Meg x 8) component data sheet

Parameter/Condition Symbol -800 -667 -53E Units

Operating one bank active-precharge current: tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRASmin (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

IDD0 TBD 904 824 mA

Operating one bank active-read-precharge current: IOUT = 0mA;

BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRASmin (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs ar e switching; Data pattern is same

as IDD4W

IDD1 TBD 1264 944 mA

Precharge power -down current: All device banks idle; tCK = tCK (IDD);

CKE is LOW; Other control and address bus inputs are stable; Data bus

inputs are floating

IDD2P TBD 128 128 mA

Precharge quiet standby current: All device banks idle;

tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Othe r control and address bus

inputs are stable; Data bus inputs are floating

IDD2Q TBD 504 424 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD);

CKE is HIGH, S# is HIGH; Other control and address bus inputs are

switching; Data bus inputs are switching

IDD2N TBD 584 504 mA

Active power-down current: All device banks open;

tCK = tCK (IDD); CKE is LOW; Other control and address

bus inputs are stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0 IDD3PF TBD 384 344 mA

Slow PDN exit

MR[12] = 1 IDD3PS TBD 144 144 mA

Active standby current: All device banks open; tCK = tCK (IDD),

tRAS = tRASmax (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Other control and address bus inputs are switching;

Data bus inputs are switching

IDD3N TBD 544 464 mA

Operating burst write current: All device banks open; Continuous

burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRASmax

(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

IDD4W TBD 1304 1144 mA

Operating burst read current: All device banks open; Continuous

burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),

tRAS = tRASmax (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between

valid commands; Address bus inputs are switching; Data bus inputs are

switching

IDD4R TBD 1464 1304 mA

Burst refresh current: tCK = tCK (IDD); Refresh command at every

tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are

switching

IDD5 TBD 2344 2184 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Othe r control and

address bus inputs are floating; Data bus inputs are floating IDD6 TBD 128 128 mA

Operating bank interleave read current: All devic e banks

interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD),

AL = tRCD (IDD)-1×tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD =

tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH be tween valid

commands; Address bus inputs are stable during deselects; Data bus

inputs are switching

IDD7 TBD 2824 2464 mA

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Serial Presence-Detect

Notes: 1. To avoid spurious st art and stop conditions, a minimum delay is plac ed between SCL = 1

and the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a

write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the

WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-

up resista nce, and the E EP R O M does not res pond to its sla v e ad dress.

Serial Presence-Detect Data

For the latest serial presence-d etect data, refer to Micron’s SPD page:

www.micron.com/SPD.

Table 11: Serial Presence-Detect EEPROM DC Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 1.7 3.6 V

Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V

Input low voltage: Logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V

Output low voltage: IOUT= 3mA VOL –0.4V

Input leakage current: VIN = GND to VDD ILI 0.10 3.0 µA

Output leakage current: VOUT = GND to VDD ILO 0.05 3.0 µA

Standby current ISB 1.6 4.0 µA

Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1.0 mA

Power supply current, WRITE: SCL clock frequency = 10 0 kHz ICCW 2.0 3.0 mA

Table 12: Serial Presence-Detect EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time the bus must be free before a new transition can start tBUF 1.3 – µs

Data-out hold time tDH 200 – ns

SDA and SCL fall time tF – 300 ns 2

Data-in hold time tHD:DAT 0 – µs

Start condition hold time tHD:STA 0.6 – µs

Clock HIGH period tHIGH 0.6 – µs

Noise suppression time constant at SCL, SDA inputs tI–50ns

Clock LOW period tLOW 1.3 – µs

SDA and SCL rise time tR–0.3µs2

SCL clock frequency fSCL – 400 kHz

Data-in setup time tSU:DAT 100 – ns

Start condition setup time tSU:STA 0.6 – µs 3

Stop condition setup time tSU:STO 0.6 – µs

WRITE cycle time tWRC – 10 ms 4

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although

considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Module Dimensions

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Module Dimensions

Figure 3: 200-Pin DDR2 SODIMM

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or TYP where noted.

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for addi-

tional design dimensions.

3.8 (0.15)

MAX

Pin 1

67.75 (2.667)

67.45 (2.656)

20.0 (0.787)

TYP

1.8 (0.071)

(2X)

0.60 (0.024)

TYP

0.45 (0.018)

TYP

2.0 (0.079) R

(2X)

Pin 199

Pin 200 Pin 2

Front view

2.0 (0.079)

TYP

6.0 (0.236) TYP

63.60 (2.504)

TYP

2.55 (0.10)

TYP

0.99 (0.039)

TYP

30.15 (1.187)

29.85 (1.175)

Back view

1.1 (0.043)

0.9 (0.035)

47.4 (1.87)

TYP 11.4 (0.45)

TYP

4.2 (0.165)

TYP

U1 U2

U3 U4

U6 U7 U8 U9

PDF: 09005aef821e5bf3/Source: 09005aef82198d54 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

2GB, 4GB (x64, DR) 200-Pin DDR2 SDRAM SODIMM

Revision History

Rev. D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/09

• “Features” on page 1: Added PC2-6400 to data transfer rates.

• Published externally.

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/09

• Added -800 speed grade.

• Not published externally — customer draft only.

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/07

• Updated file name from HTS16C256x64H.fm to HTS16C256_512x64H.fm.

• Added 4GB – MT16HTS51264H.

• Updated to latest for m at and data diet.

• Added note “Not recommended for new designs” for MT16HTS25664H – 2GB.

• Updated the IDD tables.

• Removed the SPD matrices and replaced them with a link to the online SPD Web site.

• Referenced PCB 0402 in this revision.

• Removed part number MT16HTS51264HY-40E from Table4 on page 2.

Rev. A, Released (No Mark). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .04/06

•Initial release.