IS61LV12824 ISSI®
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. D
06/22/05
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
FEATURES
• High-speed access time: 8, 10 ns
• CMOS low power operation
— 756 mW (max.) operating @ 8 ns
— 36 mW (max.) standby @ 8 ns
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Available in 119-pin Plastic Ball Grid Array
(PBGA) and 100-pin TQFP packages.
• Industrial temperature available
• Lead-free available
DESCRIPTION
The ISSI IS61LV12824 is a high-speed, static RAM organized
as 131,072 words by 24 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields ac-
cess times as fast as 8 ns with low power consumption.
When CE1, CE2 are HIGH and CE2 is LOW (deselected), the
device assumes a standby mode at which the power dissipa-
tion can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE1, CE2, CE2 and OE. The active
LOW Write Enable (WE) controls both writing and reading of
the memory.
The IS61LV12824 is packaged in the JEDEC standard
119-pin PBGA and 100-pin TQFP.
FUNCTIONAL BLOCK DIAGRAM
JUNE 2005
A0-A16
CE1
OE
WE
128K x 24
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
CE2
CE2
I/O0-I/O23
128K x 24 HIGH-SPEED CMOS STATIC RAM
WITH 3.3V SUPPLY
IS61LV12824 ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
PIN CONFIGURATION - 119-pin PBGA PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O23 Data Inputs/Outputs
CE1, CE2 Chip Enable Input LOW
CE2 Chip Enable Input HIGH
OE Output Enable Input
WE Write Enable Input
NC No Connection
Vcc Power
VCCQ I/O Power
GND Ground
1234567
ANC A11 A14 A15 A16 A4 NC
BNC A12 A13 CE1 A5 A3 NC
CI/O16 NC CE2 NC CE2 NC I/O0
DI/O17 VCCQ GND GND GND VCCQ I/O1
EI/O18 GND VCC GND VCC GND I/O2
FI/O19 VCCQ GND GND GND VCCQ I/O3
GI/O20 GND VCC GND VCC GND I/O4
HI/O21 VCCQ GND GND GND VCCQ I/O5
JVCCQ GND VCC GND VCC GND VCCQ
KI/O22 VCCQ GND GND GND VCCQ I/O6
LI/O23 GND VCC GND VCC GND I/O7
MI/O12 VCCQ GND GND GND VCCQ I/O8
NI/O13 GND VCC GND VCC GND I/O9
PI/O14 VCCQ GND GND GND VCCQ I/O10
RI/O15 NC NC NC NC NC I/O11
TNC A10 A8 WE A0 A1 NC
UNC A9 A7 OE A6 A2 NC
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Integrated Silicon Solution, Inc. — 1-800-379-4774
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Rev. D
06/22/05
PIN CONFIGURATION
100-Pin TQFP
NC
Vcc
GND
I/O0
I/O1
GND
Vcc
Q
I/O2
I/O3
GND
Vcc
Q
I/O4
I/O5
Vcc
NC
NC
GND
I/O6
I/O7
Vcc
Q
GND
I/O8
I/O9
Vcc
Q
GND
I/O10
I/O11
Vcc
GND
NC
NC
NC
A11
A12
A13
A14
A15
CE2
Vcc
GND
CE2
CE1
A16
A5
A4
A3
NC
NC
NC
NC
NC
Vcc
GND
I/O16
I/O17
GND
Vcc
Q
I/O18
I/O19
GND
Vcc
Q
I/O20
I/O21
Vcc
NC
NC
GND
I/O22
I/O23
Vcc
Q
GND
I/O12
I/O13
Vcc
Q
GND
I/O14
I/O15
Vcc
GND
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
NC
NC
NC
NC
A10
A9
A8
A7
OE
GND
Vcc
WE
A6
A0
A1
A2
NC
NC
NC
NC
46 47 48 49 50
PIN DESCRIPTIONS
A0-A16 Address Inputs
I/O0-I/O23 Data Inputs/Outputs
CE1, CE2 Chip Enable Input LOW
CE2 Chip Enable Input HIGH
OE Output Enable Input
WE Write Enable Input
NC No Connection
Vcc Power
VCCQ I/O Power
GND Ground
IS61LV12824 ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
OPERATING RANGE
Range Ambient Temperature VCC (8 ns) VCC (10 ns)
Commercial 0°C to +70°C 3.3V + 10%, – 5% 3.3V ± 10%
Industrial –40°C to +85°C 3.3V + 10%, – 5% 3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –1 1 µA
Note:
1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 2.0 ns).
VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width ≤ 2.0 ns).
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VCC Power Supply Voltage Relative to GND –0.5 to 5.0 V
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TSTG Storage Temperature –65 to + 150 °C
TBIAS Temperature Under Bias: Com. –10 to + 85 °C
Ind. –45 to + 90 °C
PTPower Dissipation 2.0 W
IOUT DC Output Current ±20 mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
Mode WEWE
WEWE
WE CE1CE1
CE1CE1
CE1 CE2 CE2CE2
CE2CE2
CE2 OEOE
OEOE
OE I/O0-I/O23 Vcc Current
Not Selected X H X X X High-Z ISB1, ISB2
XXLXX
XXXHX
Output Disabled H L H L H High-Z ICC
Read H L H L L DOUT ICC
Write L L H L X DIN ICC
IS61LV12824
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ISSI
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Integrated Silicon Solution, Inc. — 1-800-379-4774
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Rev. D
06/22/05
CAPACITANCE(1)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC Vcc Dynamic Operating VCC = Max., Com. — 210 — 180 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 240 — 210
ISB1TTL Standby Current VCC = Max., Com. — 70 — 50 mA
(TTL Inputs) VIN = VIH or VIL, f = max. Ind. — 80 — 55
CE1, CE2, ≥ VIH, CE2 ≤ VIL
ISB2CMOS Standby VCC = Max., Com. — 10 — 10 mA
Current (CMOS Inputs) CE1, CE2 ≥ VCC – 0.2V, Ind. — 20 — 20
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, f = 0
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 2 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Figure 1 Figure 2
319 Ω
5 pF
Including
jig and
scope
353 Ω
OUTPUT
3.3V
OUTPUT Z
O
= 50Ω
1.5V
50Ω
IS61LV12824 ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 10 — ns
tAA Address Access Time — 8 — 10 ns
tOHA Output Hold Time 3 — 3 — ns
tACE CE1, CE2 Access Time 8 — — 10 ns
tACE2CE2 Access Time
tDOE OE Access Time — 4 — 4 ns
tHZOE
(2)
OE to High-Z Output 0 3 0 3 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — n s
tHZCE
(2)
CE1, CE2 to High-Z Output 0 4 0 5 n s
tHZCE
2
(2)
CE2 to High-Z Output
tLZCE
(2)
CE, CE2 to Low-Z Output 3 — 3 — n s
tLZCE
2
(2)
CE2 to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
IS61LV12824
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Integrated Silicon Solution, Inc. — 1-800-379-4774
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Rev. D
06/22/05
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
(Address Controlled) (CE1 = CE2 = OE = V
IL
; CE2 = V
IH
)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1, CE2 = VIL. CE2 = VIH.
3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition.
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA t
OHA
t
RC
DOUT
ADDRESS
t RC
t OHA
t AA
t DOE
t LZOE
t ACS1
t ACS2
t LZCS1
t LZCS2
t HZOE
HIGH-Z DATA VALID
ADDRESS
OE
CS1
CS2
D
OUT
t HZCS1
t HZCS2
CS2_RD2.eps
IS61LV12824 ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 -10
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — n s
tSCE CE1, CE2 to Write End 7 — 8 — ns
tSCE
2
CE2 to Write End 7 — 8 —
tAW Address Setup Time 7 — 8 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — n s
tSA Address Setup Time 0 — 0 — ns
tPWE1WE Pulse Width (OE = HIGH) 6 — 8 — ns
tPWE2WE Pulse Width (OE = LOW) 6 — 9 — ns
tSD Data Setup to Write End 4.5 — 5 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 3.5 — 3.5 n s
tLZWE
(2)
WE HIGH to Low-Z Output 3 — 3 — n s
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
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Rev. D
06/22/05
WRITE CYCLE NO. 1
(CE Controlled, OE = HIGH or LOW)
WRITE CYCLE NO. 2(1)
(WE Controlled: OE = HIGH during Write Cycle)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCE1
t SCE2
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE1
CE2
WE
D
OUT
DIN DATAIN VALID
t LZWE
t SD
CE2_WR1.eps
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
HIGH
CE2
CE2_WR2.eps
IS61LV12824 ISSI
®
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05
WRITE CYCLE NO. 3(1)
(WE Controlled: OE
I
S
LOW
DURING
W
RITE
C
YLE
)
Note:
1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE1
WE
DOUT
DIN
OE
DATAIN VALID
t
LZWE
t
SD
HIGH
CE2
CE2_WR3.eps
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Integrated Silicon Solution, Inc. — 1-800-379-4774
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Rev. D
06/22/05
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IS61LV12824-8B Plastic Ball Grid Array
IS61LV12824-8BL Plastic Ball Grid Array, Lead-free
IS61LV12824-8TQ TQFP
10 IS61LV12824-10B Plastic Ball Grid Array
IS61LV12824-10BL Plastic Ball Grid Array, Lead-free
IS61LV12824-10TQ TQFP
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
8 IS61LV12824-8BI Plastic Ball Grid Array
10 IS61LV12824-10BI Plastic Ball Grid Array
IS61LV12824-10TQI TQFP
IS61LV12824-10TQLI TQFP, Lead-free
PACKAGING INFORMATION ISSI®
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. B
02/12/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Plastic Ball Grid Array
Package Code: B (119-pin)
Notes:
1. Controlling dimension: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protrusion and
should be measured from the bottom of the package.
4. Formed leads shall be planar with respect to one another within
0.004 inches at the seating plane.
MILLIMETERS INCHES
Sym. Min. Max. Min. Max.
N0.
Leads 119
A — 2.41 — 0.095
A1 0.50 0.70 0.020 0.028
A2 0.80 1.00 0.032 0.039
A3 1.30 1.70 0.051 0.067
A4 0.56 BSC 0.022 BSC
b 0.60 0.90 0.024 0.035
D 21.80 22.20 0.858 0.874
D1 20.32 BSC 0.800 BSC
D2 19.40 19.60 0.764 0.772
E 13.80 14.20 0.543 0.559
E1 7.62 BSC 0.300 BSC
E2 11.90 12.10 0.469 0.476
e 1.27 BSC 0.050 BSC
E1
A1
D1
7654321
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
E2
E
A2
SEATING PLANE
e
D2D
A
30ϒ
A3
A4
φ
b (119X)
Integrated Silicon Solution, Inc. — 1-800-379-4774
PACKAGING INFORMATION ISSI
®
PK13197LQ Rev. D 05/08/03
TQFP (Thin Quad Flat Pack Package)
Package Code: TQ
Thin Quad Flat Pack (TQ)
Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 100 128
A — 1.60 — 0.063 — 1.60 — 0.063
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
A2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057
b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011
D 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874
D1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791
E 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638
E1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555
e 0.65 BSC 0.026 BSC 0.50 BSC 0.020 BSC
L 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030
L1 1.00 REF. 0.039 REF. 1.00 REF. 0.039 REF.
C0
o
7
o
0
o
7
o
0
o
7
o
0
o
7
o
Notes:
1. All dimensioning and
tolerancing conforms to
ANSI Y14.5M-1982.
2. Dimensions D1 and E1 do
not include mold protrusions.
Allowable protrusion is 0.25
mm per side. D1 and E1 do
include mold mismatch and
are determined at datum
plane -H-.
3. Controlling dimension:
millimeters.
D
D1
EE1
1
N
A2 A
A1
e
b
SEATING
PLANE
CL1
L
