Semiconductor Components Industries, LLC, 2004
August, 2004 − Rev. 1 1Publication Order Number:
NE5517/D
NE5517, NE5517A, AU5517
Dual Operational
Transconductance
Amplifier
The AU5517 and NE5517 contain two current-controlled
transconductance amplifiers, each with a differential input and
push-pull output. The AU5517/NE5517 offers significant design and
performance advantages over similar devices for all types of
programmable gain applications. Circuit performance is enhanced
through the use of linearizing diodes at the inputs which enable a
10 dB signal-to-noise improvement referenced to 0.5% THD. The
AU5517/NE5517 is suited for a wide variety of industrial and
consumer applications.
Constant impedance of the buffers on the chip allow general use of
the AU5517/NE5517. These buffers are made of Darlington
transistors and a biasing network that virtually eliminate the change of
offset voltage due to a burst in the bias current IABC, hence eliminating
the audible noise that could otherwise be heard in high quality audio
applications.
Features
•Constant Impedance Buffers
•VBE of Buffer is Constant with Amplifier IBIAS Change
•Excellent Matching Between Amplifiers
•Linearizing Diodes
•High Output Signal-to-Noise Ratio
Applications
•Multiplexers
•Timers
•Electronic Music Synthesizers
•Dolby HX Systems
•Current-controlled Amplifiers, Filters
•Current-controlled Oscillators, Impedances
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PIN CONNECTIONS
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
ORDERING INFORMATION
1
2
3
4
5
6
7
89
10
11
12
13
14
16
15
IABCa
Da
+INa
−INa
VOa
V−
INBUFFERa
VOBUFFERa
IABCb
Db
+INb
−INb
VOb
V+
INBUFFERb
VOBUFFERb
N, D Packages
(Top View)
PDIP−16
N SUFFIX
CASE 648
16 1
SOIC−16
D SUFFIX
CASE 751B
16
1
MARKING
DIAGRAMS
NE5517AN
AWLYYWW
NE5517N
AWLYYWW
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
AU5517D
AWLYWW
NE5517D
AWLYWW
NE5517, NE5517A, AU5517
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PIN DESCRIPTION
Pin No. Symbol Description
1 IABCa Amplifier Bias Input A
2 DaDiode Bias A
3 +INaNon-inverted Input A
4 −INaInverted Input A
5 VOaOutput A
6 V− Negative Supply
7 INBUFFERa Buffer Input A
8 VOBUFFERa Buffer Output A
9 VOBUFFERb Buffer Output B
10 INBUFFERb Buffer Input B
11 V+ Positive Supply
12 VObOutput B
13 −INbInverted Input B
14 +INbNon-inverted Input B
15 DbDiode Bias B
16 IABCb Amplifier Bias Input B
V+
11
D4
Q6
Q7
2,15
D2
Q4 Q5
D3
−INPUT
4,13 +INPUT
3,14
AMP BIAS
INPUT
1,16 Q2
Q1
D1
V−6
Q10
D6
Q11
VOUTPUT
5,12
Q9
Q8
D5
Q14
Q15 Q16
R1
D7
D8
Q3
7,10 Q12 Q13
8,9
Figure 1. Circuit Schematic
NE5517, NE5517A, AU5517
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NOTE: V+ of output buffers and amplifiers are internally connected.
B
AMP
BIAS
INPUT
B
DIODE
BIAS
B
INPUT
(+)
B
INPUT
(−) B
OUTPUT V+ (1)
B
BUFFER
INPUT
B
BUFFER
OUTPUT
AMP
BIAS
INPUT
DIODE
BIAS INPUT
(+) INPUT
(−) OUTPUT V− BUFFER
INPUT BUFFER
OUTPUT
AAA AAAA
123 45 6 7 8
16 15 14 13 12 11 10 9
−
+
B
+
−
A
Figure 2. Connection Diagram
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage (Note 1) VS44 VDC or ±22 V
Power Dissipation, Tamb = 25 °C (Still Air) (Note 2) NE5517N, NE5517AN
NE5517D, AU5517D
PD1500
1125
mW
Thermal Resistance, Junction−to−Ambient D Package
N Package
RJA 140
94
°C/W
Differential Input Voltage VIN ±5.0 V
Diode Bias Current ID2.0 mA
Amplifier Bias Current IABC 2.0 mA
Output Short-Circuit Duration ISC Indefinite
Buffer Output Current (Note 3) IOUT 20 mA
Operating Temperature Range NE5517N, NE5517AN
AU5517T
Tamb 0 °C to +70 °C
−40 °C to +125 °C
°C
Operating Junction Temperature TJ150 °C
DC Input Voltage VDC +VS to −VS
Storage Temperature Range Tstg −65 °C to +150 °C°C
Lead Soldering Temperature (10 sec max) Tsld 230 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. For selections to a supply voltage above ±22 V, contact factory.
2. The following derating factors should be applied above 25 °C
N package at 10.6 mW/°C
D package at 7.1 mW/°C.
3. Buffer output current should be limited so as to not exceed package dissipation.
NE5517, NE5517A, AU5517
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DC ELECTRICAL CHARACTERISTICS (Note 4)
AU5517/NE5517 NE5517A
Characteristic Symbol Test Conditions Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS Overtemperature Range
IABC 5.0 A
0.4
0.3
5.0
5.0
0.4
0.3
2.0
5.0
2.0
mV
VOS/TAvg. TC of Input Offset Voltage 7.0 7.0 V/°C
VOS Including Diodes Diode Bias Current
(ID) = 500 A0.5 5 0.5 2.0 mV
Input Offset Change VOS 5.0 A ≤IABC ≤500 A 0.1 0.1 3.0 mV
Input Offset Current IOS 0.1 0.6 0.1 0.6 A
IOS/TAvg. TC of Input Offset Current 0.001 0.001 A/°C
Input Bias Current IBIAS Overtemperature Range 0.4
1.0 5.0
8.0 0.4
1.0 5.0
7.0 A
IB/TAvg. TC of Input Current 0.01 0.01 A/°C
Forward Transconductance gMOvertemperature Range 6700
5400 9600 13000 7700
4000 9600 12000 mho
gM Tracking 0.3 0.3 dB
Peak Output Current IOUT RL = 0, IABC = 5.0 A
RL = 0, IABC = 500 A
RL = 0, Overtemperature Range 350
300
5.0
500 650 3.0
350
300
5.0
500
7.0
650 A
Peak Output Voltage
Positive
Negative
VOUT RL = ∞, 5.0 A ≤ IABC ≤ 500 A
RL = ∞, 5.0 A ≤ IABC ≤ 500 A+12
−12 +14.2
−14.4 +12
−12 +14.2
−14.4
V
Supply Current ICC IABC = 500 A, both channels 2.6 4.0 2.6 4.0 mA
VOS Sensitivity Positive
Negative VOS/ V+
VOS/ V− 20
20 150
150 20
20 150
150
V/V
Common-mode Rejection
Ration CMRR 80 110 80 110 dB
Common-mode Range ±12 ±13.5 ±12 ±13.5 V
Crosstalk Referred to Input (Note 5)
20 Hz < f < 20 kHz 100 100 dB
Differential Input Current IIN IABC = 0, Input = ±4.0 V 0.02 100 0.02 10 nA
Leakage Current IABC = 0 (Refer to Test Circuit) 0.2 100 0.2 5.0 nA
Input Resistance RIN 10 26 10 26 k
Open-loop Bandwidth BW2.0 2.0 MHz
Slew Rate SR Unity Gain Compensated 50 50 V/s
Buffer Input Current INBUFFER 5 0.4 5.0 0.4 5.0 A
Peak Buffer Output Voltage VOBUFFER 5 10 10 V
VBE of Buffer Refer to Buffer VBE Test
Circuit (Note 6) 0.5 5.0 0.5 5.0 mV
4. These specifications apply for VS = ±15 V, Tamb = 25°C, amplifier bias current (IABC) = 500 A, Pins 2 and 15 open unless otherwise
specified. The inputs to the buf fers are grounded and outputs are open.
5. These specifications apply for VS = ±15 V, IABC = 500 A, ROUT = 5.0 k connected from the buf fer output to − VS and the input of the buffer
is connected to the transconductance amplifier output.
6. VS = ±15, ROUT = 5.0 k connected from Buffer output to −VS and 5.0 A ≤ IABC ≤ 500 A.
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TYPICAL PERFORMANCE CHARACTERISTICS
VOUT
VCMR
VOUT
µ
10
10
10
10
1
PEAK OUTPUT CURRENT ( A)
0.1A1A10A 100A 1000A
AMPLIFIER BIAS CURRENT (IABC)
+125°C
4
3
2
+25°C
-55°C
10
10
10
10
10
4
3
2
5
-50°C -25°C0°C25°C50°C75°C100°C125°C
0V
(+)VIN = (−)VIN = VOUT = 36V
LEAKAGE CURRENT (pA)
AMBIENT TEMPERATURE (TA)
µ
10
10
10
10
10
TRANSCONDUCTANCE (gM) — ( ohm)
4
3
2
0.1A1A10A 100A 1000A
AMPLIFIER BIAS CURRENT (IABC)
+125°C
+25°C
-55°C
5gM mq
m
M
PINS 2, 15
OPEN
10
10
1
0.1
0.01
INPUT RESISTANCE (MEG )
1
2
0.1A1A10A 100A 1000A
AMPLIFIER BIAS CURRENT (IABC)
PINS 2, 15
OPEN
10
10
10
10
1
INPUT LEAKAGE CURRENT (pA)
3
2
4
INPUT DIFFERENTIAL VOLTAGE
+125°C
+25°C
01234567
5
INPUT OFFSET VOLTAGE (mV)
0.1A1A10A 100A 1000A
AMPLIFIER BIAS CURRENT (IABC)
Figure 3. Input Offset Voltage
VS = ±15V
+125°C
+25°C
-55°C
+125°C
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
5
PEAK OUTPUT VOLTAGE AND
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8 0.1A1A10A 100A 1000A
AMPLIFIER BIAS CURRENT (IABC)
Tamb = 25°C
VCMR
RLOAD = ∞
COMMON-MODE RANGE (V)
10
10
10
1
0.1
INPUT OFFSET CURRENT (nA)
2
3
0.1A1A10A 100A 1000A
AMPLIFIER BIAS CURRENT (IABC)
Figure 4. Input Bias Current
VS = ±15V
+125°C
+25°C
-55°C
10
10
10
10
1
INPUT BIAS CURRENT (nA)
3
4
0.1A1A10A 100A 1000A
AMPLIFIER BIAS CURRENT (IABC)
Figure 5. Input Bias Current
VS = ±15V
+125°C
+25°C
-55°C
2
Figure 6. Peak Output Current Figure 7. Peak Output Voltage and
Common-Mode Range Figure 8. Leakage Current
Figure 9. Input Leakage Figure 10. Transconductance Figure 11. Input Resistance
Ω
VS = ±15V
VS = ±15V
VS = ±15V
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
1 VOLT RMS (dB)
20
0
-20
-40
-60
-80
-100
OUTPUT VOLTAGE RELATIVE TO
0.1A1A10A 100A 1000A
IABC AMPLIFIER BIAS CURRENT (A)
VS = ±15V
RL = 10k
OUTPUT NOISE
20kHz BW
VIN = 40mVP-P
VIN = 80mVP-P
VS = ±15V Tamb = +25°C
CIN
COUT
7
6
5
4
3
2
1
00.1A1A10A 100A 1000A
CAPACITANCE (pF)
AMPLIFIER BIAS CURRENT (IABC)
0.1A1A10A 100A 1000A
2000
1800
1600
1400
1200
1000
800
600
400
200
0
AMPLIFIER BIAS VOLTAGE (mV)
AMPLIFIER BIAS CURRENT (IABC)
-55°C
+25°C
+125°C
OUTPUT DISTORTION (%)
100
10
1
0.1
0.01 1 10 100 1000
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
600
500
400
300
200
100
010 100 1k 10k 100k
OUTPUT NOISE CURRENT (pA/Hz)
FREQUENCY (Hz)
IABC = 1mA
IABC = 100A
Figure 12. Amplifier Bias Voltage vs.
Amplifier Bias Current Figure 13. Input and Output
Capacitance Figure 14. Distortion vs. Differential
Input Voltage
Figure 15. Voltage vs. Amplifier Bias Current Figure 16. Noise vs. Frequency
IABC = 1mA
RL = 10k
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 17. Leakage Current Test Circuit Figure 18. Differential Input Current Test Circuit
Figure 19. Buffer VBE Test Circuit
4, 13
2, 15
3, 14
−
+
NE5517
11
6
1, 15
5, 12 7, 10
8, 9
A
+36V
4, 13
2, 15
3, 14
−
+
NE5517
11
6
1, 10
5, 12
A
+15V
−15V
4V
V
V+
50k
V−
APPLICATIONS
4, 13
2, 15
3, 14
−
+
NE5517
11
6
5, 12
1, 16
+15V
−15V
7, 10
8, 9
INPUT
OUTPUT
390pF
−15V
51
0.01F
0.001F
0.01F
Figure 20. Unity Gain Follower
10k
1.3k
10k
62k
5k
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CIRCUIT DESCRIPTION
The circuit schematic diagram of one-half of the
AU5517/NE5517, a dual operational transconductance
amplifier with linearizing diodes and impedance buffers, is
shown in Figure 21.
Transconductance Amplifier
The transistor pair, Q4 and Q5, forms a transconductance
stage. The ratio of their collector currents (I4 and I5,
respectively) is defined by the differential input voltage,
VIN, which is shown in Equation 1.
VIN KT
qIn I5
I4(eq. 1)
Where VIN is the difference of the two input voltages
KT ≅ 26 mV at room temperature (300°k).
Transistors Q1, Q2 and diode D1 form a current mirror
which focuses the sum of current I4 and I5 to be equal to
amplifier bias current IB:
I4I5IB(eq. 2)
If VIN is small, the ratio of I5 and I4 will approach unity
and the Taylor series of In function can be approximated as
KT
qIn I5
I4KT
qI5I4
I4(eq. 3)
and I4I5IB
KT
qInI5
I4KT
qI5I4
12IB2KT
qI5I4
IBVIN (eq. 4)
I5I4VIN IBq
2KT
The remaining transistors (Q6 to Q11) and diodes (D4 to D6)
form three current mirrors that produce an output current
equal to I5 minus I4. Thus:
VIN IBq
2KTIO(eq. 5)
The term IBq
2KT is then the transconductance of the amplifier
and is proportional to IB.
V+11 D4
Q6
Q7
2,15
D2
Q4 Q5
D3
−INPUT
4,13 +INPUT
3,14
AMP BIAS
INPUT
1,16 Q2
Q1
D1
V−6
Q10
D6
Q11
VOUTPUT
5,12
Q9
Q8
D5
Q14
Q15 Q16
R1
D7
D8
Q3
7,10 Q12 Q13
8,9
Figure 21. Circuit Diagram of NE5517
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Linearizing Diodes
For V IN greater than a few millivolts, Equation 3 becomes
invalid and the transconductance increases non-linearly.
Figure 22 shows how the internal diodes can linearize the
transfer function of the operational amplifier. Assume D2
and D3 are biased with current sources and the input signal
current is IS. Since I4 + I5 = IB and I5 − I4 = I0,
that is: I4 = (IB − I0), I5 = (IB + I0)
+VS
ID
IB
I5
Q4
1/2ID
ISIS
1/2ID
−VS
I4I5
D3D2
ID
2IS
ID
2ISI0I5I4
I02I
SIB
ID
Figure 22. Linearizing Diode
For the diodes and the input transistors that have identical
geometries and are subject to similar voltages and
temperatures, the following equation is true:
T
qIn
ID
2IS
ID
2IS
KT
qIn 12(IBIO)
12(IBIO)(eq. 6)
IOIS2IB
IDfor |IS|ID
2
The only limitation is that the signal current should not
exceed ID.
Impedance Buffer
The upper limit of transconductance is defined by the
maximum value of IB (2.0 mA). The lowest value of IB for
which the amplifier will function therefore determines the
overall dynamic range. At low values of IB, a buffer with
very low input bias current is desired. A Darlington
amplifier with constant-current source (Q14, Q15, Q16, D7,
D8, and R1) suits the need.
APPLICATIONS
Voltage-Controlled Amplifier
In Figure 23, the voltage divider R2, R3 divides the
input-voltage into small values (mV range) so the amplifier
operates in a linear manner.
It is:
IOUT VIN R3
R2R3gM;
VOUT IOUT RL;
AVOUT
VIN R3
R2R3gMRL
(3) gM = 19.2 IABC
(gM in mhos for IABC in mA)
Since gM is directly proportional to IABC, the amplification
is controlled by the voltage VC in a simple way.
When V C is taken relative to −VCC the following formula
is valid:
IABC (VC1.2V)
R1
The 1.2 V is the voltage across two base-emitter baths in
the current mirrors. This circuit is the base for many
applications of the AU5517/NE5517.
46
3
−
+
NE5517 5
11 1
7
8
VIN
R4 = R2/ /R3
+VCC
VC
R2
R3
R1
RL
RS
+VCC
INT
VOUT
−VCC
IOUT
IABC
TYPICAL VALUES: R1 = 47k
R2 = 10k
R3 = 200
R4 = 200
RL = 100k
RS = 47k
INT
Figure 23.
NE5517, NE5517A, AU5517
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Stereo Amplifier With Gain Control
Figure 24 shows a stereo amplifier with variable gain via
a control input. Excellent tracking of typical 0.3 dB is easy
to achieve. With the potentiometer, RP, the offset can be
adjusted. For AC-coupled amplifiers, the potentiometer
may be replaced with two 510 resistors.
Modulators
Because the transconductance of an OTA (Operational
Transconductance Amplifier) is directly proportional to
IABC, the amplification of a signal can be controlled easily.
The output current is the product from
transconductance×input voltage. The circuit is effective up
to approximately 200 kHz. Modulation of 99% is easy to
achieve.
4
3
−
+
NE5517/A
11
+VCC
8VOUT1
−VCC
13 6
14
−
+
NE5517/A
9
VC
RS
VOUT2
−VCC
VIN1
VIN2 RIN
RIN
RP+VCC RD
1
16
12
RL
+VCC
INT
INT
+VCC
RL
10
IABC
IABC
15
RP+VCC RD
1k
RC
1k
Figure 24. Gain-Controlled Stereo Amplifier
10k
30k
10k
15k
15k
10k
10k
5.1k
−VCC
4
6
3
−
+
NE5517/A
8
RS
VOUT
−VCC
VIN1
1
11
+VCC
RL
5
ID
2
RC
VIN2
SIGNAL IABC
7
CARRIER
INT
INT
+VCC
VOS
Figure 25. Amplitude Modulator
30k
15k
1k
10k
10k
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Voltage-Controlled Resistor (VCR)
Because a n O TA is capable of producing an output current
proportional to the input voltage, a voltage variable resistor
can be made. Figure 26 shows how this is done. A voltage
presented at the RX terminals forces a voltage at the input.
This voltage is multiplied by gM and thereby forces a current
through the RX terminals:
RxRRA
gMRA
where gM is approximately 19.21 MHOs at room
temperature. Figure 27 shows a Voltage Controlled Resistor
using linearizing diodes. This improves the noise
performance of the resistor.
Voltage-Controlled Filters
Figure 28 shows a Voltage Controlled Low-Pass Filter.
The circuit is a unity gain buffer until XC/gM is equal to
R/RA. Then, the frequency response rolls off at a 6dB per
octave with the −3 dB point being defined by the given
equations. Operating in the same manner, a Voltage
Controlled High-Pass Filter is shown in Figure 29. Higher
order filters can be made using additional amplifiers as
shown in Figures 30 and 31.
Voltage-Controlled Oscillators
Figure 32 shows a voltage-controlled triangle-square
wave generator. With the indicated values a range from
2.0 Hz to 200 kHz is possible by varying IABC from 1.0 mA
to 10 A.
The output amplitude is determined by IOUT ×ROUT.
Please notice the differential input voltage is not allowed
to be above 5.0 V.
With a slight modification of this circuit you can get the
sawtooth pulse generator, as shown in Figure 33.
APPLICATION HINTS
To hold the transconductance gM within the linear range,
IABC should be chosen not greater than 1.0 mA. The current
mirror ratio should be as accurate as possible over the entire
current range. A current mirror with only two transistors is
not recommended. A suitable current mirror can be built
with a PNP transistor array which causes excellent matching
and thermal coupling among the transistors. The output
current range of the DAC normally reaches from 0 to
−2.0 mA. In this application, however, the current range is
set through RREF (10 k) to 0 to −1.0 mA.
IDACMAX 2VREF
RREF 25V
10k1mA
−VCC
4
3
−
+
NE5517/A
8VOUT
−VCC
11 +VCC
RX
5
IO
2
R
7
INT
INT
C
+VCC VC
RX
RRA
gMRA
Figure 26. VCR
30k
200200100k10k
−VCC
4
3
NE5517/A
8
−VCC
11 +VCC
RX
5
ID
2
R
7
INT
INT
C
+VCC
VC
+VCC
VOS RP
1
6
Figure 27. VCR with Linearizing Diodes
30k
1k
100k10k
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12
fO
RAgM
g(R RA) 2C
NOTE:
−VCC
4
3
−
+
NE5517/A
8VOUT
−VCC
11 +VCC
5
IABC
2
R
7
INT
INT
C
+VCC
VC
RA
1
150pF
6
VIN
Figure 28. Voltage-Controlled Low-Pass Filter
30k
100k
200200100k10k
fO
RAgM
g(R RA) 2C
NOTE:
−VCC
4
3
−
+
NE5517/A
8VOUT
−VCC
11 +VCC
5
IABC
2
R
7
INT
INT
C
+VCC
VC
RA
1
6
VOS
NULL
+VCC
-VCC
0.005F
Figure 29. Voltage-Controlled High-Pass Filter
30k
100k
1k1k100k10k
NOTE:
fO
RAgM
(R RA)2C
+VCC
−
+
NE5517/A
VOUT
−VCC
+VCC
INT
INT
VC
RA
200pF
−
+
NE5517/A
+VCC
RA
R
C
−VCC
100pF
-VCC
VIN
RA
200
Figure 30. Butterworth Filter − 2nd Order
100k
200100k10k
200100
k200
15k
10k
C2
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+VCC
−
+
NE5517/A
VOUT
−VCC
+VCC
INT
INT
VC
800pF
−
+
NE5517/A
+VCC
−VCC
800pF
−VCC
6
11
3
2
1
57
13
15
14
12 10
16
LOW
PASS
9
BANDPASS OUT
Figure 31. State Variable Filter
10k
1k
20k
20k5.1k1k
15k
20k5.1k
+VCC
+
−
NE5517/A
VOUT2
−VCC
+VCC
INT
INT
+
−
NE5517/A
+VCC
−VCC
−VCC
6
11
4
3
57
14
13
12 10
VOUT1
GAIN
CONTROL
1
16
VC
C
0.1F8
INT
+VCC
9
Figure 32. Triangle−Square Wave Generator (VCO)
30k
20k
47k
10k
IB
NOTE:
VPK
(VC0.8) R1
R1R2TH
2VPK xC
IBTL
2VPKxC
ICfOSC
IC
2VPKxC ICIB
+VCC
−
+
NE5517/A
VOUT2
−VCC
+VCC
INT
INT
−
+
NE5517/A
+VCC
−VCC
−VCC
6
11
4
3
57
14
13
12 10
VOUT1
1
16
VC
C
0.1F8
INT
+VCC
2
R1R2
IC
Figure 33. Sawtooth Pulse VCO
470k
30k20k30k
47k30k
NE5517, NE5517A, AU5517
http://onsemi.com
14
ORDERING INFORMATION
Device Description Temperature Range Shipping†
AU5517DR2 16-Pin Small Outline (SO) Package −40 to +125 °C2500 Tape & Reel
NE5517D 16-Pin Small Outline (SO) Package 0 to +70 °C48 Units/Rail
NE5517DR2 16-Pin Small Outline (SO) Package 0 to +70 °C2500 Tape & Reel
NE5517N 16-Pin Plastic Dual In-Line Package (DIP) 0 to +70 °C25 Units/Rail
NE5517AN 16-Pin Plastic Dual In-Line Package (DIP) 0 to +70 °C25 Units/Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NE5517, NE5517A, AU5517
http://onsemi.com
15
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
HGD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
NE5517, NE5517A, AU5517
http://onsemi.com
16
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45
G
8 PLP
−B−
−A−
M
0.25 (0.010) B S
−T−
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019

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