THC63LVD1024_Rev.3.02_E
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THC63LVD1024
135MHz 67Bits LVDS Receiver
General Description
The THC63LVD1024 receiver is designed to support
Dual Link transmission between Host and Flat Panel
Display up to 1080p/QXGA resolutions. The
THC63LVD1024 conve rts the LVDS data streams back
into 67bits of CMOS/TTL data with falling edge or ris-
ing edge clock for convenient with a variety of LCD
panel controllers.
In Dual Link, data transmit clock frequency of
135MHz, 67bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data th roughput is 1.1Gbytes per
second.
Features
•Wide dot clock range suited for TV Signal(480i-
1080p), PC Signal(VGA-QXGA)
Dual LVD S po rt IN/Du a l TTL port Out Mod e :
8 - 135MHz(CLKOUT)
Dual LVD S port IN/Single TTL port Out Mode:
40 - 150MHz(CLKOUT)
•PLL requires No external components
•Flexible Input/Output mod e
1. Single/Dual LVDS port IN /Single/Dual TTL port OUT
2. Double Edge output
•50% output clo c k d ut y cycle
•TTL clock edge selectable
•TTL clock output timing programmable(3 step)
•2 Output data mapping for simplifying PCB layout.
•Power down mode
•144pin LQFP Exposed PAD
•EU RoHS Compliant
Block Diagram
SERIAL TO PARALLEL
PLL
35
35
RA1 +/-
RB1 +/-
RC1 +/-
RD1 +/-
MODE[2:0]
/PDWN
RCLK +/-
(8 to 135MHz)
LVDS INPUT 32 R1[9:0]
CLKOUT
TTL OUTPUT
LVDS INPUT
RE1 +/-
RA2 +/-
RB2 +/-
RC2 +/-
RD2 +/-
RE2 +/-
Port1
LVDS INPUT
Port2
DK
G1[9:0]
B1[9:0]
CONT1[2:1] Port1
OE
SERIAL TO PARALLEL
Data Formatter
1) DEMUX
3) DDR
2) MUX
R/F
MAP
32 R2[9:0]
TTL OUTPUT
G2[9:0]
B2[9:0]
CONT2[2:1] Port2
3Hsync
Vsync
DE
THC63LVD1024_Rev.3.02_E
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Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VCC
CONT12
VSYNC
DE
CONT11
VCC
R27
OE
MAP
MODE1
MODE0
MODE2
Reserved
DK
/PDWN
R20
PVCC
PGND
B17
B16
B15
B11
GND
B14
B13
B12
VCC
B10
G19
G18
G17
G16
G15
GND
VCC
G14
G13
G12
G11
G10
R19
R17
R16
GND
VCC
R15
R14
R13
R12
R10
PGND
PVCC
VCC
B19
HSYNC
GND
GND
R21
R22
R23
R24
R25
R26
VCC
R28
R29
G20
VCC
GND
G21
VCC
G22
G23
G24
G25
G26
G27
G28
G29
VCC
GND
B20
B21
B22
B23
B24
B25
R11
R/F
B26
B27
B28
B29
VCC
GND
VCC
CONT22
CONT21
CLKOUT
GND
GND
VCC
GND
CVCC
CGND
R18
B18
GND
LGND
RE2+
RE2-
RD2+
RD2-
LGND
LGND
RC2+
RC2-
LGND
LVCC
RB2+
RB2-
RA2+
RA2-
LGND
LGND
LGND
LGND
LGND
RE1+
RE1-
RD1+
RD1-
RC1+
RC1-
RCLK+
RCLK-
RB1+
RB1-
RA1-
RA1+
LVCC
LVCC
LVCC
LVCC
LQFP144
Exposed PAD
Top View
145GND(Exposed PAD)
THC63LVD1024_Rev.3.02_E
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Pin Description
Pin Name Pin # Type Description
RA1+, RA1- 111, 110 LVDS IN
The 1st Link. The 1st pixel input data when Dual Link.
RB1+, RB1- 113, 112 LVDS IN
RC1+, RC1- 117, 116 LVDS IN
RD1+, RD1- 123, 122 LVDS IN
RE1+, RE1- 125, 124 LVDS IN
RCLK+, RCLK- 119, 118 LVDS IN LVDS Clock Input.
RA2+, RA2- 129, 128 LVDS IN
The 2nd Link. These pins are disabled when Single Link.
RB2+, RB2- 131, 130 LVDS IN
RC2+, RC2- 135, 134 LVDS IN
RD2+, RD2- 141, 140 LVDS IN
RE2+, RE2- 143, 142 LVDS IN
R19 ~ R10 74 - 72, 69 - 63 OUT
The 1st Pixel Data Outputs.
G19 ~ G10 86 - 82, 79 - 75 OUT
B19 ~ B10 100, 99,
96-90, 87 OUT
R29 ~ R20 25-23, 20-14 OUT
The 2nd Pixel Data Outputs.G29 ~ G20 40, 37 - 31,
27, 26 OUT
B29 ~ B20 52 - 48, 45 - 41 OUT
CONT11,CONT12 104, 105 OUT User defined data output
CONT21,CONT22 55, 56
DE 103 OUT Data Enable Output.
VSYNC 102 OUT Vsync Output.
HSYNC 101 OUT Hsync Output.
CLKOUT 60 OUT Clock Output.
/PDWN 4 IN Power down and Output Control.(Table1)
H: Normal operation
L: Power down
MODE1, MODE0 6, 5 IN
Pixel Data Mode.
MODE1 MODE0 Mode
H H Single Link (Single-in/Single-out)
H L Single Link (Single-in/Dual-out)
L H Dual Link (Dual-in/Single-out)
L L Dual Link (Dual-in/Dual-out)
THC63LVD1024_Rev.3.02_E
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DK 7 IN
Output Clock Delay Timing Select.
R/F 8 IN Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge.
OE 9 IN Output Enable.(Table1)
H: Output enable, L: Output disable
MODE2 10 IN
DDR function enable.
The use of this function depends on the setting of
MODE<1:0>.
MODE<1:0>=LH(Dual-in/Single-out Mode)
H: DDR (Double Edge Output) function enable.
L: DDR (Double Edge Output) function disable.
MODE<1:0>=Other
Must be tied to GND
MAP 11 IN LVDS mapping table select. See Fig9,10 and Table2 - 9.
H: Mapping Mode1
L: Mapping Mode2
Reserved 3 IN Must be tied to VCC.
VCC
12, 21, 28, 29,
38, 46, 53, 57,
70, 80, 88, 97,
106
Power Power Supply Pins for TTL outputs and digital circuitry.
GND
13, 22, 30, 39,
47, 54, 58, 59,
71, 81, 89,
98,145
Ground Ground Pins for TTL outputs and digital circuitry.
LVCC 114, 120, 126,
132, 138 Power Power Supply Pins for LVDS inputs.
LGND 109, 115, 121,
127, 133, 136,
137, 139, 144 Ground Ground Pins for LVDS inputs.
PVCC 2, 107 Power Power Supply Pin for PLL circuitry.
PGND 1, 108 Ground Ground Pin for PLL circuitry.
CVCC 61 Power Power Supply Pins for TT L o ut put of CL KOUT.
CGND 62 Ground Ground Pins for TTL output of CLKOUT
Pin Name Pin # Type Description
tDOUT=Output Data Cycle
MODE[1:0] DK Offset [ns]
LL
HH
HL
L0
M
H
LH
L0
M
H
6tDOUT
28
---------------
–
6tDOUT
28
---------------
7tDOUT
28
---------------
–
7tDOUT
28
---------------
Pin Description (Continued)
THC63LVD1024_Rev.3.02_E
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Pin Description (Continued)
Table 1. Output Control
Absolute Maximum Ratings
Recommended Operating Conditions
/PDWN OE Data Outputs
(Rxn) CLKOUT
L L Hi-Z Hi-Z
L H All Low Fixed Low
H L Hi-Z Hi-Z
H H Data Out CLK Out
Supply Voltage (VCC)-0.3V ~ +4.0V
CMOS/TTL Input Voltage -0.3V ~ (VCC + 0.3V)
CMOS/TTL Output Voltage -0.3V ~ (VCC + 0.3V)
LVDS Receiver Input Voltage -0.3V ~ (VCC + 0.3V)
Output Current -30mA ~ 30mA
Junction Temperature +125
Storage Temperatu re Range -55 ~ +125
Reflow Peak Temperature / Time +260 / 10sec.
Maximum Power Dissipation @+25 4.4W
Parameter Min. Typ Max Unit
All Supply Voltage 3.0 3.3 3.6 V
Operating Ambient Temperature -40 - 85
CLK
Frequency
MODE<1:0>=LL
Dual-in/Dual-out
Ta ≦70
(Ta ≦85 )*
LVDS Input 8 - 135
(80)* MHz
Output 8 - 135
(80)* MHz
MODE<1:0>=LH
Dual-in/Single-out
Single Edge Output
(MODE2=L) LVDS Input 20 - 75 MHz
Output 40 - 150 MHz
Double Edge Output
(MODE2=H) LVDS Input 20 - 75 MHz
Output 20 - 75 MHz
MODE<1:0>=HL
Single-in/Dual-out LVDS Input 8 - 135 MHz
Output 4 - 67.5 MHz
MODE<1:0>=HH
Single-in/Single-out LVDS Input 8 - 135 MHz
Output 8 - 135 MHz
°C
°C°C
°C
°C
°C
°C
°C
THC63LVD1024_Rev.3.02_E
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Electrical Characteristics
CMOS/TTL DC Specifications VCC=VCC=PVCC=LVCC=CVCC
LVDS Receiver DC Specifications VCC=VCC=PVCC=LVCC=CVCC
Symbol Parameter Conditions Min. Typ Max Unit
VIH High Level Input Voltage /PDWN, MODE[2:0]
R/F, OE, MAP Pin
2.0 - VCC V
VIL Low Level Input Voltage GND - 0.8 V
VIH3 High Level Input Voltage 3-Level Inputs
(DK Pin)
0.8VCC -VCC V
VIM3 Middle Level Input Voltage 0.6VCC -0.4VCC V
VIL3 Low Level Input Voltage GND - 0.2VCC V
VOH High Level Output Voltage IOH= -8mA 2.4 - V
VOL Low Level Output Voltage IOL= 8mA --0.4V
IIL Input Leakage Current
/PDWN, MODE[2:0]
R/F, OE, MAP Pin -- μA
IIL3 3-Level Input Leakage Current
3-Level Inputs
(DK Pin) -- μA
Symbol Parameter Conditions Min. Typ. Max. Unit
VTH Differential Input High Threshold VIC= 1.2V --100mV
VTL Differential Input Low Threshold VIC= 1.2V -100 - - mV
IILD Differential Input Leakage Current VIN= 2.4V / 0V --30μA
0V VIN VCC
≤≤ 10±
0V VIN VCC
≤≤ 10±
THC63LVD1024_Rev.3.02_E
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Electrical Characteristics (Continued)
Supply Current VCC=VCC=PVCC=LVCC=CVCC
Symbol Parameter Condition Typ. Max. Unit
IRCCW
Receiver
Supply Current
(Worst Case
Pattern) Fig2.
CLKOUT=65MHz
CL=8pF
MODE<1:0>=HH
Single-in/Single-out
MODE2=L
-201mA
CLKOUT=85MHz - 248 mA
CLKOUT=135MHz - 364 mA
CLKOUT=32.5MHz MODE<1:0>=HL
Single-in/
Dual-out
-138mA
CLKOUT=42.5MHz - 164 mA
CLKOUT=67.5MHz - 233 mA
CLKOUT=65MHz MODE<1:0>=LH
Dual-in/Single-out
MODE2=L
DDR Output Off
-146mA
CLKOUT=85MHz - 165 mA
CLKOUT=135MHz - 210 mA
CLKOUT=150MHz - 223 mA
CLKOUT=32.5MHz MODE<1:0>=LH
Dual-in/Single-out
MODE2=H
DDR Output On
-147mA
CLKOUT=42.5MHz - 165 mA
CLKOUT=67.5MHz - 205 mA
CLKOUT=75MHz - 217 mA
CLKIN=65MHz MODE<1:0>=LL
Dual-in/Dual-out -366mA
CLKIN=85MHz - 453 mA
CLKIN=135MHz
MODE<1:0>=LL
Dual-in/Dual-out
Ta ≦ 70 -671mA
IRCCS
Receiver
Power Down
Supply Current /PDWN = L - 50 μA
°C
CLKOUT
Checker Pattern
Fig1. Test Pattern
Rxn, Gxn, Bxn
x = 1,2
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
CONT21,22
THC63LVD1024_Rev.3.02_E
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Electrical Characteristics (Continued)
Output load limitation
Output load is limited so that Junction temperature is not over 125
calculating formula
Tj = Ta + θja * P
P = VCC * (IOUTDT + IOUTCK + ICORE)
IOUTDT = 1/2 * FCLK * VCC * CLOAD * n
IOUTCK = FCLK * VCC * CLOAD
Tj : Junction temperature ≦125
Ta : Ambient temperature ≦70
θja : Package thermal resistance = 22 [ /W]
ICORE: Supply Current except all output buffers = 520mA
IOUTDT: Supply Current only output buffers of data output.
(R1,G1,B1,R2,G2,B2,HSYNC,VSYNC,DE,CONT11,CONT12,CONT21,CONT22)
IOUTCK: Supply Current only ou tput buffer of CLKOUT.
FCLK : CLKOUT Frequency
n : 67 (Number of data output pin)
Fig2. CMOS/TTL Output Load Limitation
°C
°C
°C
°C
Load Limita t ion
8
9
10
11
12
13
14
15
100 105 110 115 120 125 130 135
Frequency[MHz]
Output Load[ pF ]
THC63LVD1024_Rev.3.02_E
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Switching Characteristics
Symbol Parameter Min. Typ. Max. Unit
tRCP CLKOUT Period (Fig4) 6.67 T 250 ns
tRCH CLKOUT High Time(Fig4) - - ns
tRCL CLKOUT Low Time(Fig4) - - ns
tDOUT TTL Data OUT Period (Fig5,6) 6.67 T 250 ns
tRS TTL Data Setup to CLKOUT(Fig5,6) 0.45tDOUT -0.45 --ns
tRH TTL Data Hold to CLKOUT(Fig5,6) 0.45tDOUT -0.45 --ns
tTLH TTL Low to High Transition Time(Fig3) - 0.7 1.0 ns
tTHL TTL High to Low Transition Time(Fig3) - 0.7 1.0 ns
tSK
Receiver Skew
Margin
(Fig7)
tRCIP=65MHz -650 0 650 ps
tRCIP=85MHz -450 0 450 ps
tRCIP=108MHz -250 0 250 ps
tRCIP=135MHz -170 0 170 ps
tRIP1 Input Data Position0 (Fig7) -tSK 0+tSK ns
tRIP0 Input Data Position1 (Fig7) ns
tRIP6 Input Data Position2 (Fig7) ns
tRIP5 Input Data Position3 (Fig7) ns
tRIP4 Input Data Position4 (Fig7) ns
tRIP3 Input Data Position5 (Fig7) ns
tRIP2 Input Data Position6 (Fig7) ns
tRPLL Phase Lock Loop Set (Fig8) - - 10.0 ms
tRCD RCLK +/- to CLK OUT Delay (Fig9)
MODE<1:0>=LL DK=L, 75MHz 89.7 - 94 ns
tRCIP CLKIN Period (Fig7) 7.4 - 125.0 ns
tRCIH Differential CLKIN High Time (Fig7) - ns
tRCIL Differential CLKIN Low Time (Fig7) - ns
tDEINT MODE<1:0>=HL
(Single IN/ Dual
OUT Mode) Only
DE input period
(Fig9-1) 4tRCIP tRCIP*(2n)
n= integer -ns
tDEH DE input High time
(Fig9-1) 2tRCIP --ns
tDEL DE input Low time
(Fig9-1) 2tRCIP --ns
T
2
---
T
2
---
tRCIP
7
--------------t
SK
–tRCIP
7
--------------tRCIP
7
--------------t
SK
+
2tRCIP
7
--------------t
SK
–2tRCIP
7
--------------2
tRCIP
7
--------------t
SK
+
3tRCIP
7
--------------t
SK
–3tRCIP
7
--------------3
tRCIP
7
--------------t
SK
+
4tRCIP
7
--------------t
SK
–4tRCIP
7
--------------4
tRCIP
7
--------------t
SK
+
5tRCIP
7
--------------t
SK
–5tRCIP
7
--------------5
tRCIP
7
--------------t
SK
+
6tRCIP
7
--------------t
SK
–6tRCIP
7
--------------6
tRCIP
7
--------------t
SK
+
2tRCIP
7
----------------- 5 tRCIP
7
-----------------
2tRCIP
7
----------------- 5 tRCIP
7
-----------------
VCC=VCC=PVCC=LVCC=CVCC
THC63LVD1024_Rev.3.02_E
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VCC/2
VCC/2 VCC/2
CLKOUT
Rxn, Gxn, Bxn
x = 1,2
n = 0~9
VCC/2
VCC/2
tRCP
CLKOUT
Fig5. CLKOUT Position and Setup/Hold Timing
tRS tRH
R/F=H
R/F=L
R/F=H
R/F=L
DK=M
DK=L
CLKOUT
DK=H
R/F=H
R/F=L
6tDOUT
28
--------------------
or
7tDOUT
28
--------------------
VCC/2VCC/2
tDOUT
HSYNC,VSYNC
DE
CONT11,12
CONT21,22
6tDOUT
28
--------------------
or
7tDOUT
28
--------------------
AC Timing Diagrams
VCC/2 VCC/2 VCC/2
tRCP tRCH tRCL
CLKOUT VCC/2
Fig4. CLKOUT Period and High/Low Time
TTL Output
TTL Output Load
20%
80%
20%
80%
tTLH tTHL
C
L
=8pF
Fig3. CMOS/TTL Output Load and Transition Time
THC63LVD1024_Rev.3.02_E
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AC Timing Diagrams (Continued)
VCC/2
VCC/2 VCC/2
CLKOUT
tRCP
CLKOUT
Fig6. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode
tRS tRH
R/F=H
R/F=L
R/F=H
R/F=L
DK=M
DK=L
CLKOUT
DK=H
R/F=H
R/F=L
7tDOUT
28
--------------------
tRS tRH
VCC/2
1st Pixel
Data 2nd Pixel
Data
VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
7tDOUT
28
--------------------
7tDOUT
28
--------------------7tDOUT
28
--------------------
MODE<1:0>=LH, MODE2=H
tDOUT tDOUT
R1n, G1n, B1n
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
Vdiff = 0V Vdiff = 0V
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 Ryx0
Ryx+/-
Next CyclePrevious Cycle Current Cycle
Ryx3’ Ryx2’ Ryx1’ Ryx0’ Ryx6’’
Fig7. LVDS Input Data Position
x=1,2
y= A, B, C, D, E
Vdiff = 0V
tRCIL
tRCIH
tRCIP
RCLK
(Differential)
RCLK=(RCLK+)-(RCLK-)
THC63LVD1024_Rev.3.02_E
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AC Timing Diagrams (Continued)
Vdiff = 0V
tRCD
RCLK+
CLKOUT
R/F=L
Note:
1) Vdiff = (RCLK+) - (RCLK-)
Fig9. RCLK +/- to CLKOUT Delay
2.0V
VCC/2
tRPLL
RCLK+/-
/PDWN
CLKOUT
Fig8. PLL Lock Loop Set Time
RC1+
RCLK+
Fig9-1. Single IN / Dual OUT mode RC1(DE) input timing
DE
tDEINT
tDEH tDEL
DE DE DE DE DE
VCC/2
Current Data
Current Data
Ryx+/-
x=1,2
y= A, B, C, D, E
R1n, G1n, B1n
n = 0~9
HSYNC,VSYNC
DE
CONT11,12
THC63LVD1024_Rev.3.02_E
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Output Data Mapping
Table2. Output Color Data naming rule
Table3. TTL/CMOS Output Data Mapping (Single-out mode, MODE0=H)
XYZ Description
X=R - - Red Color Data
X=G - - Green Color Data
X=B - - Blue Color Data
Y= None - Single Pixel
Y=O - Dual Pixel 1st Pixel Data
Y=E - 2nd Pixel Data
Z=0-9 Bit number 0: LSB (Least Significant Bit)
9: MSB (Most Significant Bit)
Data Signal Receiver Output Pin Name
30-bit 24-bit 18-bit 30-bit 24-bit 18-bit
R0 - - R10 - -
R1 - - R11 - -
R2 R0 - R12 R12 -
R3 R1 - R13 R13 -
R4 R2 R0 R14 R14 R14
R5 R3 R1 R15 R15 R15
R6 R4 R2 R16 R16 R16
R7 R5 R3 R17 R17 R17
R8 R6 R4 R18 R18 R18
R9 R7 R5 R19 R19 R19
G0 - - G10 - -
G1 - - G11 - -
G2 G0 - G12 G12 -
G3 G1 - G13 G13 -
G4 G2 G0 G14 G14 G14
G5 G3 G1 G15 G15 G15
G6 G4 G2 G16 G16 G16
G7 G5 G3 G17 G17 G17
G8 G6 G4 G18 G18 G18
G9 G7 G5 G19 G19 G19
B0 - - B10 - -
B1 - - B11 - -
B2 B0 - B12 B12 -
B3 B1 - B13 B13 -
B4 B2 B0 B14 B14 B14
B5 B3 B1 B15 B15 B15
B6 B4 B2 B16 B16 B16
B7 B5 B3 B17 B17 B17
B8 B6 B4 B18 B18 B18
B9 B7 B5 B19 B19 B19
THC63LVD1024_Rev.3.02_E
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Output Data Mapping (Continued)
Table4. TTL/CMOS Output Data Mapping (Dual-out mode, MODE0=L)
1st Pixel Data 2nd Pixel Data
Data Signal Receiver Output Pin
Name Data Signal Receiver Output Pin
Name
30-bit 24-bit 18-bit 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit 30-bit 24-bit 18-bit
RE0 - - R10 - - RO0 - - R20 - -
RE1 - - R11 - - RO1 - - R22 - -
RE2 RE0 - R12 R12 - RO2 RO0 - R22 R22 -
RE3 RE1 - R13 R13 - RO3 RO1 - R23 R23 -
RE4 RE2 RE0 R14 R14 R14 RO4 RO2 RO0 R24 R24 R24
RE5 RE3 RE1 R15 R15 R15 RO5 RO3 RO1 R25 R25 R25
RE6 RE4 RE2 R16 R16 R16 RO6 RO4 RO2 R26 R26 R26
RE7 RE5 RE3 R17 R17 R17 RO7 RO5 RO3 R27 R27 R27
RE8 RE6 RE4 R18 R18 R18 RO8 RO6 RO4 R28 R28 R28
RE9 RE7 RE5 R19 R19 R19 RO9 RO7 RO5 R29 R29 R29
GE0 - - G10 - - GO0 - - G20 - -
GE1 - - G11 - - GO1 - - G22 - -
GE2 GE0 - G12 G12 - GO2 GO0 - G22 G22 -
GE3 GE1 - G13 G13 - GO3 GO1 - G23 G23 -
GE4 GE2 GE0 G14 G14 G14 GO4 GO2 GO0 G24 G24 G24
GE5 GE3 GE1 G15 G15 G15 GO5 GO3 GO1 G25 G25 G25
GE6 GE4 GE2 G16 G16 G16 GO6 GO4 GO2 G26 G26 G26
GE7 GE5 GE3 G17 G17 G17 GO7 GO5 GO3 G27 G27 G27
GE8 GE6 GE4 G18 G18 G18 GO8 GO6 GO4 G28 G28 G28
GE9 GE7 GE5 G19 G19 G19 GO9 GO7 GO5 G29 G29 G29
BE0 - - B10 - - BO0 - - B20 - -
BE1 - - B11 - - BO1 - - B22 - -
BE2 BE0 - B12 B12 - BO2 BO0 - B22 B22 -
BE3 BE1 - B13 B13 - BO3 BO1 - B23 B23 -
BE4 BE2 BE0 B14 B14 B14 BO4 BO2 BO0 B24 B24 B24
BE5 BE3 BE1 B15 B15 B15 BO5 BO3 BO1 B25 B25 B25
BE6 BE4 BE2 B16 B16 B16 BO6 BO4 BO2 B26 B26 B26
BE7 BE5 BE3 B17 B17 B17 BO7 BO5 BO3 B27 B27 B27
BE8 BE6 BE4 B18 B18 B18 BO8 BO6 BO4 B28 B28 B28
BE9 BE7 BE5 B19 B19 B19 BO9 BO7 BO5 B29 B29 B29
THC63LVD1024_Rev.3.02_E
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LVDS Input Data Mapping
Rx1+/-
RCLK+
Previous Cycle Current Cycle
Fig10. LVDS Inputs Mapped to TTL Data Outputs
x= A, B, C, D, E
Rx11(n-1) Rx10(n-1) Rx16(n) Rx15(n) Rx14(n) Rx13(n) Rx12(n) Rx11(n) Rx10(n) Rx16(n+1)
(2nd Pixel Data) (1st Pixel Data)
Rx1+/-
RCLK+
Next CycleCurrent Cycle
x= A, B, C, D, E
Rx11(n) Rx10(n) Rx16(n+1) Rx15(n+1) Rx14(n+1) Rx13(n+1) Rx12(n+1) Rx11(n+1) Rx10(n+1) Rx16(n+2)
(2nd Pixel Data)(1st Pixel Data)
MODE1= H (Single-in Mode)
Rx1+/-
RCLK+
Previous Cycle Current Cycle
Fig11. LVDS Inputs Mapped to TTL Data Outputs
MODE1= L (Dual-in Mode)
x= A, B, C, D, E
Rx11(n-1) Rx10(n-1) Rx16(n) Rx15(n) Rx14(n) Rx13(n) Rx12(n) Rx11(n) Rx10(n) Rx16(n+1)
Rx21(n-1) Rx20(n-1) Rx26(n) Rx25(n) Rx24(n) Rx23(n) Rx22(n) Rx21(n) Rx20(n) Rx26(n+1)
Rx2+/-
x= A, B, C, D, E
THC63LVD1024_Rev.3.02_E
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LVDS Input Data Mapping (Continued)
Table5. LVDS Input Data Mapping (Single-in/Single-out, MODE<1:0>=HH)
LVDS
Input Data Mapping Mode1
(Output Pin Name) Mapping Mode2
(Output Pin Name)
RA10 R14 R12
RA11 R15 R13
RA12 R16 R14
RA13 R17 R15
RA14 R18 R16
RA15 R19 R17
RA16 G14 G12
RB10 G15 G13
RB11 G16 G14
RB12 G17 G15
RB13 G18 G16
RB14 G19 G17
RB15 B14 B12
RB16 B15 B13
RC10 B16 B14
RC11 B17 B15
RC12 B18 B16
RC13 B19 B17
RC14 HSYNC HSYNC
RC15 VSYNC VSYNC
RC16 DE DE
RD10 R12 R18
RD11 R13 R19
RD12 G12 G18
RD13 G13 G19
RD14 B12 B18
RD15 B13 B19
RD16 CONT11 CONT11
RE10 R10 R10
RE11 R11 R11
RE12 G10 G10
RE13 G11 G11
RE14 B10 B10
RE15 B11 B11
RE16 CONT12 CONT12
THC63LVD1024_Rev.3.02_E
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LVDS Input Data Mapping (Continued)
Table6. LVDS Input Data Mapping (Single-in/Dual-out, MODE<1:0>=HL)
1st Pixel Data 2nd Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name) Mapping Mode2
(Output Pin Name)
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name) Mapping Mode2
(Output Pin Name)
RA10(n) R14 R12 RA10(n+1) R24 R22
RA11(n) R15 R13 RA11(n+1) R25 R23
RA12(n) R16 R14 RA12(n+1) R26 R24
RA13(n) R17 R15 RA13(n+1) R27 R25
RA14(n) R18 R16 RA14(n+1) R28 R26
RA15(n) R19 R17 RA15(n+1) R29 R27
RA16(n) G14 G12 RA16(n+1) G24 G22
RB10(n) G15 G13 RB10(n+1) G25 G23
RB11(n) G16 G14 RB11(n+1) G26 G24
RB12(n) G17 G15 RB12(n+1) G27 G25
RB13(n) G18 G16 RB13(n+1) G28 G26
RB14(n) G19 G17 RB14(n+1) G29 G27
RB15(n) B14 B12 RB15(n+1) B24 B22
RB16(n) B15 B13 RB16(n+1) B25 B23
RC10(n) B16 B14 RC10(n+1) B26 B24
RC11(n) B17 B15 RC11(n+1) B27 B25
RC12(n) B18 B16 RC12(n+1) B28 B26
RC13(n) B19 B17 RC13(n+1) B29 B27
RC14(n) HSYNC HSYNC RC14(n+1) HSYNC HSYNC
RC15(n) VSYNC VSYNC RC15(n+1) VSYNC VSYNC
RC16(n) DE DE RC16(n+1) DE DE
RD10(n) R12 R18 RD10(n+1) R22 R28
RD11(n) R13 R19 RD11(n+1) R23 R29
RD12(n) G12 G18 RD12(n+1) G22 G28
RD13(n) G13 G19 RD13(n+1) G23 G29
RD14(n) B12 B18 RD14(n+1) B22 B28
RD15(n) B13 B19 RD15(n+1) B23 B29
RD16(n) CONT11 CONT11 RD16(n+1) CONT21 CONT21
RE10(n) R10 R10 RE10(n+1) R20 R20
RE11(n) R11 R11 RE11(n+1) R21 R21
RE12(n) G10 G10 RE12(n+1) G20 G20
RE13(n) G11 G11 RE13(n+1) G21 G21
RE14(n) B10 B10 RE14(n+1) B20 B20
RE15(n) B11 B11 RE15(n+1) B21 B21
RE16(n) CONT12 CONT12 RE16(n+1) CONT22 CONT22
THC63LVD1024_Rev.3.02_E
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LVDS Input Data Mapping (Continued)
Table7. LVDS Input Data Mapping (Dual-in/Single-out DDR On or Off, MODE<1:0>=LH, MODE2=H or L)
1st Pixel Data 2nd Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name) Mapping Mode2
(Output Pin Name)
LVDS
Input Data
(2nd Pixel Data)
Mapping Mode1
(Output Pin N ame) Mapping Mode2
(Output Pin Name)
RA10 R14(n) R12(n) RA20 R14(n+1) R12(n+1)
RA11 R15(n) R13(n) RA21 R15(n+1) R13(n+1)
RA12 R16(n) R14(n) RA22 R16(n+1) R14(n+1)
RA13 R17(n) R15(n) RA23 R17(n+1) R15(n+1)
RA14 R18(n) R16(n) RA24 R18(n+1) R16(n+1)
RA15 R19(n) R17(n) RA25 R19(n+1) R17(n+1)
RA16 G14(n) G12(n) RA26 G14(n+1) G12(n+1)
RB10 G15(n) G13(n) RB20 G15(n+1) G13(n+1)
RB11 G16(n) G14(n) RB21 G16(n+1) G14(n+1)
RB12 G17(n) G15(n) RB22 G17(n+1) G15(n+1)
RB13 G18(n) G16(n) RB23 G18(n+1) G16(n+1)
RB14 G19(n) G17(n) RB24 G19(n+1) G17(n+1)
RB15 B14(n) B12(n) RB25 B14(n+1) B12(n+1)
RB16 B15(n) B13(n) RB26 B15(n+1) B13(n+1)
RC10 B16(n) B14(n) RC20 B16(n+1) B14(n+1)
RC11 B17(n) B15(n) RC21 B17(n+1) B15(n+1)
RC12 B18(n) B16(n) RC22 B18(n+1) B16(n+1)
RC13 B19(n) B17(n) RC23 B19(n+1) B17(n+1)
RC14 HSYNC(n) HSYNC(n) RC24 HSYNC(n+1) HSYNC(n+1)
RC15 VSYNC(n) VSYNC(n) RC25 VSYNC(n+1) VSYNC(n+1)
RC16 DE(n) DE(n) RC26 DE(n+1) DE(n+1)
RD10 R12(n) R18(n) RD20 R12(n+1) R18(n+1)
RD11 R13(n) R19(n) RD21 R13(n+1) R19(n+1)
RD12 G12(n) G18(n) RD22 G12(n+1) G18(n+1)
RD13 G13(n) G19(n) RD23 G13(n+1) G19(n+1)
RD14 B12(n) B18(n) RD24 B12(n+1) B18(n+1)
RD15 B13(n) B19(n) RD25 B13(n+1) B19(n+1)
RD16 CONT11(n) CONT11(n) RD26 CONT11(n+1) CONT11(n+1)
RE10 R10(n) R10(n) RE20 R10(n+1) R10(n+1)
RE11 R11(n) R11(n) RE21 R11(n+1) R11(n+1)
RE12 G10(n) G10(n) RE22 G10(n+1) G10(n+1)
RE13 G11(n) G11(n) RE23 G11(n+1) G11(n+1)
RE14 B10(n) B10(n) RE24 B10(n+1) B10(n+1)
RE15 B11(n) B11(n) RE25 B11(n+1) B11(n+1)
RE16 CONT12(n) CONT12(n) RE26 CONT12(n+1) CONT12(n+1)
THC63LVD1024_Rev.3.02_E
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LVDS Input Data Mapping (Continued)
Table8. LVDS Input Data Mapping (Dual-in/Dual-out, MODE<1:0>=LL)
1st Pixel Data 2nd Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name) Mapping Mode2
(Output Pin Name)
LVDS
Input Data
(2nd Pixel Data)
Mapping Mode1
(Output Pin Name) Mapping Mode2
(Output Pin Name)
RA10 R14 R12 RA20 R24 R22
RA11 R15 R13 RA21 R25 R23
RA12 R16 R14 RA22 R26 R24
RA13 R17 R15 RA23 R27 R25
RA14 R18 R16 RA24 R28 R26
RA15 R19 R17 RA25 R29 R27
RA16 G14 G12 RA26 G24 G22
RB10 G15 G13 RB20 G25 G23
RB11 G16 G14 RB21 G26 G24
RB12 G17 G15 RB22 G27 G25
RB13 G18 G16 RB23 G28 G26
RB14 G19 G17 RB24 G29 G27
RB15 B14 B12 RB25 B24 B22
RB16 B15 B13 RB26 B25 B23
RC10 B16 B14 RC20 B26 B24
RC11 B17 B15 RC21 B27 B25
RC12 B18 B16 RC22 B28 B26
RC13 B19 B17 RC23 B29 B27
RC14 HSYNC HSYNC RC24 N/ARC15 VSYNC VSYNC RC25
RC16 DE DE RC26
RD10 R12 R18 RD20 R22 R28
RD11 R13 R19 RD21 R23 R29
RD12 G12 G18 RD22 G22 G28
RD13 G13 G19 RD23 G23 G29
RD14 B12 B18 RD24 B22 B28
RD15 B13 B19 RD25 B23 B29
RD16 CONT11 CONT11 RD26 CONT21 CONT21
RE10 R10 R10 RE20 R20 R20
RE11 R11 R11 RE21 R21 R21
RE12 G10 G10 RE22 G20 G20
RE13 G11 G11 RE23 G21 G21
RE14 B10 B10 RE24 B20 B20
RE15 B11 B11 RE25 B21 B21
RE16 CONT12 CONT12 RE26 CONT22 CONT22
THC63LVD1024_Rev.3.02_E
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Note
1)Power On Sequence
Power on LVDS-Tx after THC63LVD1024.
2)Cable Connection and Disconnection
Don't connect and disconnect the LVDS cable, when the power is suppl ied to th e system.
3)GND Connection
Connect the each GND of the PCB which LVDS-Tx and THC63LVD1024 on it. It is better for EMI reduction to place
GND cable as close to LVDS cable as possible.
4)Multi Drop Connection
Multi drop connection is not recommended .
5)Asynchronous use
Asynchronous use such as following system is not recommended.
.
LVDS-Tx THC63LVD1024
THC63LVD1024
TCLK+
TCLK-
THC63LVD1024
THC63LVD1024
CLKOUT
DATA
DATA
IC
TCLK+
TCLK-
TCLK+
TCLK-
LVDS-Tx
LVDS-Tx
IC
CLKOUT
DATA
CLKOUT
DATA !
THC63LVD1024
THC63LVD1024
CLKOUT
DATA
DATA
IC
TCLK+
TCLK-
TCLK+
TCLK- !
IC
THC63LVD1024_Rev.3.02_E
Copyright©2015 THine Electronics, Inc. 21/23 THine Electronics, Inc.
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Package
0.08 M
22.00 BSC.
0.20 +0.07/-0.03
0.50 BSC.
SEATING PLANE
S
S
0.10
0.09～0.20
1.00 REF
1.40～1.60
0.05～0.15
1.40 +/-0.05
0.25ｍｍ
GAGE PLANE
0.60 +/-0.15
0.08～0.20R
0.08 R MIN
0.20 MIN
136
37
72
73
108
109
144
TOP VIEW
7.20
7.20
EXPOSED PAD
BOTTOM VIEW
136
37
72
73
108
109
144
22.00 BSC.
20.00 BSC.
20.00 BSC.
1 PIN INDEX
0°～7°
11°～13°
11°～13°
Unit：mm
THC63LVD1024
Exposed PAD is GND and must be soldered to PCB.
THC63LVD1024_Rev.3.02_E
Copyright©2015 THine Electronics, Inc. 22/23 THine Electronics, Inc.
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not
always apply to the customer's design. We are not responsible for possible errors and omissions
in this material. Please note if errors or omissions should be found in this material, we may not
be able to correct them immediately.
3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to
third parties the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this
product, we will be exempted from the responsibility unless it directly relates to the production
process or functions of the product.
5. This product is presumed to be used for general electric equipment, not for the applications
which require very high reliability (including medical equipment directly concerning people's
life, aerospace equipment, or nuclear control equipment). Also, when using this product for the
equipment concerned with the control and safety of the transportation means, the traffic signal
equipment, or various Types of safety equipment, please do it after applying appropriate
measures to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur
with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you
are encouraged to have sufficiently redundant or error preventive design applied to the use of
the product so as not to have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category
of strategic goods under the Foreign Exchange and Foreign Trade Control Law.
THine Electronics, Inc.
E-mail: sales@thine.co.jp
