Product Folder Sample & Buy Technical Documents Support & Community Tools & Software DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 DAC121S101/-Q1 12-Bit Micro Power, RRO Digital-to-Analog Converter 1 Features 3 Description * The DAC121S101 device is a full-featured, generalpurpose, 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes just 177 A of current at 3.6 V. The on-chip output amplifier allows rail-torail output swing and the three wire serial interface operates at clock rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPITM, QSPI, MICROWIRE and DSP interfaces. Competitive devices are limited to 20-MHz clock rates at supply voltages in the 2.7 V to 3.6 V range. 1 * * * * * * * * * DAC121S101-Q1 is AEC-Q100 Grade 1 Qualified and is Manufactured on an Automotive Grade Flow. Ensured Monotonicity Low Power Operation Rail-to-Rail Voltage Output Power-on Reset to Zero Volts Output Wide Temperature Range of -40C to +125C Wide Power Supply Range of 2.7 V to 5.5 V Small Packages Power Down Feature Key Specifications - 12-Bit Resolution - DNL -0.15, +0.25 LSB (Typical) - 8-s Output Settling Time (Typical) - 4-mV Zero Code Error (Typical) - Full-Scale Error at -0.06 %FS (Typical) - 0.64-mW (3.6-V) / 1.43-mW (5.5-V) Normal Mode Power Consumption (Typical) - 0.14-W (3.6-V) / 0.39-W (5.5-V) PowerDown Mode (Typical) The supply voltage for the DAC121S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt. The low power consumption and small packages of the DAC121S101 make it an excellent choice for use in battery operated equipment. Device Information(1) PART NUMBER 2 Applications DAC121S101 * * * * * DAC121S101-Q1 Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Automotive BODY SIZE (NOM) 2.90 mm x 1.60 mm VSSOP (8) 3.00 mm x 3.00 mm SOT (6) 2.90 mm x 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Block Diagram VA PACKAGE SOT (6) DNL vs. Output Code GND POWER-ON RESET DAC121S101 REF(+) REF(-) DAC REGISTER 12 12-BIT DAC BUFFER VOUT 12 POWER-DOWN CONTROL LOGIC INPUT CONTROL LOGIC SYNC SCLK 1k 100k DIN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description continued ........................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics.......................................... 5 AC and Timing Characteristics ................................ 7 Typical Characteristics ............................................ 10 Detailed Description ............................................ 16 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 16 16 16 17 8.5 Programming........................................................... 18 9 Application and Implementation ........................ 19 9.1 Application Information............................................ 19 9.2 Typical Application ................................................. 21 10 Power Supply Recommendations ..................... 23 10.1 Using References as Power Supplies................... 23 11 Layout................................................................... 25 11.1 Layout Guidelines ................................................. 25 11.2 Layout Example .................................................... 26 12 Device and Documentation Support ................. 26 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support .................................................... Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 27 27 27 27 27 27 13 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision I (March 2013) to Revision J * Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision H (February 2010) to Revision I * 2 Page Changed layout of National Data Sheet to TI format ........................................................................................................... 25 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 5 Description continued The DAC121S101 is a direct replacement for the AD5320 and the DAC7512 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 10-bit DAC101S101. The DAC121S101 operates over the extended industrial temperature range of -40C to +105C while the DAC121S101-Q1 operates over the Grade 1 automotive temperature range of -40C to +125C. The DAC121S101 is available in a 6-lead SOT and an 8-lead VSSOP and the DAC121S101-Q1 is available in the 6-lead SOT only. 6 Pin Configuration and Functions DDC Package 6-Pin SOT Top View DAC121S101 (Only) DGK Package 8-Pin VSSOP Top View VOUT 1 6 SYNC GND 2 5 SCLK VA 3 4 DIN VA 1 NC NC 2 3 VOUT 4 SOT VSSOP 8 GND 7 6 DIN SCLK 5 SYNC Pin Functions PIN SOT NO. VSSOP NO. I/O DIN 4 7 Input GND 2 8 -- Ground reference for all on-chip circuitry. NC -- -- No Connect. There is no internal connection to these pins. SCLK 5 6 Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. SYNC 6 5 Input Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. VA 3 1 -- VOUT 1 4 Output NAME 2 3 DESCRIPTION Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. Power supply and Reference input. Should be decoupled to GND. DAC Analog Output Voltage. Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 3 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN Supply Voltage, VA -0.3 Voltage on any Input Pin Input Current at Any Pin Package Input Current See -65 Storage Temperature, Tstg (1) (2) (3) (4) (5) V V 10 mA 20 mA 235 C 150 C (3) Soldering Temperature, Infrared, 10 Seconds (5) UNIT 6.5 (VA + 0.3) (3) Power Consumption at TA = 25C MAX (4) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are measured with respect to GND = 0 V, unless otherwise specified When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin must be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The absolute maximum junction temperature (TJMAX) for this device is 150C. The maximum allowable power dissipation is dictated by TJMAX, the junction-to-ambient thermal resistance (JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJMAX - TA) / JA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions must always be avoided. See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices. 7.2 ESD Ratings VALUE V(ESD) (1) 4 Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2500 Machine Model 250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) Operating Temperature Range (2) MIN NOM MAX UNIT DAC121S101 -40 TA 105 C DAC121S101-Q1 -40 TA 125 C Supply Voltage, VA 2.7 5.5 V Any Input Voltage (3) -0.1 (VA + 0.1) V 0 1500 Output Load SCLK Frequency (1) (2) (3) pF 30 MHz Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. All voltages are measured with respect to GND = 0 V, unless otherwise specified The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7VDC, ensure that -100mV input voltages 2.8VDC to ensure accurate conversions. I/O TO INTERNAL CIRCUITRY GND 7.4 Thermal Information DAC121S101, DAC121S101-Q1 THERMAL METRIC (1) RJA (1) DGK (VSSOP) DDC (SOT) 8 PINS 6 PINS 240 250 Junction-to-ambient thermal resistance UNIT C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN (1) TYP (1) MAX (1) UNIT STATIC PERFORMANCE INL Resolution TMIN TA TMAX 12 Monotonicity TMIN TA TMAX 12 Integral Non-Linearity Over Decimal codes 48 to 4047 DNL VA = 4.5 V to 5.5 V ZE Zero Code Error (2) +0.25 LSB -0.7 +1 LSB TA = 25C 0.11 LSB TMIN TA TMAX 0.5 +4 mV +15 -0.06 TA = 25C IOUT = 0 GE Gain Error All ones Loaded to DAC register (2) -0.15 TMIN TA TMAX Full-Scale Error (1) LSB 8 TA = 25C IOUT = 0 FSE ZCED 2.6 TMIN TA TMAX TMIN TA TMAX Differential Non-Linearity Bits TA = 25C TA = 25C VA = 2.7 V to 5.5 V Bits TMIN TA TMAX TA = 25C TMIN TA TMAX -1 -0.1 %FSR 1 -20 Zero Code Error Drift %FSR V/C Typical figures are at TJ = 25C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). This parameter is specified by design and/or characterization and is not tested in production. Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 5 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25C, unless otherwise specified. PARAMETER TC GE TEST CONDITIONS Gain Error Tempco MIN (1) TYP (1) MAX (1) UNIT VA = 3 V -0.7 ppm/C VA = 5 V -1 ppm/C OUTPUT CHARACTERISTICS Output Voltage Range (2) TMIN TA TMAX 0 VA = 3 V, IOUT = 10 A ZCO FSO VA = 3 V, IOUT = 100 A Zero Code Output Full Scale Output Maximum Load Capacitance V mV 5 mV VA = 5 V, IOUT = 10 A 3.7 mV VA = 5 V, IOUT = 100 A 5.4 mV VA = 3 V, IOUT = 10 A 2.997 V VA = 3 V, IOUT = 100 A 2.99 V VA = 5 V, IOUT = 10 A 4.995 V VA = 5 V, IOUT = 100 A 4.992 V RL = 1500 pF RL = 2 k 1500 DC Output Impedance IOS VA 1.8 pF 1.3 Ohm VA = 5 V, VOUT = 0 V, Input code = FFFh -63 mA VA = 3 V, VOUT = 0 V, Input code = FFFh -50 mA VA = 5 V, VOUT = 5 V, Input code = 000h 74 mA VA = 3 V, VOUT = 3 V, Input code = 000h 53 mA TMIN TA TMAX 1 A VA = 5 V TMIN TA TMAX 0.8 V VA = 3 V TMIN TA TMAX 0.5 V Output Short Circuit Current LOGIC INPUT IIN VIL Input Current (2) Input Low Voltage VIH Input High Voltage CIN Input Capacitance (2) (2) (2) VA = 5 V TMIN TA TMAX 2.4 VA = 3 V TMIN TA TMAX 2.1 TMIN TA TMAX V V 3 pF POWER REQUIREMENTS VA = 5.5 V Normal Mode fSCLK = 30 MHz VA = 3.6 V VA = 5.5 V Normal Mode fSCLK = 20 MHz VA = 3.6 V IA Supply Current (output unloaded) 260 TMIN TA TMAX 312 TA = 25C 177 TMIN TA TMAX 217 TA = 25C 224 TMIN TA TMAX 279 TA = 25C 158 TMIN TA TMAX 197 A A A A Normal Mode fSCLK = 0 VA = 5.5 V 153 A VA = 3.6 V 118 A All PD Modes, fSCLK = 30 MHz VA = 5 V 84 A VA = 3 V 42 A All PD Modes, fSCLK = 20 MHz VA = 5 V 56 A VA = 3 V 28 A VA = 5.5 V All PD Modes, fSCLK = 0 (2) VA = 3.6 V 6 TA = 25C Submit Documentation Feedback TA = 25C 0.07 A TMIN TA TMAX 1 TA = 25C 0.04 A TMIN TA TMAX 1 Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 Electrical Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25C, unless otherwise specified. PARAMETER TEST CONDITIONS VA = 5.5 V Normal Mode fSCLK = 30 MHz VA = 3.6 V VA = 5.5 V Normal Mode fSCLK = 20 MHz VA = 3.6 V Power Consumption (output unloaded) PC UNIT 1.43 TMIN TA TMAX 1.72 TA = 25C 0.64 TMIN TA TMAX 0.78 TA = 25C 1.23 TMIN TA TMAX 1.53 TA = 25C 0.57 TMIN TA TMAX 0.71 mW mW mW mW 0.84 W VA = 3.6 V 0.42 W All PD Modes, fSCLK = 30 MHz VA = 5 V 0.42 W VA = 3 V 0.13 W All PD Modes, fSCLK = 20 MHz VA = 5 V 0.28 W VA = 3 V 0.08 W VA = 3.6 V 7.6 MAX (1) VA = 5.5 V VA = 5.5 V Power Efficiency TYP (1) Normal Mode fSCLK = 0 All PD Modes, fSCLK = 0 (2) IOUT / IA MIN (1) TA = 25C ILOAD = 2 mA TA = 25C 0.39 W TMIN TA TMAX 5.5 TA = 25C 0.14 W TMIN TA TMAX 3.6 VA = 5 V 91% VA = 3 V 94% AC and Timing Characteristics The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25C, unless otherwise specified. PARAMETER fSCLK SCLK Frequency Output Voltage Settling Time (1) ts TEST CONDITIONS 400h to C00h code change, RL = 2 k 00Fh to FF0h code change, RL = 2 k SR MIN CL 200 pF Wake-Up Time 1/fSC SCLK Cycle Time LK tH SCLK High time tL SCLK Low Time tSUCL Set-up Time SYNC to SCLK Rising Edge tSUD Data Set-up Time (1) UNIT 30 MHz 8 TMIN TA TMAX 10 s CL = 500 pF 12 s CL 200 pF 8 s CL = 500 pF 12 s 1 V/s 12 nV-s 0.5 nV-s Code change from 800h to 7FFh Digital Feedthrough tWU MAX TA = 25C Output Slew Rate Glitch Impulse TYP TMIN TA TMAX VA = 5 V 6 s VA = 3 V 39 s TMIN TA TMAX TA = 25C TMIN TA TMAX TA = 25C TMIN TA TMAX TA = 25C TMIN TA TMAX TA = 25C TMIN TA TMAX 33 ns 5 ns 13 5 ns 13 -15 ns 0 2.5 ns 5 This parameter is specified by design and/or characterization and is not tested in production. Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 7 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com AC and Timing Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 48 to 4047. All limits are for TA = 25C, unless otherwise specified. PARAMETER tDHD Data Hold Time TEST CONDITIONS 2.5 TMIN TA TMAX 4.5 VA = 5 V tCS MIN TA = 25C SCLK fall to rise of SYNC VA = 3 V 2.7 VA 3.6 tSYNC SYNC High Time 3.6 VA 5.5 TA = 25C 0 TMIN TA TMAX 3 TA = 25C -2 TMIN TA TMAX 1 TA = 25C 9 TMIN TA TMAX 20 TA = 25C 5 TMIN TA TMAX 10 TYP MAX UNIT ns ns ns ns ns FSE 4095 x VA 4096 GE = FSE - ZE FSE = GE + ZE OUTPUT VOLTAGE ZE 0 0 4095 DIGITAL INPUT CODE Figure 1. Input / Output Transfer Characteristic 8 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 SCLK 1 13 14 15 16 tL tSUCL tH tCS | tSYNC 2 | | 1 / fSCLK | SYNC DB15 DB0 | DIN | | tDHD tSUD Figure 2. DAC121S101 Timing Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 9 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com 7.7 Typical Characteristics fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 10 Figure 3. DNL at VA = 3 V Figure 4. DNL at VA = 5 V Figure 5. INL at VA = 3 V Figure 6. INL at VA = 5 V Figure 7. TUE at VA = 3 V Figure 8. TUE at VA = 5 V Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 Typical Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated Figure 9. DNL vs. VA Figure 10. INL vs. VA Figure 11. 3-V DNL vs. fSCLK Figure 12. 5-V DNL vs. fSCLK Figure 13. 3-V DNL vs. Clock Duty Cycle Figure 14. 5-V DNL vs. Clock Duty Cycle Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 11 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 12 Figure 15. 3-V DNL vs. Temperature Figure 16. 3-V INL vs. fSCLK Figure 17. 5-V INL vs. fSCLK Figure 18. 3-V INL vs. Clock Duty Cycle Figure 19. 5-V INL vs. Clock Duty Cycle Figure 20. 3-V INL vs. Temperature Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 Typical Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated Figure 21. 5-V INL vs. Temperature Figure 22. Zero Code Error vs. fSCLK Figure 23. Zero Code Error vs. Clock Duty Cycle Figure 24. Zero Code Error vs. Temperature Figure 25. Full-Scale Error vs. fSCLK Figure 26. Full-Scale Error vs. Clock Duty Cycle Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 13 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated 14 Figure 27. Full-Scale Error vs. Temperature Figure 28. Supply Current vs. VA Figure 29. Supply Current vs. Temperature Figure 30. 5-V Glitch Response Figure 31. Power-On Reset Figure 32. 3-V Wake-Up Time Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 Typical Characteristics (continued) fSCLK = 30 MHz, TA = 25C, Input Code Range 48 to 4047, unless otherwise stated Figure 33. 5-V Wake-Up Time Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 15 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com 8 Detailed Description 8.1 Overview The DAC121S101 device is a full-featured, general purpose 12-bit voltage-output digital-to-analog converter (DAC) with 10-s settling time. Control of the output of the DAC is achieved over a 3-wire SPI interface. Once the DAC output has been set, additional communication with the DAC is not required unless the output condition needs to be changed. Likewise, the DAC121S101 power on state is 0 V. The DAC output will remain at 0 V until a valid write sequence is made. A unique benefit of the DAC121S101 is the logic levels of the SPITM input pins. The logic levels of SCLK, DIN, and SYNCB are independent of VA. As a result, the DAC121S101 can operate at a supply voltage (VA) that is higher than the microcontroller that is controlling the DAC. This feature is advantageous in applications where the analog circuitry is being run at 5 V in order to maximize signal-to-noise ratio and digital logic is running at 3 V in order to conserve power. 8.2 Functional Block Diagram VA GND POWER-ON RESET DAC121S101 REF(+) REF(-) DAC REGISTER 12 12-BIT DAC BUFFER VOUT 12 POWER-DOWN CONTROL LOGIC INPUT CONTROL LOGIC SYNC SCLK 1k 100k DIN 8.3 Feature Description 8.3.1 DAC Section The DAC121S101 is fabricated on a CMOS process with an architecture that consists of switches and a resistor string that are followed by an output buffer. The power supply serves as the reference voltage. The input coding is straight binary with an ideal output voltage of: VOUT = VA x (D / 4096) where * D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0 and 4095. (1) 8.3.2 Resistor String The resistor string is shown in Figure 34. This string consists of 4096 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. This configuration ensures that the DAC is monotonic. 16 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 Feature Description (continued) VA R R R To Output Amplifier R R Figure 34. DAC Resistor String 8.3.3 Output Amplifier The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0 V to VA. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA, in this case). For this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the amplifier are described in the Electrical Characteristics. 8.4 Device Functional Modes 8.4.1 Power-On Reset The power-on reset circuit controls the output voltage during power-up. Upon application of power the DAC register is filled with zeros and the output voltage is 0 V and remains there until a valid write sequence is made to the DAC. 8.4.2 Power-Down Modes The DAC121S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the control register. Table 1. Modes of Operation DB13 DB12 0 0 OPERATING MODE Normal Operation 0 1 Power-Down with 1k to GND 1 0 Power-Down with 100k to GND 1 1 Power-Down with Hi-Z Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 17 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of these bits the supply current drops to its power-down level and the output is pulled down with either a 1-k or a 100-K resistor, or is in a high-impedance state, as described in Table 1. The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC register are unaffected when in power-down, so when coming out of power down the output voltage returns to the same voltage it was before entering power down. Minimum power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. The time to exit power-down (Wake-Up Time) is typically tWU sec as stated in the A.C. and Timing Characteristics Table. 8.5 Programming 8.5.1 Serial Interface The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs. See the Timing Diagram for information on a write sequence. A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be brought high for the minimum specified time before the next write sequence as a falling edge of SYNC can initiate the next write cycle. Since the SYNC and DIN buffers draw more current when they are high, they must be idled low between write sequences to minimize power consumption. 8.5.2 Input Shift Register The input shift register, , has sixteen bits. The first two bits are don't cares and are followed by two bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Figure 2. DB15 (MSB) X X DB0 (LSB) PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS 0 0 1 1 0 Normal Operation 1 1 k:to GND 0 100 k: to GND 1 High Impedance Power-Down Modes Input Register Contents Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation or in the output voltage. 18 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 DSP and Microprocessor Interfacing The simplicity of the DAC121S101 implies ease of use. However, it is important to recognize that any data converter that uses its supply voltage as its reference voltage will have essentially zero PSRR (power supply rejection ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device. Interfacing the DAC121S101 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process. 9.1.1.1 ADSP-2101/ADSP2103 Interfacing Figure 35 shows a serial interface between the DAC121S101 and the ADSP-2101/ADSP2103. The DSP must be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled. ADSP-2101/ ADSP2103 TFS DT SCLK DAC121S101 SYNC DIN SCLK Figure 35. ADSP-2101/2103 Interface 9.1.1.1.1 80C51/80L51 Interface A serial interface between the DAC121S101 and the 80C51/80L51 microcontroller is shown in Figure 36. The SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line P3.3. This line is taken low when data is to transmitted to the DAC121S101. Because the 80C51/80L51 transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the 80C51/80L51 transmits data with the LSB first while the DAC121S101 requires data with the MSB first. 80C51/80L51 P3.3 DAC121S101 SYNC TXD SCLK RXD DIN Figure 36. 80C51/80L51 Interface 9.1.1.1.2 68HC11 Interface A serial interface between the DAC121S101 and the 68HC11 microcontroller is shown in Figure 37. The SYNC line of the DAC121S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51. Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 19 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com Application Information (continued) The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 must be raised to end the write sequence. 68HC11 DAC121S101 PC7 SYNC SCK SCLK MOSI DIN Figure 37. 68HC11 Interface 9.1.1.1.3 Microwire Interface Figure 38 shows an interface between a Microwire compatible device and the DAC121S101. Data is clocked out on the rising edges of the SCLK signal. MICROWIRE DEVICE DAC121S101 CS SYNC SK SCLK SO DIN Figure 38. Microwire Interface 9.1.2 Bipolar Operation The DAC121S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in Figure 39. This circuit will provide an output voltage range of 5 V. A rail-to-rail amplifier must be used if the amplifier supplies are limited to 5 V. 10 pF R2 +5V +5V 10 PF + R1 - 0.1 PF 5V + DAC121S101 -5V SYNC VOUT DIN SCLK Figure 39. Bipolar Operation The output voltage of this circuit for any code is found to be VO = (VA x (D / 4096) x ((R1 + R2) / R1) - VA x R2 / R where * D is the input code in decimal form. (2) With VA = 5 V and R1 = R2, VO = (10 x D / 4096) - 5 V (3) A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2. 20 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 Application Information (continued) Table 2. Some Rail-to-Rail Amplifiers AMP PKGS LMC7111 PDIP SOT-23 Typ VOS Typ ISUPPLY 0.9 mV 25 A LM7301 SOIC SOT-23 0.03 mV 620 A LM8261 SOT-23 0.7 mV 1 mA 9.2 Typical Application 3 VA 1 VOUT +5 120pF +5 3 + /SYNC 5 SCLK 4 DIN 8 SCLK 7 DOUT 6 /CS 2 1uF 5 1 A2 4 LM4132-3.3 4 5 3 2 .1uF DAC121S101 6 - .2uF 2 180 +5 +3.3 10 VA 9 VIO 100K 2 470pF +IN 1 VREF ADC161S626 AV = 100 2.02K 3 -IN 4, 5 +5 .2uF 100K 3 - 5 1 A1 Pressure Sensor 0.2mV/Volt/PSI 4 + 180 470pF 2 A1 and A2 = LMP7701 Figure 40. Pressure Sensor Gain Adjust 9.2.1 Design Requirements A positive supply only data acquisition system capable of digitizing a pressure sensor output. In addition to digitizing the pressure sensor output, the system designer can use the DAC121S101 to correct for gain errors in the pressure sensor output by adjusting the bias voltage to the bridge pressure sensor. Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 21 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com Typical Application (continued) 9.2.2 Detailed Design Procedure As shown in Equation 4, the output of the pressure sensor is relative to the imbalance of the resistive bridge times the output of the DAC121S101, thus providing the desired gain correction. Pressure Sensor Output = (DAC_Output x [(R2 / (R1 + R2) - (R4 / (R3 + R4)] (4) Likewise for the ADC161S626, Equation 5 shows that the ADC output is function of the Pressure Sensor Output times relative to the ratio of the ADC input divided by the DAC121S101 output voltage. ADC161S626 Output = (Pressure Sensor Output x 100 /(2 x VREF) ) x 216 (5) 9.2.3 Application Curve Figure 41. Total Unadjusted Error vs. Output Code 22 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 10 Power Supply Recommendations NOTE Information in the following power supply recommendations section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Using References as Power Supplies Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage. Because the DAC121S101 consumes very little power, a reference source may be used as the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise regulators can also be used for the power supply of the DAC121S101. Listed below are a few power supply options for the DAC121S101. 10.1.1 LM4130 The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the DAC121S101. Its primary disadvantage is the lack of 3-V and 5-V versions. However, the 4.096-V version is useful if a 0 to 4.095-V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with a 0.1-F capacitor and the VOUT pin with a 2.2-F capacitor will improve stability and reduce output noise. The LM4130 comes in a space-saving 5-pin SOT23. Input Voltage LM4130-4.1 C2 2.2 PF C1 0.1 PF DAC121S101 SYNC VOUT = 0V to 4.095V DIN SCLK Figure 42. The LM4130 as a Power Supply 10.1.2 LM4050 Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the DAC121S101. It does not come in a 3-V version, but 4.096-V and 5-V versions are available. It comes in a space-saving 3-pin SOT23. Input Voltage R VZ LM4050-4.1 or LM4050-5.0 0.47 PF DAC121S101 SYNC VOUT = 0V to 5V DIN SCLK Figure 43. The LM4050 as a Power Supply Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 23 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com Using References as Power Supplies (continued) The minimum resistor value in the circuit of Figure 43 must be chosen such that the maximum current through the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the DAC121S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum DAC121S101 current in full operation. The conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the DAC121S101 draws its maximum current. These conditions can be summarized as R(min) = ( VIN(max) - VZ(min) / (IA(min) + IZ(max)) (6) and R(max) = ( VIN(min) - VZ(max) / (IA(max) + IZ(min) ) where * * * * * VZ(min) and VZ(max) are the nominal LM4050 output voltages the LM4050 output tolerance over temperature, IZ(max) is the maximum allowable current through the LM4050, IZ(min) is the minimum current required by the LM4050 for proper regulation, IA(max) is the maximum DAC121S101 supply current, and IA(min) is the minimum DAC121S101 supply current. (7) 10.1.3 LP3985 The LP3985 is a low noise, ultra-low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC121S101. It comes in 3-V, 3.3-V and 5-V versions, among others, and sports a low 30-V noise specification at low frequencies. Because lowfrequency noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages. Input Voltage LP3985 1 PF 0.1 PF 0.01 PF DAC121S101 SYNC VOUT = 0V to 5V DIN SCLK Figure 44. Using the LP3985 Regulator An input capacitance of 1 F without any ESR requirement is required at the LP3985 input, while a 1-F ceramic capacitor with an ESR requirement of 5 m to 500 m is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation. 24 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 Using References as Power Supplies (continued) 10.1.4 LP2980 The LP2980 is an ultra-low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3-V, 3.3-V and 5-V versions, among others. Input Voltage VIN ON / OFF LP2980 VOUT 1 PF DAC121S101 SYNC VOUT = 0V to 5V DIN SCLK Figure 45. Using the LP2980 Regulator Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1-F over temperature, but values of 2.2 F or more will provide even better performance. The ESR of this capacitor must be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures. 11 Layout 11.1 Layout Guidelines A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The power applied to VA must be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VA must be connected to a power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. The DAC121S101 power supply must be bypassed with a 10-F and a 0.1-F capacitor as close as possible to the device with the 0.1 F right at the device supply pin. The 10-F capacitor must be a tantalum type and the 0.1-F capacitor must be a low ESL, low ESR type. The power supply for the DAC121S101 must only be used for analog circuits. For best accuracy and minimum noise, the printed-circuit-board containing the DAC121S101 must have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of these planes must be located in the same board layer. There must be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design will use a fencing technique to prevent the mixing of analog and digital ground current. Separate ground planes must only be used when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC121S101. Take special care to ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces. Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines must have controlled impedances. Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 25 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com 11.2 Layout Example VOUT SYNCB SOT GND C1 SCLK DIN VA Figure 46. Typical Layout 12 Device and Documentation Support 12.1 Device Support 12.1.1 Device Nomenclature 12.1.1.1 Specification Definitions DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 4096 = VA / 4096. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of VA x 4095 / 4096. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Characteristics. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF / 2n (8) where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 12 for the DAC121S101. MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. 26 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 DAC121S101, DAC121S101-Q1 www.ti.com SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. WAKE-UP TIME is the time for the output to settle to within 1/2 LSB of the final value after the device is commanded to the active mode from any of the power down modes. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: * LM4130 Precision Micropower Low Dropout Voltage Reference, SNVS048 * LM4050 Precision Micropower Shunt Voltage Reference, SNOS455 * LP3985 Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS Voltage Regulator, SNVS087 * LP2980 Micropower 50-mA Ultralow-Dropout Voltage Regulator, SLVS715 * LMC7111 Tiny CMOS Operational Amplifier with Rail-to-Rail Input and Output, SNOS753 * LM7301 Low Power, 4 MHz GBW, Rail-to-Rail Input-Output Operational Amplifier in TinyP, SNOS879 * LM8261 Single RRIO, High Output Current & Unlimited Cap Load Op Amp in SOT23-5, SNOS469 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc.. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 Submit Documentation Feedback 27 DAC121S101, DAC121S101-Q1 SNAS265J - JUNE 2005 - REVISED SEPTEMBER 2015 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright (c) 2005-2015, Texas Instruments Incorporated Product Folder Links: DAC121S101 DAC121S101-Q1 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) DAC121S101CIMK NRND SOT-23-THIN DDC 6 1000 Non-RoHS & Green Call TI Call TI -40 to 105 X61C DAC121S101CIMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X61C DAC121S101CIMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X61C DAC121S101CIMM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X60C DAC121S101QCMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 X61Q DAC121S101QCMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 X61Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2021 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DAC121S101, DAC121S101-Q1 : * Automotive: DAC121S101-Q1 * Military: DAC121S101 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) DAC121S101CIMK SOT23-THIN DDC 6 1000 178.0 8.4 DAC121S101CIMK/NOPB SOT23-THIN DDC 6 1000 178.0 DAC121S101CIMKX/NOP SOTB 23-THIN DDC 6 3000 W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DAC121S101CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 DAC121S101QCMK/NOP SOTB 23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DAC121S101QCMKX/NO SOTPB 23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC121S101CIMK SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 DAC121S101CIMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 DAC121S101CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 DAC121S101QCMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 DAC121S101CIMKX/NOP B DAC121S101QCMKX/NOP B Pack Materials-Page 2 PACKAGE OUTLINE DDC0006A SOT - 1.1 max height SCALE 4.000 SOT 3.05 2.55 1.75 1.45 PIN 1 INDEX AREA 1.100 0.847 B 1 0.1 C A 6 4X 0.95 3.05 2.75 1.9 4 3 0.5 0.3 0.2 0.1 TYP 0.0 6X C 0 -8 TYP 0.20 TYP 0.12 C A B SEATING PLANE 0.6 TYP 0.3 0.25 GAGE PLANE 4214841/B 11/2020 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. www.ti.com EXAMPLE BOARD LAYOUT DDC0006A SOT - 1.1 max height SOT SYMM 6X (1.1) 1 6 6X (0.6) SYMM 4X (0.95) 4 3 (R0.05) TYP (2.7) LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED SOLDER MASK DEFINED SOLDERMASK DETAILS 4214841/B 11/2020 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DDC0006A SOT - 1.1 max height SOT SYMM 6X (1.1) 1 6 6X (0.6) SYMM 4X(0.95) 4 3 (R0.05) TYP (2.7) SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X 4214841/B 11/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. 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