TN2510
Features
Low threshold (2.0V max.)
High input impedance
Low input capacitance (125pF max.)
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Applications
Logic level interfaces - ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
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General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input
impedance and positive temperature coeffi cient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
N-Channel Enhancement-Mode
Vertical DMOS FET
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±20V
Operating and storage temperature -55OC to +150OC
Soldering temperature* 300OC
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
Ordering Information
Device
Package Options BVDSS/BVDGS
(V)
RDS(ON)
(max)
(Ω)
ID(ON)
(min)
(A)
VGS(th)
(max)
(V)
TO-243AA (SOT-89) Die*
TN2510 TN2510N8-G TN2510ND 100 1.5 3.0 2.0
-G indicates package is RoHS compliant (‘Green’).
* MIL visual screening available.
Pin Confi guration
TO-243AA (SOT-89) (N8)
Product Marking
TO-243AA (SOT-89) (N8)
TN5AW W = Code for week sealed
= “Green” Packaging
GATE
SOURCE
DRAIN
DRAIN
2
TN2510
Electrical Characteristics (TA = 25OC unless otherwise specifi ed)
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage 100 - - V VGS = 0V, ID = 2.0mA
VGS(th) Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID= 1.0mA
ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OCV
GS = VDS, ID= 1.0mA
IGSS Gate body leakage - - 100 nA VGS = ± 20V, VDS = 0V
IDSS Zero gate voltage drain current
- - 10 µA VGS = 0V, VDS = Max Rating
- - 1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
ID(ON) On-state drain current 1.2 2.0 - AVGS = 5.0V, VDS = 25V
3.0 6.0 - VGS = 10V, VDS = 25V
RDS(ON) Static drain-to-source on-state resistance
--15
Ω
VGS = 3.0V, ID = 250mA
- 1.5 2.0 VGS = 4.5V, ID = 750mA
- 1.0 1.5 VGS = 10V, ID = 750mA
ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/OCV
GS = 10V, ID = 750mA
GFS Forward transductance 400 800 - mmho V
DS = 25V, ID = 1.0A
CISS Input capacitance - 70 125
pF
VGS = 0V,
VDS = 25V,
f = 1.0MHz
COSS Common source output capacitance - 30 70
CRSS Reverse transfer capacitance - 15 25
td(ON) Turn-on delay time - - 10
ns
VDD = 25V,
ID = 1.5A,
RGEN = 25Ω
trRise time - - 10
td(OFF) Turn-off delay time - - 20
tfFall time - - 10
VSD Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 1.5A
trr Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.5A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Notes:
† ID (continuous) is limited by max rated Tj .
‡ Mounted on FR5 Board, 25mm x 25mm x 1.57mm.
Thermal Characteristics
Package
ID
(continuous)†
(mA)
ID
(pulsed)
(A)
Power Dissipation
@TA = 25OC
(W)
θjc
(OC/W)
θja
(OC/W)
IDR
†
(mA)
IDRM
(A)
TO-243AA (SOT-89) 730 5.0 1.6‡15 78‡730 5.0
Switching Waveforms and Test Circuit
90%
10%
90% 90%
10%
10%
PULSE
GENERATOR
V
DD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
F
t
r
INPUT
INPUT
OUTPUT
10V
V
DD
R
GEN
0V
0V
3
TN2510
Typical Performance Curves
°
°
°
°
°
°
4
TN2510
Typical Performance Curves (cont.)
Gate Drive Dynamic Characteristics
Q (nanocoulombs)
G
VSG )stlov(
Tj
)ht(SG
V)dezilamron(
)N
O
(
SD
R)dezilamron(
VDS(th) and R Variation with Temperature
C)°(
On-Resistance vs. Drain Current
(amperes)
D
)smho(
)NO(SD
R
Variation with Temperature
DSS
SSD )dezilamron(VB
C)°(Tj
Transfer Characteristics
VGS (volts)
I)serepma(
D
Capacitance vs. Drain-to-Source Voltage
100
)s
d
ar
a
focip( C
VDS (volts)
I
BV
010203040
75
50
0
0246810
10
8
6
4
2
0
-50 0 50 100 150
1.1
1.0
10
8
6
4
2
0
1.2
1.1
1.0
0.9
0.8
10
8
6
4
2
0 0.5 1.0 1.5 2.0 2.5
-50 0 50 100 150
70pF
V
DS
= 40V
V
DS
= 10V
V
GS
= 5V
V
GS
= 10V
T
= -55°C
A
V
GS
= 25V
125°C
0246 108
f = 1MHz
C
ISS
C
OSS
C
RSS
0.9
190 pF
2.0
1.6
1.2
0.8
0.4
(th)
V @ 1mA
R
DS(ON)
@ 5V, 0.75A
25°C
25
0
5
TN2510
(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-TN2510
A020508
3-Lead TO-243AA (SOT-89) Package Outline (N8)
Symbol A b b1 C D D1 E E1 e e1 H L
Dimensions
(mm)
MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.13
1.50
BSC
3.00
BSC
3.94 0.89
NOM-------- --
MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 4.25 1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
Drawings not to scale.
