© 2007 Microchip Technology Inc. DS21314G-page 1
MCP601/1R/2/3/4
Features
• Single-Supply: 2.7V to 6.0V
• Rail-to-Rail Output
• Input Range Includes Ground
• Gain Bandwidth Product: 2.8 MHz (typical)
• Unity-Gain Stable
• Low Quiescent Current: 230 µA/amplifier (typical)
• Chip Select (CS): MCP603 only
• Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Available in Single, Dual, and Quad
Typical Applications
• Portable Equipment
• A/D Converter Driver
• Photo Diode Pre-amp
• Analog Filte r s
• Data Acquisition
• Notebooks and PDAs
• Sensor Interface
Available Tools
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Simulation Tool
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Description
The Microchip Technology Inc. MCP601/1R/2/3/4
family of low-power operational amplifiers (op amps)
are offered in single (MCP601), single with Chip Select
(CS) (MCP603), dual (MCP602), an d quad (MCP604)
configurations. These op amps utilize an advanced
CMOS technology that provides low bias current, high-
speed operation, high open-loop gain, and rail-to-rail
output swing. This product offering operates with a
single supply voltage that can be as low as 2.7V, while
drawing 230 µA (typical) of quiescent current per
amplifier. In addition, the common mode input voltage
range goes 0.3V below ground, making these
amplifiers ideal for single-supply operation.
These devices are appropriate for low power, battery
operated circuits due to the low quiescent current, for
A/D convert driver amplifiers because of their wide
bandwidth or for anti-aliasing filters by virtue of their low
input bias current.
The MCP601, MCP602, an d MCP603 are available in
standard 8-lead PDIP, SOIC, and TSSOP packages.
The MCP601 and MCP601R are also available in a
standard 5-lead SOT -23 package, while the MCP603 is
available in a standard 6-lead SOT-23 package. The
MCP604 is offered in standard 14-lead PDIP, SOIC,
and TSSOP packages.
The MCP601/1R/2/3/4 family is available in the
Industrial and Extended temperature ranges and has a
power supply range of 2.7V to 6.0V.
Package Types
VIN+
VIN–
VSS
VOUT
VDD
1
2
3
4
8
7
6
5
NC
NC
NC
VINA+
VINA–
VDD
VINC+
VSS
VOUTC
VINC–
VOUTA
VINB+
VIND–
VOUTD
VOUTB
VINB–
VIND+
VINA+
VINA–
VSS
VINB–
VOUTB
1
2
3
4
8
7
6
5
VDD
VINB+
VOUTA
MCP601
PDIP, SOIC, TSSOP
MCP604
PDIP, SOIC, TSSOP
MCP602
PDIP, SOIC, TSSOP
VIN+
VSS VIN–
1
2
3
5
4
VDD
VOUT
MCP601
SOT23-5
VIN+
VSS VIN–
1
2
3
6
4
VDD
VOUT
MCP603
SOT23-6
CS
5
VIN+
VIN–
VSS
VOUT
VDD
1
2
3
4
8
7
6
5
CS
NC
NC
MCP603
PDIP, SOIC, TSSOP
14
13
12
1
2
3
4
5
6
7
11
10
9
8
VIN+
VDD VIN–
1
2
3
5
4
VSS
VOUT
MCP601R
SOT23-5
2.7V to 6.0V Single Supply CMOS Op Amps
MCP601/1R/2/3/4
DS21314G-page 2 © 2007 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Input Pins.....................................................±2 mA
Analog Inputs (VIN+, VIN–) †† ........ VSS –1.0VtoV
DD +1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD Protection On All Pins (HBM; MM).............. ≥ 3 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -2 ±0.7 +2 mV
Industrial Temperature VOS -3 ±1 +3 mV TA = -40°C to +85°C (Note 1)
Extended Temperature VOS -4.5 ±1 +4.5 mV TA = -40°C to +125°C (Note 1)
Input Offset Temperature Drift ΔVOS/ΔTA—±2.5—µV/°CT
A = -40°C to +125°C
Power Supply Rejection PSRR 80 88 — dB VDD = 2.7V to 5.5V
Input Current and Impedance
Input Bias Current IB—1—pA
Industrial Temperature IB—2060pAT
A = +85°C (Note 1)
Extended Temperature IB— 450 5000 pA TA = +125°C (Note 1)
Input Offset Current IOS —±1—pA
Common Mode Input Impedance ZCM —1013||6 —Ω||pF
Differential Input Impedance ZDIFF —1013||3 —Ω||pF
Common Mode
Common Mode Input Range VCMR VSS – 0.3 — VDD – 1.2 V
Common Mode Rejection Ratio CMRR 75 90 — dB VDD = 5.0V, VCM = -0.3V to 3.8V
Open-loop Gain
DC Open-loop Gain (large signal) AOL 100 115 — dB RL = 25 kΩ to VL,
VOUT = 0.1V to VDD – 0.1V
AOL 95 110 — dB RL = 5 kΩ to VL,
VOUT = 0.1V to VDD – 0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 20 mV RL = 25 kΩ to VL, Output overdrive = 0.5V
VOL, VOH VSS + 45 — VDD – 60 mV RL = 5 kΩ to VL, Output overdrive = 0.5V
Linear Output Voltage Swing VOUT VSS + 100 — VDD – 100 mV RL = 25 kΩ to VL, AOL ≥ 100 dB
VOUT VSS + 100 — VDD – 100 mV RL = 5 kΩ to VL, AOL ≥ 95 dB
Output Short Circuit Current ISC —±22—mAV
DD = 5.5V
ISC —±12—mAV
DD = 2.7V
Power Supply
Supply Voltage VDD 2.7 — 6.0 V (Note 2)
Quiescent Current per Amplifier IQ— 230 325 µA IO = 0
Note 1: These specifications are not tested in either the SOT-23 or TSSOP packages with date codes older than YYWW = 0408.
In these cases, the minimum and maximum values are by design and characterization only.
2: All parts with date codes November 2007 and later have been screened to ensure operation at VDD=6.0V. However, the
other minimum and maximum specifications are measured at 1.4V and/or 5.5V.
© 2007 Microchip Technology Inc. DS21314G-page 3
MCP601/1R/2/3/4
AC CHARACTERISTICS
MCP603 CHIP SELECT (CS) CHARACTERISTICS
FIGURE 1-1: MCP603 Chip Select (CS)
Timing Diagram.
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Frequency Response
Gain Bandwidth Product GBWP — 2.8 — MHz
Phase Margin PM — 50 — ° G = +1 V/V
Step Response
Slew Rate SR — 2.3 — V/µs G = +1 V/V
Settling Time (0.01%) tsettle — 4.5 — µs G = +1 V/V, 3.8V step
Noise
Input Noise Voltage Eni —7—µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —29—nV/√Hz f = 1 kHz
eni —21—nV/√Hz f = 10 kHz
Input Noise Current Density ini —0.6—fA/√Hz f = 1 kHz
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, and RL = 100 kΩ to VL, CL = 50 pF, and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS — 0.2 VDD V
CS Input Current, Low ICSL -1.0 — — µA CS = 0.2VDD
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH —0.72.0µACS = VDD
Shutdown VSS current IQ_SHDN -2.0 -0.7 — µA CS = VDD
Amplifier Output Leakage in Shutdown IO_SHDN —1—nA
Timing
CS Low to Amplifier Output Turn-on Time tON —3.110µsCS ≤ 0.2VDD, G = +1 V/V
CS High to Amplifier Output High-Z Time tOFF —100—nsCS ≥ 0.8VDD, G = +1 V/V, No load.
Hysteresis VHYST —0.4—VV
DD = 5.0V
CS tOFF
VOUT
tON
Hi-Z Hi-Z
IDD 2nA 230 µA
Output Active
ISS -700 nA -230 µA
CS 700 nA 2nA
Current
(typical) (typical)
(typical) (typical)
(typical) (typical)
MCP601/1R/2/3/4
DS21314G-page 4 © 2007 Microchip Technology Inc.
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +85 °C Industrial temperature parts
TA-40 — +125 °C Extended temperature parts
Operating Temperature Range TA-40 — +125 °C Note
Storage Tempera ture Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT23 θJA —256—°C/W
Thermal Resistance, 6L-SOT23 θJA —230—°C/W
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA —163—°C/W
Thermal Resistance, 8L-TSSOP θJA —124—°C/W
Thermal Resistance, 14L-PDIP θJA —70—°C/W
Thermal Resistance, 14L-SOIC θJA —120—°C/W
Thermal Resistance, 14L-TSSOP θJA —100—°C/W
Note: The Industrial temperature parts operate over this extended range, but with reduced performance. The
Extended temperature specs do not apply to Industrial temperature parts. In any case, the internal Junction
temperature (TJ) must not exceed the absolute maximum specification of 150°C.
VDD
MCP60X
RGRF
RNVOUT
VIN
VDD/2
1µF
CLRL
VL
0.1 µF
VDD
MCP60X
RGRF
RNVOUT
VDD/2
VIN
1µF
CLRL
VL
0.1 µF
© 2007 Microchip Technology Inc. DS21314G-page 5
MCP601/1R/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
FIGURE 2-1: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-2: Slew Rate vs. Temperature.
FIGURE 2-3: Gain Bandwidth Product,
Phase Margin vs. Temperature.
FIGURE 2-4: Quiescent Current vs.
Supply Voltage.
FIGURE 2-5: Quiescent Current vs.
Temperature.
FIGURE 2-6: Input Noise Voltage Density
vs. Frequency.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified pow er supply range) and therefore outside the warranted range.
-40
-20
0
20
40
60
80
100
120
1.E-
01
1.E+
00
1.E+
01
1.E+
02
1.E+
03
1.E+
04
1.E+
05
1.E+
06
1.E+
07
Frequency (Hz)
Open-Loop Gain (dB)
-240
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
0.1 1 10 100 1k 10k 100k 1M 10M
Gain
Phase
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-50-25 0 255075100125
Ambient Temperature (°C)
Slew Rate (V/µs)
Rising Edge
Falling Edge
VDD = 5.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
0
10
20
30
40
50
60
70
80
90
100
110
Phase Margin, G = +1 (°)
GBWP
PM, G = +1
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Quiescent Current
per Amplifier (µA)
IO = 0
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0
50
100
150
200
250
300
-50-250 255075100125
Ambient Temperature (°C)
Quiescent Current
per Amplifier (µA)
VDD = 2.7V
VDD = 5.5V
IO = 0
1.E+01
1.E+02
1.E+03
1.E+04
1.E-
01
1.E+0
0
1.E+0
1
1.E+0
2
1.E+0
3
1.E+0
4
1.E+0
5
1.E+0
6Frequency (Hz)
Input Noise Voltage Density
(V/√Hz)
0.1 1 10 100 1k 10k 100k 1M
10µ
1µ
100n
10n
MCP601/1R/2/3/4
DS21314G-page 6 © 2007 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
FIGURE 2-7: Input Offset Vo ltage.
FIGURE 2-8: Input Offset Voltage vs.
Temperature.
FIGURE 2-9: Input Offset Voltage vs.
Common Mode Input Vo ltage with VDD = 2.7V.
FIGURE 2-10: Input Offset Voltage Drift.
FIGURE 2-11: CMRR, PSRR vs.
Temperature.
FIGURE 2-12: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
0%
2%
4%
6%
8%
10%
12%
14%
16%
-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0
Input Offset Voltage (mV)
Percentage of Occurrences
1200 Samples
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Input Offset Voltage (mV)
VDD = 2.7V
VDD = 5.5V
-200
-100
0
100
200
300
400
500
600
700
800
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 2.7V
TA = –40°C
TA
= +25°C
TA
= +85°C
TA = +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-10-8-6-4-20246810
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
1200 Samples
TA = –40 to +125°C
75
80
85
90
95
100
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
CMRR, PSRR (dB)
PSRR
CMRR
-200
-100
0
100
200
300
400
500
600
700
800
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
TA
= –40°C
TA
= +25°C
TA
= +85°C
TA = +125°C
© 2007 Microchip Technology Inc. DS21314G-page 7
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
FIGURE 2-13: Channel-to-Channel
Separation vs. Frequency.
FIGURE 2-14: Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-15: DC Open-Loop Gain vs.
Load Resistance.
FIGURE 2-16: CMRR, PSRR vs.
Frequency.
FIGURE 2-17: Input Bias Current, Input
Offset Current vs. Common Mode Input Voltage.
FIGURE 2-18: DC Open-Loop Gain vs.
Supply Voltage.
90
100
110
120
130
140
150
1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Channel-to-Channel
Separation (dB)
No Load
Input Referred
1k 10k 100k 1M
1
10
100
1000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias and Offset
Currents (pA)
IB
VDD = 5.5V
VCM
= 4.3V
IOS
80
90
100
110
120
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (Ω)
DC Open-Loop Gain (dB)
VDD = 2.7V
VDD = 5.5V
100 1k 10k 100k
10
20
30
40
50
60
70
80
90
100
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
CMRR, PSRR (dB)
CMRR
VDD = 5.0V
110010k1M
PSRR+
PSRR–
10 1k 100k
1
10
100
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias and Offset
Currents (pA)
IB, +85°C
VDD = 5.5V
max. VCMR ≥ 4.3V
IB, +125°C
IOS, +85°C
IOS, +125°C
80
90
100
110
120
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
DC Open-Loop Gain (dB)
RL = 25 kΩ
MCP601/1R/2/3/4
DS21314G-page 8 © 2007 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
FIGURE 2-19: Gain Bandwidth Product,
Phase Margin vs. Load Resistance.
FIGURE 2-20: Output Volt age Headroom
vs. Output Current.
FIGURE 2-21: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-22: DC Open-Loop Gain vs.
Temperature.
FIGURE 2-23: Output Voltage Headroom
vs. Temperature.
FIGURE 2-24: Output Short-Circuit Current
vs. Supply Voltage.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
1.E+02 1.E+03 1.E+04 1.E+05
Load Resistance (Ω)
Gain Bandwidth Product
(MHz)
30
40
50
60
70
80
90
100
Phase Margin, G = +1 (°)
100 10k1k 100k
VDD = 5.0V
GBWP
PM, G = +1
1
10
100
1,000
0.01 0.1 1 10
Output Current Magnitude (mA)
Output Headroom (mV);
VDD – VOH and VOL – VSS
VDD – VOH
VOL – VSS
0.1
1
10
1.E+04 1.E+05 1.E+06
Frequency (Hz)
Maximum Output Voltage
Swing (V P-P)
10k 100k 1M
VDD = 5.5V
VDD = 2.7V
80
90
100
110
120
130
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
DC Open-Loop Gain (dB)
VDD
= 5.5
V
VDD
= 2.7
V
RL = 25 kΩ
RL
= 5 kΩ
1
10
100
1000
-50-25 0 255075100125
Ambient Temperature (°C)
Output Headroom (mV);
VDD – VOH and VOL – VSS
VDD – VOH
RL = 25 kΩ
VDD = 5.5V
RL tied to VDD/2
VOL – VSS
RL = 5 kΩ
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Output Short Circuit Current
Magnitude (mA)
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
© 2007 Microchip Technology Inc. DS21314G-page 9
MCP601/1R/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
FIGURE 2-25: Large Signal Non-Inverting
Pulse Response.
FIGURE 2-26: Small Signal Non-Inverting
Pulse Response.
FIGURE 2-27: Chip Select Timing
(MCP603).
FIGURE 2-28: Large Signal Inver ting Pulse
Response.
FIGURE 2-29: Small Signal Inverting Pulse
Response.
FIGURE 2-30: Quiescent Current Through
VSS vs. Chip Select Voltage (MCP603).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (1 µs/div)
Output Voltage (V)
VDD = 5.0V
G = +1
Time (1 µs/div)
Output Voltage (20 mV/div)
VDD = 5.0V
G = +1
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Time (5 µs/div)
Output Voltage,
Chip Select Voltage (V)
VDD = 5.0V
G = +1
VIN = 2.5V
RL = 100 kΩ to GND
CS
VOUT Active
VOUT High-Z
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Time (1 µs/div)
Output Voltage (V)
VDD = 5.0V
G = –1
Time (1 µs/div)
Output Voltage (20 mV/div)
VDD = 5.0V
G = –1
-800
-700
-600
-500
-400
-300
-200
-100
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Quiescent Current
through V SS (µA)
VDD = 5.5V
MCP601/1R/2/3/4
DS21314G-page 10 © 2007 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.7V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 50 pF and CS is tied low.
FIGURE 2-31: Chip Select Pin Input
Current vs. Chip Select Voltage.
FIGURE 2-32: Hysteresis of Chip Select’s
Internal Switch.
FIGURE 2-33: The MCP601/1R/2/3/4
family of op amps shows no phase reversal
under input overdrive.
FIGURE 2-34: Measured Input Current vs.
Input Voltage (below VSS).
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Chip Select Pin Current (µA)
VDD = 5.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.00.51.01.52.02.53.03.54.04.55.0
Chip Select Voltage (V)
Internal Chip Select Switch
Output Voltage (V)
VDD = 5.0V
Amplifier Hi-Z
Amplifier On
CS Hi to Low CS Low to Hi
-1
0
1
2
3
4
5
6
Time (5 µs/div)
Input and Output Voltages (V)
VDD = +5.0V
G = +2
VIN
VOUT
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
© 2007 Microchip Technology Inc. DS21314G-page 11
MCP601/1R/2/3/4
3.0 PIN DESCRIPTIONS
Description s of the pi ns are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
3.1 Analog Outputs
The op amp output pins are low-impedance voltage
sources.
3.2 Analog Inputs
The op amp non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 Chip Select Digital Input
This is a CMOS, Schmitt-triggered input that places the
part into a low power mode of operation.
3.4 Power Supply Pins
The positive power supply pin (VDD) is 2.5V to 6.0V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
MCP601 MCP601R MCP603
Symbol Description
PDIP, SOIC,
TSSOP SOT-23-5 SOT-23-5
(Note 1) SOT-23-6 PDIP, SOIC,
TSSOP
6116 6 V
OUT Analog Output
2442 2 V
IN– Inverting Input
3333 3 V
IN+ Non-inverting Input
7527 7 V
DD Positive Power Supply
4254 4 V
SS Negative Power Supply
———8 8 CSChip Select
1, 5, 8 — — 1, 5 1 NC No Internal Connection
Note 1: The MCP601R is only available in the 5-pin SOT-23 package.
MCP602 MCP604
Symbol Description
PDIP, SOIC,
TSSOP PDIP, SOIC,
TSSOP
11 V
OUTA Analog Outpu t (op amp A)
22 V
INA– Inverting Input (op amp A)
33 V
INA+ Non-inverting Input (op amp A)
84 V
DD Positive Power Supply
55 V
INB+ Non-inverting Input (op amp B)
66 V
INB– Inverting Input (op amp B)
77 V
OUTB Analog Output (op amp B)
—8 V
OUTC Analog Output (op amp C)
—9 V
INC– Inverting Input (op amp C)
—10 V
INC+ Non-inverting Input (op amp C)
411 V
SS Negative Power Supply
—12 V
IND+ Non-inverting Input (op amp D)
—13 V
IND– Inverting Input (op amp D)
—14 V
OUTD Analog Output (op amp D)
MCP601/1R/2/3/4
DS21314G-page 12 © 2007 Microchip Technology Inc.
4.0 APPLICATIONS INFORMATION
The MCP601/1R/2/3/4 family of op amps are fabricated
on Microchip’s state-of-the-art CMOS process. They
are unity-gain stable and suitable for a wide range of
general purpose applications.
4.1 Inputs
4.1.1 PHASE REVERSAL
The MCP601/1R/2/3/4 op amp is desig ned to prevent
phase reversal when the inpu t pins exceed the supp ly
voltages. Figure 2-34 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must li mit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resi stors R1 and R2 also limit
the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-34. Applications that are
high impedance may need to limit th e useable voltage
range.
4.1.3 NORMAL OPERATION
The Common Mode Input Voltage Range (VCMR)
includes ground in single-supply systems (VSS), but
does not include VDD. This means that the amplifier
input behaves linearly as long as the Common Mode
Input Voltage (VCM) is kept within the specified VCMR
limits (VSS–0.3V to VDD–1.2V at +25°C).
Figure 4-3 shows a unity gain buffer. Since VOUT is the
same voltage as the inverting input, VOUT must be kept
below VDD–1.2V for correct operation.
FIGURE 4-3: Unity Gain Buffer has a
Limited VOUT Range.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1
MCP60X
R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
R2>VSS – (minimum expected V2)
2mA
V2R2
D2
R3
MCP60X VOUT
+
–
VIN
© 2007 Microchip Technology Inc. DS21314G-page 13
MCP601/1R/2/3/4
4.2 Rail-to-Rail Output
There are two specifications that describe the output
swing capability of the MCP601/1R/2/3/4 family of op
amps. The first specification (Maximum Output Voltage
Swing) defines the absolute maximum swing that can
be achieved under the specified load conditions. For
instance, the output voltage swings to within 15 mV of
the negative rail with a 25 kΩ load to VDD/2. Figure 2-33
shows how the output voltage is limited when the input
goes beyond the li near region of operation.
The second specification that describes the output
swing capability of these amplifiers is the Linear Output
V oltage Swing. This specification defines the maximum
output swing that can be achieved while the amplifier is
still operating in its linear region. To verify linear
operation in this range, the large signal (DC Open-Loop
Gain (AOL)) is measured at points 100 mV inside the
supply rails. The measurement must exceed the
specified gains in the specification table.
4.3 MCP603 Chip Select
The MCP603 is a single amplifier with Chip Select
(CS). When CS is pulled high, the supply current drops
to -0.7 µA (typ.), which is pu lled through the CS pin to
VSS. When this happens, the amplifier output is put into
a high-impedance state. Pulling CS low enables the
amplifier.
The CS pin has an internal 5 MΩ (typical) pull-down
resistor connected to VSS, so it will go low if the CS pin
is left floating. Figure 1-1 is the Chip Select timing
diagram and shows the output voltage, supply currents,
and CS current in response to a CS pulse. Figure 2-27
shows the measured output voltage response to a CS
pulse.
4.4 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produce s gain peaking in the frequency
response with overshoot and ringing in the step
response.
When driving large capacitive loads with these op
amps (e.g., > 40 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
FIGURE 4-4: Output resistor RISO
stabilizes large capacitive loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN) in order to make
it easier to interpret the plot for arbitrary gains. GN is the
circuit’s noise gain. For non-inverting gains, GN and the
gain are equal. For inverting gains, GN = 1 + |Gain|
(e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-5: Recommended RISO values
for capacitive loads.
Once you have selected RISO for you r circuit, double-
check the resulting frequency response peaking and
step response overshoot in your circuit. Evalu ation on
the bench and simulations with the MCP601/1R/2/3/4
SPICE macro model are very helpful. Modify RISO’s
value until the response is reasonable.
4.5 Supply Bypass
With this family of op amps, the power supply pin (VDD
for single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It also nee ds a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
nearby analog parts.
MCP60X
RISO VOUT
CL
RF
RG
+
–
Normalized Load Capacitance;
CL / GN (F)
Recommended RISO (Ω)
10p 100p 1n 10n
10
100
1k
GN = +1
GN ≥ +2
MCP601/1R/2/3/4
DS21314G-page 14 © 2007 Microchip Technology Inc.
4.6 Unused Op Amps
An unused op amp in a quad package (MCP604)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-6: Unused Op Amps.
4.7 PCB Surface Leakage
In applications where low input bias current is critical,
printed circuit board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference
would cause 5 pA of current to flow. This is greater
than the MCP601/1R/2/3/4 family’s bias current at
+25°C (1 pA, typical).
The easiest way to reduce surface leaka ge is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
FIGURE 4-7: Example Guard Ring layout.
1. Connect the guard ring to the inverting input pin
(VIN–) for non-inverting gain amplifiers, includ-
ing unity-gain buffers. This biases the guard ring
to the common mode in p ut vol tage.
2. Connect the guard ring to the non-inverting input
pin (VIN+) for inverting gain amplifiers and
transimpedance amplifiers (converts current to
voltage, such as photo detectors). This biases
the guard ring to the same reference voltage as
the op amp (e.g., VDD/2 or ground).
4.8 Typical Applications
4.8.1 ANALOG FILTERS
Figure 4-8 and Figure 4-9 show low-pass, second-
order, Butterworth filters with a cutoff frequency of
10 Hz. The filter in Figure 4-8 has a no n-inverting ga in
of +1 V/V, and the filter in Figure 4-9 has an inverting
gain of -1 V/V.
FIGURE 4-8: Second-O rd e r, Low-Pass
Sallen-Key Filter.
FIGURE 4-9: Second-O rd e r, Low-Pass
Multiple-Feedback Filter.
The MCP601/1R/2/3/4 family of op amps have low
input bias current, which allo ws the designer to select
larger resistor val ues and smaller capacitor values for
these filters. This helps produce a compact PCB layout.
These filters, and others, can be designed using
Microchip’s Design Aids; see Section 5.2 “FilterLab®
Software” and Section 5.3 “Mindi™ Simulatior
Tool”.
VDD
VDD
¼ MCP604 (A) ¼ MCP604 (B)
R1
R2
VDD
VREF
VREF VDD R2
R1R2
+
------------------
⋅=
Guard Ring VIN– VIN+
C2VOUT
R1R2
C1
VIN
47 nF
382 kΩ641 kΩ
22 nF
G = +1 V/ V
fP = 10 Hz
MCP60X
+
–
C2
VOUT
R1R3C1
VIN
R2
VDD/2
G = -1 V/V
fP = 10 Hz
618 kΩ
618 kΩ1.00 MΩ8.2 nF
47 nF MCP60X
–
+
© 2007 Microchip Technology Inc. DS21314G-page 15
MCP601/1R/2/3/4
4.8.2 INSTRUMENTATION AMPLIFIER
CIRCUITS
Instrumentation amplifiers have a di fferential input that
subtracts one input voltage from another and rejects
common mode signals. These amplifiers also provide a
single-ended output voltage.
The three-op amp instrument ation amplifier is illustrated
in Figure 4-10. One advant age of this approach is unity-
gain operation, while one disadvantage is that the
common mode input range is reduced as R2/RG gets
larger.
FIGURE 4-10: Three-Op Amp
Instrumentation Amplifier.
The two-op amp instrumentation amplifier is shown in
Figure 4-11. While its power consumption is lower than
the three-op amp version, its main drawbacks are that
the common mode range is re duced with higher gains
and it must be configured in gains of two or higher.
FIGURE 4-11: Two-Op Amp
Instrumentation Amplifier.
Both instrumentation amplifiers should use a bulk
bypass capacitor of at least 1 µF. The CMRR of these
amplifiers will be set by both the op amp CMRR and
resistor matching.
4.8.3 PHOTO DETECTION
The MCP601/1R/2/3/4 op amps can be used to easily
convert the signal from a sensor that produces an
output current (such as a photo diode) into a voltage (a
transimpedance amplifier). This i s implemented with a
single resistor (R2) in the feedback loop of the
amplifiers shown in Figure 4-12 and Figure 4-13. The
optional capacitor (C2) sometimes provides stability for
these circuits.
A photodiode configured in the Pho tovoltaic mode has
zero voltage potential placed across it (Figure 4-12). In
this mode, the light sensitivity and linearity is
maximized, making it best suited for precision
applications. The key amplifier specifications for this
application are: low input bias current, low noise,
common mode input voltage range (including g round),
and rail-to-rail output.
FIGURE 4-12: Photovoltaic Mode Detector.
In contrast, a photodiode that is configured in the
Photoconductive mode has a reverse bias voltage
across the photo-sensing element (Figure 4-13). This
decreases the diode capacitance, which facilitates
high-speed operation (e.g., high-speed digital
communications). The design trade-off is increased
diode leakage current and linearity errors. The op amp
needs to have a wide Gain Bandwidth Product
(GBWP).
FIGURE 4-13: Photoconductive Mode
Detector.
MCP60X
V1
MCP60X
V2
R2
R2
R3
MCP60X
R4
R3R4
VOUT
VREF
RG
+
–
–
+
–
+
VOUT V1V2
–()12R2
RG
---------+
⎝⎠
⎛⎞
R4
R3
------
⎝⎠
⎛⎞VREF
+=
MCP60X
V2
RG
R2R2
MCP60X
R1
VOUT
VREF
V1
R1
-
+
-
+
VOUT V1V2
–()1R1
R2
------2R1
RG
---------++
⎝⎠
⎛⎞
VREF
+=
D1
Light
VOUT
VDD
MCP60X
R2
C2
ID1
VOUT = ID1 R2
–
+
D1
Light
VOUT
VDD
MCP60X
R2
C2
ID1
VOUT = ID1 R2
VBIAS VBIAS < 0V
–
+
MCP601/1R/2/3/4
DS21314G-page 16 © 2007 Microchip Technology Inc.
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP601/1R/2/3/4 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP601/1R/2/
3/4 op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.m icrochip.com/filterl ab, the
FilterLab d esign tool provides fu ll schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can b e
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Simulatior Tool
Microchip’s Mindi™ simulator tool aids in the design of
various circuits useful for active filter, amplifier and
power-management applications. It is a free online
simulation tool available from the Microchip web site at
www.microchip.com/mindi. This interactive simulator
enables designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
simulation tool can be downloaded to a personal
computer or workstation.
5.4 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especial ly useful are:
•P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
•P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
ation Board
5.6 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental
reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
© 2007 Microchip Technology Inc. DS21314G-page 17
MCP601/1R/2/3/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
5-Lead SOT-23 (MCP601 and MCP601R only)Example:
XXNN SJ25
Device I-Temp
Code
E-Temp
Code
MCP601 SANN SLNN
MCP601R SJNN SMNN
6-Lead SOT-23 (MCP603 only) Example:
XXNN AU25
Device I-Temp
Code
E-Temp
Code
MCP603 AENN AUNN
MCP601/1R/2/3/4
DS21314G-page 18 © 2007 Microchip Technology Inc.
Package Marking Information (Continued)
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP601
I/P256
0722
MCP601
I/SN0722
256
MCP601
E/P 256
0722
MCP601E
SN 0722
256
3
e
OR
OR
3
e
8-Lead TSSOP Example:
XXXX
XYWW
NNN
601
I722
256
© 2007 Microchip Technology Inc. DS21314G-page 19
MCP601/1R/2/3/4
Package Marking Information (Continued)
14-Lead TSSOP (MCP604)Example:
XXXXXXXX
YYWW
NNN
604E
0722
256
14-Lead SOIC (150 mil) (MCP604)Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX MCP604ISL
0722256
MCP604
0722256
E/SL^^
OR
3
e
14-Lead PDIP (300 mil) (MCP604)Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
MCP604-I/P
0722256
MCP604
0722256
E/P
3
e
OR
MCP601/1R/2/3/4
DS21314G-page 20 © 2007 Microchip Technology Inc.
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© 2007 Microchip Technology Inc. DS21314G-page 27
MCP601/1R/2/3/4
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MCP601/1R/2/3/4
DS21314G-page 28 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS21314G-page 29
MCP601/1R/2/3/4
APPENDIX A: REVISION HISTORY
Revision G (December 2007)
• Updated Figure 2-15 and Figure 2-19.
• Updated Table 3-1 and Table 3-2.
• Updated notes to Section 1.0 “Electrical
Characteristics”.
• Expanded Analog Input Absolute Maximum
Voltage Range (app lies retroactively).
• Expanded operating VDD to a maximum of 6.0V.
• Added Figure 2-34.
• Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current Lim-
its”, and Section 4.1.3 “Normal Operation”.
• Corrected Section 6.0 “Packaging Informa-
tion”.
Revision F (February 2004)
• Undocumented changes.
Revision E (September 2003)
• Undocumented changes.
Revision D (April 2000)
• Undocumented changes.
Revision C (July 1999)
• Undocumented changes.
Revision B (June 1999)
• Undocumented changes.
Revision A (March 1999)
• Original Release of this Document.
MCP601/1R/2/3/4
DS21314G-page 30 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS21314G-page 31
MCP601/1R/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pr icing or delivery, refer to the factory or the listed sales office.
MCP601/1R/2/3/4
DS21314G-page 32 © 2007 Microchip Technology Inc.
NOTES:
© 2007 Microchip Technology Inc. DS21314G-page 33
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICST ART, PRO MA TE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of product s is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act .
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for th e design
and manufacture of development systems is ISO 9001:2000 certified.
DS21314G-page 34 © 2007 Microchip Technology Inc.
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10/05/07