ZGM130S Z-Wave 700 SiP Module Data Sheet The Silicon Labs Z-Wave 700 SiP Module, ZGM130S, is a fully integrated Z-Wave module, enabling rapid development of Z-Wave solutions. KEY FEATURES It is an ideal solution for energy-friendly smart home control applications such as motion sensors, door/window sensors, access control, appliance control, building automation, energy management, lighting, and security networks in the "Internet of Things". Built with low-power Gecko technology, which includes innovative low energy techniques, fast wake-up times and energy saving modes, the ZGM130S reduces overall power consumption and maximizes battery life. The module contains a native security stack and a comprehensive set of hardware peripherals usable for advanced device functionality, and offers 64 kB of flash memory for OEM applications. * Range: up to 100 meters * 9.8 mA RX current at 100 kbps, GFSK, 868 MHz * 13.3 mA TX current at 0 dBm output power at 908 MHz * 32-bit ARM(R) Cortex(R)-M4 core at 39 MHz * Flash memory: 512 kB (64 kB Application) * RAM: 64 kB (8 kB Application) Smart Home Security Lighting Health and Wellness Metering Building Automation * Autonomous Hardware Crypto Accelerator and Random Number Generator * Integrated DC-DC Converter * Robust peripheral set and up to 32 GPIO * External SAW filter optional Debug Interface H-F Crystal Oscillator H-F RC Oscillator Auxiliary H-F RC Oscillator L-F RC Oscillator Ultra L-F RC Oscillator LDMA Controller RAM Memory Supply DCDC and decoupling components 39 MHz 512 kByte Flash Program Memory ARM CortexTM M4 processor with DSP extensions, FPU and MPU Clock Management Crystal Core / Memory ETM * RX sensitivity @ 100 kbps: -97.5 dBm * 0.8 A EM4H current (128 Byte RAM retention and RTCC running from LFRCO) Z-Wave 700 ZGM130S modules can be used in a wide variety of applications: * * * * * * * TX power up to 13 dBm Energy Management Voltage Regulator Voltage Monitor DC-DC Converter Power-On Reset Brown-Out Detector Other CRYPTO CRC True Random Number Generator SMU 32-bit bus Peripheral Reflex System Radio Transceiver Serial Interfaces FRC DEMOD LNA I PGA IFADC Q Frequency Synthesizer AGC RAC PA USART Low Energy UARTTM RF Frontend CRC RF frontend matching BUFC RF frontend MOD 2 IC I/O Ports Timers and Triggers External Interrupts Timer/Counter General Purpose I/O Low Energy Timer Protocol Timer Low Energy Sensor Interface Pin Reset Pulse Counter Watchdog Timer Pin Wakeup Real Time Counter and Calendar Cryotimer Analog I/F ADC Analog Comparator IDAC Capacitive Touch VDAC Op-Amp Lowest power mode with peripheral operational: EM0--Active EM1--Sleep silabs.com | Building a more connected world. EM2--Deep Sleep EM3--Stop EM4--Hibernate EM4--Shutoff Rev. 1.0 ZGM130S Z-Wave 700 SiP Module Data Sheet Feature List 1. Feature List The ZGM130S highlighted features are listed below. * Low Power Wireless System-on-Chip. * High Performance 32-bit, 39 MHz ARM Cortex (R)-M4 with DSP instruction and floating-point unit for efficient signal processing * Embedded Trace Macrocell (ETM) for advanced debugging * 512 kB flash program memory (64 kB available for user applications) * 64 kB RAM data memory (8kB available for user applications) * TX power up to 13 dBm * Supports optional external SAW filter * Low Energy Consumption * 9.8 mA RX current at 100 kbps, GFSK, 868 MHz * 40.7 mA TX current at 13 dBm output power at 868 MHz * 13.3 mA TX current at 0 dBm output power at 908 MHz * 69 A/MHz in Active Mode (EM0) * 0.8 A EM4 current (128 Byte RAM retention and RTCC running from LFRCO) * High Receiver Performance * -97.9 dBm sensitivity at 100 kbit/s GFSK, 868 MHz * -97.5 dBm sensitivity at 100 kbit/s GFSK, 915 MHz * Supported Protocols: * Z-Wave * Support for Internet Security * General Purpose CRC * True Random Number Generator (TRNG) * 2 x Hardware Cryptographic Acceleration for AES 128/256, SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC silabs.com | Building a more connected world. * Wide selection of MCU peripherals * 12-bit 1 Msps SAR Analog to Digital Converter (ADC) * 2 x Analog Comparator (ACMP) * 2 x Digital to Analog Converter (VDAC) * 3 x Operational Amplifier (Opamp) * Digital to Analog Current Converter (IDAC) * Low-Energy Sensor Interface (LESENSE) * Multi-channel Capacitive Sense Interface (CSEN) * 32 pins connected to analog channels (APORT) shared between analog peripherals * 32 General Purpose I/O pins with output state retention and asynchronous interrupts * 8 Channel DMA Controller * 12 Channel Peripheral Reflex System (PRS) * 2 x 16-bit Timer/Counter * 3 or 4 Compare/Capture/PWM channels * 1 x 32-bit Timer/Counter * 3 Compare/Capture/PWM channels * 32-bit Real Time Counter and Calendar * 16-bit Low Energy Timer for waveform generation * 32-bit Ultra Low Energy Timer/Counter for periodic wake-up from any Energy Mode * 16-bit Pulse Counter with asynchronous operation * 2 x Watchdog Timer * 3 x Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S) * Low Energy UART (LEUART TM) * 2 x I2C interface with SMBus support and address recognition in EM3 Stop * Wide Operating Range * 1.8 V to 3.8 V single power supply * Integrated DC-DC * -40 C to 85 C * Dimensions * 9 x 9 x 1.21 mm Rev. 1.0 | 2 ZGM130S Z-Wave 700 SiP Module Data Sheet Ordering Information 2. Ordering Information Table 2.1. Ordering Information Max TX Power Antenna Flash (kB) RAM (kB) GPIO Z-Wave 13 dBm RF pin 512 64 32 Tray Z-Wave 13 dBm RF pin 512 64 32 Tape & Reel Ordering Code Protocol Stack ZGM130S037HGN1 ZGM130S037HGN1R silabs.com | Building a more connected world. Carrier Rev. 1.0 | 3 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 8 8 8 3.3 Power . . . . . . . . . . . 3.3.1 Energy Management Unit (EMU) 3.3.2 DC-DC Converter . . . . . 3.3.3 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 9 9 3.4 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . 9 3.5 Clocking . . . . . . . . . . 3.5.1 Clock Management Unit (CMU) . 3.5.2 Internal Oscillators and Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 . 9 .10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 .10 .10 .10 .10 .10 .11 .11 3.7 Communications and Other Digital Peripherals . . . . . . . . . . 3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . 3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . 3.7.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . 3.7.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . 3.7.5 Low Energy Sensor Interface (LESENSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 .11 .11 .11 .11 .11 3.8 Security Features . . . . . . . . . . . . . . 3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) 3.8.2 Crypto Accelerator (CRYPTO) . . . . . . . . 3.8.3 True Random Number Generator (TRNG) . . . . 3.8.4 Security Management Unit (SMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 .11 .12 .12 .12 3.9 Analog. . . . . . . . . . . . . . 3.9.1 Analog Port (APORT) . . . . . . . 3.9.2 Analog Comparator (ACMP) . . . . . 3.9.3 Analog to Digital Converter (ADC) . . . 3.9.4 Capacitive Sense (CSEN) . . . . . . 3.9.5 Digital to Analog Current Converter (IDAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 .12 .12 .12 .12 .13 3.2 Radio . . . . . . . . . 3.2.1 Antenna Interface . . . 3.2.2 RFSENSE . . . . . . 3.2.3 Packet and State Trace . 3.2.4 Random Number Generator . . . 3.6 Counters/Timers and PWM . . . . . . . . . 3.6.1 Timer/Counter (TIMER) . . . . . . . . 3.6.2 Wide Timer/Counter (WTIMER) . . . . . . 3.6.3 Real Time Counter and Calendar (RTCC) . . 3.6.4 Low Energy Timer (LETIMER) . . . . . . 3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) 3.6.6 Pulse Counter (PCNT) . . . . . . . . . 3.6.7 Watchdog Timer (WDOG) . . . . . . . . silabs.com | Building a more connected world. . . . . . . . . . . . . . . . . . . . . . . . . Rev. 1.0 | 4 3.9.6 Digital to Analog Converter (VDAC) 3.9.7 Operational Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .13 . . . . . . . . . . . . . . . . . . . . .13 3.11 Core and Memory . . . . . . . . . . . . 3.11.1 Processor Core . . . . . . . . . . . . 3.11.2 Memory System Controller (MSC) . . . . . 3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 .13 .13 .13 3.12 Memory Map . 3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .15 4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Electrical Characteristics . . . . . . . . 4.1.1 Absolute Maximum Ratings . . . . . . 4.1.2 Operating Conditions . . . . . . . . 4.1.3 DC-DC Converter . . . . . . . . . 4.1.4 Current Consumption . . . . . . . . 4.1.5 Wake Up Times . . . . . . . . . . 4.1.6 Brown Out Detector (BOD) . . . . . . 4.1.7 Frequency Synthesizer . . . . . . . . 4.1.8 Sub-GHz RF Transceiver Characteristics . 4.1.9 Oscillators . . . . . . . . . . . . 4.1.10 Flash Memory Characteristics . . . . . 4.1.11 General-Purpose I/O (GPIO) . . . . . 4.1.12 Voltage Monitor (VMON) . . . . . . . 4.1.13 Analog to Digital Converter (ADC) . . . 4.1.14 Analog Comparator (ACMP) . . . . . 4.1.15 Digital to Analog Converter (VDAC) . . . 4.1.16 Current Digital to Analog Converter (IDAC) 4.1.17 Capacitive Sense (CSEN) . . . . . . 4.1.18 Operational Amplifier (OPAMP) . . . . 4.1.19 Pulse Counter (PCNT) . . . . . . . 4.1.20 Analog Port (APORT) . . . . . . . . 4.1.21 I2C . . . . . . . . . . . . . . 4.1.22 USART SPI Master Timing . . . . . . 4.1.23 USART SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 .16 .17 .18 .20 .23 .23 .24 .25 .31 .33 .34 .36 .37 .39 .42 .45 .47 .49 .52 .52 .53 .56 .57 4.2 Typical Performance Curves . 4.2.1 Zwave Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 .58 5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.1 Typical ZGM130S Connections . . . . . . . . . . . . . . . . . . . . . . . .59 6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.1 ZGM130S Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . .60 6.2 GPIO Functionality Table . . . . . . . . . . . . . . . . . . . . . . . . . .63 6.3 Alternate Functionality Overview . . . . . . . . . . . . . . . . . . . . . . . .75 6.4 Analog Port (APORT) Client Maps . . . . . . . . . . . . . . . . . . . . . . .87 silabs.com | Building a more connected world. Rev. 1.0 | 5 7. LGA64 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 96 7.1 LGA64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . .96 7.2 LGA64 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .98 8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 silabs.com | Building a more connected world. Rev. 1.0 | 6 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3. System Overview 3.1 Introduction The ZGM130S product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for any battery operated application, as well as other system where ultra-small size, reliable high performance RF, low-power consumption and easy application development are key requirements. This section gives a short introduction to the full radio and MCU system. Note: The hardware functions available to application code are strictly affected by the services enabled in the Z-Wave protocol stack and the version of the stack that is used. The software release note (SRN) for the used Z-Wave protocol version should be consulted to determine whether a specific hardware block is made available by the stack through the Z-Wave API for end-application use. A detailed block diagram of the ZGM130S module is shown in the figure below. Radio Transceiver Frequency Synthesizer To RF Frontend Circuits AGC MOD LETIMER TIMER PCNT RTC / RTCC Port Mapper ARM Cortex-M4 Core 64 KB RAM Memory Protection Unit Energy Management Floating Point Unit DMA Controller IOVDD Voltage Monitor AVDD VREGVDD Watchdog Timer bypass DC-DC Converter Voltage Regulator Clock Management ULFRCO AUXHFRCO Internal Crystal 39 MHz Crystal I2C 512 KB ISP Flash Program Memory LFRCO HFRCO HFXO CRYPTO A A H P B B PBn Port C Drivers PCn Port D Drivers PDn Port F Drivers PFn CRC LESENSE Analog Peripherals IDAC VDAC Internal Reference 12-bit ADC Mux & FB Brown Out / Power-On Reset LEUART Input Mux Debug Signals (shared w/GPIO) Serial Wire and ETM Debug / Programming Port B Drivers + - RESETn PAn CRYOTIMER USART Reset Management Unit Port A Drivers Op-Amp VDD APORT I Q IFADC PGA Q RFSENSE IOVDD Digital Peripherals BUFC PA RAC DEMOD LNA RF Match CRC ANTENNA FRC Port I/O Configuration Sub-GHz RF I Temp Sense Capacitive Touch + Analog Comparator Figure 3.1. ZGM130S Block Diagram 3.2 Radio The ZGM130S features a radio transceiver supporting Z-Wave protocol. 3.2.1 Antenna Interface The antenna interface consists of a single pin, connected to internal balun and matching network. silabs.com | Building a more connected world. Rev. 1.0 | 7 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3.2.2 RFSENSE The RFSENSE block generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4. RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy consumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by enabling normal RF reception. Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using available timer peripherals. 3.2.3 Packet and State Trace The ZGM130S Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It features: * Non-intrusive trace of transmit data, receive data and state information * Data observability on a single-pin UART data output, or on a two-pin SPI data output * Configurable data output bitrate / baudrate * Multiplexed transmitted data, received data and state / meta information in a single serial data stream 3.2.4 Random Number Generator The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain. The data is suitable for use in cryptographic applications. Output from the random number generator can be used either directly or as a seed or entropy source for software-based random number generator algorithms such as Fortuna. silabs.com | Building a more connected world. Rev. 1.0 | 8 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3.3 Power The ZGM130S has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a single external supply voltage is required, from which all internal voltages are created. An integrated DC-DC buck regulator is utilized to further reduce the current consumption. 3.3.1 Energy Management Unit (EMU) The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen below a chosen threshold. 3.3.2 DC-DC Converter The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2 and EM3. Patented RF noise mitigation allows operation of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting, short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current transients. 3.3.3 Power Domains The ZGM130S has two peripheral power domains for operation in EM2 and EM3. If all of the peripherals in a peripheral power domain are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall current consumption of the device. Table 3.1. Peripheral Power Subdomains Peripheral Power Domain 1 Peripheral Power Domain 2 ACMP0 ACMP1 PCNT0 CSEN ADC0 VDAC0 LETIMER0 LEUART0 LESENSE I2C0 APORT I2C1 - IDAC 3.4 General Purpose Input/Output (GPIO) ZGM130S has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals. The GPIO subsystem supports asynchronous external pin interrupts. 3.5 Clocking 3.5.1 Clock Management Unit (CMU) The Clock Management Unit controls oscillators and clocks in the ZGM130S. Individual enabling and disabling of clocks to all peripherals is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators. silabs.com | Building a more connected world. Rev. 1.0 | 9 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3.5.2 Internal Oscillators and Crystals The ZGM130S fully integrates several oscillator sources and a high frequency crystal. * The high-frequency crystal oscillator (HFXO) and integrated 39 MHz crystal provide a precise timing reference for the MCU and radio. * An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range. * An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial Wire Viewer port with a wide frequency range. * An integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation where high accuracy is not required. * An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy consumption in low energy modes. 3.6 Counters/Timers and PWM 3.6.1 Timer/Counter (TIMER) TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit TIMER_0 only. 3.6.2 Wide Timer/Counter (WTIMER) WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to 4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only. 3.6.3 Real Time Counter and Calendar (RTCC) The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscillators with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy and convenient data storage in all energy modes down to EM4H. A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for application software. 3.6.4 Low Energy Timer (LETIMER) The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be configured to start counting on compare matches from the RTCC. 3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz RC oscillator (LFRCO) or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of interrupt periods, facilitating flexible ultra-low energy operation. silabs.com | Building a more connected world. Rev. 1.0 | 10 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3.6.6 Pulse Counter (PCNT) The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from among any of the internal oscillators, except the AUXHFRCO. The peripheral may operate in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. 3.6.7 Watchdog Timer (WDOG) The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can also monitor autonomous systems driven by PRS. 3.7 Communications and Other Digital Peripherals 3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O interface. It supports full duplex asynchronous UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices supporting: * ISO7816 SmartCards * IrDA * I2S 3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication possible with a minimum of software intervention and energy consumption. 3.7.3 Inter-Integrated Circuit Interface (I2C) The I2C interface enables communication between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The interface provided to software by the I2C peripheral allows precise timing control of the transmission process and highly automated transfers. Automatic recognition of slave addresses is provided in active and low energy modes. 3.7.4 Peripheral Reflex System (PRS) The Peripheral Reflex System provides a communication network between different peripherals without software involvement. Peripherals producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer peripherals, which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT) can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power. 3.7.5 Low Energy Sensor Interface (LESENSE) The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configurable sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy budget. 3.8 Security Features 3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) The GPCRC block implements a Cyclic Redundancy Check (CRC) function supporting a fully-programmable 16-bit polynomial. silabs.com | Building a more connected world. Rev. 1.0 | 11 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3.8.2 Crypto Accelerator (CRYPTO) The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices support AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and SHA-256). Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM. Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233. The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger signals for DMA read and write operations. 3.8.3 True Random Number Generator (TRNG) The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation). 3.8.4 Security Management Unit (SMU) The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and can optionally generate an interrupt. 3.9 Analog 3.9.1 Analog Port (APORT) The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog peripherals on a flexible selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are grouped by X/Y pairs. 3.9.2 Analog Comparator (ACMP) The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the programmable threshold. 3.9.3 Analog to Digital Converter (ADC) The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential. 3.9.4 Capacitive Sense (CSEN) The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in adverse conditions including radiated noise and moisture. The peripheral can be configured to take measurements on a single port pin or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter, as well as digital threshold comparators to reduce software overhead. silabs.com | Building a more connected world. Rev. 1.0 | 12 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3.9.5 Digital to Analog Current Converter (IDAC) The IDAC can source or sink a configurable constant current. This current can be driven on an output pin or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 A and 64 A with several ranges consisting of various step sizes. 3.9.6 Digital to Analog Converter (VDAC) The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500 ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per singleended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any CPU intervention. The VDAC is available in all energy modes down to and including EM3. 3.9.7 Operational Amplifiers The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB space, and cost as compared with standalone opamps because they are integrated on-chip. 3.10 Reset Management Unit (RMU) The RMU is responsible for handling reset of the ZGM130S. A wide range of reset sources are available, including several power supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset. 3.11 Core and Memory 3.11.1 Processor Core The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system: * ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz * Memory Protection Unit (MPU) supporting up to 8 memory segments * Up to 512 kB flash program memory * Up to 64 kB RAM data memory * Configuration and event handling of all peripherals * 2-pin Serial-Wire debug interface 3.11.2 Memory System Controller (MSC) The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep. 3.11.3 Linked Direct Memory Access Controller (LDMA) The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be implemented. silabs.com | Building a more connected world. Rev. 1.0 | 13 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview 3.12 Memory Map The ZGM130S memory map is shown in the figures below. Note that 64 kB of flash in code space is available for user code. The remainder of the code flash area is reserved for the software stack. Figure 3.2. ZGM130S Memory Map -- Core Peripherals and Code Space silabs.com | Building a more connected world. Rev. 1.0 | 14 ZGM130S Z-Wave 700 SiP Module Data Sheet System Overview Figure 3.3. ZGM130S Memory Map -- Peripherals 3.13 Configuration Summary The features of the ZGM130S are a subset of the feature set described in the device reference manual. The table below describes device specific implementation of the features. Remaining peripherals support full configuration. Table 3.2. Configuration Summary Peripheral Configuration Pin Connections USART0 IrDA SmartCard US0_TX, US0_RX, US0_CLK, US0_CS USART1 IrDA I2S SmartCard US1_TX, US1_RX, US1_CLK, US1_CS USART2 IrDA SmartCard US2_TX, US2_RX, US2_CLK, US2_CS TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0] TIMER1 - TIM1_CC[3:0] WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0] silabs.com | Building a more connected world. Rev. 1.0 | 15 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4. Electrical Specifications 4.1 Electrical Characteristics All electrical parameters in all tables are specified under the following conditions, unless stated otherwise: * Typical values are based on TAMB=25 C and VDD= 3.3 V, by production test and/or technology characterization. * Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 antenna. * Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise. Refer to for more details about operational supply and temperature limits. 4.1.1 Absolute Maximum Ratings Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx. Table 4.1. Absolute Maximum Ratings Parameter Symbol Storage temperature range Test Condition Min Typ Max Unit TSTG -40 -- 85 C Voltage on any supply pin VDDMAX -0.3 -- 3.8 V Voltage ramp rate on any supply pin VDDRAMPMAX -- -- 1 V / s DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1 2 3 -0.3 -- Min of 5.25 and IOVDD +2 V Standard GPIO pins -0.3 -- IOVDD+0.3 V Total current into supply pins IVDDMAX Source -- -- 200 mA Total current into VSS ground lines IVSSMAX Sink -- -- 200 mA Current per I/O pin IIOMAX Sink -- -- 50 mA Source -- -- 50 mA Sink -- -- 200 mA Source -- -- 200 mA -40 -- 105 C Current for all I/O pins Junction temperature IIOALLMAX TJ Note: 1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD. 2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source below the valid operating range (e.g. IOVDD shorted to VSS), the pin voltage maximum is IOVDD + 0.3 V, to avoid exceeding the maximum IO current specifications. 3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register. Pins with over-voltage tolerance disabled have the same limits as Standard GPIO. silabs.com | Building a more connected world. Rev. 1.0 | 16 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.2 Operating Conditions When assigning supply sources, the following requirements must be observed: * VREGVDD = AVDD * IOVDD AVDD 4.1.2.1 General Operating Conditions Table 4.2. General Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Operating ambient temperature range TA -G temperature grade -40 25 85 C AVDD supply voltage1 VAVDD 1.8 3.3 3.8 V VREGVDD operating supply voltage1 2 VVREGVDD DCDC in regulation 2.4 3.3 3.8 V DCDC in bypass, 50mA load 1.8 3.3 3.8 V VREGVDD current IVREGVDD DCDC in bypass, T 85 C -- -- 200 mA 1.62 -- VVREGVDD V IOVDD operating supply volt- VIOVDD age All IOVDD pins3 HFCORECLK frequency fCORE VSCALE2, MODE = WS1 -- -- 39 MHz HFCLK frequency fHFCLK VSCALE2 -- -- 39 MHz Note: 1. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate. 2. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for other loads can be calculated as VDVDD_min+ILOAD * RBYP_max. 3. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD. silabs.com | Building a more connected world. Rev. 1.0 | 17 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.3 DC-DC Converter Test conditions: V_DCDC_I=3.3 V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated. Table 4.3. DC-DC Converter Parameter Symbol Test Condition Min Typ Max Unit Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50 mA 1.8 -- VVREGVDD_ V Low noise (LN) mode, 1.8 V output, IDCDC_LOAD = 100 mA, or Low power (LP) mode, 1.8 V output, IDCDC_LOAD = 10 mA 2.4 Output voltage programmable range1 VDCDC_O Regulation DC accuracy ACCDC Regulation window2 WINREG MAX -- VVREGVDD_ V MAX 1.8 -- VVREGVDD V Low Noise (LN) mode, 1.8 V target output 1.7 -- 1.9 V Low Power (LP) mode, LPCMPBIASEMxx3 = 0, 1.8 V target output, IDCDC_LOAD 75 A 1.63 -- 2.2 V Low Power (LP) mode, LPCMPBIASEMxx3 = 3, 1.8 V target output, IDCDC_LOAD 10 mA 1.63 -- 2.1 V Steady-state output ripple VR Radio disabled -- 3 -- mVpp Output voltage under/overshoot VOV CCM Mode (LNFORCECCM3 = 1), Load changes between 0 mA and 100 mA -- 25 60 mV DCM Mode (LNFORCECCM3 = 0), Load changes between 0 mA and 10 mA -- 45 90 mV Overshoot during LP to LN CCM/DCM mode transitions compared to DC level in LN mode -- 200 -- mV Undershoot during BYP/LP to LN CCM (LNFORCECCM3 = 1) mode transitions compared to DC level in LN mode -- 40 -- mV Undershoot during BYP/LP to LN DCM (LNFORCECCM3 = 0) mode transitions compared to DC level in LN mode -- 100 -- mV DC line regulation VREG Input changes between VVREGVDD_MAX and 2.4 V -- 0.1 -- % DC load regulation IREG Load changes between 0 mA and 100 mA in CCM mode -- 0.1 -- % silabs.com | Building a more connected world. Rev. 1.0 | 18 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Max load current ILOAD_MAX Low noise (LN) mode, Medium or Heavy Drive4 -- -- 80 mA Low noise (LN) mode, Light Drive4 -- -- 50 mA Low power (LP) mode, LPCMPBIASEMxx3 = 0 -- -- 75 A Low power (LP) mode, LPCMPBIASEMxx3 = 3 -- -- 10 mA Note: 1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD. 2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits. 3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the EMU_DCDCLOEM01CFG register, depending on the energy mode. 4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medium Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15. silabs.com | Building a more connected world. Rev. 1.0 | 19 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.4 Current Consumption 4.1.4.1 Current Consumption 3.3 V using DC-DC Converter Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, 1V8 = 1.8 V DC-DC output. T = 25 C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 C. Table 4.4. Current Consumption 3.3 V using DC-DC Converter Parameter Symbol Min Typ Max Unit 39 MHz crystal, CPU running while loop from flash2 -- 87 -- A/MHz 38 MHz HFRCO, CPU running Prime from flash -- 69 -- A/MHz 38 MHz HFRCO, CPU running while loop from flash -- 70 -- A/MHz 38 MHz HFRCO, CPU running CoreMark from flash -- 82 -- A/MHz 26 MHz HFRCO, CPU running while loop from flash -- 76 -- A/MHz 1 MHz HFRCO, CPU running while loop from flash -- 615 -- A/MHz 39 MHz crystal, CPU running while loop from flash2 -- 97 -- A/MHz 38 MHz HFRCO, CPU running Prime from flash -- 80 -- A/MHz 38 MHz HFRCO, CPU running while loop from flash -- 81 -- A/MHz 38 MHz HFRCO, CPU running CoreMark from flash -- 92 -- A/MHz 26 MHz HFRCO, CPU running while loop from flash -- 94 -- A/MHz 1 MHz HFRCO, CPU running while loop from flash -- 1145 -- A/MHz Current consumption in EM0 IACTIVE_CCM_VS mode with all peripherals disabled and voltage scaling enabled, DCDC in Low Noise CCM mode3 19 MHz HFRCO, CPU running while loop from flash -- 101 -- A/MHz 1 MHz HFRCO, CPU running while loop from flash -- 1124 -- A/MHz Current consumption in EM1 IEM1_DCM mode with all peripherals disabled, DCDC in Low Noise DCM mode1 39 MHz crystal2 -- 56 -- A/MHz 38 MHz HFRCO -- 39 -- A/MHz 26 MHz HFRCO -- 46 -- A/MHz 1 MHz HFRCO -- 588 -- A/MHz 19 MHz HFRCO -- 50 -- A/MHz 1 MHz HFRCO -- 572 -- A/MHz Current consumption in EM0 IACTIVE_DCM mode with all peripherals disabled, DCDC in Low Noise DCM mode1 Current consumption in EM0 IACTIVE_CCM mode with all peripherals disabled, DCDC in Low Noise CCM mode3 Current consumption in EM1 IEM1_DCM_VS mode with all peripherals disabled and voltage scaling enabled, DCDC in Low Noise DCM mode1 silabs.com | Building a more connected world. Test Condition Rev. 1.0 | 20 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Current consumption in EM2 IEM2_VS mode, with voltage scaling enabled, DCDC in LP mode4 Current consumption in EM3 IEM3_VS mode, with voltage scaling enabled Current consumption in EM4H mode, with voltage scaling enabled IEM4H_VS Test Condition Min Typ Max Unit Full 64 kB RAM retention and RTCC running from LFRCO -- 1.5 -- A 1 bank RAM retention and RTCC running from LFRCO5 -- 1.3 -- A Full 64 kB RAM retention and CRYOTIMER running from ULFRCO -- 1.14 -- A 128 byte RAM retention, RTCC running from LFRCO -- 0.8 -- A Note: 1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD. 2. CMU_HFXOCTRL_LOWPOWER=0. 3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD. 4. DCDC Low Power Mode = Medium Drive, LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIMSEL=1, ANASW=DVDD. 5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1 silabs.com | Building a more connected world. Rev. 1.0 | 21 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.4.2 Current Consumption Using Radio 3.3 V with DC-DC Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V. DC-DC on. T = 25 C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 C. Table 4.5. Current Consumption Using Radio 3.3 V with DC-DC Parameter Symbol Test Condition Current consumption in receive mode, active packet reception (MCU in EM1 @ 39 MHz, peripheral clocks disabled) IRX_ACTIVE Current consumption in receive mode, listening for packet (MCU in EM1 @ 39 MHz, peripheral clocks disabled) IRX_LISTEN Current consumption in ITX transmit mode (MCU in EM1 @ 39 MHz, peripheral clocks disabled) silabs.com | Building a more connected world. Min Typ Max Unit 100 kbit/s, 2GFSK, F=869.85 MHz -- 9.8 10.3 mA 40 kbit/s, 2FSK, F=868.4 MHz -- 9.6 10 mA 9.6 kbit/s, Manchester, 2FSK, F=868.42 MHz -- 9.6 10 mA 100 kbit/s, 2GFSK, F=916.0 MHz -- 9.9 10.3 mA 40 kbit/s, 2FSK, F=908.4 MHz -- 9.7 10.1 mA 9.6 kbit/s, Manchester, 2FSK, F=908.42 MHz -- 9.5 9.9 mA 100 kbit/s, 2GFSK, F=869.85 MHz -- 9.9 10.3 mA 40 kbit/s, 2FSK, F=868.4 MHz -- 9.7 10.1 mA 9.6 kbit/s, Manchester, 2FSK, F=868.42 MHz -- 9.6 10 mA 100 kbit/s, 2GFSK, F=916.0 MHz -- 9.9 10.4 mA 40 kbit/s, 2FSK, F=908.40 MHz -- 9.7 10.1 mA 9.6 kbit/s, Manchester, 2FSK, F=908.42 MHz -- 9.5 9.9 mA F=868.4 MHz, CW, 13 dBm output power -- 40.7 -- mA F=908.4 MHz, CW, 4 dBm output power -- 17.9 -- mA F=908.4 MHz, CW, 0 dBm output power -- 13.3 -- mA Rev. 1.0 | 22 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.5 Wake Up Times Table 4.6. Wake Up Times Parameter Symbol Wake up time from EM1 tEM1_WU Wake up from EM2 tEM2_WU Wake up from EM3 Test Condition tEM3_WU Min Typ Max Unit -- 3 -- AHB Clocks Code execution from flash -- 10.9 -- s Code execution from RAM -- 3.8 -- s Code execution from flash -- 10.9 -- s Code execution from RAM -- 3.8 -- s Wake up from EM4H1 tEM4H_WU Executing from flash -- 90 -- s Wake up from EM4S1 tEM4S_WU Executing from flash -- 300 -- s Time from release of reset source to first instruction execution tRESET Soft Pin Reset released -- 51 -- s Any other reset released -- 358 -- s Power mode scaling time tSCALE VSCALE0 to VSCALE2, HFCLK = 19 MHz2 3 -- 31.8 -- s VSCALE2 to VSCALE0, HFCLK = 19 MHz4 -- 4.3 -- s Note: 1. Time from wake up request until first instruction is executed. Wakeup results in device reset. 2. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 s + 28 HFCLKs. 3. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/s for approximately 20 s. During this transition, peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 F capacitor) to 70 mA (with a 2.7 F capacitor). 4. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 s + 29 HFCLKs. 4.1.6 Brown Out Detector (BOD) Table 4.7. Brown Out Detector (BOD) Parameter Symbol Test Condition Min Typ Max Unit AVDD BOD threshold VAVDDBOD AVDD rising -- -- 1.8 V AVDD falling (EM0/EM1) 1.62 -- -- V AVDD falling (EM2/EM3) 1.53 -- -- V AVDD BOD hysteresis VAVDDBOD_HYST -- 20 -- mV AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/s rate -- 2.4 -- s EM4 BOD threshold VEM4DBOD AVDD rising -- -- 1.7 V AVDD falling 1.45 -- -- V -- 25 -- mV -- 300 -- s EM4 BOD hysteresis VEM4BOD_HYST EM4 BOD response time tEM4BOD_DELAY silabs.com | Building a more connected world. Supply drops at 0.1V/s rate Rev. 1.0 | 23 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.7 Frequency Synthesizer Table 4.8. Frequency Synthesizer Parameter Symbol Test Condition Min Typ Max Unit RF synthesizer frequency range fRANGE 779 - 956 MHz 779 -- 956 MHz LO tuning frequency resolution with 39 MHz crystal fRES 779 - 956 MHz -- -- 24 Hz Frequency deviation resolution with 39 MHz crystal dfRES 779 - 956 MHz -- -- 24 Hz Maximum frequency deviation with 39 MHz crystal dfMAX 779 - 956 MHz -- -- 559 kHz silabs.com | Building a more connected world. Rev. 1.0 | 24 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.8 Sub-GHz RF Transceiver Characteristics 4.1.8.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band Unless otherwise indicated, typical conditions are: T = 25 C, VREGVDD = AVDD = IOVDD = 3.3 V. Crystal frequency = 39 MHz. RF frequency band 915 MHz. Table 4.9. Sub-GHz RF Transmitter characteristics for 915 MHz Band Parameter Symbol RF tuning frequency range FRANGE Maximum TX Power1 POUTMAX Minimum active TX Power POUTMIN Output power step size POUTSTEP Output power variation vs supply at POUTMAX Output power variation vs temperature, peak to peak Min Typ Max Unit 902 -- 930 MHz -- 4 -- dBm -- -30 -- dBm output power > 0 dBm -- 0.5 -- dB POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, T = 25 C -- 2.72 -- dB POUTVAR_T -40 to +85 C -- 1.79 -- dB T = 25 C, Over specified RF tuning frequency range -- 1.11 -- dB Spurious emissions of harSPURHARM_FCC In restricted bands, per FCC Part monics at 3 dBm output pow- _14 15.205 / 15.209 er, Conducted measurement, In non-restricted bands, per FCC 3dBm match, Test FrequenPart 15.231 cy = 908.4 MHz -- -49 -42 dBm -- -53 -20 dBc Spurious emissions out-ofSPUROOB_FCC_ band at 3 dBm output power, 14 Conducted measurement, 3dBm match, Test Frequency = 908.4 MHz In non-restricted bands, per FCC Part 15.231 -- -70 -20 dBc In restricted bands (30-88 MHz), per FCC Part 15.205 / 15.209 -- -58 -46 dBm In restricted bands (88-216 MHz), per FCC Part 15.205 / 15.209 -- -70 -56 dBm In restricted bands (216-960 MHz), per FCC Part 15.205 / 15.209 -- -70 -52 dBm In restricted bands (>960 MHz), per FCC Part 15.205 / 15.209 -- -66 -42 dBm PSD per FCC Part 15.247, 9.6Kbps -- -0.7 -- dBm/ 3kHz PSD per FCC Part 15.247, 40Kbps -- 2.3 -- dBm/ 3kHz PSD per FCC Part 15.247, 100Kbps -- -4.1 -- dBm/ 3kHz Output power variation vs RF POUTVAR_F frequency Power spectral density limit PSD Test Condition 4 dBm output power setting Note: 1. If a SAW filter is used, the output power is 2 - 3 dBm lower due to insertion loss. Always adjust the output power to match the limits set by the RF regulatory authorities for the region in which the device is used. silabs.com | Building a more connected world. Rev. 1.0 | 25 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.8.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band Unless otherwise indicated, typical conditions are: T = 25 C, VREGVDD = AVDD = IOVDD = 3.3 V. Crystal frequency = 39 MHz. RF frequency band 915 MHz. Table 4.10. Sub-GHz RF Receiver Characteristics for 915 MHz Band Parameter Symbol Tuning frequency range FRANGE Max usable input level, 1% FER SAT100K Sensitivity2 3 SENS Test Condition Min Typ Max Unit 902 -- 930 MHz Desired is reference 100 kbps GFSK signal1 -- 10 -- dBm Desired is reference 100 kbps GFSK signal1, 1% FER, frequency = 916 MHz, T 85 C -- -97.5 -- dBm Desired is reference 40 kbps 2FSK signal4, 1% FER, frequency = 908.4 MHz, T 85 C -- -101.3 -- dBm Desired is reference 9.6 kbps 2FSK signal5, 1% FER, frequency = 908.42 MHz, T 85 C -- -102.5 -- dBm Level above which RFSENSE will trigger6 RFSENSETRIG CW at 915 MHz -- -28.1 -- dBm Level below which RFSENSE will not trigger6 RFSENSETHRES CW at 915 MHz -- -50 -- dBm Image rejection, Interferer is CW at image frequency C/IIMAGE Desired is 100 kbps GFSK signal1 at 3dB above sensitivity level, 1% FER, frequency = 916 MHz -- 34.7 -- dB Desired is reference 40 kbps 2FSK signal4 at 3dB above sensitivity level, 1% FER, frequency = 908.4 MHz -- 36.2 -- dB Desired is reference 9.6 kbps 2FSK signal5 at 3dB above sensitivity level, 1% FER, frequency = 908.42 MHz -- 36.1 -- dB Interferer CW at Desired 1 MHz -- 48.7 -- dB Interferer CW at Desired 2 MHz -- 54.8 -- dB Interferer CW at Desired 5 MHz -- 64.1 -- dB Interferer CW at Desired 10 MHz7 -- 67.7 -- dB Interferer CW at Desired 100 MHz7 -- 78.8 -- dB Blocking selectivity, 1% FER. C/IBLOCKER_100 Desired is 100 kbps GFSK signal1 at 3dB above sensitivity level, frequency = 916 MHz silabs.com | Building a more connected world. Rev. 1.0 | 26 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Min Typ Max Unit Interferer CW at Desired 1 MHz -- 53.0 -- dB Interferer CW at Desired 2 MHz -- 58.9 -- dB Interferer CW at Desired 5 MHz -- 71.4 -- dB Interferer CW at Desired 10 MHz7 -- 79.2 -- dB Interferer CW at Desired 100 MHz7 -- 82.8 -- dB Interferer CW at Desired 1 MHz -- 54.2 -- dB Interferer CW at Desired 2 MHz -- 62.9 -- dB Interferer CW at Desired 5 MHz -- 72.4 -- dB Interferer CW at Desired 10 MHz7 -- 80.4 -- dB Interferer CW at Desired 100 MHz7 -- 84.0 -- dB Desired is 100 kbps GFSK signal1 at 3dB above sensitivity level, frequency = 916 MHz -- 31.6 -- dB Upper limit of input power RSSIMAX range over which RSSI resolution is maintained -- -- 5 dBm Lower limit of input power RSSIMIN range over which RSSI resolution is maintained -98 -- -- dBm Over RSSIMIN to RSSIMAX range -- 0.25 -- dBm Max spurious emissions dur- SPURRX_FCC ing active receive mode, per FCC Part 15.109(a) 216-960 MHz -- -82.25 -49.2 dBm Above 960 MHz -- -68.41 -41.2 dBm Max spurious emissions dur- SPURRX_ARIB ing active receive mode,per ARIB STD-T108 Section 3.3 Below 710 MHz, RBW=100kHz -- -69.17 -54 dBm 710-900 MHz, RBW=1MHz -- -71.76 -55 dBm 900-915 MHz, RBW=100kHz -- -72.55 -55 dBm 915-930 MHz, RBW=100kHz -- -73.07 -55 dBm 930-1000 MHz, RBW=100kHz -- -72.84 -54 dBm Above 1000 MHz, RBW=1MHz -- -71.49 -47 dBm Blocking selectivity, 1% FER. C/IBLOCKER_40 Desired is 40 kbps 2FSK signal4 at 3dB above sensitivity level, frequency = 908.4 MHz Blocking selectivity, 1% FER. C/IBLOCKER_9p6 Desired is 9.6 kbps 2FSK signal5 at 3dB above sensitivity level, frequency = 908.42 MHz Intermod selectivity, 1% FER. CW interferers at 400 kHz and 800 kHz offsets RSSI resolution C/IIM RSSIRES Test Condition Note: 1. Definition of reference signal is 100 kbps 2GFSK, BT=0.6, f = 58 kHz, NRZ, '0' = F_center + f/2, '1' = F_center - f/2 2. Minimum Packet Error Rate floor will be ~0.5% for desired input signal levels between specified datasheet sensitivity level and -10dBm. 3. Minimum Packet Error Rate floor will be ~ 1% for desired input signal levels > -10dBm. 4. Definition of reference signal is 40 kbps 2FSK, f = 40 kHz, NRZ, '0' = F_center + f/2, '1' = F_center - f/2 5. Definition of reference signal is 9.6 kbps 2FSK, f = 40 kHz, Manchester, '0' = Transition from (F_center + 20k + f/2), '1' = Transition from (F_center + 20k - f/2) 6. RFSENSE performance is only valid from 0 to 85 C. RFSENSE should be disabled outside this temperature range. 7. Minimum Packet Error Rate floor for signals in presecene of blocker will increase above 1% for blocker levels above -30dBm. silabs.com | Building a more connected world. Rev. 1.0 | 27 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.8.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band Unless otherwise indicated, typical conditions are: T = 25 C, VREGVDD = AVDD = IOVDD = 3.3 V. Crystal frequency = 39 MHz. RF frequency band 868 MHz. Table 4.11. Sub-GHz RF Transmitter characteristics for 868 MHz Band Parameter Symbol RF tuning frequency range FRANGE Maximum TX Power1 POUTMAX Minimum active TX Power POUTMIN Output power step size POUTSTEP Output power variation vs supply at POUTMAX Output power variation vs temperature, peak to peak Min Typ Max Unit 863 -- 876 MHz -- 13 -- dBm -- -30 -- dBm output power > 0 dBm -- 0.5 -- dB POUTVAR_V 1.8 V < VVREGVDD < 3.3 V, T = 25 C -- 2.6 -- dB POUTVAR_T -40 to +85 C -- 1.4 -- dB T = 25 C, Over specified RF tuning frequency range -- 0.5 -- dB Output power variation vs RF POUTVAR_F frequency Test Condition 13 dBm output power setting Spurious emissions of harmonics, Conducted measurement, Test Frequency = 868.4 MHz SPURHARM_ETSI Per ETSI EN 300-220, Section 7.8.2.1 -- -39 -30 dBm Spurious emissions out-ofband, Conducted measurement, Test Frequency = 868.4 MHz SPUROOB_ETSI Per ETSI EN 300-220, Section 7.8.2.1 (47-74 MHz, 87.5-118 MHz, 174-230 MHz, and 470-862 MHz) -- -69 -54 dBm Per ETSI EN 300-220, Section 7.8.2.1 (other frequencies below 1 GHz) -- -70 -36 dBm Per ETSI EN 300-220, Section 7.8.2.1 (frequencies above 1 GHz) -- -66 -30 dBm Note: 1. If a SAW filter is used, the output power is 2 - 3 dBm lower due to insertion loss. Always adjust the output power to match the limits set by the RF regulatory authorities for the region in which the device is used. silabs.com | Building a more connected world. Rev. 1.0 | 28 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.8.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band Unless otherwise indicated, typical conditions are: T = 25 C, VREGVDD = AVDD = IOVDD = 3.3 V. Crystal frequency = 39 MHz. RF frequency band 868 MHz. Table 4.12. Sub-GHz RF Receiver Characteristics for 868 MHz Band Parameter Symbol Tuning frequency range FRANGE Max usable input level, 1% FER SAT100k Sensitivity2 3 SENS Test Condition Min Typ Max Unit 863 -- 876 MHz Desired is reference 100 kbps GFSK signal1 -- 10 -- dBm Desired is reference 100 kbps GFSK signal1, 1% FER, frequency = 869.85 MHz, T 85 C -- -97.9 -- dBm Desired is reference 40 kbps 2FSK signal4, 1% FER, frequency = 868.4 MHz, T 85 C -- -101.5 -- dBm Desired is reference 9.6 kbps 2FSK signal5, 1% FER, frequency = 868.42 MHz, T 85 C -- -102.6 -- dBm Level above which RFSENSE will trigger6 RFSENSETRIG CW at 868 MHz -- -28.1 -- dBm Level below which RFSENSE will not trigger6 RFSENSETHRES CW at 868 MHz -- -50 -- dBm Image rejection, Interferer is CW at image frequency C/IIMAGE Desired is 100kbps GFSK signal1 at 3dB above sensitivity level, 1% FER, frequency = 869.85 MHz -- 33.4 -- dB Desired is reference 40 kbps 2FSK signal4 at 3dB above sensitivity level, 1% FER, frequency = 868.4 MHz -- 34.5 -- dB Desired is reference 9.6 kbps 2FSK signal5 at 3dB above sensitivity level, 1% FER, frequency = 868.42 MHz -- 35.3 -- dB Interferer CW at Desired 1 MHz -- 49.6 -- dB Interferer CW at Desired 2 MHz -- 55.6 -- dB Interferer CW at Desired 5 MHz -- 68.1 -- dB Interferer CW at Desired 10 MHz7 -- 75.1 -- dB Interferer CW at Desired 100 MHz7 -- 77.4 -- dB Blocking selectivity, 1% FER. C/IBLOCKER_100 Desired is 100 kbps GFSK signal1 at 3 dB above sensitivity level, frequency = 869.85 MHz silabs.com | Building a more connected world. Rev. 1.0 | 29 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Min Typ Max Unit Interferer CW at Desired 1 MHz -- 53.4 -- dB Interferer CW at Desired 2 MHz -- 59.8 -- dB Interferer CW at Desired 5 MHz -- 71.9 -- dB Interferer CW at Desired 10 MHz7 -- 79.5 -- dB Interferer CW at Desired 100 MHz7 -- 81.1 -- dB Interferer CW at Desired 1 MHz -- 54.8 -- dB Interferer CW at Desired 2 MHz -- 60.7 -- dB Interferer CW at Desired 5 MHz -- 72.8 -- dB Interferer CW at Desired 10 MHz7 -- 80.3 -- dB Interferer CW at Desired 100 MHz7 -- 82.1 -- dB Upper limit of input power RSSIMAX range over which RSSI resolution is maintained -- -- 5 dBm Lower limit of input power RSSIMIN range over which RSSI resolution is maintained -98 -- -- dBm Over RSSIMIN to RSSIMAX range -- 0.25 -- dBm 30 MHz to 1 GHz -- -67.46 -57 dBm 1 GHz to 12 GHz -- -69.7 -47 dBm Blocking selectivity, 1% FER. C/IBLOCKER_40 Desired is 40 kbps 2FSK signal4 at 3 dB above sensitivity level, frequency = 868.4 MHz Blocking selectivity, 1% FER. C/IBLOCKER_9p6 Desired is 9.6 kbps 2FSK signal5 at 3 dB above sensitivity level, frequency = 868.42 MHz RSSI resolution RSSIRES Max spurious emissions dur- SPURRX ing active receive mode Test Condition Note: 1. Definition of reference signal is 100 kbps 2GFSK, BT=0.6, f = 58 kHz, NRZ, '0' = F_center + f/2, '1' = F_center - f/2 2. Minimum Packet Error Rate floor will be ~0.5% for desired input signal levels between specified datasheet sensitivity level and -10dBm. 3. Minimum Packet Error Rate floor will be ~ 1% for desired input signal levels > -10dBm. 4. Definition of reference signal is 40 kbps 2FSK, f = 40 kHz, NRZ, '0' = F_center + f/2, '1' = F_center - f/2 5. Definition of reference signal is 9.6 kbps 2FSK, f = 40 kHz, Manchester, '0' = Transition from (F_center + 20k + f/2), '1' = Transition from (F_center + 20k - f/2) 6. RFSENSE performance is only valid from 0 to 85 C. RFSENSE should be disabled outside this temperature range. 7. Minimum Packet Error Rate floor for signals in presecene of blocker will increase above 1% for blocker levels above -30dBm. silabs.com | Building a more connected world. Rev. 1.0 | 30 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.9 Oscillators 4.1.9.1 High-Frequency Crystal Oscillator (HFXO) Internal crystal = TXC P/N 8Y39072002 Table 4.13. High-Frequency Crystal Oscillator (HFXO) Parameter Symbol Test Condition Min Typ Max Unit Crystal frequency fHFXO 39 MHz required for radio transciever operation -- 39 -- MHz Calibrated precision PRECHFXO -2 -- 2 ppm 5-year aging AGINGHFXO -3 -- 3 ppm Temperature drift DRIFTHFXO -13 -- 13 ppm -40 C to 85 C 4.1.9.2 Low-Frequency RC Oscillator (LFRCO) Table 4.14. Low-Frequency RC Oscillator (LFRCO) Parameter Symbol Test Condition Min Typ Max Unit Oscillation frequency fLFRCO ENVREF1 = 1 31.3 32.768 33.6 kHz ENVREF1 = 0 31.3 32.768 33.4 kHz -- 500 -- s ENVREF = 1 in CMU_LFRCOCTRL -- 342 -- nA ENVREF = 0 in CMU_LFRCOCTRL -- 494 -- nA Startup time tLFRCO Current consumption 2 ILFRCO Note: 1. In CMU_LFRCOCTRL register. 2. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register. silabs.com | Building a more connected world. Rev. 1.0 | 31 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.9.3 High-Frequency RC Oscillator (HFRCO) Table 4.15. High-Frequency RC Oscillator (HFRCO) Parameter Symbol Test Condition Min Typ Max Unit Frequency accuracy fHFRCO_ACC At production calibrated frequencies, across supply voltage and temperature -2.5 -- 2.5 % Start-up time tHFRCO fHFRCO 19 MHz -- 300 -- ns 4 < fHFRCO < 19 MHz -- 1 -- s fHFRCO 4 MHz -- 2.5 -- s fHFRCO = 38 MHz -- 267 299 A fHFRCO = 32 MHz -- 224 248 A fHFRCO = 26 MHz -- 189 211 A fHFRCO = 19 MHz -- 154 172 A fHFRCO = 16 MHz -- 133 148 A fHFRCO = 13 MHz -- 118 135 A fHFRCO = 7 MHz -- 89 100 A fHFRCO = 4 MHz -- 34 44 A fHFRCO = 2 MHz -- 29 40 A fHFRCO = 1 MHz -- 26 36 A -- 0.8 -- % Current consumption on all supplies IHFRCO Coarse trim step size (% of period) SSHFRCO_COARS Fine trim step size (% of period) SSHFRCO_FINE -- 0.1 -- % Period jitter PJHFRCO -- 0.2 -- % RMS Frequency limits fHFRCO_BAND FREQRANGE = 0, FINETUNINGEN = 0 3.47 -- 6.15 MHz FREQRANGE = 3, FINETUNINGEN = 0 6.24 -- 11.45 MHz FREQRANGE = 6, FINETUNINGEN = 0 11.3 -- 19.8 MHz FREQRANGE = 7, FINETUNINGEN = 0 13.45 -- 22.8 MHz FREQRANGE = 8, FINETUNINGEN = 0 16.5 -- 29.0 MHz FREQRANGE = 10, FINETUNINGEN = 0 23.11 -- 40.63 MHz FREQRANGE = 11, FINETUNINGEN = 0 27.27 -- 48 MHz FREQRANGE = 12, FINETUNINGEN = 0 33.33 -- 54 MHz E silabs.com | Building a more connected world. Rev. 1.0 | 32 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.9.4 Ultra-low Frequency RC Oscillator (ULFRCO) Table 4.16. Ultra-low Frequency RC Oscillator (ULFRCO) Parameter Symbol Oscillation frequency fULFRCO Test Condition Min Typ Max Unit 0.95 1 1.07 kHz Min Typ Max Unit 10000 -- -- cycles 10 -- -- years Burst write, 128 words, average time per word 20 26.3 30 s Single word 62 68.9 80 s 4.1.10 Flash Memory Characteristics1 Table 4.17. Flash Memory Characteristics1 Parameter Symbol Flash erase cycles before failure ECFLASH Flash data retention RETFLASH Word (32-bit) programming time tW_PROG Test Condition Page erase time2 tPERASE 20 29.5 40 ms Mass erase time3 tMERASE 20 30 40 ms Device erase time4 5 tDERASE -- 56.2 70 ms Erase current6 IERASE -- -- 2.0 mA Write current6 IWRITE -- -- 3.5 mA Supply voltage during flash erase and write VFLASH 1.62 -- 3.6 V Page Erase Note: 1. Flash data retention information is published in the Quarterly Quality and Reliability Report. 2. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup and hold times for flash control signals are included. 3. Mass erase is issued by the CPU and erases all flash. 4. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock Word (ULW). 5. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup and hold times for flash control signals are included. 6. Measured at 25 C. silabs.com | Building a more connected world. Rev. 1.0 | 33 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.11 General-Purpose I/O (GPIO) Table 4.18. General-Purpose I/O (GPIO) Parameter Symbol Test Condition Min Typ Max Unit Input low voltage1 VIL GPIO pins -- -- IOVDD*0.3 V Input high voltage1 VIH GPIO pins IOVDD*0.7 -- -- V Output high voltage relative to IOVDD VOH Sourcing 3 mA, IOVDD 3 V, IOVDD*0.8 -- -- V IOVDD*0.6 -- -- V IOVDD*0.8 -- -- V IOVDD*0.6 -- -- V -- -- IOVDD*0.2 V -- -- IOVDD*0.4 V -- -- IOVDD*0.2 V -- -- IOVDD*0.4 V All GPIO pins except PB14 and PB15, GPIO IOVDD -- 0.1 30 nA PB14 and PB15, GPIO IOVDD -- 0.1 50 nA IOVDD < GPIO IOVDD + 2 V -- 3.3 15 A 30 40 65 k 15 25 45 ns DRIVESTRENGTH2 = WEAK Sourcing 1.2 mA, IOVDD 1.62 V, DRIVESTRENGTH2 = WEAK Sourcing 20 mA, IOVDD 3 V, DRIVESTRENGTH2 = STRONG Sourcing 8 mA, IOVDD 1.62 V, DRIVESTRENGTH2 = STRONG Output low voltage relative to VOL IOVDD Sinking 3 mA, IOVDD 3 V, DRIVESTRENGTH2 = WEAK Sinking 1.2 mA, IOVDD 1.62 V, DRIVESTRENGTH2 = WEAK Sinking 20 mA, IOVDD 3 V, DRIVESTRENGTH2 = STRONG Sinking 8 mA, IOVDD 1.62 V, DRIVESTRENGTH2 = STRONG Input leakage current IIOLEAK Input leakage current on 5VTOL pads above IOVDD I5VTOLLEAK I/O pin pull-up/pull-down resistor3 RPUD Pulse width of pulses retIOGLITCH moved by the glitch suppression filter silabs.com | Building a more connected world. Rev. 1.0 | 34 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Output fall time, From 70% to 30% of VIO tIOOF CL = 50 pF, Min Typ Max Unit -- 1.8 -- ns -- 4.5 -- ns -- 2.2 -- ns -- 7.4 -- ns DRIVESTRENGTH2 = STRONG, SLEWRATE2 = 0x6 CL = 50 pF, DRIVESTRENGTH2 = WEAK, SLEWRATE2 = 0x6 Output rise time, From 30% to 70% of VIO tIOOR CL = 50 pF, DRIVESTRENGTH2 = STRONG, SLEWRATE = 0x62 CL = 50 pF, DRIVESTRENGTH2 = WEAK, SLEWRATE2 = 0x6 Note: 1. GPIO input threshold are proportional to the IOVDD supply, except for RESETn which is proportional to AVDD. 2. In GPIO_Pn_CTRL register. 3. GPIO pull-ups are referenced to the IOVDD supply, except for RESETn, which connects to AVDD. silabs.com | Building a more connected world. Rev. 1.0 | 35 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.12 Voltage Monitor (VMON) Table 4.19. Voltage Monitor (VMON) Parameter Symbol Test Condition Supply current (including I_SENSE) IVMON Loading of monitored supply ISENSE Threshold range VVMON_RANGE Threshold step size NVMON_STESP Response time tVMON_RES Hysteresis VVMON_HYST silabs.com | Building a more connected world. Min Typ Max Unit In EM0 or EM1, 1 active channel -- 6.3 8 A In EM0 or EM1, All channels active -- 12.5 15 A In EM2, EM3 or EM4, 1 channel active and above threshold -- 62 -- nA In EM2, EM3 or EM4, 1 channel active and below threshold -- 62 -- nA In EM2, EM3 or EM4, All channels active and above threshold -- 99 -- nA In EM2, EM3 or EM4, All channels active and below threshold -- 99 -- nA In EM0 or EM1 -- 2 -- A In EM2, EM3 or EM4 -- 2 -- nA 1.62 -- 3.4 V Coarse -- 200 -- mV Fine -- 20 -- mV Supply drops at 1V/s rate -- 460 -- ns -- 26 -- mV Rev. 1.0 | 36 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.13 Analog to Digital Converter (ADC) Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated. Table 4.20. Analog to Digital Converter (ADC) Parameter Symbol Resolution VRESOLUTION Input voltage range1 VADCIN Test Condition Single ended Differential Input range of external refer- VADCREFIN_P ence voltage, single ended and differential Min Typ Max Unit 6 -- 12 Bits -- -- VFS V -VFS/2 -- VFS/2 V 1 -- VAVDD V Power supply rejection2 PSRRADC At DC -- 80 -- dB Analog input common mode rejection ratio CMRRADC At DC -- 80 -- dB 1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4 -- 270 290 A 250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 1 4 -- 125 -- A 62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 1 4 -- 80 -- A Current from all supplies, us- IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer. SPROG = 0, GPBIASACC = 1 4 Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL SPROG = 0, GPBIASACC = 1 4 -- 45 -- A -- 8 -- A Current from all supplies, us- IADC_STANDing internal reference buffer. BY_LP Duty-cycled operation. AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC 125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4 -- 105 -- A 35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 1 4 -- 70 -- A 1 Msps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4 -- 325 -- A 250 ksps / 4 MHz ADCCLK, BIASPROG = 6, GPBIASACC = 0 4 -- 175 -- A 62.5 ksps / 1 MHz ADCCLK, BIASPROG = 15, GPBIASACC = 0 4 -- 125 -- A Current from all supplies, us- IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIAing internal reference buffer. SPROG = 0, GPBIASACC = 0 4 Duty-cycled operation. WAR5 ksps / 16 MHz ADCCLK BIAMUPMODE3 = NORMAL SPROG = 0, GPBIASACC = 0 4 -- 85 -- A -- 16 -- A Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_LP Continuous operation. WARMUPMODE3 = KEEPADCWARM Current from all supplies, us- IADC_CONTINUing internal reference buffer. OUS_HP Continuous operation. WARMUPMODE3 = KEEPADCWARM Current from all supplies, us- IADC_STANDing internal reference buffer. BY_HP Duty-cycled operation. AWARMUPMODE3 = KEEPINSTANDBY or KEEPINSLOWACC 125 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4 -- 160 -- A 35 ksps / 16 MHz ADCCLK, BIASPROG = 0, GPBIASACC = 0 4 -- 125 -- A Current from HFPERCLK HFPERCLK = 16 MHz -- 140 -- A IADC_CLK silabs.com | Building a more connected world. Rev. 1.0 | 37 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol ADC clock frequency Min Typ Max Unit fADCCLK -- -- 16 MHz Throughput rate fADCRATE -- -- 1 Msps Conversion time5 tADCCONV 6 bit -- 7 -- cycles 8 bit -- 9 -- cycles 12 bit -- 13 -- cycles WARMUPMODE3 = NORMAL -- -- 5 s WARMUPMODE3 = KEEPINSTANDBY -- -- 2 s WARMUPMODE3 = KEEPINSLOWACC -- -- 1 s Internal reference6, differential measurement 58 67 -- dB External reference7, differential measurement -- 68 -- dB Spurious-free dynamic range SFDRADC (SFDR) 1 MSamples/s, 10 kHz full-scale sine wave -- 75 -- dB Differential non-linearity (DNL) DNLADC 12 bit resolution, No missing codes -1 -- 2 LSB Integral non-linearity (INL), End point method INLADC 12 bit resolution -6 -- 6 LSB Offset error VADCOFFSETERR -3 0 3 LSB Gain error in ADC VADCGAIN Using internal reference -- -0.2 3.5 % Using external reference -- -1 -- % -- -1.84 -- mV/C Startup time of reference generator and ADC core SNDR at 1Msps and fIN = 10kHz Temperature sensor slope tADCSTART SNDRADC VTS_SLOPE Test Condition Note: 1. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin. 2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL. 3. In ADCn_CTRL register. 4. In ADCn_BIASPROG register. 5. Derived from ADCCLK. 6. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The differential input range with this configuration is 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum value is production-tested using sine wave input at 1.5 dB lower than full scale. 7. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential input range with this configuration is 1.25 V. silabs.com | Building a more connected world. Rev. 1.0 | 38 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.14 Analog Comparator (ACMP) Table 4.21. Analog Comparator (ACMP) Parameter Symbol Test Condition Input voltage range VACMPIN Supply voltage VACMPVDD Active current not including voltage reference3 IACMP Current consumption of inter- IACMPREF nal voltage reference3 silabs.com | Building a more connected world. Min Typ Max Unit ACMPVDD = ACMPn_CTRL_PWRSEL 1 -- -- VACMPVDD V BIASPROG2 0x10 or FULLBIAS2 = 0 1.8 -- VVREGVDD_ V 0x10 < BIASPROG2 0x20 and FULLBIAS2 = 1 2.1 BIASPROG2 = 1, FULLBIAS2 = 0 -- 50 -- nA BIASPROG2 = 0x10, FULLBIAS2 =0 -- 306 -- nA BIASPROG2 = 0x02, FULLBIAS2 =1 -- 6.1 11 A BIASPROG2 = 0x20, FULLBIAS2 =1 -- 74 92 A VLP selected as input using 2.5 V Reference / 4 (0.625 V) -- 50 -- nA VLP selected as input using VDD -- 20 -- nA VBDIV selected as input using 1.25 V reference / 1 -- 4.1 -- A VADIV selected as input using VDD/1 -- 2.4 -- A MAX -- VVREGVDD_ V MAX Rev. 1.0 | 39 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Hysteresis (VCM = 1.25 V, BIASPROG2 = 0x10, FULLBIAS2 = 1) VACMPHYST Comparator delay5 tACMPDELAY Min Typ Max Unit HYSTSEL4 = HYST0 -3 0 3 mV HYSTSEL4 = HYST1 5 18 27 mV HYSTSEL4 = HYST2 12 33 50 mV HYSTSEL4 = HYST3 17 46 67 mV HYSTSEL4 = HYST4 23 57 86 mV HYSTSEL4 = HYST5 26 68 104 mV HYSTSEL4 = HYST6 30 79 130 mV HYSTSEL4 = HYST7 34 90 155 mV HYSTSEL4 = HYST8 -3 0 3 mV HYSTSEL4 = HYST9 -27 -18 -5 mV HYSTSEL4 = HYST10 -50 -33 -12 mV HYSTSEL4 = HYST11 -67 -45 -17 mV HYSTSEL4 = HYST12 -86 -57 -23 mV HYSTSEL4 = HYST13 -104 -67 -26 mV HYSTSEL4 = HYST14 -130 -78 -30 mV HYSTSEL4 = HYST15 -155 -88 -34 mV BIASPROG2 = 1, FULLBIAS2 = 0 -- 30 95 s BIASPROG2 = 0x10, FULLBIAS2 =0 -- 3.7 10 s BIASPROG2 = 0x02, FULLBIAS2 =1 -- 360 1000 ns BIASPROG2 = 0x20, FULLBIAS2 =1 -- 35 -- ns -35 -- 35 mV Offset voltage VACMPOFFSET BIASPROG2 =0x10, FULLBIAS2 =1 Reference voltage VACMPREF Internal 1.25 V reference 1 1.25 1.47 V Internal 2.5 V reference 1.98 2.5 2.8 V CSRESSEL6 = 0 -- infinite -- k CSRESSEL6 = 1 -- 15 -- k CSRESSEL6 = 2 -- 27 -- k CSRESSEL6 = 3 -- 39 -- k CSRESSEL6 = 4 -- 51 -- k CSRESSEL6 = 5 -- 102 -- k CSRESSEL6 = 6 -- 164 -- k CSRESSEL6 = 7 -- 239 -- k Capacitive sense internal re- RCSRES sistance silabs.com | Building a more connected world. Rev. 1.0 | 40 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Note: 1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD. 2. In ACMPn_CTRL register. 3. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP + IACMPREF. 4. In ACMPn_HYSTERESIS registers. 5. 100 mV differential drive. 6. In ACMPn_INPUTSEL register. silabs.com | Building a more connected world. Rev. 1.0 | 41 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.15 Digital to Analog Converter (VDAC) DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output. Table 4.22. Digital to Analog Converter (VDAC) Parameter Symbol Test Condition Min Typ Max Unit Output voltage VDACOUT Single-Ended 0 -- VVREF V -VVREF -- VVREF V 500 ksps, 12-bit, DRIVESTRENGTH = 2, REFSEL = 4 -- 396 -- A 44.1 ksps, 12-bit, DRIVESTRENGTH = 1, REFSEL = 4 -- 72 -- A 200 Hz refresh rate, 12-bit Sample-Off mode in EM2, DRIVESTRENGTH = 2, REFSEL = 4, SETTLETIME = 0x02, WARMUPTIME = 0x0A -- 1.2 -- A Differential1 Current consumption including references (2 channels)2 IDAC Current from HFPERCLK3 IDAC_CLK -- 5.8 -- A/MHz Sample rate SRDAC -- -- 500 ksps DAC clock frequency fDAC -- -- 1 MHz Conversion time tDACCONV fDAC = 1MHz 2 -- -- s Settling time tDACSETTLE 50% fs step settling to 5 LSB -- 2.5 -- s Startup time tDACSTARTUP Enable to 90% fs output, settling to 10 LSB -- -- 12 s Output impedance ROUT DRIVESTRENGTH = 2, 0.4 V VOUT VOPA - 0.4 V, -8 mA < IOUT < 8 mA, Full supply range -- 2 -- DRIVESTRENGTH = 0 or 1, 0.4 V VOUT VOPA - 0.4 V, -400 A < IOUT < 400 A, Full supply range -- 2 -- DRIVESTRENGTH = 2, 0.1 V VOUT VOPA - 0.1 V, -2 mA < IOUT < 2 mA, Full supply range -- 2 -- DRIVESTRENGTH = 0 or 1, 0.1 V VOUT VOPA - 0.1 V, -100 A < IOUT < 100 A, Full supply range -- 2 -- Vout = 50% fs. DC -- 65.5 -- dB Power supply rejection ratio4 PSRR silabs.com | Building a more connected world. Rev. 1.0 | 42 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Min Typ Max Unit 500 ksps, single-ended, internal 1.25V reference -- 60.4 -- dB 500 ksps, single-ended, internal 2.5V reference -- 61.6 -- dB 500 ksps, single-ended, 3.3V VDD reference -- 64.0 -- dB 500 ksps, differential, internal 1.25V reference -- 63.3 -- dB 500 ksps, differential, internal 2.5V reference -- 64.4 -- dB 500 ksps, differential, 3.3V VDD reference -- 65.8 -- dB Signal to noise and distortion SNDRDAC_BAND 500 ksps, single-ended, internal 1.25V reference ratio (1 kHz sine wave), Noise band limited to 22 kHz 500 ksps, single-ended, internal 2.5V reference -- 65.3 -- dB -- 66.7 -- dB 500 ksps, single-ended, 3.3V VDD reference -- 70.0 -- dB 500 ksps, differential, internal 1.25V reference -- 67.8 -- dB 500 ksps, differential, internal 2.5V reference -- 69.0 -- dB 500 ksps, differential, 3.3V VDD reference -- 68.5 -- dB -- 70.2 -- dB Signal to noise and distortion SNDRDAC ratio (1 kHz sine wave), Noise band limited to 250 kHz Test Condition Total harmonic distortion THD Differential non-linearity5 DNLDAC -0.99 -- 1 LSB Intergral non-linearity INLDAC -4 -- 4 LSB Offset error6 VOFFSET T = 25 C -8 -- 8 mV Across operating temperature range -25 -- 25 mV T = 25 C, Low-noise internal reference (REFSEL = 1V25LN or 2V5LN) -2.5 -- 2.5 % T = 25 C, Internal reference (REFSEL = 1V25 or 2V5) -5 -- 5 % T = 25 C, External reference (REFSEL = VDD or EXT) -1.8 -- 1.8 % Across operating temperature range, Low-noise internal reference (REFSEL = 1V25LN or 2V5LN) -3.5 -- 3.5 % Across operating temperature range, Internal reference (REFSEL = 1V25 or 2V5) -7.5 -- 7.5 % Across operating temperature range, External reference (REFSEL = VDD or EXT) -2.0 -- 2.0 % Gain error6 VGAIN silabs.com | Building a more connected world. Rev. 1.0 | 43 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol External load capactiance, OUTSCALE=0 CLOAD Test Condition Min Typ Max Unit -- -- 75 pF Note: 1. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is limited to the single-ended range. 2. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive the load. 3. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when the clock to the DAC peripheral is enabled in the CMU. 4. PSRR calculated as 20 * log10(VDD / VOUT), VDAC output at 90% of full scale 5. Entire range is monotonic and has no missing codes. 6. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at 10% of full scale to ideal VDAC output at 10% of full scale with the measured gain. silabs.com | Building a more connected world. Rev. 1.0 | 44 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.16 Current Digital to Analog Converter (IDAC) Table 4.23. Current Digital to Analog Converter (IDAC) Parameter Symbol Number of ranges NIDAC_RANGES Output current IIDAC_OUT Linear steps within each range NIDAC_STEPS Step size SSIDAC Total accuracy, STEPSEL1 = ACCIDAC 0x10 silabs.com | Building a more connected world. Test Condition Min Typ Max Unit -- 4 -- ranges RANGESEL1 = RANGE0 0.05 -- 1.6 A RANGESEL1 = RANGE1 1.6 -- 4.7 A RANGESEL1 = RANGE2 0.5 -- 16 A RANGESEL1 = RANGE3 2 -- 64 A -- 32 -- steps RANGESEL1 = RANGE0 -- 50 -- nA RANGESEL1 = RANGE1 -- 100 -- nA RANGESEL1 = RANGE2 -- 500 -- nA RANGESEL1 = RANGE3 -- 2 -- A EM0 or EM1, AVDD=3.3 V, T = 25 C -3 -- 3 % EM0 or EM1, Across operating temperature range -18 -- 22 % EM2 or EM3, Source mode, RANGESEL1 = RANGE0, AVDD=3.3 V, T = 25 C -- -2 -- % EM2 or EM3, Source mode, RANGESEL1 = RANGE1, AVDD=3.3 V, T = 25 C -- -1.7 -- % EM2 or EM3, Source mode, RANGESEL1 = RANGE2, AVDD=3.3 V, T = 25 C -- -0.8 -- % EM2 or EM3, Source mode, RANGESEL1 = RANGE3, AVDD=3.3 V, T = 25 C -- -0.5 -- % EM2 or EM3, Sink mode, RANGESEL1 = RANGE0, AVDD=3.3 V, T = 25 C -- -0.7 -- % EM2 or EM3, Sink mode, RANGESEL1 = RANGE1, AVDD=3.3 V, T = 25 C -- -0.6 -- % EM2 or EM3, Sink mode, RANGESEL1 = RANGE2, AVDD=3.3 V, T = 25 C -- -0.5 -- % EM2 or EM3, Sink mode, RANGESEL1 = RANGE3, AVDD=3.3 V, T = 25 C -- -0.5 -- % Rev. 1.0 | 45 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Start up time tIDAC_SU Settling time, (output settled tIDAC_SETTLE within 1% of steady state value), Current consumption2 IIDAC Output voltage compliance in ICOMP_SRC source mode, source current change relative to current sourced at 0 V Output voltage compliance in ICOMP_SINK sink mode, sink current change relative to current sunk at IOVDD Min Typ Max Unit Output within 1% of steady state value -- 5 -- s Range setting is changed -- 5 -- s Step value is changed -- 1 -- s EM0 or EM1 Source mode, excluding output current, Across operating temperature range -- 11 15 A EM0 or EM1 Sink mode, excluding output current, Across operating temperature range -- 13 18 A EM2 or EM3 Source mode, excluding output current, T = 25 C -- 0.023 -- A EM2 or EM3 Sink mode, excluding output current, T = 25 C -- 0.041 -- A EM2 or EM3 Source mode, excluding output current, T 85 C -- 11 -- A EM2 or EM3 Sink mode, excluding output current, T 85 C -- 13 -- A RANGESEL1 = RANGE0, output voltage = min(VIOVDD, VAVDD2-100 mV) -- 0.11 -- % RANGESEL1 = RANGE1, output voltage = min(VIOVDD, VAVDD2-100 mV) -- 0.06 -- % RANGESEL1 = RANGE2, output voltage = min(VIOVDD, VAVDD2-150 mV) -- 0.04 -- % RANGESEL1 = RANGE3, output voltage = min(VIOVDD, VAVDD2-250 mV) -- 0.03 -- % RANGESEL1 = RANGE0, output voltage = 100 mV -- 0.12 -- % RANGESEL1 = RANGE1, output voltage = 100 mV -- 0.05 -- % RANGESEL1 = RANGE2, output voltage = 150 mV -- 0.04 -- % RANGESEL1 = RANGE3, output voltage = 250 mV -- 0.03 -- % Note: 1. In IDAC_CURPROG register. 2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects between AVDD (0) and DVDD (1). silabs.com | Building a more connected world. Rev. 1.0 | 46 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.17 Capacitive Sense (CSEN) Table 4.24. Capacitive Sense (CSEN) Parameter Symbol Test Condition Single conversion time (1x accumulation) tCNV Maximum external capacitive CEXTMAX load Min Typ Max Unit 12-bit SAR Conversions -- 20.2 -- s 16-bit SAR Conversions -- 26.4 -- s Delta Modulation Conversion (single comparison) -- 1.55 -- s IREFPROG=7 (Gain = 1x), including routing parasitics -- 68 -- pF IREFPROG=0 (Gain = 10x), including routing parasitics -- 680 -- pF -- 1 -- k 12-bit SAR conversions, 20 ms conversion rate, IREFPROG=7 (Gain = 1x), 10 channels bonded (total capacitance of 330 pF)1 -- 326 -- nA Delta Modulation conversions, 20 ms conversion rate, IREFPROG=7 (Gain = 1x), 10 channels bonded (total capacitance of 330 pF)1 -- 226 -- nA 12-bit SAR conversions, 200 ms conversion rate, IREFPROG=7 (Gain = 1x), 10 channels bonded (total capacitance of 330 pF)1 -- 33 -- nA Delta Modulation conversions, 200 ms conversion rate, IREFPROG=7 (Gain = 1x), 10 channels bonded (total capacitance of 330 pF)1 -- 25 -- nA 12-bit SAR conversions, 20 ms scan rate, IREFPROG=0 (Gain = 10x), 8 samples per scan1 -- 690 -- nA Delta Modulation conversions, 20 ms scan rate, 8 comparisons per sample (DMCR = 1, DMR = 2), IREFPROG=0 (Gain = 10x), 8 samples per scan1 -- 515 -- nA 12-bit SAR conversions, 200 ms scan rate, IREFPROG=0 (Gain = 10x), 8 samples per scan1 -- 79 -- nA Delta Modulation conversions, 200 ms scan rate, 8 comparisons per sample (DMCR = 1, DMR = 2), IREFPROG=0 (Gain = 10x), 8 samples per scan1 -- 57 -- nA Maximum external series im- REXTMAX pedance Supply current, EM2 bonded ICSEN_BOND conversions, WARMUPMODE=NORMAL, WARMUPCNT=0 Supply current, EM2 scan conversions, WARMUPMODE=NORMAL, WARMUPCNT=0 ICSEN_EM2 silabs.com | Building a more connected world. Rev. 1.0 | 47 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Supply current, continuous conversions, WARMUPMODE=KEEPCSENWARM ICSEN_ACTIVE SAR or Delta Modulation conversions of 33 pF capacitor, IREFPROG=0 (Gain = 10x), always on -- 90.5 -- A HFPERCLK supply current ICSEN_HFPERCLK Current contribution from HFPERCLK when clock to CSEN block is enabled. -- 2.25 -- A/MHz Note: 1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the peripheral is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a specific application can be estimated by multiplying the current per sample by the total number of samples per period (total_current = single_sample_current * (number_of_channels * accumulation)). silabs.com | Building a more connected world. Rev. 1.0 | 48 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.18 Operational Amplifier (OPAMP) Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAINOUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as specified in table footnotes1 2. Table 4.25. Operational Amplifier (OPAMP) Parameter Symbol Test Condition Supply voltage (from AVDD) VOPA HCMDIS = 0, Rail-to-rail input range Input voltage VIN Min Typ Max Unit 2 -- 3.8 V HCMDIS = 1 1.62 -- 3.8 V HCMDIS = 0, Rail-to-rail input range VVSS -- VOPA V HCMDIS = 1 VVSS -- VOPA-1.2 V Input impedance RIN 100 -- -- M Output voltage VOUT VVSS -- VOPA V Load capacitance3 CLOAD OUTSCALE = 0 -- -- 75 pF OUTSCALE = 1 -- -- 37.5 pF DRIVESTRENGTH = 2 or 3, 0.4 V VOUT VOPA - 0.4 V, -8 mA < IOUT < 8 mA, Buffer connection, Full supply range -- 0.25 -- DRIVESTRENGTH = 0 or 1, 0.4 V VOUT VOPA - 0.4 V, -400 A < IOUT < 400 A, Buffer connection, Full supply range -- 0.6 -- DRIVESTRENGTH = 2 or 3, 0.1 V VOUT VOPA - 0.1 V, -2 mA < IOUT < 2 mA, Buffer connection, Full supply range -- 0.4 -- DRIVESTRENGTH = 0 or 1, 0.1 V VOUT VOPA - 0.1 V, -100 A < IOUT < 100 A, Buffer connection, Full supply range -- 1 -- Buffer connection 0.99 1 1.01 - 3x Gain connection 2.93 2.99 3.05 - 16x Gain connection 15.07 15.7 16.33 - DRIVESTRENGTH = 3, OUTSCALE = 0 -- 580 -- A DRIVESTRENGTH = 2, OUTSCALE = 0 -- 176 -- A DRIVESTRENGTH = 1, OUTSCALE = 0 -- 13 -- A DRIVESTRENGTH = 0, OUTSCALE = 0 -- 4.7 -- A Output impedance Internal closed-loop gain Active current4 ROUT GCL IOPA silabs.com | Building a more connected world. Rev. 1.0 | 49 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Open-loop gain GOL Loop unit-gain frequency5 Phase margin Output voltage noise UGF PM NOUT silabs.com | Building a more connected world. Min Typ Max Unit DRIVESTRENGTH = 3 -- 135 -- dB DRIVESTRENGTH = 2 -- 137 -- dB DRIVESTRENGTH = 1 -- 121 -- dB DRIVESTRENGTH = 0 -- 109 -- dB DRIVESTRENGTH = 3, Buffer connection -- 3.38 -- MHz DRIVESTRENGTH = 2, Buffer connection -- 0.9 -- MHz DRIVESTRENGTH = 1, Buffer connection -- 132 -- kHz DRIVESTRENGTH = 0, Buffer connection -- 34 -- kHz DRIVESTRENGTH = 3, 3x Gain connection -- 2.57 -- MHz DRIVESTRENGTH = 2, 3x Gain connection -- 0.71 -- MHz DRIVESTRENGTH = 1, 3x Gain connection -- 113 -- kHz DRIVESTRENGTH = 0, 3x Gain connection -- 28 -- kHz DRIVESTRENGTH = 3, Buffer connection -- 67 -- DRIVESTRENGTH = 2, Buffer connection -- 69 -- DRIVESTRENGTH = 1, Buffer connection -- 63 -- DRIVESTRENGTH = 0, Buffer connection -- 68 -- DRIVESTRENGTH = 3, Buffer connection, 10 Hz - 10 MHz -- 146 -- Vrms DRIVESTRENGTH = 2, Buffer connection, 10 Hz - 10 MHz -- 163 -- Vrms DRIVESTRENGTH = 1, Buffer connection, 10 Hz - 1 MHz -- 170 -- Vrms DRIVESTRENGTH = 0, Buffer connection, 10 Hz - 1 MHz -- 176 -- Vrms DRIVESTRENGTH = 3, 3x Gain connection, 10 Hz - 10 MHz -- 313 -- Vrms DRIVESTRENGTH = 2, 3x Gain connection, 10 Hz - 10 MHz -- 271 -- Vrms DRIVESTRENGTH = 1, 3x Gain connection, 10 Hz - 1 MHz -- 247 -- Vrms DRIVESTRENGTH = 0, 3x Gain connection, 10 Hz - 1 MHz -- 245 -- Vrms Rev. 1.0 | 50 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Slew rate6 SR DRIVESTRENGTH = 3, INCBW=17 -- 4.7 -- V/s DRIVESTRENGTH = 3, INCBW=0 -- 1.5 -- V/s DRIVESTRENGTH = 2, INCBW=17 -- 1.27 -- V/s DRIVESTRENGTH = 2, INCBW=0 -- 0.42 -- V/s DRIVESTRENGTH = 1, INCBW=17 -- 0.17 -- V/s DRIVESTRENGTH = 1, INCBW=0 -- 0.058 -- V/s DRIVESTRENGTH = 0, INCBW=17 -- 0.044 -- V/s DRIVESTRENGTH = 0, INCBW=0 -- 0.015 -- V/s Startup time8 TSTART DRIVESTRENGTH = 2 -- -- 12 s Input offset voltage VOSI DRIVESTRENGTH = 2 or 3, T = 25 C -2 -- 2 mV DRIVESTRENGTH = 1 or 0, T = 25 C -2 -- 2 mV DRIVESTRENGTH = 2 or 3, across operating temperature range -12 -- 12 mV DRIVESTRENGTH = 1 or 0, across operating temperature range -45 -- 30 mV DC power supply rejection ratio9 PSRRDC Input referred -- 70 -- dB DC common-mode rejection ratio9 CMRRDC Input referred -- 70 -- dB Total harmonic distortion THDOPA DRIVESTRENGTH = 2, 3x Gain connection, 1 kHz, VOUT = 0.1 V to VOPA - 0.1 V -- 90 -- dB DRIVESTRENGTH = 0, 3x Gain connection, 0.1 kHz, VOUT = 0.1 V to VOPA - 0.1 V -- 90 -- dB silabs.com | Building a more connected world. Rev. 1.0 | 51 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Note: 1. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V, VOUTPUT = 0.5 V. 2. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5 V. Nominal voltage gain is 3. 3. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information. 4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause another ~10 A current when the OPAMP drives 1.5 V between output and ground. 5. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth product of the OPAMP and 1/3 attenuation of the feedback network. 6. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range. 7. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is 3, or the OPAMP may not be stable. 8. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV. 9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR and CMRR specifications do not apply to this transition region. 4.1.19 Pulse Counter (PCNT) Table 4.26. Pulse Counter (PCNT) Parameter Symbol Test Condition Min Typ Max Unit Input frequency FIN Asynchronous Single and Quadrature Modes -- -- 10 MHz Sampled Modes with Debounce filter set to 0. -- -- 8 kHz Min Typ Max Unit 4.1.20 Analog Port (APORT) Table 4.27. Analog Port (APORT) Parameter Symbol Test Condition Supply current1 2 IAPORT Operation in EM0/EM1 -- 7 -- A Operation in EM2/EM3 -- 63 -- nA Note: 1. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in reported peripheral currents. Additional peripherals requesting access to APORT do not incur further current. 2. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. periodic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of the requests by the specified continuous current number. silabs.com | Building a more connected world. Rev. 1.0 | 52 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.21 I2C 4.1.21.1 I2C Standard-mode (Sm)1 Table 4.28. I2C Standard-mode (Sm)1 Parameter Symbol SCL clock frequency2 Test Condition Min Typ Max Unit fSCL 0 -- 100 kHz SCL clock low time tLOW 4.7 -- -- s SCL clock high time tHIGH 4 -- -- s SDA set-up time tSU_DAT 250 -- -- ns SDA hold time3 tHD_DAT 100 -- 3450 ns Repeated START condition set-up time tSU_STA 4.7 -- -- s (Repeated) START condition tHD_STA hold time 4 -- -- s STOP condition set-up time tSU_STO 4 -- -- s Bus free time between a STOP and START condition tBUF 4.7 -- -- s Note: 1. For CLHR set to 0 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual. 3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). silabs.com | Building a more connected world. Rev. 1.0 | 53 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.21.2 I2C Fast-mode (Fm)1 Table 4.29. I2C Fast-mode (Fm)1 Parameter Symbol SCL clock frequency2 Test Condition Min Typ Max Unit fSCL 0 -- 400 kHz SCL clock low time tLOW 1.3 -- -- s SCL clock high time tHIGH 0.6 -- -- s SDA set-up time tSU_DAT 100 -- -- ns SDA hold time3 tHD_DAT 100 -- 900 ns Repeated START condition set-up time tSU_STA 0.6 -- -- s (Repeated) START condition tHD_STA hold time 0.6 -- -- s STOP condition set-up time tSU_STO 0.6 -- -- s Bus free time between a STOP and START condition tBUF 1.3 -- -- s Note: 1. For CLHR set to 1 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual. 3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW). silabs.com | Building a more connected world. Rev. 1.0 | 54 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.21.3 I2C Fast-mode Plus (Fm+)1 Table 4.30. I2C Fast-mode Plus (Fm+)1 Parameter Symbol SCL clock frequency2 Test Condition Min Typ Max Unit fSCL 0 -- 1000 kHz SCL clock low time tLOW 0.5 -- -- s SCL clock high time tHIGH 0.26 -- -- s SDA set-up time tSU_DAT 50 -- -- ns SDA hold time tHD_DAT 100 -- -- ns Repeated START condition set-up time tSU_STA 0.26 -- -- s (Repeated) START condition tHD_STA hold time 0.26 -- -- s STOP condition set-up time tSU_STO 0.26 -- -- s Bus free time between a STOP and START condition tBUF 0.5 -- -- s Note: 1. For CLHR set to 0 or 1 in the I2Cn_CTRL register. 2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual. silabs.com | Building a more connected world. Rev. 1.0 | 55 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.22 USART SPI Master Timing Table 4.31. SPI Master Timing Parameter Symbol SCLK period 1 2 3 tSCLK CS to MOSI 1 2 Test Condition Min Typ Max Unit 2* tHFPERCLK -- -- ns tCS_MO -12.5 -- 14 ns SCLK to MOSI 1 2 tSCLK_MO -8.5 -- 10.5 ns MISO setup time 1 2 tSU_MI IOVDD = 1.62 V 90 -- -- ns IOVDD = 3.0 V 42 -- -- ns -9 -- -- ns tH_MI MISO hold time 1 2 Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0). 2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD). 3. tHFPERCLK is one period of the selected HFPERCLK. CS tCS_MO tSCKL_MO SCLK CLKPOL = 0 tSCLK SCLK CLKPOL = 1 MOSI tSU_MI tH_MI MISO Figure 4.1. SPI Master Timing Diagram silabs.com | Building a more connected world. Rev. 1.0 | 56 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.1.23 USART SPI Slave Timing Table 4.32. SPI Slave Timing Parameter Symbol SCLK period 1 2 3 Test Condition Min Typ Max Unit tSCLK 6* tHFPERCLK -- -- ns SCLK high time1 2 3 tSCLK_HI 2.5 * tHFPERCLK -- -- ns SCLK low time1 2 3 tSCLK_LO 2.5 * tHFPERCLK -- -- ns CS active to MISO 1 2 tCS_ACT_MI 4 -- 70 ns CS disable to MISO 1 2 tCS_DIS_MI 4 -- 50 ns MOSI setup time 1 2 tSU_MO 12.5 -- -- ns MOSI hold time 1 2 3 tH_MO 13 -- -- ns SCLK to MISO 1 2 3 tSCLK_MI 6 + 1.5 * tHFPERCLK -- 45 + 2.5 * tHFPERCLK ns Note: 1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0). 2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD). 3. tHFPERCLK is one period of the selected HFPERCLK. CS tCS_ACT_MI tCS_DIS_MI SCLK CLKPOL = 0 SCLK CLKPOL = 1 tSCLK_HI tSU_MO tSCLK_LO tSCLK tH_MO MOSI tSCLK_MI MISO Figure 4.2. SPI Slave Timing Diagram 4.2 Typical Performance Curves Typical performance curves indicate typical characterized performance under the stated conditions. silabs.com | Building a more connected world. Rev. 1.0 | 57 ZGM130S Z-Wave 700 SiP Module Data Sheet Electrical Specifications 4.2.1 Zwave Radio Figure 4.3. RF Transmitter Output Power RF transmitter output power measured based on reference design BRD4200 at the output of the ZGM130S device. silabs.com | Building a more connected world. Rev. 1.0 | 58 ZGM130S Z-Wave 700 SiP Module Data Sheet Typical Connection Diagrams 5. Typical Connection Diagrams 5.1 Typical ZGM130S Connections Typical connections for the ZGM130S module are shown in Figure 5.1 Typical Power Connections for ZGM130S on page 59 and Figure 5.2 Typical RF Connections for ZGM130S on page 59. Main Supply VREGVDD IOVDD AVDD Figure 5.1. Typical Power Connections for ZGM130S ANTENNA RF filtering and matching Figure 5.2. Typical RF Connections for ZGM130S silabs.com | Building a more connected world. Rev. 1.0 | 59 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions 6. Pin Definitions 6.1 ZGM130S Device Pinout Figure 6.1. ZGM130S Device Pinout The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the supported features for each GPIO pin, see 6.2 GPIO Functionality Table or 6.3 Alternate Functionality Overview. silabs.com | Building a more connected world. Rev. 1.0 | 60 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Table 6.1. ZGM130S Device Pinout Pin Name Pin(s) Description Pin Name Pin(s) Description VSS 1 10 11 12 13 14 16 17 18 19 20 21 22 24 25 32 33 43 48 49 51 53 54 55 64 Ground PF0 2 GPIO (5V) PF1 3 GPIO (5V) PF2 4 GPIO (5V) PF3 5 GPIO (5V) PF4 6 GPIO (5V) PF5 7 GPIO (5V) PF6 8 GPIO (5V) RESETn 15 Reset input, active low. This pin is internally pulled up to AVDD. To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure that reset is released. PF7 9 GPIO (5V) ANTENNA 23 50 Ohm RF IO. PD9 26 GPIO (5V) PD10 27 GPIO (5V) PD11 28 GPIO (5V) PD12 29 GPIO (5V) PD13 30 GPIO PD14 31 GPIO PD15 34 GPIO PA0 35 GPIO PA1 36 GPIO PA2 37 GPIO PA3 38 GPIO PA4 39 GPIO PA5 40 GPIO (5V) PB11 41 GPIO PB12 42 GPIO AVDD 44 Analog power supply. PB13 45 GPIO PB14 46 GPIO PB15 47 GPIO 1V8 50 1.8V output of the internal DC-DC converter. Internally decoupled - do not add external decoupling. VREGVDD 52 Voltage regulator VDD input silabs.com | Building a more connected world. Rev. 1.0 | 61 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Pin Name Pin(s) Description DECOUPLE 56 N.C. This pin is the decouple output for an on-chip voltage regulator. This pin is internally decoupled, and should be left unconnected on the PCB. PC6 58 PC8 PC10 Pin Name Pin(s) Description IOVDD 57 Digital IO power supply. GPIO (5V) PC7 59 GPIO (5V) 60 GPIO (5V) PC9 61 GPIO (5V) 62 GPIO (5V) PC11 63 GPIO (5V) Note: 1. GPIO with 5V tolerance are indicated by (5V). silabs.com | Building a more connected world. Rev. 1.0 | 62 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions 6.2 GPIO Functionality Table A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO pin, followed by the functionality available on that pin. Refer to 6.3 Alternate Functionality Overview for a list of GPIO locations available for each function. Table 6.2. GPIO Functionality Table GPIO Name PA0 PA1 PA2 Pin Alternate Functionality / Description Analog Timers Communication Radio Other BUSDY BUSCX ADC0_EXTN TIM0_CC0 #0 TIM0_CC1 #31 TIM0_CC2 #30 TIM0_CDTI0 #29 TIM0_CDTI1 #28 TIM0_CDTI2 #27 TIM1_CC0 #0 TIM1_CC1 #31 TIM1_CC2 #30 TIM1_CC3 #29 WTIM0_CC0 #0 LETIM0_OUT0 #0 LETIM0_OUT1 #31 PCNT0_S0IN #0 PCNT0_S1IN #31 US0_TX #0 US0_RX #31 US0_CLK #30 US0_CS #29 US0_CTS #28 US0_RTS #27 US1_TX #0 US1_RX #31 US1_CLK #30 US1_CS #29 US1_CTS #28 US1_RTS #27 LEU0_TX #0 LEU0_RX #31 I2C0_SDA #0 I2C0_SCL #31 FRC_DCLK #0 FRC_DOUT #31 FRC_DFRAME #30 MODEM_DCLK #0 MODEM_DIN #31 MODEM_DOUT #30 CMU_CLK1 #0 PRS_CH6 #0 PRS_CH7 #10 PRS_CH8 #9 PRS_CH9 #8 ACMP0_O #0 ACMP1_O #0 LES_CH8 BUSCY BUSDX ADC0_EXTP VDAC0_EXT TIM0_CC0 #1 TIM0_CC1 #0 TIM0_CC2 #31 TIM0_CDTI0 #30 TIM0_CDTI1 #29 TIM0_CDTI2 #28 TIM1_CC0 #1 TIM1_CC1 #0 TIM1_CC2 #31 TIM1_CC3 #30 WTIM0_CC0 #1 LETIM0_OUT0 #1 LETIM0_OUT1 #0 PCNT0_S0IN #1 PCNT0_S1IN #0 US0_TX #1 US0_RX #0 US0_CLK #31 US0_CS #30 US0_CTS #29 US0_RTS #28 US1_TX #1 US1_RX #0 US1_CLK #31 US1_CS #30 US1_CTS #29 US1_RTS #28 LEU0_TX #1 LEU0_RX #0 I2C0_SDA #1 I2C0_SCL #0 FRC_DCLK #1 FRC_DOUT #0 FRC_DFRAME #31 MODEM_DCLK #1 MODEM_DIN #0 MODEM_DOUT #31 CMU_CLK0 #0 PRS_CH6 #1 PRS_CH7 #0 PRS_CH8 #10 PRS_CH9 #9 ACMP0_O #1 ACMP1_O #1 LES_CH9 VDAC0_OUT1ALT / OPA1_OUTALT #1 BUSDY BUSCX OPA0_P TIM0_CC0 #2 TIM0_CC1 #1 TIM0_CC2 #0 TIM0_CDTI0 #31 TIM0_CDTI1 #30 TIM0_CDTI2 #29 TIM1_CC0 #2 TIM1_CC1 #1 TIM1_CC2 #0 TIM1_CC3 #31 WTIM0_CC0 #2 WTIM0_CC1 #0 LETIM0_OUT0 #2 LETIM0_OUT1 #1 PCNT0_S0IN #2 PCNT0_S1IN #1 US0_TX #2 US0_RX #1 US0_CLK #0 US0_CS #31 US0_CTS #30 US0_RTS #29 US1_TX #2 US1_RX #1 US1_CLK #0 US1_CS #31 US1_CTS #30 US1_RTS #29 LEU0_TX #2 LEU0_RX #1 I2C0_SDA #2 I2C0_SCL #1 FRC_DCLK #2 FRC_DOUT #1 FRC_DFRAME #0 MODEM_DCLK #2 MODEM_DIN #1 MODEM_DOUT #0 PRS_CH6 #2 PRS_CH7 #1 PRS_CH8 #0 PRS_CH9 #10 ACMP0_O #2 ACMP1_O #2 LES_CH10 silabs.com | Building a more connected world. Rev. 1.0 | 63 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name PA3 PA4 PA5 Pin Alternate Functionality / Description Analog Timers Communication Radio Other BUSCY BUSDX VDAC0_OUT0 / OPA0_OUT TIM0_CC0 #3 TIM0_CC1 #2 TIM0_CC2 #1 TIM0_CDTI0 #0 TIM0_CDTI1 #31 TIM0_CDTI2 #30 TIM1_CC0 #3 TIM1_CC1 #2 TIM1_CC2 #1 TIM1_CC3 #0 WTIM0_CC0 #3 WTIM0_CC1 #1 LETIM0_OUT0 #3 LETIM0_OUT1 #2 PCNT0_S0IN #3 PCNT0_S1IN #2 US0_TX #3 US0_RX #2 US0_CLK #1 US0_CS #0 US0_CTS #31 US0_RTS #30 US1_TX #3 US1_RX #2 US1_CLK #1 US1_CS #0 US1_CTS #31 US1_RTS #30 LEU0_TX #3 LEU0_RX #2 I2C0_SDA #3 I2C0_SCL #2 FRC_DCLK #3 FRC_DOUT #2 FRC_DFRAME #1 MODEM_DCLK #3 MODEM_DIN #2 MODEM_DOUT #1 PRS_CH6 #3 PRS_CH7 #2 PRS_CH8 #1 PRS_CH9 #0 ACMP0_O #3 ACMP1_O #3 LES_CH11 GPIO_EM4WU8 VDAC0_OUT1ALT / OPA1_OUTALT #2 BUSDY BUSCX OPA0_N TIM0_CC0 #4 TIM0_CC1 #3 TIM0_CC2 #2 TIM0_CDTI0 #1 TIM0_CDTI1 #0 TIM0_CDTI2 #31 TIM1_CC0 #4 TIM1_CC1 #3 TIM1_CC2 #2 TIM1_CC3 #1 WTIM0_CC0 #4 WTIM0_CC1 #2 WTIM0_CC2 #0 LETIM0_OUT0 #4 LETIM0_OUT1 #3 PCNT0_S0IN #4 PCNT0_S1IN #3 US0_TX #4 US0_RX #3 US0_CLK #2 US0_CS #1 US0_CTS #0 US0_RTS #31 US1_TX #4 US1_RX #3 US1_CLK #2 US1_CS #1 US1_CTS #0 US1_RTS #31 LEU0_TX #4 LEU0_RX #3 I2C0_SDA #4 I2C0_SCL #3 FRC_DCLK #4 FRC_DOUT #3 FRC_DFRAME #2 MODEM_DCLK #4 MODEM_DIN #3 MODEM_DOUT #2 PRS_CH6 #4 PRS_CH7 #3 PRS_CH8 #2 PRS_CH9 #1 ACMP0_O #4 ACMP1_O #4 LES_CH12 VDAC0_OUT0ALT / OPA0_OUTALT #0 BUSCY BUSDX TIM0_CC0 #5 TIM0_CC1 #4 TIM0_CC2 #3 TIM0_CDTI0 #2 TIM0_CDTI1 #1 TIM0_CDTI2 #0 TIM1_CC0 #5 TIM1_CC1 #4 TIM1_CC2 #3 TIM1_CC3 #2 WTIM0_CC0 #5 WTIM0_CC1 #3 WTIM0_CC2 #1 LETIM0_OUT0 #5 LETIM0_OUT1 #4 PCNT0_S0IN #5 PCNT0_S1IN #4 US0_TX #5 US0_RX #4 US0_CLK #3 US0_CS #2 US0_CTS #1 US0_RTS #0 US1_TX #5 US1_RX #4 US1_CLK #3 US1_CS #2 US1_CTS #1 US1_RTS #0 US2_TX #0 US2_RX #31 US2_CLK #30 US2_CS #29 US2_CTS #28 US2_RTS #27 LEU0_TX #5 LEU0_RX #4 I2C0_SDA #5 I2C0_SCL #4 FRC_DCLK #5 FRC_DOUT #4 FRC_DFRAME #3 MODEM_DCLK #5 MODEM_DIN #4 MODEM_DOUT #3 CMU_CLKI0 #4 PRS_CH6 #5 PRS_CH7 #4 PRS_CH8 #3 PRS_CH9 #2 ACMP0_O #5 ACMP1_O #5 LES_CH13 ETM_TCLK #1 silabs.com | Building a more connected world. Rev. 1.0 | 64 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name PB11 PB12 PB13 Pin Alternate Functionality / Description Analog Timers Communication Radio Other BUSCY BUSDX OPA2_P TIM0_CC0 #6 TIM0_CC1 #5 TIM0_CC2 #4 TIM0_CDTI0 #3 TIM0_CDTI1 #2 TIM0_CDTI2 #1 TIM1_CC0 #6 TIM1_CC1 #5 TIM1_CC2 #4 TIM1_CC3 #3 WTIM0_CC0 #15 WTIM0_CC1 #13 WTIM0_CC2 #11 WTIM0_CDTI0 #7 WTIM0_CDTI1 #5 WTIM0_CDTI2 #3 LETIM0_OUT0 #6 LETIM0_OUT1 #5 PCNT0_S0IN #6 PCNT0_S1IN #5 US0_TX #6 US0_RX #5 US0_CLK #4 US0_CS #3 US0_CTS #2 US0_RTS #1 US1_TX #6 US1_RX #5 US1_CLK #4 US1_CS #3 US1_CTS #2 US1_RTS #1 LEU0_TX #6 LEU0_RX #5 I2C0_SDA #6 I2C0_SCL #5 FRC_DCLK #6 FRC_DOUT #5 FRC_DFRAME #4 MODEM_DCLK #6 MODEM_DIN #5 MODEM_DOUT #4 PRS_CH6 #6 PRS_CH7 #5 PRS_CH8 #4 PRS_CH9 #3 ACMP0_O #6 ACMP1_O #6 BUSDY BUSCX OPA2_OUT TIM0_CC0 #7 TIM0_CC1 #6 TIM0_CC2 #5 TIM0_CDTI0 #4 TIM0_CDTI1 #3 TIM0_CDTI2 #2 TIM1_CC0 #7 TIM1_CC1 #6 TIM1_CC2 #5 TIM1_CC3 #4 WTIM0_CC0 #16 WTIM0_CC1 #14 WTIM0_CC2 #12 WTIM0_CDTI0 #8 WTIM0_CDTI1 #6 WTIM0_CDTI2 #4 LETIM0_OUT0 #7 LETIM0_OUT1 #6 PCNT0_S0IN #7 PCNT0_S1IN #6 US0_TX #7 US0_RX #6 US0_CLK #5 US0_CS #4 US0_CTS #3 US0_RTS #2 US1_TX #7 US1_RX #6 US1_CLK #5 US1_CS #4 US1_CTS #3 US1_RTS #2 LEU0_TX #7 LEU0_RX #6 I2C0_SDA #7 I2C0_SCL #6 FRC_DCLK #7 FRC_DOUT #6 FRC_DFRAME #5 MODEM_DCLK #7 MODEM_DIN #6 MODEM_DOUT #5 PRS_CH6 #7 PRS_CH7 #6 PRS_CH8 #5 PRS_CH9 #4 ACMP0_O #7 ACMP1_O #7 BUSCY BUSDX OPA2_N TIM0_CC0 #8 TIM0_CC1 #7 TIM0_CC2 #6 TIM0_CDTI0 #5 TIM0_CDTI1 #4 TIM0_CDTI2 #3 TIM1_CC0 #8 TIM1_CC1 #7 TIM1_CC2 #6 TIM1_CC3 #5 WTIM0_CC0 #17 WTIM0_CC1 #15 WTIM0_CC2 #13 WTIM0_CDTI0 #9 WTIM0_CDTI1 #7 WTIM0_CDTI2 #5 LETIM0_OUT0 #8 LETIM0_OUT1 #7 PCNT0_S0IN #8 PCNT0_S1IN #7 US0_TX #8 US0_RX #7 US0_CLK #6 US0_CS #5 US0_CTS #4 US0_RTS #3 US1_TX #8 US1_RX #7 US1_CLK #6 US1_CS #5 US1_CTS #4 US1_RTS #3 LEU0_TX #8 LEU0_RX #7 I2C0_SDA #8 I2C0_SCL #7 FRC_DCLK #8 FRC_DOUT #7 FRC_DFRAME #6 MODEM_DCLK #8 MODEM_DIN #7 MODEM_DOUT #6 CMU_CLKI0 #0 PRS_CH6 #8 PRS_CH7 #7 PRS_CH8 #6 PRS_CH9 #5 ACMP0_O #8 ACMP1_O #8 DBG_SWO #1 GPIO_EM4WU9 silabs.com | Building a more connected world. Rev. 1.0 | 65 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name PB14 PB15 PC6 Pin Alternate Functionality / Description Analog Timers Communication Radio Other BUSDY BUSCX TIM0_CC0 #9 TIM0_CC1 #8 TIM0_CC2 #7 TIM0_CDTI0 #6 TIM0_CDTI1 #5 TIM0_CDTI2 #4 TIM1_CC0 #9 TIM1_CC1 #8 TIM1_CC2 #7 TIM1_CC3 #6 WTIM0_CC0 #18 WTIM0_CC1 #16 WTIM0_CC2 #14 WTIM0_CDTI0 #10 WTIM0_CDTI1 #8 WTIM0_CDTI2 #6 LETIM0_OUT0 #9 LETIM0_OUT1 #8 PCNT0_S0IN #9 PCNT0_S1IN #8 US0_TX #9 US0_RX #8 US0_CLK #7 US0_CS #6 US0_CTS #5 US0_RTS #4 US1_TX #9 US1_RX #8 US1_CLK #7 US1_CS #6 US1_CTS #5 US1_RTS #4 LEU0_TX #9 LEU0_RX #8 I2C0_SDA #9 I2C0_SCL #8 FRC_DCLK #9 FRC_DOUT #8 FRC_DFRAME #7 MODEM_DCLK #9 MODEM_DIN #8 MODEM_DOUT #7 CMU_CLK1 #1 PRS_CH6 #9 PRS_CH7 #8 PRS_CH8 #7 PRS_CH9 #6 ACMP0_O #9 ACMP1_O #9 BUSCY BUSDX TIM0_CC0 #10 TIM0_CC1 #9 TIM0_CC2 #8 TIM0_CDTI0 #7 TIM0_CDTI1 #6 TIM0_CDTI2 #5 TIM1_CC0 #10 TIM1_CC1 #9 TIM1_CC2 #8 TIM1_CC3 #7 WTIM0_CC0 #19 WTIM0_CC1 #17 WTIM0_CC2 #15 WTIM0_CDTI0 #11 WTIM0_CDTI1 #9 WTIM0_CDTI2 #7 LETIM0_OUT0 #10 LETIM0_OUT1 #9 PCNT0_S0IN #10 PCNT0_S1IN #9 US0_TX #10 US0_RX #9 US0_CLK #8 US0_CS #7 US0_CTS #6 US0_RTS #5 US1_TX #10 US1_RX #9 US1_CLK #8 US1_CS #7 US1_CTS #6 US1_RTS #5 LEU0_TX #10 LEU0_RX #9 I2C0_SDA #10 I2C0_SCL #9 FRC_DCLK #10 FRC_DOUT #9 FRC_DFRAME #8 MODEM_DCLK #10 MODEM_DIN #9 MODEM_DOUT #8 CMU_CLK0 #1 PRS_CH6 #10 PRS_CH7 #9 PRS_CH8 #8 PRS_CH9 #7 ACMP0_O #10 ACMP1_O #10 BUSBY BUSAX TIM0_CC0 #11 TIM0_CC1 #10 TIM0_CC2 #9 TIM0_CDTI0 #8 TIM0_CDTI1 #7 TIM0_CDTI2 #6 TIM1_CC0 #11 TIM1_CC1 #10 TIM1_CC2 #9 TIM1_CC3 #8 WTIM0_CC0 #26 WTIM0_CC1 #24 WTIM0_CC2 #22 WTIM0_CDTI0 #18 WTIM0_CDTI1 #16 WTIM0_CDTI2 #14 LETIM0_OUT0 #11 LETIM0_OUT1 #10 PCNT0_S0IN #11 PCNT0_S1IN #10 US0_TX #11 US0_RX #10 US0_CLK #9 US0_CS #8 US0_CTS #7 US0_RTS #6 US1_TX #11 US1_RX #10 US1_CLK #9 US1_CS #8 US1_CTS #7 US1_RTS #6 LEU0_TX #11 LEU0_RX #10 I2C0_SDA #11 I2C0_SCL #10 FRC_DCLK #11 FRC_DOUT #10 FRC_DFRAME #9 MODEM_DCLK #11 MODEM_DIN #10 MODEM_DOUT #9 CMU_CLK0 #2 CMU_CLKI0 #2 PRS_CH0 #8 PRS_CH9 #11 PRS_CH10 #0 PRS_CH11 #5 ACMP0_O #11 ACMP1_O #11 ETM_TCLK #3 silabs.com | Building a more connected world. Rev. 1.0 | 66 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name PC7 PC8 PC9 Pin Alternate Functionality / Description Analog Timers Communication Radio Other BUSAY BUSBX TIM0_CC0 #12 TIM0_CC1 #11 TIM0_CC2 #10 TIM0_CDTI0 #9 TIM0_CDTI1 #8 TIM0_CDTI2 #7 TIM1_CC0 #12 TIM1_CC1 #11 TIM1_CC2 #10 TIM1_CC3 #9 WTIM0_CC0 #27 WTIM0_CC1 #25 WTIM0_CC2 #23 WTIM0_CDTI0 #19 WTIM0_CDTI1 #17 WTIM0_CDTI2 #15 LETIM0_OUT0 #12 LETIM0_OUT1 #11 PCNT0_S0IN #12 PCNT0_S1IN #11 US0_TX #12 US0_RX #11 US0_CLK #10 US0_CS #9 US0_CTS #8 US0_RTS #7 US1_TX #12 US1_RX #11 US1_CLK #10 US1_CS #9 US1_CTS #8 US1_RTS #7 LEU0_TX #12 LEU0_RX #11 I2C0_SDA #12 I2C0_SCL #11 FRC_DCLK #12 FRC_DOUT #11 FRC_DFRAME #10 MODEM_DCLK #12 MODEM_DIN #11 MODEM_DOUT #10 CMU_CLK1 #2 PRS_CH0 #9 PRS_CH9 #12 PRS_CH10 #1 PRS_CH11 #0 ACMP0_O #12 ACMP1_O #12 ETM_TD0 BUSBY BUSAX TIM0_CC0 #13 TIM0_CC1 #12 TIM0_CC2 #11 TIM0_CDTI0 #10 TIM0_CDTI1 #9 TIM0_CDTI2 #8 TIM1_CC0 #13 TIM1_CC1 #12 TIM1_CC2 #11 TIM1_CC3 #10 WTIM0_CC0 #28 WTIM0_CC1 #26 WTIM0_CC2 #24 WTIM0_CDTI0 #20 WTIM0_CDTI1 #18 WTIM0_CDTI2 #16 LETIM0_OUT0 #13 LETIM0_OUT1 #12 PCNT0_S0IN #13 PCNT0_S1IN #12 US0_TX #13 US0_RX #12 US0_CLK #11 US0_CS #10 US0_CTS #9 US0_RTS #8 US1_TX #13 US1_RX #12 US1_CLK #11 US1_CS #10 US1_CTS #9 US1_RTS #8 LEU0_TX #13 LEU0_RX #12 I2C0_SDA #13 I2C0_SCL #12 FRC_DCLK #13 FRC_DOUT #12 FRC_DFRAME #11 MODEM_DCLK #13 MODEM_DIN #12 MODEM_DOUT #11 PRS_CH0 #10 PRS_CH9 #13 PRS_CH10 #2 PRS_CH11 #1 ACMP0_O #13 ACMP1_O #13 ETM_TD1 BUSAY BUSBX TIM0_CC0 #14 TIM0_CC1 #13 TIM0_CC2 #12 TIM0_CDTI0 #11 TIM0_CDTI1 #10 TIM0_CDTI2 #9 TIM1_CC0 #14 TIM1_CC1 #13 TIM1_CC2 #12 TIM1_CC3 #11 WTIM0_CC0 #29 WTIM0_CC1 #27 WTIM0_CC2 #25 WTIM0_CDTI0 #21 WTIM0_CDTI1 #19 WTIM0_CDTI2 #17 LETIM0_OUT0 #14 LETIM0_OUT1 #13 PCNT0_S0IN #14 PCNT0_S1IN #13 US0_TX #14 US0_RX #13 US0_CLK #12 US0_CS #11 US0_CTS #10 US0_RTS #9 US1_TX #14 US1_RX #13 US1_CLK #12 US1_CS #11 US1_CTS #10 US1_RTS #9 LEU0_TX #14 LEU0_RX #13 I2C0_SDA #14 I2C0_SCL #13 FRC_DCLK #14 FRC_DOUT #13 FRC_DFRAME #12 MODEM_DCLK #14 MODEM_DIN #13 MODEM_DOUT #12 PRS_CH0 #11 PRS_CH9 #14 PRS_CH10 #3 PRS_CH11 #2 ACMP0_O #14 ACMP1_O #14 ETM_TD2 silabs.com | Building a more connected world. Rev. 1.0 | 67 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name PC10 PC11 PD9 Pin Alternate Functionality / Description Analog Timers Communication Radio Other BUSBY BUSAX TIM0_CC0 #15 TIM0_CC1 #14 TIM0_CC2 #13 TIM0_CDTI0 #12 TIM0_CDTI1 #11 TIM0_CDTI2 #10 TIM1_CC0 #15 TIM1_CC1 #14 TIM1_CC2 #13 TIM1_CC3 #12 WTIM0_CC0 #30 WTIM0_CC1 #28 WTIM0_CC2 #26 WTIM0_CDTI0 #22 WTIM0_CDTI1 #20 WTIM0_CDTI2 #18 LETIM0_OUT0 #15 LETIM0_OUT1 #14 PCNT0_S0IN #15 PCNT0_S1IN #14 US0_TX #15 US0_RX #14 US0_CLK #13 US0_CS #12 US0_CTS #11 US0_RTS #10 US1_TX #15 US1_RX #14 US1_CLK #13 US1_CS #12 US1_CTS #11 US1_RTS #10 LEU0_TX #15 LEU0_RX #14 I2C0_SDA #15 I2C0_SCL #14 I2C1_SDA #19 I2C1_SCL #18 FRC_DCLK #15 FRC_DOUT #14 FRC_DFRAME #13 MODEM_DCLK #15 MODEM_DIN #14 MODEM_DOUT #13 CMU_CLK1 #3 PRS_CH0 #12 PRS_CH9 #15 PRS_CH10 #4 PRS_CH11 #3 ACMP0_O #15 ACMP1_O #15 ETM_TD3 GPIO_EM4WU12 BUSAY BUSBX TIM0_CC0 #16 TIM0_CC1 #15 TIM0_CC2 #14 TIM0_CDTI0 #13 TIM0_CDTI1 #12 TIM0_CDTI2 #11 TIM1_CC0 #16 TIM1_CC1 #15 TIM1_CC2 #14 TIM1_CC3 #13 WTIM0_CC0 #31 WTIM0_CC1 #29 WTIM0_CC2 #27 WTIM0_CDTI0 #23 WTIM0_CDTI1 #21 WTIM0_CDTI2 #19 LETIM0_OUT0 #16 LETIM0_OUT1 #15 PCNT0_S0IN #16 PCNT0_S1IN #15 US0_TX #16 US0_RX #15 US0_CLK #14 US0_CS #13 US0_CTS #12 US0_RTS #11 US1_TX #16 US1_RX #15 US1_CLK #14 US1_CS #13 US1_CTS #12 US1_RTS #11 LEU0_TX #16 LEU0_RX #15 I2C0_SDA #16 I2C0_SCL #15 I2C1_SDA #20 I2C1_SCL #19 FRC_DCLK #16 FRC_DOUT #15 FRC_DFRAME #14 MODEM_DCLK #16 MODEM_DIN #15 MODEM_DOUT #14 CMU_CLK0 #3 PRS_CH0 #13 PRS_CH9 #16 PRS_CH10 #5 PRS_CH11 #4 ACMP0_O #16 ACMP1_O #16 DBG_SWO #3 BUSCY BUSDX TIM0_CC0 #17 TIM0_CC1 #16 TIM0_CC2 #15 TIM0_CDTI0 #14 TIM0_CDTI1 #13 TIM0_CDTI2 #12 TIM1_CC0 #17 TIM1_CC1 #16 TIM1_CC2 #15 TIM1_CC3 #14 WTIM0_CC1 #31 WTIM0_CC2 #29 WTIM0_CDTI0 #25 WTIM0_CDTI1 #23 WTIM0_CDTI2 #21 LETIM0_OUT0 #17 LETIM0_OUT1 #16 PCNT0_S0IN #17 PCNT0_S1IN #16 US0_TX #17 US0_RX #16 US0_CLK #15 US0_CS #14 US0_CTS #13 US0_RTS #12 US1_TX #17 US1_RX #16 US1_CLK #15 US1_CS #14 US1_CTS #13 US1_RTS #12 LEU0_TX #17 LEU0_RX #16 I2C0_SDA #17 I2C0_SCL #16 FRC_DCLK #17 FRC_DOUT #16 FRC_DFRAME #15 MODEM_DCLK #17 MODEM_DIN #16 MODEM_DOUT #15 CMU_CLK0 #4 PRS_CH3 #8 PRS_CH4 #0 PRS_CH5 #6 PRS_CH6 #11 ACMP0_O #17 ACMP1_O #17 LES_CH1 silabs.com | Building a more connected world. Rev. 1.0 | 68 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name PD10 PD11 PD12 Pin Alternate Functionality / Description Analog Timers Communication Radio Other BUSDY BUSCX TIM0_CC0 #18 TIM0_CC1 #17 TIM0_CC2 #16 TIM0_CDTI0 #15 TIM0_CDTI1 #14 TIM0_CDTI2 #13 TIM1_CC0 #18 TIM1_CC1 #17 TIM1_CC2 #16 TIM1_CC3 #15 WTIM0_CC2 #30 WTIM0_CDTI0 #26 WTIM0_CDTI1 #24 WTIM0_CDTI2 #22 LETIM0_OUT0 #18 LETIM0_OUT1 #17 PCNT0_S0IN #18 PCNT0_S1IN #17 US0_TX #18 US0_RX #17 US0_CLK #16 US0_CS #15 US0_CTS #14 US0_RTS #13 US1_TX #18 US1_RX #17 US1_CLK #16 US1_CS #15 US1_CTS #14 US1_RTS #13 LEU0_TX #18 LEU0_RX #17 I2C0_SDA #18 I2C0_SCL #17 FRC_DCLK #18 FRC_DOUT #17 FRC_DFRAME #16 MODEM_DCLK #18 MODEM_DIN #17 MODEM_DOUT #16 CMU_CLK1 #4 PRS_CH3 #9 PRS_CH4 #1 PRS_CH5 #0 PRS_CH6 #12 ACMP0_O #18 ACMP1_O #18 LES_CH2 BUSCY BUSDX TIM0_CC0 #19 TIM0_CC1 #18 TIM0_CC2 #17 TIM0_CDTI0 #16 TIM0_CDTI1 #15 TIM0_CDTI2 #14 TIM1_CC0 #19 TIM1_CC1 #18 TIM1_CC2 #17 TIM1_CC3 #16 WTIM0_CC2 #31 WTIM0_CDTI0 #27 WTIM0_CDTI1 #25 WTIM0_CDTI2 #23 LETIM0_OUT0 #19 LETIM0_OUT1 #18 PCNT0_S0IN #19 PCNT0_S1IN #18 US0_TX #19 US0_RX #18 US0_CLK #17 US0_CS #16 US0_CTS #15 US0_RTS #14 US1_TX #19 US1_RX #18 US1_CLK #17 US1_CS #16 US1_CTS #15 US1_RTS #14 LEU0_TX #19 LEU0_RX #18 I2C0_SDA #19 I2C0_SCL #18 FRC_DCLK #19 FRC_DOUT #18 FRC_DFRAME #17 MODEM_DCLK #19 MODEM_DIN #18 MODEM_DOUT #17 PRS_CH3 #10 PRS_CH4 #2 PRS_CH5 #1 PRS_CH6 #13 ACMP0_O #19 ACMP1_O #19 LES_CH3 VDAC0_OUT1ALT / OPA1_OUTALT #0 BUSDY BUSCX TIM0_CC0 #20 TIM0_CC1 #19 TIM0_CC2 #18 TIM0_CDTI0 #17 TIM0_CDTI1 #16 TIM0_CDTI2 #15 TIM1_CC0 #20 TIM1_CC1 #19 TIM1_CC2 #18 TIM1_CC3 #17 WTIM0_CDTI0 #28 WTIM0_CDTI1 #26 WTIM0_CDTI2 #24 LETIM0_OUT0 #20 LETIM0_OUT1 #19 PCNT0_S0IN #20 PCNT0_S1IN #19 US0_TX #20 US0_RX #19 US0_CLK #18 US0_CS #17 US0_CTS #16 US0_RTS #15 US1_TX #20 US1_RX #19 US1_CLK #18 US1_CS #17 US1_CTS #16 US1_RTS #15 LEU0_TX #20 LEU0_RX #19 I2C0_SDA #20 I2C0_SCL #19 FRC_DCLK #20 FRC_DOUT #19 FRC_DFRAME #18 MODEM_DCLK #20 MODEM_DIN #19 MODEM_DOUT #18 PRS_CH3 #11 PRS_CH4 #3 PRS_CH5 #2 PRS_CH6 #14 ACMP0_O #20 ACMP1_O #20 LES_CH4 silabs.com | Building a more connected world. Rev. 1.0 | 69 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name PD13 PD14 PD15 Pin Alternate Functionality / Description Analog Timers Communication Radio Other VDAC0_OUT0ALT / OPA0_OUTALT #1 BUSCY BUSDX OPA1_P TIM0_CC0 #21 TIM0_CC1 #20 TIM0_CC2 #19 TIM0_CDTI0 #18 TIM0_CDTI1 #17 TIM0_CDTI2 #16 TIM1_CC0 #21 TIM1_CC1 #20 TIM1_CC2 #19 TIM1_CC3 #18 WTIM0_CDTI0 #29 WTIM0_CDTI1 #27 WTIM0_CDTI2 #25 LETIM0_OUT0 #21 LETIM0_OUT1 #20 PCNT0_S0IN #21 PCNT0_S1IN #20 US0_TX #21 US0_RX #20 US0_CLK #19 US0_CS #18 US0_CTS #17 US0_RTS #16 US1_TX #21 US1_RX #20 US1_CLK #19 US1_CS #18 US1_CTS #17 US1_RTS #16 LEU0_TX #21 LEU0_RX #20 I2C0_SDA #21 I2C0_SCL #20 FRC_DCLK #21 FRC_DOUT #20 FRC_DFRAME #19 MODEM_DCLK #21 MODEM_DIN #20 MODEM_DOUT #19 PRS_CH3 #12 PRS_CH4 #4 PRS_CH5 #3 PRS_CH6 #15 ACMP0_O #21 ACMP1_O #21 LES_CH5 BUSDY BUSCX VDAC0_OUT1 / OPA1_OUT TIM0_CC0 #22 TIM0_CC1 #21 TIM0_CC2 #20 TIM0_CDTI0 #19 TIM0_CDTI1 #18 TIM0_CDTI2 #17 TIM1_CC0 #22 TIM1_CC1 #21 TIM1_CC2 #20 TIM1_CC3 #19 WTIM0_CDTI0 #30 WTIM0_CDTI1 #28 WTIM0_CDTI2 #26 LETIM0_OUT0 #22 LETIM0_OUT1 #21 PCNT0_S0IN #22 PCNT0_S1IN #21 US0_TX #22 US0_RX #21 US0_CLK #20 US0_CS #19 US0_CTS #18 US0_RTS #17 US1_TX #22 US1_RX #21 US1_CLK #20 US1_CS #19 US1_CTS #18 US1_RTS #17 LEU0_TX #22 LEU0_RX #21 I2C0_SDA #22 I2C0_SCL #21 FRC_DCLK #22 FRC_DOUT #21 FRC_DFRAME #20 MODEM_DCLK #22 MODEM_DIN #21 MODEM_DOUT #20 CMU_CLK0 #5 PRS_CH3 #13 PRS_CH4 #5 PRS_CH5 #4 PRS_CH6 #16 ACMP0_O #22 ACMP1_O #22 LES_CH6 GPIO_EM4WU4 VDAC0_OUT0ALT / OPA0_OUTALT #2 BUSCY BUSDX OPA1_N TIM0_CC0 #23 TIM0_CC1 #22 TIM0_CC2 #21 TIM0_CDTI0 #20 TIM0_CDTI1 #19 TIM0_CDTI2 #18 TIM1_CC0 #23 TIM1_CC1 #22 TIM1_CC2 #21 TIM1_CC3 #20 WTIM0_CDTI0 #31 WTIM0_CDTI1 #29 WTIM0_CDTI2 #27 LETIM0_OUT0 #23 LETIM0_OUT1 #22 PCNT0_S0IN #23 PCNT0_S1IN #22 US0_TX #23 US0_RX #22 US0_CLK #21 US0_CS #20 US0_CTS #19 US0_RTS #18 US1_TX #23 US1_RX #22 US1_CLK #21 US1_CS #20 US1_CTS #19 US1_RTS #18 LEU0_TX #23 LEU0_RX #22 I2C0_SDA #23 I2C0_SCL #22 FRC_DCLK #23 FRC_DOUT #22 FRC_DFRAME #21 MODEM_DCLK #23 MODEM_DIN #22 MODEM_DOUT #21 CMU_CLK1 #5 PRS_CH3 #14 PRS_CH4 #6 PRS_CH5 #5 PRS_CH6 #17 ACMP0_O #23 ACMP1_O #23 LES_CH7 DBG_SWO #2 silabs.com | Building a more connected world. Rev. 1.0 | 70 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Analog PF0 PF1 PF2 Timers Communication Radio Other TIM0_CC0 #24 TIM0_CC1 #23 TIM0_CC2 #22 TIM0_CDTI0 #21 TIM0_CDTI1 #20 TIM0_CDTI2 #19 TIM1_CC0 #24 TIM1_CC1 #23 TIM1_CC2 #22 TIM1_CC3 #21 WTIM0_CDTI1 #30 WTIM0_CDTI2 #28 LETIM0_OUT0 #24 LETIM0_OUT1 #23 PCNT0_S0IN #24 PCNT0_S1IN #23 US0_TX #24 US0_RX #23 US0_CLK #22 US0_CS #21 US0_CTS #20 US0_RTS #19 US1_TX #24 US1_RX #23 US1_CLK #22 US1_CS #21 US1_CTS #20 US1_RTS #19 US2_TX #14 US2_RX #13 US2_CLK #12 US2_CS #11 US2_CTS #10 US2_RTS #9 LEU0_TX #24 LEU0_RX #23 I2C0_SDA #24 I2C0_SCL #23 FRC_DCLK #24 FRC_DOUT #23 FRC_DFRAME #22 MODEM_DCLK #24 MODEM_DIN #23 MODEM_DOUT #22 PRS_CH0 #0 PRS_CH1 #7 PRS_CH2 #6 PRS_CH3 #5 ACMP0_O #24 ACMP1_O #24 DBG_SWCLKTCK BOOT_TX BUSAY BUSBX TIM0_CC0 #25 TIM0_CC1 #24 TIM0_CC2 #23 TIM0_CDTI0 #22 TIM0_CDTI1 #21 TIM0_CDTI2 #20 TIM1_CC0 #25 TIM1_CC1 #24 TIM1_CC2 #23 TIM1_CC3 #22 WTIM0_CDTI1 #31 WTIM0_CDTI2 #29 LETIM0_OUT0 #25 LETIM0_OUT1 #24 PCNT0_S0IN #25 PCNT0_S1IN #24 US0_TX #25 US0_RX #24 US0_CLK #23 US0_CS #22 US0_CTS #21 US0_RTS #20 US1_TX #25 US1_RX #24 US1_CLK #23 US1_CS #22 US1_CTS #21 US1_RTS #20 US2_TX #15 US2_RX #14 US2_CLK #13 US2_CS #12 US2_CTS #11 US2_RTS #10 LEU0_TX #25 LEU0_RX #24 I2C0_SDA #25 I2C0_SCL #24 FRC_DCLK #25 FRC_DOUT #24 FRC_DFRAME #23 MODEM_DCLK #25 MODEM_DIN #24 MODEM_DOUT #23 PRS_CH0 #1 PRS_CH1 #0 PRS_CH2 #7 PRS_CH3 #6 ACMP0_O #25 ACMP1_O #25 DBG_SWDIOTMS BOOT_RX BUSBY BUSAX TIM0_CC0 #26 TIM0_CC1 #25 TIM0_CC2 #24 TIM0_CDTI0 #23 TIM0_CDTI1 #22 TIM0_CDTI2 #21 TIM1_CC0 #26 TIM1_CC1 #25 TIM1_CC2 #24 TIM1_CC3 #23 WTIM0_CDTI2 #30 LETIM0_OUT0 #26 LETIM0_OUT1 #25 PCNT0_S0IN #26 PCNT0_S1IN #25 US0_TX #26 US0_RX #25 US0_CLK #24 US0_CS #23 US0_CTS #22 US0_RTS #21 US1_TX #26 US1_RX #25 US1_CLK #24 US1_CS #23 US1_CTS #22 US1_RTS #21 LEU0_TX #26 LEU0_RX #25 I2C0_SDA #26 I2C0_SCL #25 FRC_DCLK #26 FRC_DOUT #25 FRC_DFRAME #24 MODEM_DCLK #26 MODEM_DIN #25 MODEM_DOUT #24 CMU_CLK0 #6 PRS_CH0 #2 PRS_CH1 #1 PRS_CH2 #0 PRS_CH3 #7 ACMP0_O #26 ACMP1_O #26 DBG_TDO DBG_SWO #0 GPIO_EM4WU0 BUSBY BUSAX silabs.com | Building a more connected world. Rev. 1.0 | 71 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Analog PF3 PF4 BUSAY BUSBX BUSBY BUSAX silabs.com | Building a more connected world. Timers Communication Radio Other TIM0_CC0 #27 TIM0_CC1 #26 TIM0_CC2 #25 TIM0_CDTI0 #24 TIM0_CDTI1 #23 TIM0_CDTI2 #22 TIM1_CC0 #27 TIM1_CC1 #26 TIM1_CC2 #25 TIM1_CC3 #24 WTIM0_CDTI2 #31 LETIM0_OUT0 #27 LETIM0_OUT1 #26 PCNT0_S0IN #27 PCNT0_S1IN #26 US0_TX #27 US0_RX #26 US0_CLK #25 US0_CS #24 US0_CTS #23 US0_RTS #22 US1_TX #27 US1_RX #26 US1_CLK #25 US1_CS #24 US1_CTS #23 US1_RTS #22 US2_TX #16 US2_RX #15 US2_CLK #14 US2_CS #13 US2_CTS #12 US2_RTS #11 LEU0_TX #27 LEU0_RX #26 I2C0_SDA #27 I2C0_SCL #26 FRC_DCLK #27 FRC_DOUT #26 FRC_DFRAME #25 MODEM_DCLK #27 MODEM_DIN #26 MODEM_DOUT #25 CMU_CLK1 #6 PRS_CH0 #3 PRS_CH1 #2 PRS_CH2 #1 PRS_CH3 #0 ACMP0_O #27 ACMP1_O #27 DBG_TDI TIM0_CC0 #28 TIM0_CC1 #27 TIM0_CC2 #26 TIM0_CDTI0 #25 TIM0_CDTI1 #24 TIM0_CDTI2 #23 TIM1_CC0 #28 TIM1_CC1 #27 TIM1_CC2 #26 TIM1_CC3 #25 LETIM0_OUT0 #28 LETIM0_OUT1 #27 PCNT0_S0IN #28 PCNT0_S1IN #27 US0_TX #28 US0_RX #27 US0_CLK #26 US0_CS #25 US0_CTS #24 US0_RTS #23 US1_TX #28 US1_RX #27 US1_CLK #26 US1_CS #25 US1_CTS #24 US1_RTS #23 US2_TX #17 US2_RX #16 US2_CLK #15 US2_CS #14 US2_CTS #13 US2_RTS #12 LEU0_TX #28 LEU0_RX #27 I2C0_SDA #28 I2C0_SCL #27 FRC_DCLK #28 FRC_DOUT #27 FRC_DFRAME #26 MODEM_DCLK #28 MODEM_DIN #27 MODEM_DOUT #26 PRS_CH0 #4 PRS_CH1 #3 PRS_CH2 #2 PRS_CH3 #1 ACMP0_O #28 ACMP1_O #28 Rev. 1.0 | 72 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Analog PF5 PF6 BUSAY BUSBX BUSBY BUSAX silabs.com | Building a more connected world. Timers Communication Radio Other TIM0_CC0 #29 TIM0_CC1 #28 TIM0_CC2 #27 TIM0_CDTI0 #26 TIM0_CDTI1 #25 TIM0_CDTI2 #24 TIM1_CC0 #29 TIM1_CC1 #28 TIM1_CC2 #27 TIM1_CC3 #26 LETIM0_OUT0 #29 LETIM0_OUT1 #28 PCNT0_S0IN #29 PCNT0_S1IN #28 US0_TX #29 US0_RX #28 US0_CLK #27 US0_CS #26 US0_CTS #25 US0_RTS #24 US1_TX #29 US1_RX #28 US1_CLK #27 US1_CS #26 US1_CTS #25 US1_RTS #24 US2_TX #18 US2_RX #17 US2_CLK #16 US2_CS #15 US2_CTS #14 US2_RTS #13 LEU0_TX #29 LEU0_RX #28 I2C0_SDA #29 I2C0_SCL #28 FRC_DCLK #29 FRC_DOUT #28 FRC_DFRAME #27 MODEM_DCLK #29 MODEM_DIN #28 MODEM_DOUT #27 PRS_CH0 #5 PRS_CH1 #4 PRS_CH2 #3 PRS_CH3 #2 ACMP0_O #29 ACMP1_O #29 TIM0_CC0 #30 TIM0_CC1 #29 TIM0_CC2 #28 TIM0_CDTI0 #27 TIM0_CDTI1 #26 TIM0_CDTI2 #25 TIM1_CC0 #30 TIM1_CC1 #29 TIM1_CC2 #28 TIM1_CC3 #27 LETIM0_OUT0 #30 LETIM0_OUT1 #29 PCNT0_S0IN #30 PCNT0_S1IN #29 US0_TX #30 US0_RX #29 US0_CLK #28 US0_CS #27 US0_CTS #26 US0_RTS #25 US1_TX #30 US1_RX #29 US1_CLK #28 US1_CS #27 US1_CTS #26 US1_RTS #25 US2_TX #19 US2_RX #18 US2_CLK #17 US2_CS #16 US2_CTS #15 US2_RTS #14 LEU0_TX #30 LEU0_RX #29 I2C0_SDA #30 I2C0_SCL #29 FRC_DCLK #30 FRC_DOUT #29 FRC_DFRAME #28 MODEM_DCLK #30 MODEM_DIN #29 MODEM_DOUT #28 CMU_CLK1 #7 PRS_CH0 #6 PRS_CH1 #5 PRS_CH2 #4 PRS_CH3 #3 ACMP0_O #30 ACMP1_O #30 Rev. 1.0 | 73 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions GPIO Name Pin Alternate Functionality / Description Analog PF7 BUSAY BUSBX silabs.com | Building a more connected world. Timers Communication TIM0_CC0 #31 TIM0_CC1 #30 TIM0_CC2 #29 TIM0_CDTI0 #28 TIM0_CDTI1 #27 TIM0_CDTI2 #26 TIM1_CC0 #31 TIM1_CC1 #30 TIM1_CC2 #29 TIM1_CC3 #28 LETIM0_OUT0 #31 LETIM0_OUT1 #30 PCNT0_S0IN #31 PCNT0_S1IN #30 US0_TX #31 US0_RX #30 US0_CLK #29 US0_CS #28 US0_CTS #27 US0_RTS #26 US1_TX #31 US1_RX #30 US1_CLK #29 US1_CS #28 US1_CTS #27 US1_RTS #26 US2_TX #20 US2_RX #19 US2_CLK #18 US2_CS #17 US2_CTS #16 US2_RTS #15 LEU0_TX #31 LEU0_RX #30 I2C0_SDA #31 I2C0_SCL #30 Radio Other FRC_DCLK #31 FRC_DOUT #30 FRC_DFRAME #29 MODEM_DCLK #31 MODEM_DIN #30 MODEM_DOUT #29 CMU_CLKI0 #1 CMU_CLK0 #7 PRS_CH0 #7 PRS_CH1 #6 PRS_CH2 #5 PRS_CH3 #4 ACMP0_O #31 ACMP1_O #31 GPIO_EM4WU1 Rev. 1.0 | 74 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions 6.3 Alternate Functionality Overview A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO pin. Refer to 6.2 GPIO Functionality Table for a list of functions available on each GPIO pin. Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0. Table 6.3. Alternate Functionality Overview Alternate Functionality ACMP0_O ACMP1_O LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 0: PA0 4: PA4 8: PB13 1: PA1 5: PA5 2: PA2 24 - 27 28 - 31 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 Description Analog comparator ACMP0, digital output. Analog comparator ACMP1, digital output. 0: PA0 Analog to digital converter ADC0 external reference input negative pin. 0: PA1 Analog to digital converter ADC0 external reference input positive pin. BOOT_RX 0: PF1 Bootloader RX. BOOT_TX 0: PF0 Bootloader TX. ADC0_EXTN ADC0_EXTP CMU_CLK0 CMU_CLK1 CMU_CLKI0 0: PA1 4: PD9 1: PB15 5: PD14 2: PC6 6: PF2 3: PC11 7: PF7 0: PA0 4: PD10 1: PB14 5: PD15 2: PC7 6: PF3 3: PC10 7: PF6 0: PB13 4: PA5 1: PF7 2: PC6 silabs.com | Building a more connected world. Clock Management Unit, clock output number 0. Clock Management Unit, clock output number 1. Clock Management Unit, clock input number 0. Rev. 1.0 | 75 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality LOCATION 0-3 4-7 0: PF0 DBG_SWCLKTCK DBG_SWDIOTMS 1: PB13 2: PD15 3: PC11 0: PF3 20 - 23 24 - 27 28 - 31 Description Debug-interface Serial Wire clock input and JTAG Test Clock. Debug-interface Serial Wire data input / output and JTAG Test Mode Select. Debug-interface Serial Wire viewer Output. Note that this function is not enabled after reset, and must be enabled by software to be used. Debug-interface JTAG Test Data In. Note that this function becomes available after the first valid JTAG command is received, and has a built-in pull up when JTAG is active. DBG_TDI 0: PF2 Debug-interface JTAG Test Data Out. Note that this function becomes available after the first valid JTAG command is received. DBG_TDO ETM_TD0 16 - 19 Note that this function is enabled to the pin out of reset, and has a built-in pull up. 0: PF2 ETM_TCLK 12 - 15 Note that this function is enabled to the pin out of reset, and has a built-in pull down. 0: PF1 DBG_SWO 8 - 11 1: PA5 3: PC6 3: PC7 silabs.com | Building a more connected world. Embedded Trace Module ETM clock . Embedded Trace Module ETM data 0. Rev. 1.0 | 76 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality ETM_TD1 ETM_TD2 ETM_TD3 FRC_DCLK FRC_DFRAME FRC_DOUT GPIO_EM4WU0 GPIO_EM4WU1 GPIO_EM4WU4 GPIO_EM4WU8 GPIO_EM4WU9 GPIO_EM4WU12 I2C0_SCL LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description 3: PC8 Embedded Trace Module ETM data 1. 3: PC9 Embedded Trace Module ETM data 2. 3: PC10 Embedded Trace Module ETM data 3. 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA2 4: PB11 8: PB15 12: PC9 16: PD10 20: PD14 24: PF2 28: PF6 1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 3: PA5 7: PB14 11: PC8 15: PD9 19: PD13 23: PF1 27: PF5 31: PA1 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 Frame Controller, Data Sniffer Clock. Frame Controller, Data Sniffer Frame active Frame Controller, Data Sniffer Output. 0: PF2 Pin can be used to wake the system up from EM4 0: PF7 Pin can be used to wake the system up from EM4 0: PD14 Pin can be used to wake the system up from EM4 0: PA3 Pin can be used to wake the system up from EM4 0: PB13 Pin can be used to wake the system up from EM4 0: PC10 Pin can be used to wake the system up from EM4 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 silabs.com | Building a more connected world. I2C0 Serial Clock Line input / output. Rev. 1.0 | 77 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality I2C0_SDA LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 0: PA0 4: PA4 8: PB13 1: PA1 5: PA5 2: PA2 3: PA3 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 19: PC10 LES_CH3 LES_CH4 LES_CH5 LES_CH6 LES_CH7 LES_CH8 LES_CH9 LES_CH10 LES_CH11 LES_CH12 LES_CH13 LETIM0_OUT0 LETIM0_OUT1 Description I2C0 Serial Data input / output. I2C1 Serial Clock Line input / output. 19: PC11 I2C1_SDA LES_CH2 28 - 31 18: PC10 I2C1_SCL LES_CH1 24 - 27 20: PC11 I2C1 Serial Data input / output. 0: PD9 LESENSE channel 1. 0: PD10 LESENSE channel 2. 0: PD11 LESENSE channel 3. 0: PD12 LESENSE channel 4. 0: PD13 LESENSE channel 5. 0: PD14 LESENSE channel 6. 0: PD15 LESENSE channel 7. 0: PA0 LESENSE channel 8. 0: PA1 LESENSE channel 9. 0: PA2 LESENSE channel 10. 0: PA3 LESENSE channel 11. 0: PA4 LESENSE channel 12. 0: PA5 LESENSE channel 13. 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 silabs.com | Building a more connected world. Low Energy Timer LETIM0, output channel 0. Low Energy Timer LETIM0, output channel 1. Rev. 1.0 | 78 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality LEU0_RX LEU0_TX MODEM_DCLK MODEM_DIN MODEM_DOUT OPA0_N OPA0_P OPA1_N OPA1_P OPA2_N OPA2_OUT OPA2_P LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 0: PA2 4: PB11 8: PB15 12: PC9 16: PD10 20: PD14 24: PF2 28: PF6 1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 3: PA5 7: PB14 11: PC8 15: PD9 19: PD13 23: PF1 27: PF5 31: PA1 Description LEUART0 Receive input. LEUART0 Transmit output. Also used as receive input in half duplex communication. MODEM data clock out. MODEM data in. MODEM data out. 0: PA4 Operational Amplifier 0 external negative input. 0: PA2 Operational Amplifier 0 external positive input. 0: PD15 Operational Amplifier 1 external negative input. 0: PD13 Operational Amplifier 1 external positive input. 0: PB13 Operational Amplifier 2 external negative input. 0: PB12 Operational Amplifier 2 output. 0: PB11 Operational Amplifier 2 external positive input. silabs.com | Building a more connected world. Rev. 1.0 | 79 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality PCNT0_S0IN PCNT0_S1IN PRS_CH0 PRS_CH1 PRS_CH2 PRS_CH3 PRS_CH4 LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 0: PA0 4: PA4 8: PB13 1: PA1 5: PA5 2: PA2 24 - 27 28 - 31 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 0: PF0 4: PF4 8: PC6 12: PC10 1: PF1 5: PF5 9: PC7 13: PC11 2: PF2 6: PF6 10: PC8 3: PF3 7: PF7 11: PC9 0: PF1 4: PF5 1: PF2 5: PF6 2: PF3 6: PF7 3: PF4 7: PF0 0: PF2 4: PF6 1: PF3 5: PF7 2: PF4 6: PF0 3: PF5 7: PF1 0: PF3 4: PF7 8: PD9 12: PD13 1: PF4 5: PF0 9: PD10 13: PD14 2: PF5 6: PF1 10: PD11 14: PD15 3: PF6 7: PF2 11: PD12 0: PD9 4: PD13 1: PD10 5: PD14 2: PD11 6: PD15 Description Pulse Counter PCNT0 input number 0. Pulse Counter PCNT0 input number 1. Peripheral Reflex System PRS, channel 0. Peripheral Reflex System PRS, channel 1. Peripheral Reflex System PRS, channel 2. Peripheral Reflex System PRS, channel 3. Peripheral Reflex System PRS, channel 4. 3: PD12 PRS_CH5 0: PD10 4: PD14 1: PD11 5: PD15 2: PD12 6: PD9 Peripheral Reflex System PRS, channel 5. 3: PD13 PRS_CH6 0: PA0 4: PA4 8: PB13 12: PD10 16: PD14 1: PA1 5: PA5 9: PB14 13: PD11 17: PD15 2: PA2 6: PB11 10: PB15 14: PD12 3: PA3 7: PB12 11: PD9 15: PD13 silabs.com | Building a more connected world. Peripheral Reflex System PRS, channel 6. Rev. 1.0 | 80 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality PRS_CH7 PRS_CH8 PRS_CH9 PRS_CH10 LOCATION 0-3 4-7 8 - 11 12 - 15 0: PA1 4: PA5 8: PB14 1: PA2 5: PB11 9: PB15 2: PA3 6: PB12 10: PA0 3: PA4 7: PB13 0: PA2 4: PB11 8: PB15 1: PA3 5: PB12 9: PA0 2: PA4 6: PB13 10: PA1 3: PA5 7: PB14 0: PA3 4: PB12 8: PA0 12: PC7 1: PA4 5: PB13 9: PA1 13: PC8 2: PA5 6: PB14 10: PA2 14: PC9 3: PB11 7: PB15 11: PC6 15: PC10 0: PC6 4: PC10 1: PC7 5: PC11 16 - 19 20 - 23 24 - 27 28 - 31 Description Peripheral Reflex System PRS, channel 7. Peripheral Reflex System PRS, channel 8. 16: PC11 Peripheral Reflex System PRS, channel 9. Peripheral Reflex System PRS, channel 10. 2: PC8 3: PC9 PRS_CH11 0: PC7 4: PC11 1: PC8 5: PC6 Peripheral Reflex System PRS, channel 11. 2: PC9 3: PC10 TIM0_CC0 TIM0_CC1 TIM0_CC2 TIM0_CDTI0 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 0: PA2 4: PB11 8: PB15 12: PC9 16: PD10 20: PD14 24: PF2 28: PF6 1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 3: PA5 7: PB14 11: PC8 15: PD9 19: PD13 23: PF1 27: PF5 31: PA1 0: PA3 4: PB12 8: PC6 12: PC10 16: PD11 20: PD15 24: PF3 28: PF7 1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 3: PB11 7: PB15 11: PC9 15: PD10 19: PD14 23: PF2 27: PF6 31: PA2 silabs.com | Building a more connected world. Timer 0 Capture Compare input / output channel 0. Timer 0 Capture Compare input / output channel 1. Timer 0 Capture Compare input / output channel 2. Timer 0 Complimentary Dead Time Insertion channel 0. Rev. 1.0 | 81 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality TIM0_CDTI1 TIM0_CDTI2 TIM1_CC0 TIM1_CC1 TIM1_CC2 TIM1_CC3 US0_CLK US0_CS US0_CTS LOCATION 0-3 4-7 0: PA4 4: PB13 1: PA5 12 - 15 16 - 19 8: PC7 12: PC11 16: PD12 20: PF0 24: PF4 28: PA0 5: PB14 9: PC8 13: PD9 17: PD13 21: PF1 25: PF5 29: PA1 2: PB11 6: PB15 10: PC9 14: PD10 18: PD14 22: PF2 26: PF6 30: PA2 3: PB12 7: PC6 11: PC10 15: PD11 19: PD15 23: PF3 27: PF7 31: PA3 0: PA5 4: PB14 8: PC8 12: PD9 16: PD13 20: PF1 24: PF5 28: PA1 1: PB11 5: PB15 9: PC9 13: PD10 17: PD14 21: PF2 25: PF6 29: PA2 2: PB12 6: PC6 10: PC10 14: PD11 18: PD15 22: PF3 26: PF7 30: PA3 3: PB13 7: PC7 11: PC11 15: PD12 19: PF0 23: PF4 27: PA0 31: PA4 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 0: PA2 4: PB11 8: PB15 12: PC9 16: PD10 20: PD14 24: PF2 28: PF6 1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 3: PA5 7: PB14 11: PC8 15: PD9 19: PD13 23: PF1 27: PF5 31: PA1 0: PA3 4: PB12 8: PC6 12: PC10 16: PD11 20: PD15 24: PF3 28: PF7 1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 3: PB11 7: PB15 11: PC9 15: PD10 19: PD14 23: PF2 27: PF6 31: PA2 0: PA2 4: PB11 8: PB15 12: PC9 16: PD10 20: PD14 24: PF2 28: PF6 1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 3: PA5 7: PB14 11: PC8 15: PD9 19: PD13 23: PF1 27: PF5 31: PA1 0: PA3 4: PB12 8: PC6 12: PC10 16: PD11 20: PD15 24: PF3 28: PF7 1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 3: PB11 7: PB15 11: PC9 15: PD10 19: PD14 23: PF2 27: PF6 31: PA2 0: PA4 4: PB13 8: PC7 12: PC11 16: PD12 20: PF0 24: PF4 28: PA0 1: PA5 5: PB14 9: PC8 13: PD9 17: PD13 21: PF1 25: PF5 29: PA1 2: PB11 6: PB15 10: PC9 14: PD10 18: PD14 22: PF2 26: PF6 30: PA2 3: PB12 7: PC6 11: PC10 15: PD11 19: PD15 23: PF3 27: PF7 31: PA3 silabs.com | Building a more connected world. 8 - 11 20 - 23 24 - 27 28 - 31 Description Timer 0 Complimentary Dead Time Insertion channel 1. Timer 0 Complimentary Dead Time Insertion channel 2. Timer 1 Capture Compare input / output channel 0. Timer 1 Capture Compare input / output channel 1. Timer 1 Capture Compare input / output channel 2. Timer 1 Capture Compare input / output channel 3. USART0 clock input / output. USART0 chip select input / output. USART0 Clear To Send hardware flow control input. Rev. 1.0 | 82 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality US0_RTS US0_RX US0_TX US1_CLK US1_CS US1_CTS US1_RTS US1_RX LOCATION 0-3 4-7 0: PA5 4: PB14 8: PC8 12: PD9 16: PD13 20: PF1 24: PF5 28: PA1 1: PB11 5: PB15 9: PC9 13: PD10 17: PD14 21: PF2 25: PF6 29: PA2 2: PB12 6: PC6 10: PC10 14: PD11 18: PD15 22: PF3 26: PF7 30: PA3 3: PB13 7: PC7 11: PC11 15: PD12 19: PF0 23: PF4 27: PA0 31: PA4 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 0: PA0 4: PA4 8: PB13 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 1: PA1 5: PA5 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 2: PA2 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 3: PA3 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 0: PA2 4: PB11 8: PB15 12: PC9 16: PD10 20: PD14 24: PF2 28: PF6 1: PA3 5: PB12 9: PC6 13: PC10 17: PD11 21: PD15 25: PF3 29: PF7 2: PA4 6: PB13 10: PC7 14: PC11 18: PD12 22: PF0 26: PF4 30: PA0 3: PA5 7: PB14 11: PC8 15: PD9 19: PD13 23: PF1 27: PF5 31: PA1 0: PA3 4: PB12 8: PC6 12: PC10 16: PD11 20: PD15 24: PF3 28: PF7 1: PA4 5: PB13 9: PC7 13: PC11 17: PD12 21: PF0 25: PF4 29: PA0 2: PA5 6: PB14 10: PC8 14: PD9 18: PD13 22: PF1 26: PF5 30: PA1 3: PB11 7: PB15 11: PC9 15: PD10 19: PD14 23: PF2 27: PF6 31: PA2 0: PA4 4: PB13 8: PC7 12: PC11 16: PD12 20: PF0 24: PF4 28: PA0 1: PA5 5: PB14 9: PC8 13: PD9 17: PD13 21: PF1 25: PF5 29: PA1 2: PB11 6: PB15 10: PC9 14: PD10 18: PD14 22: PF2 26: PF6 30: PA2 3: PB12 7: PC6 11: PC10 15: PD11 19: PD15 23: PF3 27: PF7 31: PA3 0: PA5 4: PB14 8: PC8 12: PD9 16: PD13 20: PF1 24: PF5 28: PA1 1: PB11 5: PB15 9: PC9 13: PD10 17: PD14 21: PF2 25: PF6 29: PA2 2: PB12 6: PC6 10: PC10 14: PD11 18: PD15 22: PF3 26: PF7 30: PA3 3: PB13 7: PC7 11: PC11 15: PD12 19: PF0 23: PF4 27: PA0 31: PA4 0: PA1 4: PA5 8: PB14 12: PC8 16: PD9 20: PD13 24: PF1 28: PF5 1: PA2 5: PB11 9: PB15 13: PC9 17: PD10 21: PD14 25: PF2 29: PF6 2: PA3 6: PB12 10: PC6 14: PC10 18: PD11 22: PD15 26: PF3 30: PF7 3: PA4 7: PB13 11: PC7 15: PC11 19: PD12 23: PF0 27: PF4 31: PA0 silabs.com | Building a more connected world. 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description USART0 Request To Send hardware flow control output. USART0 Asynchronous Receive. USART0 Synchronous mode Master Input / Slave Output (MISO). USART0 Asynchronous Transmit. Also used as receive input in half duplex communication. USART0 Synchronous mode Master Output / Slave Input (MOSI). USART1 clock input / output. USART1 chip select input / output. USART1 Clear To Send hardware flow control input. USART1 Request To Send hardware flow control output. USART1 Asynchronous Receive. USART1 Synchronous mode Master Input / Slave Output (MISO). Rev. 1.0 | 83 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality US1_TX LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 0: PA0 4: PA4 8: PB13 1: PA1 5: PA5 2: PA2 3: PA3 12: PC7 16: PC11 20: PD12 24: PF0 28: PF4 9: PB14 13: PC8 17: PD9 21: PD13 25: PF1 29: PF5 6: PB11 10: PB15 14: PC9 18: PD10 22: PD14 26: PF2 30: PF6 7: PB12 11: PC6 15: PC10 19: PD11 23: PD15 27: PF3 31: PF7 12: PF0 16: PF5 13: PF1 17: PF6 14: PF3 18: PF7 US2_CLK 24 - 27 28 - 31 Description USART1 Asynchronous Transmit. Also used as receive input in half duplex communication. USART1 Synchronous mode Master Output / Slave Input (MOSI). 30: PA5 USART2 clock input / output. 15: PF4 11: PF0 US2_CS 12: PF1 16: PF6 13: PF3 17: PF7 29: PA5 USART2 chip select input / output. 14: PF4 15: PF5 US2_CTS 10: PF0 12: PF3 11: PF1 13: PF4 16: PF7 28: PA5 USART2 Clear To Send hardware flow control input. 14: PF5 15: PF6 US2_RTS 9: PF0 12: PF4 10: PF1 13: PF5 11: PF3 14: PF6 27: PA5 USART2 Request To Send hardware flow control output. 15: PF7 US2_RX 13: PF0 16: PF4 14: PF1 17: PF5 15: PF3 18: PF6 31: PA5 USART2 Synchronous mode Master Input / Slave Output (MISO). 19: PF7 0: PA5 14: PF0 16: PF3 15: PF1 17: PF4 18: PF5 US2_TX 19: PF6 0: PA1 VDAC0_EXT silabs.com | Building a more connected world. USART2 Asynchronous Receive. 20: PF7 USART2 Asynchronous Transmit. Also used as receive input in half duplex communication. USART2 Synchronous mode Master Output / Slave Input (MOSI). Digital to analog converter VDAC0 external reference input pin. Rev. 1.0 | 84 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Alternate Functionality VDAC0_OUT0 / OPA0_OUT VDAC0_OUT0AL T / OPA0_OUTALT VDAC0_OUT1 / OPA1_OUT VDAC0_OUT1AL T / OPA1_OUTALT WTIM0_CC0 WTIM0_CC1 LOCATION 0-3 4-7 8 - 11 12 - 15 16 - 19 20 - 23 Description Digital to Analog Converter DAC0 output channel number 0. 0: PA5 Digital to Analog Converter DAC0 alternative output for channel 0. 1: PD13 2: PD15 0: PD14 Digital to Analog Converter DAC0 output channel number 1. 0: PD12 Digital to Analog Converter DAC0 alternative output for channel 1. 1: PA2 2: PA4 0: PA0 4: PA4 1: PA1 5: PA5 15: PB11 16: PB12 26: PC6 28: PC8 17: PB13 27: PC7 29: PC9 2: PA2 18: PB14 30: PC10 3: PA3 19: PB15 31: PC11 0: PA2 13: PB11 16: PB14 24: PC6 28: PC10 1: PA3 14: PB12 17: PB15 25: PC7 29: PC11 2: PA4 15: PB13 26: PC8 31: PD9 11: PB11 1: PA5 7: PB11 WTIM0_CDTI0 WTIM0_CDTI1 12: PB12 22: PC6 24: PC8 29: PD9 13: PB13 23: PC7 25: PC9 30: PD10 14: PB14 26: PC10 31: PD11 15: PB15 27: PC11 8: PB12 18: PC6 20: PC8 25: PD9 28: PD12 9: PB13 19: PC7 21: PC9 26: PD10 29: PD13 10: PB14 22: PC10 27: PD11 30: PD14 11: PB15 23: PC11 Wide timer 0 Capture Compare input / output channel 1. 8: PB14 16: PC6 20: PC10 24: PD10 28: PD14 6: PB12 9: PB15 17: PC7 21: PC11 25: PD11 29: PD15 18: PC8 23: PD9 26: PD12 30: PF0 27: PD13 31: PF1 19: PC9 4: PB12 14: PC6 16: PC8 21: PD9 24: PD12 28: PF0 5: PB13 15: PC7 17: PC9 22: PD10 25: PD13 29: PF1 6: PB14 18: PC10 23: PD11 26: PD14 30: PF2 7: PB15 19: PC11 27: PD15 31: PF3 silabs.com | Building a more connected world. Wide timer 0 Capture Compare input / output channel 2. Wide timer 0 Complimentary Dead Time Insertion channel 0. 31: PD15 5: PB11 7: PB13 3: PB11 Wide timer 0 Capture Compare input / output channel 0. 27: PC9 0: PA4 WTIM0_CDTI2 28 - 31 0: PA3 3: PA5 WTIM0_CC2 24 - 27 Wide timer 0 Complimentary Dead Time Insertion channel 1. Wide timer 0 Complimentary Dead Time Insertion channel 2. Rev. 1.0 | 85 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Certain alternate function locations may have non-interference priority. These locations will take precedence over any other functions selected on that pin (i.e. another alternate function enabled to the same pin inadvertently). Some alternate functions may also have high speed priority on certain locations. These locations ensure the fastest possible paths to the pins for timing-critical signals. The following table lists the alternate functions and locations with special priority. Table 6.4. Alternate Functionality Priority Alternate Functionality Location Priority CMU_CLKI0 1: PF7 High Speed silabs.com | Building a more connected world. Rev. 1.0 | 86 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions 6.4 Analog Port (APORT) Client Maps The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs, DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal routing. Figure 6.2 APORT Connection Diagram on page 87 shows the APORT routing for this device family (note that available features may vary by part number). A complete description of APORT functionality can be found in the Reference Manual. PF1 ACMP0 PF2 NEG PF3 PF4 PF5 1X 2X 3X 4X NEXT0 NEXT2 NEG 1Y 2Y 3Y 4Y NEXT1 ADC0 AX AY BX BY EXTP EXTN POS OPA0 NEG OUT POS OPA2 DY DX CY CX PB13 NEG OPA2_N OUT2 1X IDAC0 OPA1_P 1X 2X 3X 4X POS OPA1_N 1Y 2Y 3Y 4Y NEG OUT1 OUT1ALT OUT1 OUT2 OUT3 OUT4 NEXT1 1Y OUT0ALT OPA0_N OUT1ALT OUT0 OPA1 OUT OUT2 OUT2ALT OUT1 OUT2 OUT3 OUT4 NEXT2 VDAC0_OUT0ALT VDAC0_OUT1ALT PA5 PA4 PA3 OPA0_P OUT1ALT ADC_EXTP OUT VDAC0_OUT1ALT PA1 ADC_EXTN PA0 OPA1_N OUT0ALT PA2 PD15 VDAC0_OUT0ALT OUT1 OPA2_N 1Y 2Y 3Y 4Y PB11 OPA2_P OPA2_P 1X 2X 3X 4X NEG PB12 1X 1Y 3X 3Y 2X 2Y 4X 4Y VDAC0_OUT0ALT BUSAX, BUSBY, ... PB14 OPA1_P APORTnX, APORTnY AX, BY, ... OUT0 OUT0ALT OUT1 OUT2 OUT3 OUT4 NEXT0 PB15 ACMP1 VDAC0_OUT0ALT CEXT_SENSE OPA0_N 1Y 2Y 3Y 4Y 1Y 2Y 3Y 4Y NEXT1 NEXT0 POS OUT0ALT CSEN OPA0_P 1X 2X 3X 4X 1X 2X 3X 4X NEXT1 NEXT0 OUT1ALT CEXT nX, nY 1Y 2Y 3Y 4Y NEXT1 NEXT0 POS PF6 PF7 PC6 PC7 PC9 PC8 PC10 PC11 POS PF0 1X 2X 3X 4X NEXT1 NEXT0 PD14 PD13 PD12 PD11 PD10 PD9 Figure 6.2. APORT Connection Diagram Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins. silabs.com | Building a more connected world. Rev. 1.0 | 87 ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin connection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared bus used by this connection is indicated in the Bus column. CH0 CH1 CH2 CH3 CH4 CH5 CH6 PC6 PD10 PD9 PD11 PD9 PD10 PD12 PD11 PD13 PD13 PD14 PD15 PA0 PD12 PC6 PD14 PD15 PA0 PA1 PA1 PA2 CH7 PC8 PC7 PC7 PC8 PC9 PC10 PA4 PA3 PA3 PA4 PA5 PA2 PF0 CH8 CH9 PC9 PC11 PC11 PF1 PF1 PA5 silabs.com | Building a more connected world. CH10 PC10 CH11 CH12 CH13 CH14 CH15 CH16 PF0 CH17 CH18 PF2 PF4 PF3 PF3 PF2 CH19 CH20 PF4 CH21 PB11 PB11 PB12 PB13 PB13 PB14 PB14 PB15 PB15 PB12 PF6 PF5 PF7 PF7 PF5 PF6 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus BUSAX BUSAY BUSBX BUSBY BUSCX BUSCY BUSDX BUSDY APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port Table 6.5. ACMP0 Bus and Pin Mapping Rev. 1.0 | 88 silabs.com | Building a more connected world. PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PA5 PA3 PB11 PB11 PB13 PB15 PB15 PB13 BUSCY BUSDX PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSCX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSBX PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Table 6.6. ACMP1 Bus and Pin Mapping Rev. 1.0 | 89 silabs.com | Building a more connected world. PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PD9 PD11 PD13 PD15 PA1 PA3 PA5 PA5 PA3 PB11 PB11 PB13 PB15 PB15 PB13 BUSCY BUSDX PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSCX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSBX PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT4Y APORT4X APORT3Y APORT3X APORT2Y APORT2X APORT1Y APORT1X Port ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Table 6.7. ADC0 Bus and Pin Mapping Rev. 1.0 | 90 silabs.com | Building a more connected world. PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSCX CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus APORT1Y APORT1X Port PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSDX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSBX APORT4Y APORT4X APORT2Y APORT2X PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSCX PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX APORT3Y APORT3X APORT1Y APORT1X CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus Port ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Table 6.8. CSEN Bus and Pin Mapping CEXT CEXT_SENSE Table 6.9. IDAC0 Bus and Pin Mapping Rev. 1.0 | 91 silabs.com | Building a more connected world. PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSDX PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSCX PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSBX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX APORT4X APORT3X APORT2X APORT1X PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY APORT4Y APORT3Y APORT2Y APORT1Y CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus Port ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions Table 6.10. VDAC0 / OPA Bus and Pin Mapping OPA0_N OPA0_P Rev. 1.0 | 92 silabs.com | Building a more connected world. PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY APORT4Y APORT3Y APORT2Y APORT1Y PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSDX PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSCX PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSBX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX APORT4X APORT3X APORT2X APORT1X PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY APORT4Y APORT3Y APORT2Y APORT1Y CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus Port ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions OPA1_N OPA1_P OPA2_N Rev. 1.0 | 93 silabs.com | Building a more connected world. PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY APORT4Y APORT3Y APORT2Y APORT1Y PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSDX PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSCX PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSBX PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSAX APORT4X APORT3X APORT2X APORT1X PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY APORT4Y APORT3Y APORT2Y APORT1Y CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus Port ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions OPA2_OUT OPA2_P VDAC0_OUT0 / OPA0_OUT Rev. 1.0 | 94 silabs.com | Building a more connected world. PD10 PD12 PD14 PA0 PA2 PA4 PB12 PB14 BUSDY PD9 PD11 PD13 PD15 PA1 PA3 PA5 PB11 PB13 PB15 BUSCY PC6 PC8 PC10 PF0 PF2 PF4 PF6 BUSBY PC7 PC9 PC11 PF1 PF3 PF5 PF7 BUSAY APORT4Y APORT3Y APORT2Y APORT1Y CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31 Bus Port ZGM130S Z-Wave 700 SiP Module Data Sheet Pin Definitions VDAC0_OUT1 / OPA1_OUT Rev. 1.0 | 95 ZGM130S Z-Wave 700 SiP Module Data Sheet LGA64 Package Specifications 7. LGA64 Package Specifications L1 64 49 7.1 LGA64 Package Dimensions 1 b L 17 32 e/2 e e/2 64X SMT PAD ddd C A B BOTTOM VIEW Figure 7.1. LGA64 Package Drawing silabs.com | Building a more connected world. Rev. 1.0 | 96 ZGM130S Z-Wave 700 SiP Module Data Sheet LGA64 Package Specifications Table 7.1. LGA64 Package Dimensions Dimension Min Typ Max A 1.12 1.21 1.30 A1 0.17 0.21 0.25 b 0.20 0.25 0.30 D 9.00 BSC e 0.50 BSC E 9.00 BSC L 0.30 0.35 0.40 L1 0.10 0.15 0.20 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.10 Note: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.0 | 97 ZGM130S Z-Wave 700 SiP Module Data Sheet LGA64 Package Specifications 7.2 LGA64 PCB Land Pattern 64 X Y 1 17 C2 C1 Figure 7.2. LGA64 PCB Land Pattern Drawing Table 7.2. LGA64 PCB Land Pattern Dimensions Dimension Typ C1 8.50 C2 8.50 X 0.30 Y 0.35 Note: 1. All dimensions shown are in millimeters (mm). 2. This Land Pattern Design is based on the IPC-7351 guidelines. 3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05mm. 4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60mm minimum, all the way around the pad. 5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. The stencil thickness should be 0.125mm (5 mils). 7. The ratio of stencil aperture to land pad size should be 1:1 for all pads. 8. A No-Clean, Type-3 solder paste is recommended. 9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.0 | 98 ZGM130S Z-Wave 700 SiP Module Data Sheet Revision History 8. Revision History Revision 1.0 May 2019 * Added bullet about optional SAW filter to front page and feature lists. * Table 4.11 Sub-GHz RF Transmitter characteristics for 868 MHz Band on page 28 : Updated POUTMAX footnote with details about SAW insertion loss. * Table 4.9 Sub-GHz RF Transmitter characteristics for 915 MHz Band on page 25 : Updated POUTMAX footnote with details about SAW insertion loss. Revision 0.5 January 2019 * Updated electrical characteristics with latest characterization results. Revision 0.2 December 2018 * Crystal frequency changed to 39 MHz. * Updated electrical characteristics with latest characterization estimates. * Table 4.9 Sub-GHz RF Transmitter characteristics for 915 MHz Band on page 25: PSD conditions updated to specify PSD at each data rate. * Table 6.3 Alternate Functionality Overview on page 75: Table formatting update. Revision 0.1 August 2018 * Initial Release. silabs.com | Building a more connected world. Rev. 1.0 | 99 Simplicity Studio One-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux! IoT Portfolio www.silabs.com/IoT SW/HW www.silabs.com/simplicity Quality www.silabs.com/quality Support and Community community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. 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