INTEGRATED CIRCUITS PLC18V8Z Zero standby power CMOS versatile PAL devices Product specification Replaces data sheet PLC18V8Z35/PLC18V8ZI of Dec 19 1995, and data sheet PLC18V8Z25/PLC18V8ZI of Dec 19, 1995 1997 Aug 08 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z * Industrial control * Medical Instruments * Portable communications equipment DESCRIPTION The PLC18V8Z is a universal PAL device featuring high performance and virtually zero-standby power for power sensitive applications. They are reliable, user-configurable substitutes for discrete TTL/CMOS logic. While compatible with TTL and HCT logic, the PLC18V8Z can also replace HC logic over the VCC range of 4.5 to 5.5V. PIN CONFIGURATIONS D, DB, DH, N, Packages The PLC18V8Z is a two-level logic element comprised of 10 inputs, 74 AND gates (product terms) and 8 output Macro cells. I0/CLK 1 20 VCC I1 2 19 F7 I2 3 18 F6 I3 4 17 F5 I4 5 16 F4 I5 6 15 F3 I6 7 14 F2 I7 8 13 F1 I8 9 12 F0 Each output features an "Output Macro Cell" which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback. As a result, the PLC18V8Z is capable of emulating all common 20-pin PAL devices to reduce documentation, inventory, and manufacturing costs. A power-up reset function and a Register Preload function have been incorporated in the PLC18V8Z architecture to facilitate state machine design and testing. With a standby current of less than 100A and active power consumption of 1.5mA/MHz, the PLC18V8Z is ideally suited for power sensitive applications in battery operated/backed portable instruments and computers. GND 10 11 I9/OE D = Plasitc Small Outline Large Package (300mil-wide) DB = Plastic Shrink Small Outline Package (5.3mm wide) DH = Plastic Thin Shrink Small Outline Package (4.4mm wide) N = Plastic Dual In-Line Package (DIP) (300mil-wide) The PLC18V8Z is also processed to industrial requirements for operation over an extended temperature range of -40C to +85C and supply voltage of 4.5V to 5.5V. Ordering information can be found on the following page. A Package FEATURES * 20-pin Universal Programmable Array Logic * Virtually Zero-Standby-power - 20A (typical) * Available in DIP, PLCC, SOL (Small Outline), SSOP (Shrink Small Outline), and TSSOP (Thin Shrink Small Outline) packages I2 I0/ I1 CLK VCC F7 3 2 1 20 19 I3 4 18 F6 I4 5 17 F5 I5 6 16 F4 I6 7 15 F3 I7 8 14 F2 9 * Functional replacement for Series 20 PAL devices 10 11 12 13 I8 GND I9/ F0 F1 OE - IOL = 24mA A = Plastic Leaded Chip Carrier * Up to 18 inputs and 8 input/output macro cells * Programmable output polarity * Power-up reset on all registers * Register Preload capability * Synchronous Preset/Asynchronous Reset * Security fuse to prevent duplication of proprietary designs * Also available in 3V operation-the P3C18V8Z SP00544 PIN DESCRIPTIONS APPLICATIONS * Battery powered instruments * Laptop and pocket computers I Dedicated Input B Bidirectional input/output O Dedicated output D Registered output (D-type flip-flop) F Output/Input Macrocell CLK Clock Input OE Output Enable VCC Supply Voltage GND Ground PAL is a registered trademark of Advanced Micro Devices, Inc. 1997 Aug 08 2 853-2016 18258 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 20-Pin (300mil-wide) Plastic Dual In-Line Package, 25ns tPD PLC18V8Z25N SOT146-1 20-Pin (350mil square) Plastic Leaded Chip Carrier Package PLC18V8Z25A SOT380-1 20-Pin (300mil-wide) Plastic Small Outline Large Package PLC18V8Z25D SOT163-1 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package PLC18V8Z25DB SOT339-1 PLC18V8Z25DH SOT360-1 DESCRIPTION Commercial Temperature Range 5% Power Supplies 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package 20-Pin (300mil-wide) Plastic Dual In-Line Package. 35ns tPD PLC18V8Z35N SOT146-1 20-Pin (350mil square) Plastic Leaded Chip Carrier Package PLC18V8Z35A SOT380-1 20-Pin (300mil square) Plastic Small Outline Large Package Package PLC18V8Z35D SOT163-1 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package PLC18V8Z35DB SOT339-1 20-Pin (4.4mm-wide) Plastic Thin shrink Small Outline Package PLC18V8Z35DH SOT260-1 20-Pin (300mil-wide) Plastic Dual In-Line Package 25ns tPD PLC18V8ZIAN SOT146-1 20-Pin (350mil square) Plastic Leaded Chip Carrier Package PLC18V8ZIAA SOT380-1 20-Pin (300mil-wide) Plastic Small Outline Large Package PLC18V8ZIAD SOT163-1 PLC18V8ZIADB SOT339-1 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package Industrial Temperature Range 10% Power Supplies 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package PLC18V8ZIADH SOT360-1 PLC18V8ZIN SOT146-1 20-Pin (350mil square) Plastic Leaded chip Carrier Package PLC18V8ZIA SOT380-1 20-Pin (300mil square) Plastic Small Outline Large Package PLC18V8ZZID SOT163-1 20-Pin (5.3mm-wide) Plastic Shrink Small Outline Package PLC18V8ZIDB SOT339-1 20-Pin (4.4mm-wide) Plastic Thin Shrink Small Outline Package PLC18V8ZIDH SOT360-1 20-Pin (300mil-wide) Plastic Dual In-Line Package, 40ns tPD 1997 Aug 08 3 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z PAL DEVICE TO PLC18V8Z OUTPUT PIN CONFIGURATION CROSS REFERENCE PIN NO. PLC 18V8Z 16L8 16H8 16P8 16P8 16R4 16RP4 16R6 16RP6 16R8 16RP8 16L2 16H2 16P2 14L4 14H4 14P4 12L6 12H6 12P6 10L8 10H8 10P8 1 I0/CLK I CLK CLK CLK I I I I 19 F7 B B B D I I I O 18 F6 B B D D I I O O 17 F5 B D D D I O O O 16 F4 B D D D O O O O 15 F3 B D D D O O O O 14 F2 B D D D I O O O 13 F1 B B D D I I O O 12 F0 B B B D I I I O 11 I9/OE I OE OE OE I I I I The Philips Semiconductors' state-of-the-art Floating-Gate CMOS EPROM process yields bipolar equivalent performance at less than one-quarter the power consumption. The erasable nature of the EPROM process enables Philips Semiconductors to functionally test the devices prior to shipment to the customer. Additionally, this allows Philips Semiconductors to extensively stress test, as well as ensure the threshold voltage of each individual EPROM cell. 100% programming yield is subsequently guaranteed. FUNCTIONAL DIAGRAM I0/ CLK I0 CONFIG. CELL 9 I1 I7 PROGRAMMABLE AND ARRAY 36 ROWS X 72 COLUMNS I2 OMC F7 CLK 9 OMC F6 OMC F1 OMC F0 9 9 I8 SP AR OE CONFIG. CELL I9/OE I9 SP00013 1997 Aug 08 4 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z LOGIC DIAGRAM 0 4 8 12 16 20 24 28 32 35 I0/CLK 1 CLK DIR SP 19 F7 AC1 AC2 AR I1 2 DIR CLK OE SP I2 18 F6 AC1 AC2 AR 3 DIR CLK OE SP I3 4 DIR AC1 AC2 AR CLK OE 17 F5 SP I4 5 DIR AC1 AC2 AR CLK OE 16 F4 SP I5 6 DIR AC1 AC2 AR CLK OE 15 F3 SP I6 7 DIR AC1 AC2 AR CLK OE 14 F2 SP I7 8 DIR AC1 AC2 AR CLK OE 13 F1 SP I8 AC1 AC2 AR CLK OE 9 SP AR 12 F0 I1 I1 F7 F7 I2 I2 F6 F6 I3 I3 F5 F5 I4 I4 F4 F4 I5 I5 F3 F3 I6 I6 F2 F2 I7 I7 F1 F1 I8 I8 F0 F0 I0 I0 I9 I9 11 I9/OE NOTES: In the unprogrammed or virgin state: All cells are in a conductive state. All AND gate locations are pulled to a logic "0" (Low). Output polarity is inverting. 1997 Aug 08 CONFIG. CELL Pins 1 and 11 are configured as Inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as bidirectional I/O, with the outputs disabled via the direction term. Denotes a programmable cell location. SP00012 5 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z OUTPUT MACRO CELL (OMC) FROM AND ARRAY 1 DIRECTION CONTROL TERM 11 VCC 01 OE 00 MUX SP AR { FROM AND ARRAY TO ALL OMCs 10 D 01 10 OUT 11 MUX 00 S X(n) OUTPUT POLARITY CONTROL Q F CLK AC1n AC2n 00 F 10 MUX 11 01 TO ALL OMCs 11 OE NOTE: Denotes a programmable cell location. SP00014 THE OUTPUT MACRO CELL (OMC) DESIGN SECURITY The PLC18V8Z series devices have 8 individually programmable Output Macro Cells. The 72 AND inputs (or product terms) from the programmable AND array are connected to the 8 OMCs in groups of 9. Eight of the AND terms are dedicated to logic functions; the ninth is for asynchronous direction control, which enables/disables the respective bidirectional I/O pin. Two product terms are dedicated for the Synchronous Preset and Asynchronous Reset functions. The PLC18V8Z series devices have a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the device cannot be copied or retrieved. Each OMC can be independently programmed via 16 architecture control bits, AC1n and AC2n (one pair per macro cell). Similarly, each OMC has a programmable output polarity control bit (Xn). By configuring the pair of architecture control bits according to the configuration cell table, 4 different configurations may be implemented. Note that the configuration cell is automatically programmed based on the OMC configuration. 1997 Aug 08 6 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z If any one OMC is configured as registered, the configuration cell will be automatically configured (via the design software) to ensure that the clock and output enable functions are enabled on Pins 1 and 11, respectively. If none of the OMCs are registered, the configuration cell will be programmed such that Pins 1 and 11 are dedicated inputs. The programming codes are as follows: CONFIGURATION CELL A single configuration cell controls the functions of Pins 1 and 11. Refer to Functional Diagram. When the configuration cell is programmed, Pin 1 is a dedicated clock and Pin 11 is dedicated for output enable. When the configuration cell is unprogrammed, Pins 1 and 11 are both dedicated inputs. Note that the output enable for all registered OMCs is common--from Pin 11 only. Output enable control of the bidirectional I/O OMCs is provided from the AND array via the direction product term. Pin 1 = CLK, Pin 11 = OE L Pin 1 and Pin 11 = Input H CONTROL CELL CONFIGURATIONS FUNCTION AC11 Registered mode AC2N CONFIG. CELL COMMENTS Dedicated clock from Pin 1. OE Control for all registerd OMCs from Pin 11 only. Programmed Programmed Programmed Bidirectional I/O mode1 Unprogrammed Unprogrammed Unprogrammed Pins 1 and 11 are dedicated inputs. 3-State control from AND array only. Fixed input mode Unprogrammed Programmed Unprogrammed Pins 1 and 11 are dedicated inputs. Programmed Unprogrammed Unprogrammed Pins 1 and 11 are dedicated inputs. The feedback path (via FMUX) is disabled. Fixed output mode NOTE: 1. This is the virgin state as shipped from the factory. ARCHITECTURE CONTROL--AC1 and AC2 11 OE DIR SP Q F(D), F (D) AR S S S F(B), F (B) 1 F(O), F (O) CLK OMC CONFIGURATION REGISTERED (D-TYPE) CODE OMC CONFIGURATION CODE OMC CONFIGURATION CODE D BIDIRECTIONAL I/O1 (COMBINATORIAL) B FIXED OUTPUT O 1 1 SP F (I) CLK Q F(D), F (D) AR NC SP CLK Q AR OE NC OE 11 11 OMC CONFIGURATION CODE CONFIGURATION CELL CODE CONFIGURATION CELL CODE FIXED INPUT I PIN 1 = CLK PIN 11 = OE L PIN 1 = INPUT PIN 11 = INPUT H6 SP00015 NOTES: A factory shipped unprogrammed device is configured such that: 1. This is the initial unprogrammed state. All cells are in a conductive state. 2. All AND gates are pulled to a logic "0" (Low). 3. Output polarity is inverting. 4. Pins 1 and 11 are configured as inputs 0 and 9. The clock and OE functions are disabled. 5. All Output Macro Cells (OMCs) are configured as bidirectional I/O, with the outputs disabled via the direction term. 6. This configuration cannot be used if any OMCs are configured as registered (Code = D). 1997 Aug 08 7 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z ABSOLUTE MAXIMUM RATINGS1 PARAMETER SYMBOL VCC Supply voltage VCC Operating supply voltage VIN Input voltage VOUT Output voltage t/V Input/clock transition rise or IIN Input currents IOUT Output currents Tamb Operating temperature range Tstg Storage temperature range RATINGS UNIT -0.5 to +7 VDC 4.5 to 5.5 (Industrial) 4.75 to 5.25 (Commercial) VDC -0.5 to VCC + 0.5 VDC -0.5 to VCC + 0.5 VDC 250 ns/V maximum -10 to +10 mA +24 mA -40 to +85 (Industrial) 0 to +75 (Commercial) C -65 to +150 C fall2 NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. All digital circuits can oscillate or trigger prematurely when input rise and fall times are very long. When the input signal to a device is at or near the switching threshold, noise on the line will be amplified and can cause oscillation which, if the frequency is low enough, can cause subsequent stages to switch and give erroneous results. For this reason, Schmitt-triggers are recommended if rise/fall times are likely to exceed 250ns at VCC = 4.5V. THERMAL RATINGS VOLTAGE WAVEFORMS TEMPERATURE +3.0V Maximum junction 150C Maximum ambient 75C Allowable thermal rise ambient to junction 75C 90% 10% 0V 5ns tR tF +3.0V AC TEST CONDITIONS 90% VCC +5V 10% S1 0V 5ns C1 C2 R1 5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. BY I0 Input Pulses INPUTS I9 BW BX R2 DUT GND NOTE: C1 and C2 are to bypass VCC to GND. 1997 Aug 08 5ns BZ CL OUTPUTS SP00006 8 SP00017 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z DC ELECTRICAL CHARACTERISTICS Commercial = 0C Tamb +75C, 4.75V VCC 5.25V; Industrial = -40C Tamb +85C, 4.5V VCC 5.5V LIMITS SYMBOL PARAMETER TEST CONDITION MIN TYP1 MAX UNIT Input voltage VIL Low VCC = MIN -0.3 0.8 V VIH High VCC = MAX 2.0 VCC + 0.3 V 0.100 0.500 V V Output voltage2 VOL Low VCC = MIN, IOL = 20A VCC = MIN, IOL = 24mA VOH High VCC = MIN, IOH = -3.2mA VCC = MIN, IOH = -20A 2.4 VCC - 0.1V V V Input current IIL Low7 VIN = GND -10 A IIH High VIN = VCC 10 A VOUT = VCC VOUT = GND 10 -10 A A -130 mA 100 A 1.5 mA/MHz Output current IO(OFF) Hi-Z state IOS Short-circuit3 ICC VCC supply current (Standby) ICC/f VOUT = GND VCC supply current VCC = MAX, VIN = 0 or VCC8 (Active)4 VCC = MAX (CMOS 20 inputs)5, 6 Capacitance CI Input CB I/O VCC = 5V, VIN = 2.0V 12 pF VB = 2.0V 15 pF 45 6 5 4 I CC(mA) 30 t PD 3 2 1 15 0 -1 100A 0 0 6 12 18 24 -2 30 f(MHz) 0 20 40 60 80 100 120 140 160 180 200 OUTPUT CAPACITANCE LOADING (pF) SP00018 SP00019 Figure 2. tPD vs Output Capacitance Loading (Typical) Frequency5, 6 Figure 1. ICC vs (Worst Case) NOTES: 1. All typical values are at VCC = 5V, Tamb = +25C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short-circuit should not exceed one second. Test one at a time. 4. Tested with TTL input levels: VIL = 0.45V, VIH = 2.4V. Measured with all outputs switching. 5. ICC/TTL input = 2mA. 6. ICC vs frequency (registered configuration) = 2mA/MHz. 7. IIL for Pin 1 (I0/CLK) is 10A with VIN = 0.4V. 8. VIN includes CLK and OE if applicable. 1997 Aug 08 9 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z AC ELECTRICAL CHARACTERISTICS4 Commercial = 0C Tamb +75C, 4.75V VCC < 5.25V; Industrial = -40C Tamb +85C, 4.5V VCC 5.5V; R2 = 390 TEST CONDITION1 SYMBOL PARAMETER FROM TO tCKP Clock period (Minimum tIS + tCKO) CLK + tCKH Clock width High CLK + tCKL Clock width Low tARW Async reset pulse width Input or feedback data hold time CLK + Input 200 I , F CLK + PLC18V8Z25 (Commercial) PLC18V8ZIA (Industrial) MIN R1 () CL (pF) MIN CLK + 200 50 33 33 ns CLK - 200 50 15 15 ns CLK - CLK + 200 50 15 15 ns I , F I +, F + 25 25 ns 50 0 0 ns 200 50 18 18 ns MAX MAX UNIT Pulse width Hold time tIH Setup time tIS Input or feedback data setup time Propagation delay tPD Delay from input to active output I , F F 200 50 25 25 ns tCKO Clock High to output valid access Time CLK + F 200 50 15 15 ns tOE13 Product term enable to outputs off I , F F Active-High R = 1.5k Active-Low R = 550 50 25 25 ns tOD12 Product term disable to outputs off I , F F From VOH R = From VOL R = 200 5 25 25 ns tOD22 Pin 11 output disable High to outputs off OE - F From VOH R = From VOL R = 200 5 20 20 ns tOE23 Pin 11 output enable to active output OE + F Active-High R = 1.5k Active-Low R = 550 50 20 20 ns tARD Async reset delay I , F F+ 30 30 ns tARR Async reset recovery time I , F CLK + 20 20 ns tSPR Sync preset recovery time I , F CLK + 20 20 ns tPPR Power-up reset VCC + F+ 25 25 ns 30 30 MHz Frequency of operation fMAX Maximum frequency I/(tIS + tCKO) 200 50 NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. Resistor values of 1.5k and 550 provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns. 1997 Aug 08 10 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z AC ELECTRICAL CHARACTERISTICS4 Commercial = 0C Tamb +75C, 4.75V VCC < 5.25V; Industrial = -40C Tamb +85C, 4.5V VCC 5.5V; R2 = 390 PLC18V8Z35 (Commercial) TEST CONDITION1 SYMBOL PARAMETER FROM TO tCKP Clock period (Minimum tIS + tCKO) CLK + tCKH Clock width High CLK + tCKL Clock width Low tARW Async reset pulse width Input or feedback data hold time CLK + Input 200 I , F CLK + PLC18V8ZI (Industrial) R1 () CL (pF) MIN CLK + 200 50 47 57 ns CLK - 200 50 20 25 ns CLK - CLK + 200 50 20 25 ns I , F I +, F + 35 40 ns 50 0 0 ns 200 50 25 30 ns MAX MIN MAX UNIT Pulse width Hold time tIH Setup time tIS Input or feedback data setup time Propagation delay tPD Delay from input to active output I , F F 200 50 35 40 ns tCKO Clock High to output valid access Time CLK + F 200 50 22 27 ns tOE13 Product term enable to outputs off I , F F Active-High R = 1.5k Active-Low R = 550 50 35 40 ns tOD12 Product term disable to outputs off I , F F From VOH R = From VOL R = 200 5 35 40 ns tOD22 Pin 11 output disable High to outputs off OE - F From VOH R = From VOL R = 200 5 25 40 ns tOE23 Pin 11 output enable to active output OE + F Active-High R = 1.5k Active-Low R = 550 50 25 30 ns tARD Async reset delay I , F F+ 35 40 ns tARR Async reset recovery time I , F CLK + 25 30 ns tSPR Sync preset recovery time I , F CLK + 25 30 ns tPPR Power-up reset VCC + F+ 35 40 ns 21 18 MHz Frequency of operation fMAX Maximum frequency I/(tIS + tCKO) 200 50 NOTES: 1. Refer also to AC Test Conditions. (Test Load Circuit) 2. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH - 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 3. Resistor values of 1.5k and 550 provide 3-State levels of 1.0V and 2.0V, respectively. Output timing measurements are to 1.5V level. 4. Leave all the cells on unused product terms intact (unprogrammed) for all patterns. 1997 Aug 08 11 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z POWER-UP RESET In order to facilitate state machine design and testing, a power-up reset function has been incorporated in the PLC18V8Z. All internal registers will reset to Active-Low (logical "0") after a specified period of time (tPPR). Therefore, any OMC that has been configured as a registered output will always produce an Active-High on the associated output pin because of the inverted output buffer. The internal feedback (Q) of a registered OMC will also be set Low. The programmed polarity of OMC will not affect the Active-High output condition during a system power-up condition. TIMING DIAGRAMS EEE EEE INPUTS I/O, REG. FEEDBACK VALID INPUT tIS VALID INPUT tIH tCKH tCKL EEEEEEEE EEEEEEEE CLK tCKP PIN 11 OE tCKO tOD2 tOE2 3-STATE REGISTERED OUTPUTS EEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEE EEEEEEEE EEEEEEEE EEEEEEEE ANY INPUT PROGRAMMED FOR DIRECTION CONTROL tOD1 tPD tOE1 3-STATE COMBINATORIAL OUTPUTS Switching Waveforms +5V 4.5V 3.0V EEEEEEEE EEEEEEEE EEEEEEEE EEEEEEE EEEEEEE EEEE EEEE VCC 0V tPPR F (OUTPUTS) I, B (INPUTS) VOH 1.5V 1.5V VOL tCKO +3V 1.5V 1.5V 0V tCKL tIS tIH +3V CLK 1.5V 1.5V 1.5V 0V tIS tCKH tCKL tCKP NOTE: Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled). Power-Up Reset SP00020 1997 Aug 08 12 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z TIMING DIAGRAMS (Continued) tARW ASYNCHRONOUS RESET INPUT tARD REGISTERED OUTPUT tARR CLOCK Asynchronous Reset tIS tIH tSPR SYNCHRONOUS PRESET INPUT CLOCK tCKO REGISTERED OUTPUT Synchronous Preset SP00021 1997 Aug 08 13 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z REGISTER PRELOAD FUNCTION (DIAGNOSTIC MODE ONLY) In order to facilitate the testing of state machine/controller designs, a diagnostic mode register preload feature has been incorporated into the PLC18V8Z series device. This feature enables the user to load the registers with predetermined states while a super voltage is applied to Pins 11 and 6 (I9/OE and I5). (See diagram for timing and sequence.) To read the data out, Pins 11 and 6 must be returned to normal TTL levels. The outputs, F0 - F7, must be enabled in order to read data out. The Q outputs of the registers will reflect data in as input via F0 - F7 during preload. Subsequently, the register Q output via the feedback path will reflect the data in as input via F0 - F7. Refer to the voltage waveform for timing and voltage references. tPL = 10sec. REGISTER PRELOAD (DIAGNOSTIC MODE) 12.0V 12.0V I9/OE (PIN 11) 5.0V 5.0V tPL tPL tPL tPL tPL tPL OE(VOL) 12.0V I5 (PIN 6) 5.0V I0/CLK I0/CLK (PIN 1) tOE F0-7 I1-4, 6-8 PRELOAD DATA IN tCKL PRELOAD DATA OUT EEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEE 1997 Aug 08 tCKO 14 tIS DATA OUT F0-7 tIH I1-4, 6-8 SP00022 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z With Logic programming, the AND/OR/EX-OR gate input connections necessary to implement the desired logic function are coded directly from logic equations using the Program Table. Similarly, various OMC configurations are implemented by programming the Architecture Control bits AC1 and AC2. Note that the configuration cell is automatically programmed based on the OMC configuration. LOGIC PROGRAMMING The PLC18V8Z series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors' SNAP design software package. ABEL and CUPL design software packages also support the PLC18V8Z architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. In this table, the logic state of variables I, P and B associated with each Sum Term S is assigned a symbol which results in the proper fusing pattern of corresponding link pairs, defined as follows: PLC18V8Z logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. OUTPUT POLARITY - (O, B) S S O, B O, B X X ACTIVE LEVEL CODE ACTIVE LEVEL CODE INVERTING1 L NON-INVERTING H SP00023 "AND" ARRAY - (I, B) I, B I, B I, B I, B I, B I, B I, B P I, B I, B I, B I, B P I, B P P STATE CODE STATE CODE STATE CODE STATE DON'T CARE - INACTIVE1 O I, B H I, B CODE L SP00024 NOTE: 1. A factory shipped unprogrammed device is configured such that all cells are in a conductive state. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. 1997 Aug 08 15 Philips Semiconductors * Zero standby power CMOS versatile PAL devices PURCHASE ORDER # TOTAL NUMBER OF PARTS * * * O OMC ARCH. L H OUTPUT POLARITY NON-INVERTING PIN 1, PIN 11 = INPUT H PIN 1 = CLK; PIN 11 = OE L CONFIG. CELL* INVERTING CONTROL I D REGISTERED (D-TYPE) FIXED INPUT O B ACTIVE OUTPUT NOT USED Product specification 0 D A A A A A A A A 12 SP00029 PLC18V8Z A DIRECTION CONTROL D OR ARRAY (FIXED) DATA CANNOT BE ENTERED INTO THE OR ARRAY FIELD DUE TO THE FIXED NATURE OF THE DEVICE ARCHITECTURE. CONFIGURATION CELL (CLK/OE CONTROL) ARCH. CONTROL BITS OUTPUT POLARITY T AND OR (FIXED) E I F (I) F (B, O, D) R M 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 D 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 D 19 A 20 A 21 A 22 A 23 A 24 A 25 A 26 A 27 D 28 A 29 A 30 A 31 A 32 A 33 A 34 A 35 A 36 D 37 A 38 A 39 A 40 A 41 A 42 A 43 A 44 A 45 D 46 A 47 A 48 A 49 A 50 A 51 A 52 A 53 A 54 D 55 A 56 A 57 A 58 A 59 A 60 A 61 A 62 A 63 64 65 66 67 68 69 70 71 SP AR 11 9 8 7 6 5 4 3 2 1 19 18 17 16 15 14 13 12 19 18 17 16 15 14 13 PIN INACTIVE H FIXED OUTPUT BIDIRECTIONAL I/O 16 * THE CONFIGURATION CELL IS AUTOMATICALLY PROGRAMMED BASED ON THE OMC ARCHITECTURE. ** FOR SP, AR: "-" IS NOT ALLOWED. I, F (I, B) L **DON'T CARE - I, F (I, B) AND ARRAY VARIABLE NAME CF(XXXX) PHILIPS DEVICE # DATE REV. PROGRAM TABLE # PROGRAM TABLE 1997 Aug 08 CUSTOMER SYMBOLIZED PART # NOTES: In the unprogrammed or virgin state: All AND gate locations are pulled to a logic "0" (Low). Output polarity is inverting. Pins 1 and 11 are configured as inputs 0 and 9, respectively, via the configuration cell. The clock and OE functions are disabled. All output macro cells (OMC) are configured as combinatorial I/O, with the outputs disabled via the direction control term. CUSTOMER NAME Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z SNAP RESOURCE SUMMARY DESIGNATIONS I0/CLK DINV8 I0 CONFIG. CELL NINV8 9 CKEV8 NOUTV8 I1 OMC AND CLK 9 PROGRAMMABLE AND ARRAY 36 ROWS X 72 COLUMNS I2 I7 F7 NOUTV8 F6 OMC 9 NOUTV8 OMC F1 9 NOUTV8 I8 OMC F0 SP AR OE CONFIG. CELL I9/OE I9 1 FROM AND ARRAY TO ALL OMCs DIRECTION CONTROL TERM 11 VCC 01 00 OE MUX XORREG SP AR 10 OR FROM AND ARRAY XORDIR DFFV8 S NOUTV8 F D X(n) OUTPUT POLARITY CONTROL Q CLK AC1n XORINV AC2n F MUX 00 10 11 01 FDMUX NOTE: Denotes a programmable cell location. OE11V8 TO ALL OMCs 11 OE SP00025 1997 Aug 08 17 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z DIP20: plastic dual in-line package; 20 leads (300 mil) 1997 Aug 08 18 SOT146-1 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z PLCC20: plastic leaded chip carrier; 20 leads 1997 Aug 08 SOT380-1 19 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z SO20: plastic small outline package; 20 leads; body width 7.5 mm 1997 Aug 08 20 SOT163-1 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 1997 Aug 08 21 SOT339-1 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm 1997 Aug 08 22 SOT360-1 Philips Semiconductors Product specification Zero standby power CMOS versatile PAL devices PLC18V8Z DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 1997 Aug 08 23