HD63P05Y1,HD63SPA05Y1, HD6SPBOD5Y1 CMOS MCU (Microcomputer Unit) The HD63P05Y1 is a CMOS 8-bit single-chip microcom- puter unit which has a 4k-byte or &k-byte EPROM on the package. It is compatible with the HD6305Y1 except for ROM which is not included in the HD63POS5Y1. It can be used not only for debugging and evaluating the internal program of HD6305X1 or HD6305Y1, but also for small-sized production preceding mask ROM. FEATURES Pin compatible with HD6305%1 and HD6305Y'1 256-byte of RAM A total of 31 terminals, including 24 1/0s, 7 inputs Two timers B-bit timer with a 7-bit prescaler (programmable prescaler; event counter) - 15-bit timer (commonly used with the SCI clock divider) On-chip serial interface circuit (synchronized with clock} Six interrupts (two external, two timer, one serial and one software} @ Low power dissipation modes Wait, Stop and Standby Mode @ Minimum instruction cycle time HD63P05Y1...... 1 ys (f = 1 MHz) HD63PA05Y1 ... .0.67 us (f = 1.5 MHz) HD63PB05Y1..... 0.5 ps (f = 2 MHz} Similar to HD68B00 instruction set Bit manipulation Bit test and branch Versatile interrupt handling Full set of conditional branches New instructions STOP, WAIT, DAA Applicable to 4k or 8k bytes of EPROM 4k bytes; HN482732A &k bytes; HN482764, HN27C64 @ TYPE OF PRODUCTS PRELIMINARY HD63P05Y 1, HD63PA05Y 1, HD63PBO5Y 1 {OC-64SP) = PIN ARRANGEMENT Type No. Bus Timing Applied EPROM HD63P05Y 1 1 MHz HN482732A-30, HN482764-3, HN27C64-30 HD63PA05Y1] 1.5 MHz | HN482732A-30, HN482764-3, HN27C64-30 HD63PB0SY1| 2 MHz HN482732A-25, HN482764, HN27C64-25 (Note) EPROM is not attached to the MCU. @ PROGRAM DEVELOPMENT SUPPORT TOOLS @ Cross assembler software for use with IBM PCs and compatibles @ Incircuit emulator for use with |BM PCs and compatibles {Top View} @ HITACHI Hitachi America, Ltd. e Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 599HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 = BLOCK DIAGRAM | iP XTAL EXTAL AAWAESNUM iNT STeY i i Miscella- Pri Timer/ J Oscillator = TIMER aot escaler F Counter neous 7 Register Timer contra Accumulator hg +__ ok A Ay -e} ge cPU 0, Port A Awe te ES Index Control . OwinT, Ape re [Os ij = Register x 0 &h od, ter 4 82 | 22 KO p] 2 BE a: Porro Terminals a,, a] ox as Condition Code 5 SR 9, _~sInour Ag _o = Register cc h+ dD, Terminals Ao = cPu P BD. Stack 6 Pointer sp 8, <-r L Program 5, ~_-+ 02 ounter Port B Rey 05] 22 6 High' PCH ALU He) Bee r2l/Oe ox Program Terminas %*4 fe] 2h Counter |}. Adria Bs yas 8 Low's! PCL /= ADA, Boo ~ o2 = ADA, 8 ~ = fe ADR a ADRs 4 ADA, \ [-* ADA, Co | | _y 2 [> 40 Port C 7 1 o 2 > ADA, -\_* - og 1/0 cas 08] 23 2568 3 ADR Terminals C,<+ Se a KS RAM z AOR, vex G-4 2 2 et += ADA, } cme o2 ADRo Caf Tx Serial fap em HATA p== DATA, Serial Controt SL j= DATA, Data Register CO jpoe DATA, Register| Serial 25 = pata; Status za - oar, Register -== Data, p-= Data, On Package ceo TT a l ' l he Ay i I AL iJ ro A, 4 l H A, 4 l A, i l be As Ve Address, I ie Aslet CE = ! le Ar 7 oO EPROM A ee utput ; e Ay ae l Pe Aila I HN482732A[ He A)! l HN482764 [Pt Au I jHN27C64 h TEI* ! ' ! I I i I poe Oo 1 tr O.i4 > O21 Deta Pm O11 \ ry ie Os i mput ! pe Os | ae I Os le l O71 > | | i | nn | HITACHI 600 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD6G3PBO5Y1 8 ABSOLUTE MAXIMUM RATINGS Iter Symbol! Value Unit Supply voltage Vec -0.3 ~ +7.0 v Input voltage Vin -0.3~ Veco + 0.3 Operating temperature Topr 0~ +70 c Storage temperature Tog -55 ~ +150 c [NOTE] These products have a protection circuit in their input terminals against high electrostatic voltage or high electric fields. Notwithstanding, be careful not to apply any voltage higher than the absolute maximum rating to these high input impedance circuits. To assure normal operation, we recommended Vin. Vout: Vss S !Vin Of Your! S Vcc B ELECTRICAL CHARACTERISTICS #DC Characteristics (Voc = 5.0V + 10%, Vss = GND, Tg = 0 ~ +70C, unless otherwise specified.) Test : . . typ. ax. it Item Symbo! Condition min yp max Uni Input RES, STBY Vec-0.5 - Veo +03 Vv voltage EXTAL Vin Ver x 0.7 _ Voc +03 Vv High Others 2.0 | Voge +0.3 V Input volt- All Input Vv, -0.3 _ 0.8 Vv age Low npu IL Output Ion = 200 A 24 v High Alt Input Vou OH voltage lon =-10 pA Vec-0.7 _ _ Vv Output Low All output VoL Io, = 1.6 mA _ 0.55 V voltage Operating _ 5 10 mA eee Wait - 2 5 mA Current loc f= 1MHz* dissipation Step _ 2 10 nA Standby _ 2 10 pA TIMER, Input int leakage , hl 1 pA current D,~Dz STBY Ag~ Az By ~ By Vin = 0.5 ~ Co ~ Cy Vec-0 5V Three- ADR state 0 es \Irs1l _ _ 1 nA current ~ ADR i3. DATAg ~ DATA, E**, RWS* Input All / f= 1MHz, _ _ 45 F Capacity terminais Cin Vin = OV p * The value at f = xMHz can be calculated by the following equation: loc Ue xMHz} = Iog (f= IMHz) multiplied by x ** At standby made *** All output and RES terminals are open (ViH min = VCC-1-0V. ViL max = 0.8V), and Icc of EPROM is not inciuded. @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 # (415) 589-8300 601HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 AC Characteristics (Vee. = 5.0V + 10%, Vgg = GND, T, = 0 ~ +70C, unless otherwise specified.) Test HD63P05Y1 HD63PA05Y 1 HO63PB05Y1 ; Item Symboi Conditi - Unit ONdItion | min | typ | max | min | typ | max | min | typ | max Cycle Time teye 1 - 16/0666 | 10 | 0.5 - 10 us Enable Rise Time te, - - 26 - _ 20 - = 20 ns Enable Fall Time ter - _ 20 - - 20 - - 20 ns Enable Pulse Width (High Level] PWen 450 _ _ 300 _ _- 220 _ - ns Enable Pulse Width (Low" Level) PWeL Fig. 1 450 - - 300 - - 220 - - ns Address Delay Time tap - - 250 - - 190 - - 180 ns Address Hold Time tay 40 - = 30 _ - 20 - - ns Data Delay Time tow - - 250 - - 160 - - 120 ns Data Hold Time {Write} tHw 40 - - 30 - 20 - ~ ns Data Set-up Time (Read) tosrR 80 _ - 60 - - 50 - - ns Data Hold Time (Read) tur 0 - - 0 - - 0 - - ns Port Electrical Characteristics (Vee = 5.0V + 10%, Vgg = GND, Tg = 0~ +70C, unless otherwise specified.) Item Symbol Test min typ max Unit Condition Output valt- Von lon = -200uA 2.4 - - Vv age High Ports A, lon = - 102A Veo -0.7 - - Output volt- age oLow"" VoL lot = 1.6mA - - 0.55 v Input volt- age High" VIH 2.0 - Vec + 0.3 v Input volt- Ports A age Low B,c,D Vit -0.3 - 0.8 Vv Input leak- Vin = 05~ _ age current ial Vec - 0.5V 7 \ HA Port Timing (Voc = 5.0V+10%, Vsg = GND, Ta = G ~ +70C, unless otherwise noted.) Item Symbol c Test HD63P05Y1 HOGSPAOSY' HD63PB05Y 1 Unit ondition | min | typ | max | min | typ | max | min | typ | max Port Data Set-up Time (Port A, B, C, D} Ttpps cia 2 200 - - 200 _ - 200 - - ns 7 ig. Port Data Hold Time (Port A, B, C, D} tron 200} - | | 20) - | - | 20] - | - [es Port Data Delay Ti . (Port A,B, C) yom teow Fig. 3 - _ 300 - _ 300 _ 300 ns @ HITACHI 602 Hitachi America, Ltd. Hitachi Piaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Control Signal Timing (Voc = .0V410%, Vgg = GND, Ta = 0 ~ +70C, unless otherwise noted.) Test HD63P05Y 1 HD63PA05Y 1 HD63PBO05Y t . Item Symbol Cc ves 3 - - Unit ondition | min | typ | max | min | typ | max | min | typ | max : teye _ _ teyc _ _ teye _ INT Puise Width Twe +250 +200 +200 ns inv . t t t INT, Pulse Width tiwL2 +950 - - +200 - - +300 - ns RES Pulse Width trawe 5 - - 5 - - 5 - - teye Control Set-up Time tes Fig. & 250 - - 250 - - 250 = - ns : : t t t Timer Pulse Width trwe 60; ~ | |+a00} ~ | ~ {+300/ | 7 | Oscillation Start Time (Crystal) tose Fig.5,Fig.20*| - 20 _ - 20 - - 20 ms Reset Delay Time teHe Fig. 19 80 - - 80 - - 80 - ms * CL = 22pF +20%, R, = 60S! max. @ SCI Timing (Vgc = 5.0V10%, Vgg = GND, Ta = 0 ~ +70C, unless otherwise specified.) Test HD63PO5Y 1 HD63PA05Y1 HD63PBO5Y 1 bol ve: Unit tem Symbol J condition min | typ | max | min] typ | max | min | typ | max Clock cycle tSeye 1 |32768] 0.67 )21845| 6.5 |16384) us Data output delay time ttxp Fig. 6, - - 250 - - 250 - - 250 ns Data set-up time tsrx Fig. 7 200 | - - {| 200] - | 200; - - ns Data hold time tHRx 100 - - 100 _ ~ 100 - - ns @ HITACHI Hitachi America, Lid. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 {415} 589-8300 603HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 leye E ben ter me tay aw aay Address Valid | Ww ress Vali RAW 0.6V + tow ~~ tow MCU Write 2-4V sta DATAs ~ DATA? 0.6V Valid + bth MCU Read DATA ~ DATA? Data Valid Figure 1 Bus Timing E 2.4V E \ __9.6V7 teon +0.6V teps * teow Port 2.0V Data 4 Port 2.4V Data A,B,C,D -O.8V Valid A.B.C 0.6V Valid Figure 2 Port Data Set-up and Hold Times Figure 3 Port Data Delay Time {MCU Write} (MCU Read) interrupt Test F SULIU LU LULL LL LPL LS 7] Address i ( X X X X X X X X X -X Y Bus Op Code Op Coe ppp SP SP-1 SP-2 SP-3 SP-4 Vector Vector X_A Address Address +? se se. New INT.INT2 PCo~ Address Address PC? Data Bus x X X x x x X X X YX ~ Y Y Y On Operand Irreievant PCe~ IX ACC Vector Vector i Cade Op Cade Data Ce cc mse Usa First Inst. of . PCs Address Address Interrupt Routine Ri i Figure 4 Interrupt Sequence @ HITACHI 604 Hitachi America, Lid. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 LALELELI LLL LS eins LL f>tosc4 Bus tecle_ LL Ff Vec0.5V _ 5V \ ar ats 1FFF FFF FFE 1FFF New PC FFF Rw TEL. WL Data Bus TL, EL me ee MMM Ly} FigureS Reset Timing tscyc Clock Output av -_- Cs/CK 0.6V 0.6V / 0.6V tx - a\ Data Output f24v Xx " C7/TX +0.6v 4 Usax turx ___- + Data Input f2.0V 2.0V Ce/RX 1 o ev o.av | H Ve Figure6 SCI Timing (tnternal Clock) Uscye ee Clock Input sel 2.0V Cs/EK 0.8V trxp Data Output 2. 4V - C7/TX 0.6V +) tsrx turx ai i Data Input F2.0V 2.0V C6/AX 0.8V 0.8V ul I | VF Figure? SCI Timing(External Clock) HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Paint Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 605HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Vee TTL Load {Port} lor= 1.6mA 2.4kQ Test point . aoe terminal T " 9O0pF 12kQ [NOTES] 1. The load capacitance includes stray capacitanca caused by the probe, etc. 2. All diodes are 182074 @) Figure 8 Test Load DESCRIPTION ON PIN FUNCTIONS Here is the description of HD63PO05Y1 MCU input and output signals. eVec. Vss Power is supplied to the MCU using these two pins. When the operating voltage of the EPROM is S.0V + 5%, change Vcc according to that of EPROM. GINT, INT2 Used for requesting an external interrupt to the MCU. For details, see INTERRUPT. The INT2 is used as the port De pin. @XTAL, EXTAL Ate input pins to the internal clock circuit. A crystal oscillator (AT cut, 2.0 to 8.0 MHz) or ceramic oscillator is con- nected to these pins, For instance, in order to obtain the system clack ] MHz, a 4 MHz resonant fundamental crystal is useful because the divide-by-4 circuitry is included. EXTAL accepts an external clock input of duty 50% (+10%)} to drive, then the interna! clock is a quarter the frequency of the external clock. External drive frequency will be 4 or less times the maximum internal clock. For external driving, no XTAL should be connected. Refer to INTERNAL OSCILLATOR for using these input pins, e@TIMER Is an external input pin to control the internal Timer. For details, see TIMER, @RES Is used for resetting MCU. For details, see RESET. eNUM Is not for user application. It must be connected to Vcc through 1k resistance. @Input/Output Pins (Ac ~ A7, Bo ~ B1, Co ~ C7) 24 pins consist of three 8-bit 1/0 ports (A, B, C). Each of them is used as input or output pin, through program control of the data direction register. For details, see I/O PORTS. {nput Pins (D: ~ D7) Are 7 input-only pins compatible with the TTL and CMOS. De _is used as INT2. When the De is used as the port, set the INT2 interrupt mask bit of the miscellaneous register to 1 to prevent an INT: from accidental interruption. Enable (E) Supplies E clock. Output is a single-phase, TFL compatible and 1/4 crystal oscillation frequency or 1/4 external clock frequency. It can drive one TTL load and a 90pF condenser. @ Read/Write (R/W) Is an output pin compatible with the TTL. This indicates to peripheral and memory devices whether MCU is in Read (High), or in Write (Low). The normal standby state is Read (High). Its output can drive one TTL load and a S0pF condenser. Data Bus (DATAo ~ DATA7) Are three-state buffers compatible with the TTL. Each of them can drive one TTL load and 90pF. @ Address Bus (ADRo ~ ADRi3) Are compatible with the TTL and can drive one TTL load and 90pF. e@STBY Used for bringing the MCU into the standby mode. With STBY at Low level, the oscillation stops and internal situa- tion is reset, For details, see STANDBY MODE. The follow- ing are !/O pins for serial communication interface (SCI), and used as ports Cs, Cs, and C7. For details, see SERIAL COMMUNICATION INTERFACE, @CK (Cs) Used to input or output clocks when receiving or transmit- ting serial data, Rx (Ce) Used to receive serial data. @Tx (C7) Used to transmit serial data, BMEMORY MAP The memory map of the HD63POSY] MCU is shown in Fig. 9. During interrupt, the contents of the registers are saved in the stack as shown in Fig. 10. The saving begins with the lower byte (PCL) of the program counter. Then the stack pointer value is decremented, and the higher byte (PCH) of the program counter, index register (X), accumulator (A) and condition code register (CC) are stacked in this order. In subroutine calls, only the contents of the program counter (PCH and PCL) are stacked. @ HITACHI 606 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 o $0000 O|__PORT A_]$00 1/0 Ports 1[ PORT 8 1$01 Ber 2l PORT C _|s02 63] $003F 3] PORT D $03" 64 RAM $0040 4 PoaATAocDR [$04 {192Bytes) 5] PORT B DOR $05" Stack 6] PorTc DOR |$06 255 SQOFF Not Used 256 RAM $0100 Q] Timer Data Reg [SOS (G4Bytes) Q| Timer CTRL Reg |$O9 es 31 yt $013F 10] Misc Reg |goa 320 $0140 EPROM Not Used (7,872Bytes} Lee ed 16] ScICTAL Reg [$10 B18 Interrupt SIFFG \ 47[ Scrsts Rea ($11 8191L_Vectors | S1FFF 18] SCI Data Reg 1942 8192 $2000 Not Used 31 oF se $iF External 32 External $20 Memory Space 63 Memory Space $3F * Write onty register 16383 S3FFF ** Read only register Figure 9 Memory Map of HD63P05Y1 MCU 765 43 2 10 Pull Condition nai ut Code Register n+ n-3 Accumulator n+2 n-2 index Register n+3 n-110 06 PCH n+4 n PCL* n+5 Push * In a subroutine call, only PCL and PCH are stacked. Figure 10 Sequence of Interrupt Stacking = REGISTERS There are five registers which the programmers can handle. @ Accumulator {A) The accumulator is a general purpose 8-bit register which holds operands, the results of arithmetic operations or data processing. @ index Register (X) The index register is an 8-bit register used for the index addressing mode, It contains an 8-bit value to be added to an instruction value to create an effective address. The index register can also be used for data manipulations using the read- modify-write instruction. The index register may also be used as a temporary storage area. @ Program Counter (PC) 7 (] 7 S 4 LM egister es Pi m PC Counter 13 65 0 k Lofofofojofoj+jij___sP Beanter Condition [x] l [w]z[c]Code Register Lie : Borrow Zero Negative Interrupt Mask Half Carry Figure 11 Programming Model The program counter is a 14-bit register which contains the address of the next instruction to be executed. Stack Pointer (SP} The stack pointer is a 14-bit register which indicates the address of the next free location in the stack. Initially, the stack pointer is set to SOOFF. It is decremented as data is pushed in, and incremented as it is pulled out. The upper 8 bits of the stack pointer are fixed to 00000011. During an MCU reset or when the reset stack pointer (RSP) instruction is executed, the pointer is set to the location S$OOFF. A subroutine or interrupt may be nested down to location $00CI which allows programmers to use up to 31 levels of subroutine call or 12 levels of interrupt response. Condition Code Register (CC) The condition code register is a 5-bit register. Each bit indicates the result of the executed instruction. These bits can be individually tested by conditional branch instructions. The CC bits are as follows. Half Carry (H): Used to indicate a carry occurring between bits 3 and 4 during an arithmetic operation (ADD, ADC). Setting this bit causes all interrupts to be masked except for software ones. If an inter- rupt occurs while the bit I is set, the interrupt is latched, and processed as scon as the interrupt mask bit (I) is reset. (Exactly, the interrupt enters the processing routine after the instruction next to the CLI is executed.) Interrupt (1): Negative (N): Used to indicate that the result of the latest arithmetic operation, logical operation or data processing is negative (Bit 7 is logical *1). Zero (Z): Used to indicate that the result of the latest arithmetic operation, logical operation or data processing is zero. Carry/Borrow Shows a carry or borrow occurring in the (C}: latest arithmetic operation. This bit is also affected by the Bit Test and Branch, Shift and @ HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 607HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Rotate instructions. B(NTERRUPT There are six different types of interrupt: external inter- tupt (INT, INT2), internal timer interrupts (TIMER, TIMER 2), serial interrupt (SCT) and interrupt by an instruction (SWI). Of these six interrupts, the INT2 and TIMER, and SCI and TIMER 2 respectively generate the same vector address. When an interrupt occurs, the program in execution stops and CPU state at the interrupt is saved onto the stack. In addition, the interrupt causes the interrupt mask bit (I) in the condition code register to be set and obtains the start address of the interrupt routine from an assigned interrupt vector address before the interrupt routine starts from the state address. The system exits from the interrupt routine by RTE instruction. When the RTI instruction is executed, the CPU state before the interrupt (saved in the stack) is pulled and the CPU starts the program again from the next step to the interrupted one, Table 1. lists the priority of interrupts and their vector addresses. Table 1 Priority of Interrupts Interrupt Priority Vector Address RES 1 SIFFE, S$1FFF Swi 2 S1FFC, $1FFD iNT 3 SIFFA, SIFFB TIMER/INT2 4 StFF8, S$1FF9 SCI/TIMER2 5 SiFF6, $1FF7 A flow chart of the interrupt is shown in Fig. 12. Also a block diagram of the interrupt request source is shown in Fig. 13. In_the block diagram, both the external interrupts INT and INF2 are edge trigger inputs. At the falling edge of the input, an interrupt request is generated and latched. ; The INT interrupt request is automatically cleared if a program jumps to the INT routine. In the case of INT2, the Clear 1 Set] $FFSP CLR INT Logic SFFTDR ODDR'S Fetch Instruction SSRS = 0.SSAT SC =1? $7FTimer Prescaler $50TCR $3FSSR $00--SCR $7F-MR Load PC From Reset:$1FFE, $1FFF N ~ Y oTIMER, _[ Stack PC, X, A, CC i 1-4 Bit 1 Load PC From Swi $1FFC $1FFO INT S1FFA.S FFB TIMER $1 FFG. S1FFS Execute Instruction Instruction Execute iRY, BUFER.SIFFO SCI SIFFE.S1FET TIMER 2 $1678 $1FF7 L____] Figure 12 Interrupt Flowchart interrupt request is cleared when O is written in bit 7 of the miscellaneous register. For external interrupts(INT,INTz ), internal timer interrupts (TIMER, TIMER2) and serial inter- rupt (SCI), these interrupt requests are held, but not operated, while bit I of the condition code register is set, Immediately after the bit I is cleared, the corresponding interrupt is activated, The INT2 interrupt can be masked by setting bit 6 of the miscellaneous register; the TIMER interrupt by bit 6 of the timer control register, the SCI interrupt by bit 5 of the serial Status register and the TIMER2 interrupt by bit 4 of the serial status register, _ The state of the INT pin is tested by BIL or BIH instruc- tions, The INT falling edge detector circuit and its latch circuit are independent of tests by these instructions. The state of INT2 pin is also independent, @ HITACHI 608 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 BIH/BIL Test INT tnter- rupt Latch | Vectoring generated SiFFA, $1FFB Condition Code Register (CC) Zz 4 9 iNT | Faltting Edge Detector \ Miscellaneous Register (MR) INT2 Timer Controt Register (TCR} TIMER Serial Status Register (SSR) SC! TIMER: L_| Ci Interrupt Control Circuit Vectoring generated [ssr7 SSARE|SSAS ssral TIMER? SIFFS, SIFFS ___ Vectoring genarated $1FF6,S1FF7 Figure 13 Interrupt Request Generation Circuitry Miscellaneous Register (MR: SO00A) The interrupt vector address for external interrupt INT2 is the same as that for the TIMER interrupt, as shown in Table 1. For this reason, a special register called a miscellaneous register (MR: $O00A) is available for INT2 interrupt control. Bit 7 of the miscellaneous register is of INT2 interrupt request flag. When the falling edge is detected at the INT, pin, 1! is set in bit 7. The software in the interrupt routine (vector address: $1FF8, $1FF9) checks to see if it is INT2 interrupt. Bit 7 is reset by software. Bit 6 is the INT2 interrupt mask bit. If the bit is set to "1", the INT2 interrupt is disabled. Miscellaneous Register (MR;$000A) 7 6 5 4 3 2 1 0 weer 1117] Po INT? tnterrupt Mask INT? Interrupt Request Flag Both READ and WRITE are possible with bit 7, but 1 can not be written to in this bit by software. Therefore, interrupt requests by software are not possible. By resetting, bit 7 is cleared and bit 6 is entered 1, TIMER The MCU timer block diagram is shown in Fig. 14, The 8- bit counter is loaded under program control and is decre- mented by the clock input. When the timer data register (TDR) reaches 0, the timer interrupt request bit (bit 7) in the timer controi register is set, The MCU responds to this inter- rupt by saving the present CPU state in the stack, fetching the timer interrupt routine address from address $1FF8 and $1FF9. The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the timer control register. The mask bit (I) in the condition code register can also disable the timer interrupt. The source clock for the timer can be either an external signal from the timer input pin or the internal E signal (oscillator clock divided by 4). If the E signal is selected as the source, the clock input can be gated by the input to the timer input pin. When the timer counter reaches 0, it starts counting down from $FF. The count can be monitored at any time by reading the timer data register. This function allows knowledge of the length of time after a timer interrupt with a program, without destroying the contents of the counter. When the MCU is reset, both the prescaler and counter return to the initial state of logical 1. At the same time, the timer interrupt request bit (bit 7) is cleared and the timer interrupt mask bit (bit 6) is set. Write O in the timer inter- Tupt request bit (bit 7} to clear it. TCR? Timer interrupt request 0 Absent 4 Present TCR6 Timer interrupt mask 0 Enabled 1 Disabled @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300 609HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Timer Control Register (TCR; $0009) Selection of a clock source, selection of a prescaler fre- quency division ratic, and a timer interrupt can be controlled by the timer control register (TCR; $0009). For the selection of a clock source, any one of the four modes (see Table 2) can be selected by bits 5 and 4 of the timer control register (TCR). Timer Control Register (TCR; $0009) 7 6 4 3 2 +1 ~D TCA FIT CREITCRSITCR4 rero}rcralreni|rcRo NY Prescaler initialize lock input source After resetting, the TCR is initialized to E under timer terminal control (bit 5 = 0, bit 4 = 1). Hf the timer terminal is 1, the counter starts counting down with SFF immediately after the reset. Table 2 Clock Source Selection L Prescaler division ratio selection |_1 rrr TCR . Clock input source Bit 5 Bit 4 0 0 Internal clock E 0 1 E under timer terminal control 1 0 No clock input (counting stopped) 1 1 Event input from timer terminal Timer interrupt mask (Internal Clock} Timer interrupt request Initialize Timer Control 4 Register } | (TCR:$0009) TIMER Input Terminal Clock Input TCR7ITCRE, rvs TCR3}TCAZITCAIITCAO +4|-6/ 16] 32/64 a Ly Multiplexer Timer Data Register (TDR:$0008) 8-Bit Counter Timer Interrupt | | Write Read Table 3 Prescaler Division Ratio Selection Figure 14 Timer Block Diagram The prescaler is initialized by writing 1 in bit 3. The bit is always 0, when READ. A prescaler division ratio is selected by a combination of the three bits (bits 0, 1 and 2) of the timer control register (See Table 3). There are eight division ratios; +1, +2, +4, +8, +16, +32, +64 and +128. After resetting,the TCR returns to the +1 mode. The timer interrupt is enabled when the timer interrupt mask bit is 0, and disabled when the bit is 1, When a timer interrupt occurs, 1 is set in the timer interrupt request bit. The bit is cleared by writing O into it. SSERIAL COMMUNICATION INTERFACE (SCI) Used for 8-bit data communication. Transfer rate ranges from Js to about 32 ms (when oscillated at 4 MHz), and there are sixteen selections. The SCI consists of three registers, one octal counter and one prescaler. (See Fig. 15) The SCI] communicates with the CPU through the data bus, and with peripherals through bits 5, 6 and 7 of port C. Operations of the registers and data transfer are described below, @ HITACHI TCR Bit 2 Bit 1 Bio Prescaler division ratio 0 0 0 +1 0 0 1 +2 0 1 0 +4 0 1 1 =B 1 0 0 +16 1 0 1 +32 1 1 0 +64 1 1 1 +128 610 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 SCi Control Registers (SCR; $0010} SCR7| SCRE SCR5 SCR4 SCR3 SCR2]SCR1/SCRO E ; L : Transfer Multi-] Pre- [WJ plexer| scaler | Clock me OTe 7 Cs(C } i ' > i ' . ' SCI Data Registers LN ! SOR: $0012) Eighth i ' Counter 7 6 5 4 2 7 0. Initialize i Ce(Rx) + MSB LSB ' CrtTxy 1 | i i L...... J Ly [6 5 4 3 2 i QO SSR7|SSR6|SSR5|SSR4|SSR3 soe eens Not Used SCI/TIMER:2 Figure 15 SCI Block Diagram @SCI Control Register (SCR; $0010) Bit 7 (SCR7) When this bit is set, the DDR corresponding to the C, 7 6 5 4 3 2 1 0 becomes 1 and this terminal serves for output of SCI data. scr7|scre}scrs |scra|scr3|scr2|scri|Scro After resetting the bit is cleared to 0. Bit 6 (SCR6) When this bit is set, the DDR corresponding to the C, SCR? C> terminal becomes 0 and this terminal serves for input of SCI data. After resetting the bit is cleared to 0. 0 Used as 1/0 terminal (by DOR}. - Bits and 4 (SCR5, SCR4) ' Serial data output {DDR output) These bits are used to select a clock source. After resetting the bits are cleared to 0. SCRE Ce terminal Bits 3~ 0 (SCR3 ~ SCRO) 0 Used as I/O terminal (by DOR). These bits are used to select a transfer clock rate. After resetting the bits are cleared to 0. 1 Serial data input (DDR input) Transfer clock rate SCR3 | S SCR5 |SCR4] Clock source C, terminal CR2 | SCR | SCRO 4.00MHz | 4.194 MHz 0 0 ~ Used as I/O terminal (by 9 9 0 o Vas 0.95 ps 0 1 _ DOR). 0 0 0 1 2 ps 1.91 ps 1 0 Internal Clock output (DDR output} ' Aus 3.82 us 0 0 1 1 8 us 7.64 ps 1 1 External Clock input (DDR input} a ? 2 z ? ? 1 1 1 1 32768 us 1/32 5 @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 611HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 SCI Deta Register (SOR; $0012) A serial-parallel conversion register that is used for transfer of data. SCI Status Register (SSA; $0011) i & 5 4 2 2 1 SSR7| SSRB| SSAE |SSR4 ssA3 Bit 7 (SSR7} Bit 7 is the SCI interrupt request bit which is set on com- pletion of transmitting or receiving 8-bit data. It is cleared when reset or data is written to or read from the SCI data register with the SCR5S=1. The bit can be cleared by writing OQ into it, Bit 6 (SSR6) Bit 6 is the TIMER: interrupt request bit. TIMER: is com- monly used with the serial clock generator, and SSRG6 is set each time the internal transfer clock falls, When resetting , the bit is cleared. It can also be cleared by writing 0 into it. (For details, see TIMER: ). Bit 5 (SSR5)} Bit 5 is the SCI interrupt mask bit which can be set of cleared by software. When it is 1"", the SCI interrupt (SSR7) is masked, When resetting, it is set to 1. Bit 4 (SSR4) Bit 4 is the TIMER, interrupt mask bit which can be set or cleared by software. When the bit is 1, the TIMER, interrupt (SSR6) is masked. When resetting, it is set to yy. Bit 3 (SSR3) When 1 is written into this bit, the prescaler of the trans- fer clock generator is initialized. When READ, the bit is always 0. Bits 2? ~0 Not used. SSR? SCI interrupt request 0 Absent 1 Present SSRE6 TIMER, interrupt request 0 Absent 1 Present SSA5 $Ci interrupt mask 0 Enabled 1 Disabled SSR4 TIMER, interrupt mask 0 Enabled 1 Disabled @ Data Transmission By writing the desired control bits into the SC] control registers, a transfer rate and a transfer clock source are deter- mined and bits 7 and 5 of port C are set at the serial data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data written in the SCI data register is output from the C7/Tx terminal, starting with the LSB, synchronously with the falling edge of the serial clock (See Fig. 16). When 8 bits of data have been transmitted, the interrupt request bit is set in bit 7 of the SCI status register with the rising edge of the last serial clock. This request can be masked by setting bit 5 of the SCI status re- gister. Once the data has been sent, the 8th bit data (MSB) stays at the C7/Tx terminal. If an external clock source has been selected, the transfer rate determined by bits 0 to 3 of the SCI control register is ignored, and the Cs/CK terminal is set as input. If the internal clock has been selected, the Cs/ CK terminal is set as output and clocks are output at the transfer rate selected by bits 0 to 3 of the SC] control re- gister. Secgs Chock (Cy CR) Outour Data (Cz 'Tat aoe emmymr ot NY EL Figure 16 SCI Timing Chart Data Reception By writing the desired control bits into the SCI control register, a transfer rate and a transfer clock source are de- termined and bit 6 and 5 of port C are set at the serial data input terminal and the serial clock terminal, respectively. Then dummy-writing or -reading the SCI data register, the system is ready for receiving data. (This procedure is not needed after reading subsequent received data. It must be taken after reset and after not reading subsequent received data.) The data from the C,/Rx terminal is input to the SCT data register synchronously with the rising edge of the serial clock (see Fig. 16). When 8 bits of data have been re- ceived, the interrupt request bit is set in bit 7 of the SCI status register. This request can be masked by setting bit 5 of the SCI status register. If an external clock source have been selected, the transfer rate determined by bits 0 ~ 3 of the SCI control register is ignored, and the data is received synchro- nously with the clock from the Cs {CK terminal. If the internal clock has been selected, the C,/CK terminal is set as output and clocks are output at the transfer rate selected by bits 0 ~ 3 of the SCI control register. e TIMER: The SCI transfer clock generator can be used as a timer. The clock selected by bits 3 to 0 of the SCI control register (4 ws to approx. 32 ms (when oscillated at 4 MHz)) is input to bit 6 of the SCI status register and the TIMER: interrupt request bit is set at each falling edge of the clock. Since inter- Tupt requests occur periodically, TIMER2 can be used as a teload counter or clock. @ HITACHI 612 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 @@ @ : Transfer clock generator is reset and mask bit (bit 4 of SCI. status register} is cleared. @,.@ : TIMER? interrupt request @.@ : TIMER: interrupt request bit cleared TIMER: is commonly used with the SCI transfer clock generator. If wanting to use TIMER2 independently of the SCI, specify External (SCRS = 1, SCR4 = 1) as the SCI clock source. _ If Internal is selected as the clock source, reading or writing the SDR causes the prescaler of the transfer clock generator to be initialized. #0 PORTS There are 24 input/output terminals (ports A, B, C). Each 1/O terminal can be selected for either input or output by the data direction register. Specifically, an I/O port will be input if 0 is written in the data direction register, and output if 1 is written in the data direction register. Port A, B or C reads latched data if it has been programmed as output, even with the output load, the output level fluctuating. (See Fig. 17). When resetting the data direction register and data register go to 0 and all input/output terminals are used as input. Seven input-only terminals are available (port D). Writing to these ones is invalid. All input/output terminals and input terminals are TTL compatible and CMOS compatible in respect of both input and output. If I/O ports or input ports are not used, they should be connected to Vgg via resistors. With none connected to these terminals, there is the possibility of power being consumed despite their not being used. 4) D> ~ Fi pist ait of data an of Status of Input to Hecho utp! output MCU register data 1 Q 0 0 1 1 1 1 0 x 3-state Pin Figure 17. Input/Output Port Diagram BRESET _ The MCU can be reset either by external reset input (RES) or power-on reset. (See Fig. 18). On power up, the reset input must be held Low for at least tose to assure that the internal oscillator is stabilized, A sufficient delay time can be obtained by connecting a capacitance to the RES input as shown in Fig. 19. 5V 45V Vee / OV AES Vin RES Terminal CL " tan Internal Reset Figure 18 Power On and Reset Timing 100k2 ty pF Vee WA HD63P05Y 1 MCU Figure 19 Input Reset Delay Circuit SINTERNAL OSCILLATOR The internal oscillator circuit is designed to meet the . _ 6/EXTAL als L 20-80MHA 5] .,, HD63PO5Y1 tt MCU T 10~22pF = 20% Crystal Oscillator t-r4 EXTAL GC 45 XTAL ee Cuz cu External Ceramic Oscillator Clock Input_GJEXTAL NC 5)XTAL HD63P05Y1 MCU J External Clock Drive Figure 20 Internal Oscillator Circuit @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 613HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 requirement for minimum external configurations. It can be driven by connecting a crystal (AT cut 2.0 ~ 8.0MHz)} or ceramic oscillator between pins 5 and 6 depending on the re- quired oscillation frequency stability. Three different terminal connections are shown in Fig, 20. Figs. 21 and 22 illustrate the specifications and typical arrange- ment of the crystal. Ci AT Cut Een Parallet L As Resonance +4 Co=7pF max. yal Co EMTAL =2.0~8.0MHz } Rs=602 max. Figure 21 Parameters of Crystal ta} Cr 4 Y) Crystal cs Ci XTAL EXTAL Crystal MCU [NOTE] Use as short wirings as possible for connection of the crystal with the EXTAL and XTAL terminals. Do not allow these wirings to cross others. Figure 22 Typical Crystal Arrangement BLOW POWER DISSIPATION MODE The HD63P05Yi has three low power dissipation modes: wait, stop and standby. o Wait Mode When a WAIT instruction being executed, the MCU enters into the wait mode. In this mode, the oscillator stays active but the internal clock stops. The CPU stops but the peripheral functions the timer and the serial communication inter- face stay active. (NOTE: Once the system has entered the wait mode, the serial communication interface can no longer be retriggered.) In the wait mode, the registers, RAM and I/O terminals hold the condition just before entering the wait mode. Both address (Ao ~ Aiz) and chip enable (CE) for the EPROM are in 1 state. Release from this mode can be done by interrupt (INT, TIMER/INT: or SCI/TIMER2), RES or STBY. The RES resets the MCU and the STBY brings it into the standby mode. (This will be mentioned later.) When interrupt is requested to the CPU and accepted. the wait mode is released and the CPU is brought to the operation mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register, after release from the wait mode the MCU executes the instruction follow- ing WAIT. If an interrupt other than the INT (i.e., TIMER/ INT: or SCI/TIMER2) is masked by the timer control re- gister, miscellaneous register or serial status register, there is no interrupt request to the CPU, so the wait mode cannot be released. Fig. 23 shows a flowchart of the wait function. Stop Mode When STOP instruction is being executed, the MCU enters the stop mode. In this mode, the oscillator stops and the CPU and peripheral functions become inactive but the RAM, register and I/O terminals hold the condition they had just before entering the stop mode, Both address (Ao ~ Aiz) and chip enable (CE) for the EPROM are in ] state. Release from this mode can be done by an external inter- rupt (INT or I or INTz), RES or STBY. The RES resets the MCU and the STBY brings it into the standby mode. When an interrupt is requested and accepted by the CPU, the stop mede is released and the CPU is brought in the opera- tion mode and vectors to the interrupt routine. If the inter- rupt is masked by the I bit of the condition code register, after release from the stop mode, the MCU executes the instruction following STOP. If the INT; interrupt is masked by the miscellaneous register, there is no interrupt request to the MCU, so the stop mode cannot be released. Fig. 24 shows the flowchart of the stop function. Fig. 25 shows a timing chart of the return to the operation mode from the stop mode. For releasing from the stop mode by an interrupt, oscilla- tion starts upon input of the interrupt? and, after the intemal delay time for stabilized oscillation, the CPU becomes active. For restarting by RES, oscillation starts when the RES goes O" and the CPU restarts when the RES goes 1.. The dura- tion of RES=0" must exceed tgs to assure stabilized oscil- lation. Standby Mode The MCUenters the standby mode when the STBY terminal goes Low. In this mode, all operations stop and the internal condition is reset but the contents of the RAM are held. The I/O terminals turn to high-impedance state. Both address (Ao ~ Aiz) and chip enable (CE) for the EPROM are in 1 state. The standby mode should be released by bringing STBY High. The CPU must be restarted by resetting. The timing of input signals at the RES and STBY terminals is shown in Fig. 26. Table 4 lists the status of each parts of the MCU in each low power dissipation modes. Transitions between each mode are shown in Fig. 27. @ HITACHI 614 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 { Wait ) Oscillator Active Timer and Serial Clock Active All Other Clocks Stop to Standby Mode Restart Processor Clocks Initialize CPU, TIMER, SCI, 10 and All Other Functions No Load PC from $1FFE, $1FFF Restart Processor Clocks Load PC from Interrupt Vector Addresses Fetch instruction Figure 23. Wait Mode Flow Chart @ HITACHI Hitachi America, Lid. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 615HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 ( Stop ) Oscillator and All Clocks Stop. STB to Standby Mode Turn on Oscillator Wait for Time Delay to Stabilize RES SJ Yes Load PC from Turn on Oscillator S1FFE, $1FFF Wait for Time Delay to Stabilize Load PC fram Interrupt Vector Addresses Fetch Instruction Figure 24 Stop Mode Flow Chart @ HITACHI 616 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 osewlator TTT Ao e LFULU LY Time required for oscillation to become L [=> STOP instruction Interrupt stabilized (built-in delay time) Instructions executed restart (a} Restart by Interrupt oseitator TTT A e LIUUL_, Time required for oscillation to become Sroute stabilized (tose) Reset start RES if dF (b) Restart by Reset Figure 25 Timing Chart of Releasing from Stop Made fs it | Ww losc Restart Figure 26 Timing Chart of Releasing from Standby Mode RES Table 4 Status of Each Part of MCU in Low Power Dissipation Modes Condition Mode Start Oscil- Timer, . VO Escape lator cPu Serial Register RAM terminal WAIT in- . . STBY, RES, INT, ENT :. WAIT : Active Stop Active Hold Hold Hold ach interrupt request of Soft. | struction TIMER, TIMER;, SCI | ware) STOP in- STBY AES iNT INT? STOP struction Stop Stop Stop Hold Hold Hold STB8Y, RES, INT, INT2 Stand- Hard- a=rav_- " High im- | aways pe by ware STBY="Low Stop Stop Stop Reset Hold pedance STBY="High HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 617HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Standby Mode Figure 27 Transitions among Active Mode, Wait Mode, Stop Mode, Standby Mode and Reset PRECAUTION TO THE BOARD DESIGN OF OSCILLA TION CIRCUIT As shown in Fig.28, the cross talk may disturb normal oscillation if signal lines are set near the oscillation circuit. When designing a board, be careful of this. Crystal and Cy must be put near XTAL and EXTAL pins as possible. Signal ime c pte 5 IXTAL fit 6 (EXTAL} +- - Signa line cy HD63PO0SY1 Figure 28 Precaution to the board design of oscillation circuit 8 PRECAUTION TO USE THE EPROM ON-PACKAGE 8-BIT SINGLE-CHIP MICROCOMPUTER Please be careful of the following, since this MCU has a special structure with pin socket on the package. (1) Dont apply high static voltage or surge voltage over MAXIMUM RATINGS to the socket pins as well as the LSI pins. If so, that may cause permanent damage to the device. (2) When using 32k EPROM (24-pin), insert it leaving the four pins above open. (3) When inserting this into system products like mask ROM type single chip microcomputer, be careful of the follow- ing to give effective contact between the EPROM pins and socket pins. @ HITACHI (b) 4 Pins (On index side) open. 24 Pin EPROM should be inserted on the mark side with 4 above open. Oo 0 bee c c c Co Cc o Cc oO c a a 9O9O06d%7DULmDNHDLDULUDUUCUMUCUCO 4G2 JAPAN HO63P05Y1 When soldering the LSI onto a printed circuit board, the recommended condition is Temperature: lower than 250C Time: within 10 sec. Be careful that detergent or coating does not get into the socket during flux washing or board coating after soldering, because that may cause bad effect on socket contact. Avoid permanent application of this under conditions 618 Hitachi America, Lid. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, GA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 of continuous vibration. (d) The socket, repeatedly inserted and removed, loses its contactability. It is recommended to use new one when used in production. SBIT MANIPULATION The HD63P05Y1 MCU can use a single instruction (BSET ot BCLR) to set or clear one bit of the RAM within page 0 or an I/O port (except the write-only registers such as the data direction register). Every bit of memory of I/O within page 0 ($00 ~ $FF) can be tested by the BRSET or BRCLR instruc- tion; depending on the result of the test, the program can branch to required destinations. Since bits in the RAM on page O, or 1/0 can be manipulated, the user may use a bit within the RAM on page O as a flag or handie a single I/O bit as an independent I/O terminal. Fig. 29 shows an example of bit manipulation and the validity of test instructions. In the example, the program is configured assuming that bit 0 of port A is connected to a zero cross detector circuit and bit | of the same port to the trigger of a triac. The program shown can activate the triac within a time of 10us from zero-crossing through the use of only 7 bytes on the memory. The on-chip timer provides a required time of delay and pulse width modulation of power is also possible. SELF 1. BRCLA 0, PORT A, SELF 1 BSET 1, PORTA BCLA 1,PORT A Figure 29 Example of Bit Manipulation SADDRESSING MODES Ten different addressing modes are available to the HD63P0S5Y1 MCU. o Immediate See Fig. 30, The immediate addressing mode provides access to a constant which does not vary during execution of the program. This access requires an instruction length of 2 bytes. The effective address (EA) is PC and the operand is fetched from the byte that follows the operation cade. Direct See Fig. 31. In the direct addressing mode, the address of the operand is contained in the 2nd byte of the instruction. The user can gain direct access to memory up to the lower 255th address. 192 byte RAM and I/O registers are on page 0 of address space so that the direct addressing mode may be utilized. Extended See Fig. 32. The extended addressing is used for referenc- ing to all addresses of memory. The EA is the contents of the 2 bytes that follow the operation code. An extended addressing instruction requires a length of 3 bytes. e Relative See Fig. 33. The relative addressing mode is used with branch instructions only. When a branch occurs, the program counter is toaded with the contents of the byte following the operation code. EA = (PC) + 2 + Rel., where Rel. indicates a signed 8-bit data following the operation code. If no branch occurs, Rel. = 0. When a branch occurs, the program jumps to any byte in the range +129 to -127. A branch instruction requires a length of 2 bytes. Indexed (No Offset) See Fig. 34. The indexed addressing mode allows access up to the lower 255th address of memory. In this mode, an instruction requires a length of one byte. The EA is the contents of the index register. Indexed (68-bit Offset) See Fig. 35. The EA is the contents of the byte follow- ing the operation code, plus the contents of the index register. This mode allows access up to the lower 511th address of memory. Each instruction when used in the index addressing mode (8-bit offset) requires a length of 2 bytes. e Indexed (16-bit Offset} See Fig. 36. The contents of the 2 bytes following the operation code are added to content of the index register to compute the value of EA. In this mode, the complete memory can be accessed. When used in the indexed address- ing mode (16-bit offset), an instruction must be 3 bytes long. Bit Set/Clear See Fig. 37, This addressing mode is applied to the BSET and BCLR instructions that can set or clear any bit on page 0. The lower 3 bits of the operation code specify the bit to be set or cleared. The byte that follows the operation code indicates an address within page 0. Bit Test and Branch See Fig. 38. This addressing mode is applied to the BRSET and BRCLR instructions that can test any bit within page 0 and can be branched in the relative addressing mode. The byte to be tested is addressed depending on the contents of the byte following the operation code. Individual bits within the byte to be tested are specified by the lower 3 bits of the operation code. The 3rd byte represents a relative value which will be added to the program counter when a branch condition is established. Each of these instructions should be 3 bytes long. The value of the test bit is written in the carry bit of the condition code register. e Implied See Fig. 39. This mode involves no EA. All information needed for execution of an instruction is contained in the operation code. Direct manipulation on the accumulator and index register is included in the implied addressing mode. Other instructions such as SWI and RTI are also used in this mode. All instructions used in the implied addressing mode should have a jength of one byte. @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 619HD63P05Y1, HD63PAO5Y1, HD63PBOS5Y1 A Index Reg : Stack Point PROG LDA 3 $FB8 O5BE as Prog Count cc Cc Figure 30 Example of Immediate Addressing CAT FCB 32 0048 PROG LDA CAT 052D OS2 [. Figure 31 Example of Direct Addressing EA Memory O6ES i : Adder ween 0000 A PROG LDA CAT 0409 C6 index Reg osoaf 06 Cc 0408 ES J Stack Point : Prog Count C fs Figure 32 Example of Extended Addressing @ HITACHI 620 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Memory PROG BEQ PROG2 O4A7 O4AB8 Figure 33 Example of Relative Addressing Memory TABL FCC Li 0088 PAOG LDA X O5F a Figure 34 Example of Indexed (No Offset) Addressing EA Memory aos r ' 1 ' : Adder TABL FCB g8F 0089 ar I FCB R86 OOBA 86 A FCB RCF O08C CF Index Reg } Stack Point PROG LDA TABL x 0758 6 one 8 Prog Count : : ) Figure 35 Example of Indexed (8-bit Offset) Addressing } HITACHI Hitachi America, Ltd. Hitachi Plaza e 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 621HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 622 EA Memory 0780 : Adder A - fe) Index Reg PROG LDA TABL X 0692 D6 Stack Point 0693 o7 0654 7E rag Count FOB 886 OF 7F a6 FCB ADB 0780 OB FCB WCF O7B1 CF eT Figure 36 Example of Indexed (16-bit Offset} Addressing Memory PORT B EQU 1 G001 index Reg PROG BCLR E PORT B OSaF Stach Point os90 rog Count cc Co Figure 37 Example of Bit Set/Clear Addressing Memory PORT C EQU 2 0002 PROG GRCLA 2 PORT C PROG 2 057. 06 05 Figure 38 Example of Bit Test and Branch Addressing @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HDG3PBO5Y1 I EA Memory eC 7 a + , PROG TAX OSBA A == Index Heg Les Stack Point Prog Count cc Figure 39 Example of Implied Addressing BINSTRUCTION SET There are 62 basic instructions available to the HD63P05Y1 MCU. They can be classified into five categories: register/ memory, read/modify/write, branch, bit manipulation, and control. The details of each instruction are described in Tables 5 through 11. Register/Memory Instructions Most of these instructions use two operands. One operand is either an accumulator or index register. The other is derived from memory using one of the addressing modes used on the MCU. There is no register operand in the unconditional jump instruction (JMP) and the subroutine jump instruction (JSR). See Table S. o Read/Modity/Write Instructions These instructions read a memory or register, then modify or test its contents, and write the modified value into the memory or register. Zero test instruction (TST) does not write data, and is handled as an exception in the read/modify/ write group. See Table 6. Branch Instructions A branch instruction branches from the program sequence in progress if a particular condition is established. See Table 7. e Bit Manipulation Instructions These instructions can be used with any bit located up to the lower 255th address of memory. Two groups are available; one for setting or clearing and the other for bit testing and branching. See Table 8. Control Instructions The control instructions control the operation of the MCU which is executing a program. See Table 9. List of Instructions in Alphabetical Order Table 10 lists all the instructions used on the MCU in the alphabetical order. e Operation Code Map Table 11 shows the operation code map for the instructions used on the MCU, @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 623HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Table 5 Register/Memory Instructions Addressing Modes Indexed | ind Indexed Booiean/ Condition Operations Mnemonic Immediate | = Direct Extended | (No Offset] | (8-8: Offset) | (16-Be Offset! Sanne Code OP) s | ~ (OP) s | ~;OP] | ~ [op] 2 | - [or] | - for] f- Hy) 1 IN| Zz] c Losd A from Mamory LDA A6/ 2/2 |B6] 2 | 3 )/ce) 3) 4/F6] 1/3 1e6) 2] 4 [pel a}s|Ma e7elalale Load X fram Memory (Dx AE} 2 | 2/BE} 2/3 /CE/ 3) 4/FE] 1/3 jee} 2/4 /Dbei 3/5] uMx *1e@ialal Store A in Memory STA B7'2)3/C7) 3) 41677 1) 4 /&7/ 214 /o7/ 3/5 [aw @lelalale Store X in Mamory STX BF) 2) 3 /CF) 3/4 /FF/ 1] 4+F1 2/4 /oF] 3/5 | x *@lelarlale Add Memory to A ADO AB) 2 | 2 |B&| 2 | 3 |cB/ 3/ 4/fB/ 1/3 /EB) 2] 4 {oBI 3/5) 4+MaA ALT@LATALA Add Memory and Carry toa ADC AS, 2 | 2 |B9| 2; 3/C9)3/4)/F9/ 113 /69| 2] 4 ]091 3/5 |] A+mecHa Al @>l ajaAla Subtract Memory SUB AO) 2) 2/BO) 2 | 3 |col 3] 4/Fo; 1} 3 eo] 2) 4 ool 3] 5) a-ma @elT@lalada Subtract Memory from A with Borrow SBC Az) 2] 2 |82/ 2/3 /c2/ 3 F2) 0] 3/62) 2] 4/D2; 3/5 | aA-mcoa @lelala AND Memory to A AND A4) 2/2/84) 2/3 /C4) 3] 4 /F4}4 |] 3 lea! 2 04) 3/5 /A- MA @e;,e,aAlAle OR Memory with A ORA AA) 212 (BA) 2/3 JCA) 3] 4 [FA] 1) 3 EA) 2 | 4 iDA] 3] 5 | a+MaA eles * Excluswe OR Memory with A or AB, 2] 2/88; 2 | 3 (CB) 3] 4 | FB} 1 | 3 ee) 2] 4 oe] 3) 5 | AgMa e/elalale Arithmetic Compare A with Memory CMP Al/ 272/81) 2/3 (C1) 3,4 /Fi] 1] 3 ]/E&t) 2] 4/p1]3]/5s]/a_-m @lelalala Arithmetic Compare X with Memory CPx AQ, 2) 2 |B3) 2/3 /C3) 3) 4/]F39) 1] 3/63} 2] 4 |pal 3} six-m @#felAlala Bit Test Memory with A (Lagical Compare) BIT AB) 2 | 2/85) 2/3 (C5) a] 4/esft]3iesj2}4losia/5/a-mM A Jump Unconditional JMP Bc] 2) 2 [cc] 3] 3 ]Fc] 1] 2 |ec| 2 i 3 |OC} 3} 4 ele Jump to Subroutine JSR J Tao} 2 ls col : Pg lFo| 1 5 ED 2 | 5 [O0D) 3] 6 - eleleje Symbols: Op = Operation # == Number of bytes ~ = Number of cycles Table 6 Read/Modify/Write Instructions Addressing Modes 1 T indexed Indexed Condition Operations Mnemonic f : Boolean/ Arithmetic Operation Code Imphed{A) | ImpliedixX) Direct (No Offset) | (B-Bit Offset] oP! s orl s | - [ar] op] | - [op] s HI tEN TZ [Cc Increment 'NC 4c} 1} 2 {5C) 1,2 (3c; 2/5 jac] 1] 5 6c] 2] 6 [A+1~aorxs+ixorM+toMlelelaAlale Decrement DEC 4A; 1] 2 5A) 112 (9A) 2/5 174 1: 5 /6Al 216 | a&-1-Aar X-1-KX or M-I1-M |e. e A|A|@ Clear CLA 4Fi 4] 2/56, 1) 2)3F! 2/5) 7F) 1) 5 |6F] 2] 6 | OOA or OOX of OO=M e,0/0/1 i* Complement com 143, 1/2 (83) 1 | 2/33) 2] 5:73) 115 163) 2] 6 | AA or KX of MoM efefalait Negate | O0-A-A or OO-XK | {2's Complement) NEG 40} 1/2 (50) 1) 2)3012/5]70! 1 | 5 [6a] 2: 6 jor 00g_-Mom @,ealAlAlaA Rotate Left Thru Carry ROL 49f 1/2/99) 1/2/39| 2) 5/79) 1/5/69] 2] 6 @lelAlAla Rotate Right Thru Carry ROA 46/1) 2 (56) 1) 2 136/275 (76/1/15 [66/216 @lelAlALA Logical Shift Left LSt 48/1) 2/8) 1) 2/38) 2/5 |78]/ 1] 5 jea} 2/6 @ Pe yalaAla Logical Shift Aight LSR 44/1) 2/54) 1) 2/34) 215/74, 1) 5]64] 2/6 @ re /Olala Arithmetic Shift Right ASA 47) 1/2/87) 1) 2/37) 2]5 137711) 5/67) 2/6 PAL ALA Arithmetic Shift Lett ASL 48/1} 2 (58) 1 | 2/38] 2 | 5 | 78) 1 | 5 |68) 2 | 6 | Equal to LSL Pl elaAlAsA Test for Negative i i or Zero TST 40/1)2 50) 1| 2 (3B 2) 4 {70 1) 4 leo) 215 A-00 or X--00 or M-00 e,elajsal@ Symbois: Op = Operation # = Number of bytes ~ = Number of cycles @ HITACHI 624 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Table 7 Branch Instructions Addressing Modes i . . = Condition Code Operations Mnemonic Relative Branch Test OP | + ~ HiT IN; 2/C Branch Always BRA 20 2 3 | None ee e|s/e Branch Never BRN 21 2 3 | None e,/e |e, e|e Branch IF Higher BH! 22 |} 2 3. )C+Z=0 e,e@eleiele Branch IF Lower or Same BLS 23 2 3 | C+Z= e,@e,@ele/\e Branch IF Carry Clear BCC 24 2 3 |C=0 e@ elel\ele (Branch IF Higher or Same) (BHS) 24/2 [3 [c=0 e eleleie Branch JF Carry Set BcSs 25 2 3 |C=1 ei ele iele (Branch IF Lower) (BLO) 25 2 3 |C=1 @;el/ei sie Branch IF Not Equal BNE 26 2 3 |Z=0 eliel/ele;e Branch IF Equal BEQ 27 2 3 \Z=1 e' e@el/e/e/)e Branch IF Half Carry Clear BHCC 28 2 3 |H=0 @e\/e@el/ele;e Branch IF Half Carry Set BHCS 29 2 3 |H=1 e,ele\iele Branch IF Plus BPL 2A 2 3 |N=0 ei ele ie ie Branch IF Minus BM! 28 2 3 | N=1 elielelieie Branch IF Interrupt Mask Bit is Clear BMC 2C 2 3 |1=0 e\e,e,@, 6 Branch IF Interrupt Mask Bit is Set BMS 2D] 2 3 |l=1 e e@ele'ie,e Branch IF Interrupt Line is Low BIL 2E 2 3 | INT=0 e|/eie|e ie Branch IF tnterrupt Line is High BIH 2F 2 3 | INT=1 eo e/e- sie Branch to Subroutine BSR AD 2 5 |}- else;eleie Symbols: Op = Operation # == Number of bytes ~ = Number of cycles Table 8 Bit Manipulation Instructions Addressing Modes Operations Mnemonic Bit Set/Ciear | Bit Test and Branch Arithmetic Branch Condition Code op |s|[-| oP | =| | Operation HT ITN] z]C Branch IF Bit n is set BRSET nin=O.:-7} -|- 2-n 3/5 oe Mn=1 @eil/e@e;elela Branch iF Bit nis clear | BRCLR nin=0.--?) - ~/|]0142-n/ 3/5 Mn=0 @eie el@ian Set Bit n BSET nin=0..-7) | 1042-n}| 2] 5 - -|- |1-Mn ele; ele ,e Clear Bit n BCLR nin=0-.-7) [114+2-n/} 2/5 _ -| |0-Mn eljsele|e;e Symbols: Op = Operation # == Number of bytes ~ = Number of cycles @ HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 625HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Table 9 Control Instructions Addressing Modes . Operations Mnemonic Implied Boolean Operation Condition Code OP | # ~ H/ I|]N;);Z/Cc Transfer A to X TAX 97 1 2 | AX @elelelele Transfer X ta A TXA oF 1 2 | XA e,;el;elele Set Carry Bit SEC 99 1 1 1c @eljejele 1 Clear Carry Bit cCLe 9B 1 1 |}O- @elel/e;e/0 Set Interrupt Mask Bit SEI 9B 1 2 | 1 elljelele Clear Interrupt Mask Bit cul SA 1 2 |a-1 e|O;lel/ele Software interrupt Swi B3 1 10 @;l1i/@e/ele Return from Subroutine RTS 81 1 5 e;el|/e;e|e Return from Interrupt AT! 80 1 8 P17), 77 74) 7 Reset Stack Pointer RSP 9c 1 2 | $FFSP elejelel|e No-Qperation NOP 9D 1 1 | Advance Prog. Catr. Only ejelelele Decimal Adjust A DAA BD | t | 2 | Soa tes binery add of BCD charcters into @elelalasa* Stop STOP BE 1 4 elel/elele Wait WAIT BF 1 4 elelietele Symbols: Op = Operation * Are BCD characters of upper byte 10 or more? {They are not cleared if set in advance.) # == Number of bytes ~ = Number of cycles Table 10 tnstruction Set {in Alphabetical Order) Addressing Modes Condition Code Bit Bit Indexed | Indexed | Indexed Set/ Test & implied | Immediate | Direct | Extended} Relative | (No Offset}| (8-Bit) | (16-Bit) Clear Branch x x x x x * x x x MEM] xX] x] mM] MY] KP RK H A A . e e s e e e e e Cy . * * e e e e elele(/elale el(ele;e;e ee e/e ele ele; e)/e/e;e/e); elelelelejele/>l/el/el|eiel/slelelelele|/>)/>i>([>)> [2 ejelelelel/el/el>i/ejelelel/e/@elele@e/e/e;> >) >) >15- 7,6 e;erelelel/elel/esele elelelelelelele|>|> (ee); >) >, o x x x x * x x x elejeletsse Condition Code Symbols: {to be continued) H Half Carry (From Bit 3} c Carry /Borrow ! Interrupt Mask A Test and Set if True. Cleared Otherwise N Negstive (Sign Bit) e Not Affected z Zero ? Load CC Register From Stack @ HITACHI 626 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Table 10 Instruction Set (in Alphabetical Order] Addressing Modes Condition Code Bit Bit Indexed | Indexed | indexed Set/ Test & Implied Direct Relative |(No Offset}| (8-Bit) | (16-Bit} | Clear | Branch BRN x SRCLR BRSET BSET BSR cLC cL CLR CMP COM CPX DAA DEC EOR INC JMP JSR LDA LOX LSL LSR NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB Swi TAX TST TXA WAIT Mnemonic x | xX] mM) x] | x] x] x x x x x x mm x x x x x ra x x x x x x x be vlelelelelel/eleielelelelelel/elelele el/ele/eleieie/e/e/e)/T ~wlelelelelelelelel|elel(elele/el/e/e/el/e(ele|/c.e/e/e/e)/e) 6 ~|@)|@) ei>lelel>|>lel>/ele/>le;slel>j>[>le]>]ol>|>[>/e/e >|[> ,>]>]/>]/>]/> [olelelelele/e,e! 2 elel>lelel>l>lel>lelel>lel~lel>/>]/> 1 e][>]>]>)>j>]/e/e >l>]>[>] >) >] >] -)e])e)@,e@;e@e;e@) ee] N elelielelel>jelelele|al>lej~rjel>|>j/ele)/>|>]/>,e/ele/e)/e;e/ >]>]-L>pele)cle le; >)> le, o @eljele|e/;-(|e/6)/e;@ Condition Code Symbols: H Half Carry (From Bit 3} Interrupt Mask N Negative (Sign Bit) 2 Zero Carry /Borrow Test and Set if True. Cleared Otherwise Not Affected Load CC Register From Stack ~~ OPO HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 627HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 Table 11. Operation Code Map Bit Manipulation Branch Read/Modify/Write Control Register /Memory Test & Set/ Branch Clear Rel DIR | A x | Xt} .X0 | IMP | IMP | IMM! DIR | EXT] .X2 | .X1 | xO oO 1 2 3 4 5 6 7 8 9 A B c D E F | HIGH 0! BRSETO BSETO BRA NEG RTI SUB oO 1 | BRCLRO BCLRO BRN RTS" CMP 1 | 2 | BRSETt BSET1 BHI $BC 2 3 | BRCLR1 BCiR1 BLS COM swi' CPX 3yL 4, BRSET2 BSET2 BCC LSR AND 4 2 5 | BRCLR2 BCLA2 Bcs BIT 6 | BRSET3 BSET3 BNE ROR LDA 6 7 | BRCLR3 BCLA3 BEQ ASR TAX STA {STA+1) 7 8 | BRSET4 BSET4 BHCC LSL/ASL cLc EOR 8 9) BRCLR4 BCLRA4 BHCS ROL SEC ADC 9 A | BRSETS BSET5S BPL DEC cLi* ORA A B; BRCLRS BCLAS BMI SEI* ADD 8 C | BRSET6 BSET6 BMC INC RSP* JMP( 1) c D| BACLR6E | BCLA6 | BMS |tst-1] TST | TSTi-1) [DAA*|NOP[BSR| JSA(+2) | JSR(+1) [sAe2] D E | BRSET? BSET7 BIL STOP*) LDX E F | BRCLR7 BCLR? BIH CLR WAIT*| TXA STX STXI+1)) F 3/5 2/5 2/3 [2/5] 1/2] 1/2| 26] 1/5] 17 | 1/1 | 272 | 2/3 | 3/4 | 3/5 | 2/4] 1/3 (NOTES) 1. " is an undefined operation code. 2. The lowermost numbers in each column represent a byte count and the number of cycles required {byte count/number of cycles). The number of cycles for the mnemonics asterisked [*) is as follows: ATI 8 TAX 2 RTS 5 RSP 2 Swi 10 TXA 2 DAA 2 8SR 5 stop 4 cul 2 WAIT 4 SE! 2 3. The parenthesized numbers must be added to the cycle count of the particular instruction. Additional Instructions @ PRECAUTION 2PROGRAM OF WRITE ONLY REGISTER The following new instructions are used on the HD63PO05Y1: Read/Modify/Write instructions are unavailable for changing the DAA Converts the contents of the accumulator into BCD contents of Write Only Register (e.g. DDR; Data Direction Register code. . . . of I/O port) of HD6305X, HD6305Y and HD63P0SY. WAIT Causes the MCU to enter the wait mode. For this mode, (1) Data cannot be read from Write Only Register. (e.g. DDR of see the topic, Wait Mode. 1/0 port STOP Causes the MCU to enter the stop mode. For this mode, see the topic, Stop Mode. While Read/Modify/Wnite instructions are executed in following sequence. @ PRECAUTION 1BOARD DESIGN OF OSCILLATION (i) Reads the contents from appointed address. CIRCUIT (ii) Changes the data which has been read. When connecting crystal and ceramic resonator with the XTAL and EXTAL pins to oscillate, observe the followings in designing the | board. ck (1} Locate crystal, ceramic resonator, and load capacity C, and XTAL C> as near the LSI as possible. (Induction of noise from @ EXTAL 5 outside to the XTAL and EXTAL pins may cause trouble in ce oscillation.) (2) Wire the signal lines to the neighboring XTAL and EXTAL p+ pins as far apart as possible. HD6305X (3) Board design of situating signal lines or power supply lines aoe oes | near the oscillator circuit as shown as Figure 41, should not be used because of trouble in oscillation by induction. The resis- tor between the XTAL and EXTAL, and pins close to them should be IOMQ or more. The circuit in Fig. 40 is an example of good board design. Figure 40 Design of Oscillation Circuit Board @ HITACHI 628 Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 (415) 589-8300HD63P05Y1, HD63PA05Y1, HD63PBO5Y1 (iii) Turn the data back to the original address. Thus, Read/Modify/Write instructions cannot be ap- plied to Write Only Register such as DOR. (2) For the same reason, do not set DOR of 1/O port using BSET and BCLR instructions. (3) Stored instructions (e.g. STA and STX, etc.) are available for writing into the Write Only Register. @ PRECAUTION 3--SENDING/RECEIVING PROGRAM OF SERIAL DATA Be careful that malfunction may occur if SDR (SERIAL DATA REGISTER: $0012) is read or written during transmitting or receiv- ing serial data. W@ PRECAUTION 4WAIT/STOP INSTRUCTIONS PROGRAM When I bit of condition code register is *1 and interrupt (INT, TIMER/INT2, SCI/TIMER 2) is held, the MCU does net enter into WAIT mode by executing WAIT instruction. In that case, after the 4 dummy cycles, the MCU executes the next instruction. In the same way, when external interrupts (INT, INT) are held at the bit I set, the MCU does not enter into the STOP mode by execut- ing STOP instruction. In that case the MCU executes the best in- struction after the 4 dummy cycles. --Signal A -Signal B ----/|--__-1_ + Signal tot cl ext (Part) 1's EXTAL jae Vy c2 14 I ot HD6305X HD6305 HD63P05Y Figure 41 Example of Circuit Causing Trouble in Oscillation @ PRECAUTION WHEN USING BIL/BIH INSTRUCTION (1) Execute Instruction after the INT Voltage level has stabilized above Vin or below VIL: (2) INT voltage level needs to be stabilized while BIL/BIH Instruc- tion Execution. There may be a malfunction by glitch on control signal_if BIL/BIH Instruction Execution has exercized in unstablized INT signal level. VIH INT vii BIL/BIH i 5 \ f Avold BIL/BIH instruction Execution @ PRECAUTION TO USE BSR If there is 2nd BSR programmed on the address which is directed by first BSR, 2nd BSR may not be executed correctly. For this reason, BSR should not be programmed on the address which is directed by first BSR. If necessary, please program as following. (1) On the address which first BSR directed, NOP instruction should be inserted before second BSR. (2) On the address which first BSR directed, JSR instruction should be programmed instead of 2nd BSR. SSR LBLI LBL BSR LBL2 ==, I 1 { ] | | LBL2--- ---- LBL3 --7- ---- example of malfunction of 2nd BSR execution BSR LBL | 1 | LBL1 NOP BSR LBL2 ! 1 \ LBL2-F- exampie of counter measure (NOP is inserted) BSR "| J S t I | l LBu1 SR LBL2 ! | l ! 1 LBL2-- -=- { \ example of counter measure (JSR is used instead of BSR) @ HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 629