Dual, 16 MHz, Rail-to-Rail
FET Input Amplifier
AD823
Rev. D
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FEATURES
Single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 3 V to 36 V
High load drive
Capacitive load drive of 500 pF, G = +1
Output current of 15 mA, 0.5 V from supplies
Excellent ac performance on 2.6 mA/amplifier
−3 dB bandwidth of 16 MHz, G = +1
350 ns settling time to 0.01% (2 V step)
Slew rate of 22 V/μs
Good dc performance
800 μV maximum input offset voltage
2 μV/°C offset voltage drift
25 pA maximum input bias current
Low distortion: −108 dBc worst harmonic @ 20 kHz
Low noise: 16 nV/√Hz @ 10 kHz
No phase inversion with inputs to the supply rails
APPLICATIONS
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 16-bit data acquisition systems
Medical instrumentation
GENERAL DESCRIPTION
The AD823 is a dual precision, 16 MHz, JFET input op amp
that can operate from a single supply of 3.0 V to 36 V or from
dual supplies of ±1.5 V to ±18 V. It has true single-supply
capability with an input voltage range extending below ground
in single-supply mode. Output voltage swing extends to within
50 mV of each rail for IOUT ≤ 100 µA, providing outstanding
output dynamic range.
An offset voltage of 800 µV maximum, an offset voltage drift of
2 µV/°C, input bias currents below 25 pA, and low input voltage
noise provide dc precision with source impedances up to a
Gigaohm. It provides 16 MHz, −3 dB bandwidth, −108 dB THD
@ 20 kHz, and a 22 V/µs slew rate with a low supply current of
2.6 mA per amplifier. The AD823 drives up to 500 pF of direct
capacitive load as a follower and provides an output current of
15 mA, 0.5 V from the supply rails. This allows the amplifier to
handle a wide range of load conditions.
CONNECTION DIAGRAM
AD823
OUT1
+IN2
–IN2
OUT2
+V
S
–IN1
+IN1
–V
S
1
2
3
4
8
7
6
5
00901-001
Figure 1. 8-Lead PDIP and SOIC
3V
GND
00901-002
R
L
= 100kΩ
C
L
= 50pF
+V
S
= +3V
G = +1
500mV 200µs
Figure 2. Output Swing, +VS = +3 V, G = +1
FREQUENCY (Hz)
–8
OUTPUT (dB)
1k
–6
–7
2
1
10k 100k 1M
+V
S
= +5V
G = +1
–5
–4
–3
–2
–1
0
10M
00901-003
Figure 3. Small Signal Bandwidth, G = +1
This combination of ac and dc performance, plus the outstanding
load drive capability, results in an exceptionally versatile ampli-
fier for applications such as A/D drivers, high speed active
filters, and other low voltage, high dynamic range systems.
The AD823 is available over the industrial temperature range of
−40°C to +85°C and is offered in both 8-lead PDIP and 8-lead
SOIC packages.
AD823
Rev. D | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 13
Output Impedance ..................................................................... 14
Application Notes ........................................................................... 15
Input Characteristics .................................................................. 15
Output Characteristics............................................................... 15
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/10—Rev. C to Rev. D
Changes to Figure 34 ...................................................................... 11
Changes to Figure 36 ...................................................................... 13
5/10—Rev. B to Rev. C
Changes to Table 4 ............................................................................ 6
2/07—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to DC Performance .......................................................... 5
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide ......................................................... 19
5/04—Rev. 0 to Rev. A
Changes to Specifications ................................................................ 2
Changes to Ordering Guide ......................................................... 17
Updated Outline Dimensions ....................................................... 17
5/95—Revision 0: Initial Version
AD823
Rev. D | Page 3 of 20
SPECIFICATIONS
At TA = 25°C, +VS = +5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p G = +1 12 16 MHz
Full Power Response VO = 2 V p-p 3.5 MHz
Slew Rate G = −1, VO = 4 V Step 14 22 V/μs
Settling Time
to 0.1% G = −1, VO = 2 V Step 320 ns
to 0.01% G = −1, VO = 2 V Step 350 ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 1 kHz 1 fA/√Hz
Harmonic Distortion RL = 600 Ω to 2.5 V, VO = 2 V p-p, f = 20 kHz −108 dBc
Crosstalk
f = 1 kHz RL = 5 kΩ −105 dB
f = 1 MHz RL = 5 kΩ −63 dB
DC PERFORMANCE
Initial Offset 0.2 0.8 mV
Maximum Offset Over temperature 0.3 2.0 mV
Offset Drift 2 μV/°C
Input Bias Current VCM = 0 V to 4 V 3 25 pA
at TMAX VCM = 0 V to 4 V 0.5 5 nA
Input Offset Current 2 20 pA
at TMAX 0.5 nA
Open-Loop Gain VO = 0.2 V to 4 V, RL = 2 kΩ 20 45 V/mV
TMIN to TMAX 20 V/mV
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range −0.2 to +3 −0.2 to +3.8 V
Input Resistance 1013 Ω
Input Capacitance 1.8 pF
Common-Mode Rejection Ratio VCM = 0 V to 3 V 60 76 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 μA 0.025 to 4.975 V
IL = ±2 mA 0.08 to 4.92 V
IL = ±10 mA 0.25 to 4.75 V
Output Current VOUT = 0.5 V to 4.5 V 16 mA
Short-Circuit Current Sourcing to 2.5 V 40 mA
Sinking to 2.5 V 30 mA
Capacitive Load Drive G = +1 500 pF
POWER SUPPLY
Operating Range 3 36 V
Quiescent Current TMIN to TMAX, total 5.2 5.6 mA
Power Supply Rejection Ratio VS = 5 V to 15 V, TMIN to TMAX 70 80 dB
AD823
Rev. D | Page 4 of 20
At TA = 25°C, +VS = +3.3 V, RL = 2 kΩ to 1.65 V, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p G = +1 12 15 MHz
Full Power Response VO = 2 V p-p 3.2 MHz
Slew Rate G = −1, VO = 2 V Step 13 20 V/μs
Settling Time
to 0.1% G = −1, VO = 2 V Step 250 ns
to 0.01% G = −1, VO = 2 V Step 300 ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 1 kHz 1 fA/√Hz
Harmonic Distortion RL = 100 Ω, VO = 2 V p-p, f = 20 kHz −93 dBc
Crosstalk
f = 1 kHz RL = 5 kΩ −105 dB
f = 1 MHz RL = 5 kΩ −63 dB
DC PERFORMANCE
Initial Offset 0.2 1.5 mV
Maximum Offset Over temperature 0.5 2.5 mV
Offset Drift 2 μV/°C
Input Bias Current VCM = 0 V to 2 V 3 25 pA
at TMAX VCM = 0 V to 2 V 0.5 5 nA
Input Offset Current 2 20 pA
at TMAX 0.5 nA
Open-Loop Gain VO = 0.2 V to 2 V, RL = 2 kΩ 15 30 V/mV
TMIN to TMAX 12 V/mV
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range −0.2 to +1 −0.2 to +1.8 V
Input Resistance 1013 Ω
Input Capacitance 1.8 pF
Common-Mode Rejection Ratio VCM = 0 V to 1 V 54 70 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 μA 0.025 to 3.275 V
IL = ±2 mA 0.08 to 3.22 V
IL = ±10 mA 0.25 to 3.05 V
Output Current VOUT = 0.5 V to 2.5 V 15 mA
Short-Circuit Current Sourcing to 1.5 V 40 mA
Sinking to 1.5 V 30 mA
Capacitive Load Drive G = +1 500 pF
POWER SUPPLY
Operating Range 3 36 V
Quiescent Current TMIN to TMAX, total 5.0 5.7 mA
Power Supply Rejection Ratio VS = 3.3 V to 15 V, TMIN to TMAX 70 80 dB
AD823
Rev. D | Page 5 of 20
At TA = 25°C, VS = ±15 V, RL = 2 kΩ to 0 V, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth, VO ≤ 0.2 V p-p G = +1 12 16 MHz
Full Power Response VO = 2 V p-p 4 MHz
Slew Rate G = −1, VO = 10 V Step 17 25 V/μs
Settling Time
to 0.1% G = −1, VO = 10 V Step 550 ns
to 0.01% G = −1, VO = 10 V Step 650 ns
NOISE/DISTORTION PERFORMANCE
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 1 kHz 1 fA/√Hz
Harmonic Distortion RL = 600 Ω, VO = 10 V p-p, f = 20 kHz −90 dBc
Crosstalk
f = 1 kHz RL= 5 kΩ −105 dB
f = 1 MHz RL= 5 kΩ −63 dB
DC PERFORMANCE
Initial Offset 0.7 3.5 mV
Maximum Offset Over temperature 1.0 7 mV
Offset Drift 2 μV/°C
Input Bias Current VCM = 0 V 5 30 pA
V
CM = −10 V 60 pA
at TMAX VCM = 0 V 0.5 5 nA
Input Offset Current 2 20 pA
at TMAX 0.5 nA
Open-Loop Gain VO = +10 V to −10 V, RL = 2 kΩ 30 60 V/mV
TMIN to TMAX 30 V/mV
INPUT CHARACTERISTICS
Input Common-Mode Voltage Range −15.2 to +13 −15.2 to +13.8 V
Input Resistance 1013 Ω
Input Capacitance 1.8 pF
Common-Mode Rejection Ratio VCM = −15 V to +13 V 66 82 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
IL = ±100 μA −14.95 to +14.95 V
IL = ±2 mA −14.92 to +14.92 V
IL = ±10 mA −14.75 to +14.75 V
Output Current VOUT = −14.5 V to +14.5 V 17 mA
Short-Circuit Current Sourcing to 0 V 80 mA
Sinking to 0 V 60 mA
Capacitive Load Drive G = +1 500 pF
POWER SUPPLY
Operating Range 3 36 V
Quiescent Current TMIN to TMAX, total 7.0 8.4 mA
Power Supply Rejection Ratio VS = 5 V to 15 V, TMIN to TMAX 70 80 dB
AD823
Rev. D | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 36 V
Internal Power Dissipation
PDIP (N) 1.3 W
SOIC (R) 0.9 W
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±VS
Output Short-Circuit Duration See Figure 4
Storage Temperature Range N, R −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature Range
(Soldering, 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Specification is for device in free air.
Table 5. Thermal Resistance
Package Type θJA Unit
8-Lead PDIP 90 °C/W
8-Lead SOIC 160 °C/W
MAXIMUM POWER DISSIP
A
TION (W)
AMBIENT TEMPERATURE (°C)
2.0
1.5
0
–50 90–40 –30 –20 –10 0 10 20 30 50 60 70 8040
1.0
0.5
8-LEAD PDIP
8-LEAD SOIC
T
J
= 150°C
00901-004
Figure 4. Maximum Power Dissipation vs. Temperature
ESD CAUTION
AD823
Rev. D | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET VOLTAGE (µV)
80
0
–200 200–150
UNITS
–100 –50 0 50 100 150
70
40
30
20
10
60
50
+V
S
= +5V
314 UNITS
σ = 40µV
00901-005
Figure 5. Typical Distribution of Input Offset Voltage
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
22
0
–6 7–5
UNITS
–4 –3 –2 3 4 5
20
6
4
2
18
16
14
12
10
8
6–1 0 1 2
+V
S
= +5V
–55°C TO +125°C
103 UNITS
00901-006
Figure 6. Typical Distribution of Input Offset Voltage Drift
COMMON-MODE VOLTAGE (V)
–4
INPUT BIAS CURRENT (pA)
–5
0
–1
–2
–3
3+V
S
= +5V
1
2
–4 –3 –2 –1 0 1 5432
0
0901-007
Figure 7. Input Bias Current vs. Common-Mode Voltage
INPUT BIAS CURRENT (pA)
100
0
UNITS
0
90
40
30
20
10
80
70
+V
S
= +5V
317 UNITS
σ = 0.4pA
50
60
12 34567 8910
00901-008
Figure 8. Typical Distribution of Input Bias Current
TEMPERATURE (°C)
0.1
INPUT BIAS CURRENT (pA)
0
100
10
1
10000 +V
S
= +5V
V
CM
= 0V
1000
25 50 75 100 125
0
0901-009
Figure 9. Input Bias Current vs. Temperature
COMMON-MODE VOLTAGE (V)
0.1
INPUT BIAS CURRENT (pA)
–16
100
10
1
1000
–12 4 8 12 16
V
S
= ±15V
–8 –4 0
00901-010
Figure 10. Input Bias Current vs. Common-Mode Voltage
AD823
Rev. D | Page 8 of 20
LOAD RESISTANCE (Ω)
60
80
70
90
100
110
OPEN-LOOP GAIN (dB)
100 1k 10k 100k 500k
V
S
= ±2.5V
00901-011
Figure 11. Open-Loop Gain vs. Load Resistance
OUTPUT VOLTAGE (V)
0.1
OPEN-LOOP GAIN (k
–2.5
100
10
1
1000
–2.0 –0.5 0.5 1.0 2.5
R
L
= 10kΩ
–1.5 –1.0 0 1.5 2.0
R
L
= 1kΩ
R
L
= 100Ω
V
V)
00901-012
Figure 12. Open-Loop Gain vs. Output Voltage, VS = ±2.5 V
FREQUENCY (Hz)
–
40
–110
–50
–80
–90
–100
–60
–70
100 100k
THD (dB)
1k 10k
+VS = +3V
VOUT = 2V p-p
RL = 100Ω
+VS = +3V
VOUT = 2V p-p
RL = 5kΩ
+VS = +5V
VOUT = 2V p-p
RL = 5kΩ
VS = ±15V
VOUT = 10V p-p
RL = 600Ω
VS = ±2.5V
VOUT = 2V p-p
RL = 1kΩ
1M
ALL
OTHERS
00901-013
Figure 13. Total Harmonic Distortion vs. Frequency
TEMPERATURE (°C)
86
90
89
88
87
95
91
92
93
94
OPEN-LOOP GAIN (dB)
–55
+VS = +5V
RL = 2kΩ
–25 5 35 65 95 125
00901-014
Figure 14. Open-Loop Gain vs. Temperature
FREQUENCY (Hz)
100
–20
80
40
20
0
60
100 100M1k 10k 100k 1M 10M
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
PHASE
GAIN
RL = 2kΩ
CL = 20pF
100
–20
80
40
20
0
60
00901-015
Figure 15. Open-Loop Gain and Phase Margin vs. Frequency
FREQUENCY (Hz)
100
30
310 1M100 1k 10k 100k
10
+V
S
= +5V
INPUT VOLTAGE NOISE (nV/
√
Hz)
0
0901-016
Figure 16. Input Voltage Noise vs. Frequency
AD823
Rev. D | Page 9 of 20
FREQUENCY (MHz)
5
–5
CLOSED-LOOP GAIN (dB)
0.30
4
–1
–2
–3
–4
3
2
0
1
3.27 6.24 9.21 12.18 15.15 18.12 21.09 24.06 27.03 30.00
–55°C
+125°C
+27°C
C
L
= 20pF
R
L
= 2kΩ
G = +1
0
0901-017
Figure 17. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
0.01
10
100
0.1
1
OUTPUT RESISTANCE (Ω)
100 1k 10k 100k 10M1M
+V
S
= +5V
GAIN = +1
00901-018
Figure 18. Output Resistance vs. Frequency, +VS = +5 V, Gain = +1
SETTLING TIME (ns)
–10
OUTPUT STEP SIZE FROM 0
V
TO V
SHOWN
(V)
10
100 200 400 500 700600
V
S
= ±15V
C
L
= 20pF
–8
0
300
–6
–4
–2
2
4
6
81% 0.1% 0.01%
1% 0.1% 0.01%
00901-019
Figure 19. Output Step Size vs. Settling Time (Inverter)
FREQUENCY (Hz)
20
70
60
90
80
30
40
50
CMRR (dB)
10
V
S
= ±15V
100 1k 10k 100k 10M1M
+V
S
= +5V
00901-020
Figure 20. Common-Mode Rejection Ratio vs. Frequency
LOAD CURRENT (mA)
0.01
1
10
0.1
OUTPUT S
A
TUR
A
TION VOLTAG E (V)
0.1 1 10 100
+V
S
= +5V
V
S
– V
OH
25°C
V
OL
25°C
0
0901-021
Figure 21. Output Saturation Voltage vs. Load Current
SUPPLY VOLTAGE (±V)
0
QUIESCENT CURRENT (mA)
0
4
2
10
8
51015
6
20
+125°C
+25°C
–55°C
00901-022
Figure 22. Quiescent Current vs. Supply Voltage
AD823
Rev. D | Page 10 of 20
FREQUENCY (Hz)
0
30
20
10
100
40
50
60
70
80
90
POWER SUPPLY REJECTION (dB)
100 1k 10k 100k 1M 10M
+PSRR
–PSRR
+V
S
= +5V
00901-023
Figure 23. Power Supply Rejection vs. Frequency
FREQUENCY (Hz)
0
OUTPUT VOLTAGE (V p-p)
10k
10
30
100k 1M 10M
20
R
L
= 2kΩ
G = +1
V
S
= ±15V
+V
S
= +5V
+V
S
= +3V
00901-024
Figure 24. Large Signal Frequency Response
100kΩ
3V
V
OUT
50pF
100kΩ
50Ω
100kΩ
V
IN
= 2.9V p-p
0
0901-025
500mV 10µs
V
IN
= 2.9V p-p
+V
S
= +3V
G = –1
Figure 25. Output Swing, +VS = +3 V, G = −1
R
S
C
L
V
IN
CAPACITOR (pF × 1000)
0
SERIES RESISTANCE (Ω)
0
12
9
6
3
21
Ф
M
= 20°
15
18
12345678910
Ф
M
= 45°
+V
S
= +5V
00901-026
Figure 26. Series Resistance vs. Capacitive Load
FREQUENCY (Hz)
–1301k
–110
–120
–
30
–40
10k 100k 1M
+V
S
= +5V
–100
–90
–80
CROSSTALK (dB)
–70
–60
–50
10M
00901-027
Figure 27. Crosstalk vs. Frequency
20kHz, 20V p-p
–15V
+15V
50pF
604Ω
00901-028
5V 20µs
VIN = 20V p-p
VS = ±15V
G = +1
Figure 28. Output Swing, VS = ±15 V, G = +1
AD823
Rev. D | Page 11 of 20
5
V
GND
00901-029
500mV 200µs
RL = 300Ω
CL = 50pF
RF = RG = 2kΩ
+VS = +5V
G = –1
Figure 29. Output Swing, +VS = +5 V, G = −1
1.55
V
1.45
V
00901-030
25mV 50ns
V
IN
= 100mV STEP
+V
S
= +3V
G = +1
Figure 30. Pulse Response, +VS = +3 V, G = +1
5
V
GND
00901-031
500mV 100ns
R
L
= 2kΩ
C
L
= 50pF
+V
S
= +5V
G = +2
Figure 31. Pulse Response, +VS = +5 V, G = +2
3V
GND
00901-032
500mV 200µs
RL = 100kΩ
CL = 50pF
+VS = +3V
G = +1
Figure 32. Output Swing, +VS = +3 V, G = +1
5
V
GND
00901-033
500mV 100ns
RL = 2kΩ
CL = 50pF
+VS = +5V
G = +1
Figure 33. Pulse Response, +VS = +5 V, G = +1
00901-034
500mV 200ns
R
L
= 2kΩ
C
L
= 470pF
+V
S
= +5V
G = +1
Figure 34. Pulse Response, +VS = +5 V, G = +1, CL = 470 pF
AD823
Rev. D | Page 12 of 20
10
–
10
V
00901-035
5V 500ns
R
L
= 100kΩ
C
L
= 50pF
V
S
= ±15V
G = +1
Figure 35. Pulse Response, VS = ±15 V, G = +1
AD823
Rev. D | Page 13 of 20
THEORY OF OPERATION
The AD823 is fabricated on the Analog Devices, Inc. proprietary
complementary bipolar (CB) process that enables the construction
of PNP and NPN transistors with similar fT’s in the 600 MHz to
800 MHz region. In addition, the process also features N-Channel
JFETs that are used in the input stage of the AD823. These
process features allow the construction of high frequency, low
distortion op amps with picoamp input currents. This design
uses a differential output input stage to maximize bandwidth
and headroom (see Figure 36). The smaller signal swings
required on the S1P/S1N outputs reduce the effect of the
nonlinear currents due to junction capacitances and improve
the distortion performance. With this design, harmonic
distortion of better than −91 dB @ 20 kHz into 600  with
VOUT = 4 V p-p on a single 5 V supply is achieved. The
complementary common emitter design of the output stage
provides excellent load drive without the need for emitter
followers, thereby improving the output range of the device
considerably with respect to conventional op amps. The
AD823 can drive 20 mA with the outputs within 0.6 V of the
supply rails. The AD823 also offers outstanding precision for a
high speed op amp. Input offset voltages of 1 mV maximum
and offset drift of 2 µV/°C are achieved through the use of the
Analog Devices advanced thin film trimming techniques.
A nested integrator topology is used in the AD823 (see Figure 37).
The output stage can be modeled as an ideal op amp with a
single-pole response and a unity-gain frequency set by
transconductance gm2 and Capacitor C2. R1 is the output
impedance of the input stage; gm is the input transconductance.
C1 and C5 provide Miller compensation for the overall op amp.
The unity-gain frequency occurs at gm/C5. Solving the node
equations for this circuit yields
()
[]
()
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+
⎥
⎦
⎤
⎢
⎣
⎡
×++
=
1
2
11211
0
2
C
g
sACsR
A
Vi
V
m
OUT
where:
A0 = gmgm2 R2R1 (open-loop gain of op amp)
A2 = gm2 R2 (open-loop gain of output stage).
The first pole in the denominator is the dominant pole of the
amplifier and occurs at ~18 Hz. This equals the input stage
output impedance R1 multiplied by the Miller-multiplied value
of C1. The second pole occurs at the unity-gain bandwidth of
the output stage, which is 23 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard 2-stage architecture would allow.
V
CC
V
INP
V
INN
V
EE
R42 R37
J1 J6
I1 C6 R33 I2 R43
I3 Q56
S1P
Q72 Q61
Q46
I5
V
BE
+0.3V
S1N
Q53 Q35
Q48
V
CC
Q21
Q62 Q60
Q54
R44 R28
Q52 I4 Q59
A = 1
V
B
C1
Q17
A = 19
V
OUT
C2
Q18
Q49
Q55
Q43 I6 Q44
A = 1
Q57
A = 19
Q58
V1
00901-036
Figure 36. Simplified Schematic
AD823
Rev. D | Page 14 of 20
OUTPUT IMPEDANCE
The low frequency open-loop output impedance of the common-
emitter output stage used in this design is approximately 30 kΩ.
Although this is significantly higher than a typical emitter
follower output stage, when it is connected with feedback, the
output impedance is reduced by the open-loop gain of the op
amp. With 109 dB of open-loop gain, the output impedance is
reduced to <0.2 Ω. At higher frequencies, the output impedance
rises as the open-loop gain of the op amp drops; however, the
output also becomes capacitive due to the integrator capacitors
C1 and C2. This prevents the output impedance from ever
becoming excessively high (see Figure 18), which can cause
stability problems when driving capacitive loads. In fact, the AD823
has excellent cap-load drive capability for a high frequency op
amp. Figure 34 shows the AD823 connected as a follower while
driving 470 pF direct capacitive load. Under these conditions,
the phase margin is approximately 20°. If greater phase margin
is desired, a small resistor can be used in series with the output
to decouple the effect of the load capacitance from the op amp
(see Figure 26). In addition, running the part at higher gains
also improves the capacitive load drive capability of the op amp.
V
OUT
S1N C1
S1P
C5R1
R1
g
m
VI
g
m
VI
g
m2
C2
R2
00901-037
Figure 37. Small Signal Schematic
AD823
Rev. D | Page 15 of 20
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD823, N-Channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input common-
mode voltage extends from 0.2 V below −VS to 1 V < +VS. Driving
the input voltage closer to the positive rail causes a loss of amplifier
bandwidth and increased common-mode voltage error.
The AD823 does not exhibit phase reversal for input voltages up
to and including +VS. Figure 38 shows the response of an AD823
voltage follower to a 0 V to 5 V (+VS) square wave input. The
input and output are superimposed. The output polarity tracks
the input polarity up to +VS, with no phase reversal. The reduced
bandwidth above a 4 V input causes the rounding of the output
wave form. For input voltages greater than +VS, a resistor in
series with the AD823’s noninverting input prevents phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 39.
GND
100
0%
1V 2µs
1V
90
00901-038
10
Figure 38. AD823 Input Response: RP = 0, VIN = 0 to +VS
+VS
GND
5V
VIN
RP
VOUT
AD823
1V
10 µs1V
00901-039
90
100
10
0%
Figure 39. AD823 Input Response:
VIN = 0 to +VS + 200 mV, VOUT = 0 to +VS, RP = 49.9 kΩ
Because the input stage uses N-Channel JFETs, input current
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS − 0.4 V, the input current reverses direction as internal
device junctions become forward biased. This is illustrated in
Figure 7.
A current limiting resistor should be used in series with the
input of the AD823 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage is applied to the AD823 when ±VS = 0. The
amplifier becomes damaged if left in that condition for more
than 10 seconds. A 1 kΩ resistor allows the amplifier to
withstand up to 10 V of continuous overvoltage and increases
the input voltage noise by a negligible amount.
Input voltages less than −VS are a completely different story.
The amplifier can safely withstand input voltages 20 V below
−VS as long as the total voltage from the positive supply to the
input terminal is less than 36 V. In addition, the input stage
typically maintains picoamp level input currents across that
input voltage range.
The AD823 is designed for 16 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(see Figure 16). This noise performance, along with the AD823’s
low input current and current noise, means that the AD823
contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz.
OUTPUT CHARACTERISTICS
The AD823’s unique bipolar rail-to-rail output stage swings
within 25 mV of the supplies with no external resistive load.
The AD823’s approximate output saturation resistance is 25 Ω
sourcing and sinking. This can be used to estimate the output
saturation voltage when driving heavier current loads. For
instance, when driving 5 mA, the saturation voltage to the rails
is approximately 125 mV.
If the AD823’s output is driven hard against the output
saturation voltage, it recovers within 250 ns of the input
returning to the amplifier’s linear operating region.
A/D Driver
The rail-to-rail output of the AD823 makes it useful as an A/D
driver in a single-supply system. Because it is a dual op amp, it
can be used to drive both the analog input of the A/D as well as
its reference input. The high impedance FET input of the
AD823 is well suited for minimal loading of high output
impedance devices.
AD823
Rev. D | Page 16 of 20
Figure 40 shows a schematic of an AD823 being used to drive
both the input and reference input of an AD1672, a 12-bit,
3-MSPS, single-supply ADC. One amplifier is configured as a
unity-gain follower to drive the analog input of the AD1672,
which is configured to accept an input voltage that ranges from
0 V to 2.5 V.
The other amplifier is configured as a gain of 2 to drive the
reference input from a 1.25 V reference. Although the AD1672
has its own internal reference, there are systems that require
greater accuracy than the internal reference provides. On the other
hand, if the AD1672 internal reference is used, the second AD823
amplifier can be used to buffer the reference voltage for driving
other circuitry while minimally loading the reference source.
13
14
12
11
10
9
8
7
6
5
4
3
2
1
19 18
+5VA
10µF
0.1µF
2
3
5
6
4
7
1
8
49.9Ω
10µF 0.1µF 0.1µF 10µF
0.1µF
+5
V
A
+5VD
+5VD
20
21
22
23
24
25
26
27
16
CLOCK
1kΩ
1kΩ
V
IN
V
REF
(1.25V)
BIT1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12 (LSB)
15 OTR
REFOUT
AIN1
AIN2
REFIN
REFCOM
NCOMP2
NCOMP1
ACOM
COM
REF
DCOM
AD823
+V
CC
+V
DD
28 19
AD1672
00901-040
Figure 40. AD823 Driving Input and Reference of the
AD1672, a 12-Bit, 3-MSPS ADC
The circuit was tested with a 500 kHz sine wave input that was
heavily low-pass filtered (60 dB) to minimize the harmonic content
at the input to the AD823. The digital output of the AD1672 was
analyzed by performing a fast Fourier transform (FFT).
During the testing, it was observed that at 500 kHz, the output
of the AD823 cannot go below ~350 mV (operating with
negative supply at ground) without seriously degrading the
second harmonic distortion. Another test was performed with a
200 Ω pull-down resistor to ground that allowed the output to
go as low as 200 mV without seriously affecting the second
harmonic distortion. There was, however, a slight increase in
the third harmonic term with the resistor added, but it was still
less than the second harmonic.
Figure 41 is an FFT plot of the results of driving the AD1672
with the AD823 with no pull-down resistor. The input
amplitude was 2.15 V p-p and the lower voltage excursion was
350 mV. The input frequency was 490 kHz, which was chosen
to spread the location of the harmonics.
The distortion analysis is important for systems requiring good
frequency domain performance. Other systems may require
good time domain performance. The noise and settling time
performance of the AD823 provides the necessary information
for its applicability for these systems.
569
3
1
V
IN
= 2.15V p-p
G = +1
FI = 490kHz
15dB/DI
V
7
8
00901-041
2
4
Figure 41. FFT of AD1672 Output Driven by AD823
3 V, Single-Supply Stereo Headphone Driver
The AD823 exhibits good current drive and total harmonic
distortion plus noise (THD+N) performance, even at 3 V
single supplies. At 20 kHz, THD+N equals −62 dB (0.079%) for
a 300 mV p-p output signal. This is comparable to other single-
supply op amps that consume more power and cannot run on
3 V power supplies.
In Figure 42, each channel’s input signal is coupled via a 1 µF
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway
between the power supplies (+1.5 V). The gain is 1.5. Each half
of the AD823 can then be used to drive a headphone channel. A
5 Hz high-pass filter is realized by the 500 µF capacitors and the
headphones that can be modeled as 32 Ω load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz to 20 kHz) are delivered to the headphones.
MYLAR
1µF
1/2
AD823
L
R
HEADPHONES
32Ω IMPEDANCE
4.99kΩ
MYLAR
1µF
4.99kΩ
10kΩ
10kΩ
47.5kΩ
95.3kΩ
47.5kΩ
500µF
500µF
3
V
95.3kΩ
0.1µF
+
0.1µF
CHANNEL 1
CHANNEL 2
95.3kΩ
+
+
7
4
5
6
1/2
AD823
38
2
1
1
0
0901-042
Figure 42. 3 V Single-Supply Stereo Headphone Driver
AD823
Rev. D | Page 17 of 20
Second-Order Low-Pass Filter Single-Supply Half-Wave and Full-Wave Rectifiers
An AD823 configured as a unity-gain follower and operated
with a single supply can be used as a simple half-wave rectifier.
The AD823 inputs maintain picoamp level input currents even
when driven well below the minus supply. The rectifier puts
that behavior to good use, maintaining an input impedance of
over 1011 Ω for input voltages from within 1 V of the positive
supply to 20 V below the negative supply.
Figure 43 depicts the AD823 configured as a second-order
Butterworth low-pass filter. With the values as shown, the
corner frequency equals 200 kHz. Component selection is
shown in the following equations:
R1 = R2 = User Selected (Typical Values: 10 kΩ to 100 kΩ)
()
R1f
.
faradsC1
cutoff ×
=2π
4141
The full-wave and half-wave rectifier shown in Figure 45
operates as follows: when VIN is above ground, R1 is boot-
strapped through the unity-gain follower A1 and the loop of
Amplifier A2. This forces the inputs of A2 to be equal, thus no
current flows through R1 or R2, and the circuit output tracks
the input. When VIN is below ground, the output of A1 is forced
to ground. The noninverting input of Amplifier A2 sees the
ground level output of A1; therefore, A2 operates as a unity-
gain inverter. The output at Node C is then a full-wave rectified
version of the input. Node B is a buffered half-wave rectified
version of the input. Input voltage supply to ±18 V can be
rectified, depending on the voltage supply used.
R1f
C2
cutoff ×
=2π
707.0
1/2
AD823
C3
0.1µF
+5V
C4
0.1µF
VOUT
V
IN
C1
28pF
–5V
C2
56pF
R1
20kΩR2
20kΩ
50pF
00901-043
3
2
1
8
4
0.01µF
V
IN
+VS
1/2
AD823
HALF-WAVE
RECTIFIED OUTPUT
FULL-WAVE
RECTIFIED OUTPUT
A1
R2
100kΩ
R1
100kΩ
6
5
7
1/2
AD823
A2
A
B
C
A2
00901-044
Figure 43. Second-Order Low-Pass Filter
A plot of the filter is shown in Figure 44; better than 50 dB of
high frequency rejection is provided.
FREQUENCY (Hz)
–40
HIGH FREQUENCY REJECTION (dB)
1k
–50
–30
–60
0
–20
10k 100k 1M 10M 100M
–10
V
DB
– V
OUT
00901-044
Figure 45. Full-Wave and Half-Wave Rectifier
100
A
B
C
2V 200µs
2V
10
0%
00901-046
90
Figure 44. Frequency Response of Filter
Figure 46. Single-Supply Half-Wave and Full-Wave Rectifier
AD823
Rev. D | Page 18 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
Figure 47. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 48. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
AD823
Rev. D | Page 19 of 20
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD823AN −40°C to +85°C 8-Lead PDIP N-8
AD823ANZ −40°C to +85°C 8-Lead PDIP N-8
AD823AR −40°C to +85°C 8-Lead SOIC_N R-8
AD823AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13” Tape and Reel R-8
AD823AR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7” Tape and Reel R-8
AD823ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD823ARZ-RL −40°C to +85°C 8-Lead SOIC_N, 13” Tape and Reel R-8
AD823ARZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7” Tape and Reel R-8
AD823AR-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD823
Rev. D | Page 20 of 20
NOTES
©1995–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00901-0-6/10(D)