8-bit AVR Microcontrollers ATmega48PA/88PA/168PA DATASHEET COMPLETE Introduction (R) (R) The Atmel picoPower ATmega48PA/88PA/168PA is a low-power CMOS 8bit microcontroller based on the AVR(R) enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega48PA/ 88PA/168PA achieves throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power consumption versus processing speed. Feature High Performance, Low Power Atmel(R)AVR(R) 8-Bit Microcontroller Family * Advanced RISC Architecture - 131 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 20 MIPS Throughput at 20MHz - On-chip 2-cycle Multiplier * High Endurance Non-volatile Memory Segments - 4K/8K/16KBytes of In-System Self-Programmable Flash program Memory - 256/512/512Bytes EEPROM - 512/1K/1KBytes Internal SRAM - Write/Erase Cycles: 10,000 Flash/100,000 EEPROM - Data Retention: 20 years at 85C/100 years at 25C(1) - Optional Boot Code Section with Independent Lock Bits * In-System Programming by On-chip Boot Program * True Read-While-Write Operation - Programming Lock for Software Security * Atmel(R) QTouch(R) Library Support - Capacitive Touch Buttons, Sliders and Wheels - QTouch and QMatrix(R) Acquisition - Up to 64 sense channels Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 * * * * * * * Peripheral Features - Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Six PWM Channels - 8-channel 10-bit ADC in TQFP and QFN/MLF package * Temperature Measurement - 6-channel 10-bit ADC in PDIP Package * Temperature Measurement - Two Master/Slave SPI Serial Interface - One Programmable Serial USART - One Byte-oriented 2-wire Serial Interface (Philips I2C compatible) - Programmable Watchdog Timer with Separate On-chip Oscillator - One On-chip Analog Comparator - Interrupt and Wake-up on Pin Change Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages - 23 Programmable I/O Lines - 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF Operating Voltage: - 1.8 - 5.5V Temperature Range: - -40C to 105C Speed Grade: - 0 - 4MHz @ 1.8 - 5.5V - 0 - 10MHz @ 2.7 - 5.5V - 0 - 20MHz @ 4.5 - 5.5V Power Consumption at 1MHz, 1.8V, 25C - Active Mode: 0.2mA - Power-down Mode: 0.1A - Power-save Mode: 0.75A (Including 32kHz RTC) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 2 Table of Contents Introduction......................................................................................................................1 Feature............................................................................................................................ 1 1. Description.................................................................................................................9 2. Configuration Summary........................................................................................... 10 3. Ordering Information ............................................................................................... 11 3.1. 3.2. 3.3. ATmega48PA..............................................................................................................................11 ATmega88PA .............................................................................................................................12 ATmega168PA............................................................................................................................13 4. Block Diagram......................................................................................................... 14 5. Pin Configurations................................................................................................... 15 5.1. 5.2. Pin-out........................................................................................................................................ 15 Pin Descriptions..........................................................................................................................19 6. I/O Multiplexing........................................................................................................ 21 7. Resources................................................................................................................23 8. Data Retention.........................................................................................................24 9. About Code Examples............................................................................................. 25 10. Capacitive Touch Sensing....................................................................................... 26 10.1. QTouch Library........................................................................................................................... 26 11. AVR CPU Core........................................................................................................ 27 11.1. 11.2. 11.3. 11.4. 11.5. Overview.....................................................................................................................................27 ALU - Arithmetic Logic Unit........................................................................................................28 Status Register...........................................................................................................................28 General Purpose Register File................................................................................................... 30 Stack Pointer.............................................................................................................................. 31 11.6. Instruction Execution Timing...................................................................................................... 33 11.7. Reset and Interrupt Handling..................................................................................................... 34 12. AVR Memories.........................................................................................................36 12.1. 12.2. 12.3. 12.4. 12.5. 12.6. Overview.....................................................................................................................................36 In-System Reprogrammable Flash Program Memory................................................................ 36 SRAM Data Memory...................................................................................................................37 EEPROM Data Memory............................................................................................................. 39 I/O Memory.................................................................................................................................40 Register Description................................................................................................................... 41 13. System Clock and Clock Options............................................................................ 51 13.1. Clock Systems and Their Distribution.........................................................................................51 13.2. Clock Sources............................................................................................................................ 52 13.3. Low Power Crystal Oscillator......................................................................................................54 13.4. Full Swing Crystal Oscillator.......................................................................................................55 13.5. Low Frequency Crystal Oscillator...............................................................................................56 13.6. Calibrated Internal RC Oscillator................................................................................................57 13.7. 128kHz Internal Oscillator.......................................................................................................... 58 13.8. External Clock............................................................................................................................ 59 13.9. Timer/Counter Oscillator.............................................................................................................60 13.10. Clock Output Buffer....................................................................................................................60 13.11. System Clock Prescaler............................................................................................................. 60 13.12. Register Description...................................................................................................................61 14. PM - Power Management and Sleep Modes...........................................................65 14.1. Overview.....................................................................................................................................65 14.2. Sleep Modes...............................................................................................................................65 14.3. BOD Disable...............................................................................................................................66 14.4. Idle Mode....................................................................................................................................66 14.5. ADC Noise Reduction Mode.......................................................................................................66 14.6. Power-Down Mode.....................................................................................................................67 14.7. Power-save Mode.......................................................................................................................67 14.8. Standby Mode............................................................................................................................ 68 14.9. Extended Standby Mode............................................................................................................ 68 14.10. Power Reduction Register......................................................................................................... 68 14.11. Minimizing Power Consumption................................................................................................. 68 14.12. Register Description...................................................................................................................69 15. SCRST - System Control and Reset....................................................................... 74 15.1. 15.2. 15.3. 15.4. Resetting the AVR...................................................................................................................... 74 Reset Sources............................................................................................................................74 Power-on Reset..........................................................................................................................75 External Reset............................................................................................................................76 15.5. 15.6. 15.7. 15.8. 15.9. Brown-out Detection...................................................................................................................76 Watchdog System Reset............................................................................................................ 77 Internal Voltage Reference.........................................................................................................77 Watchdog Timer......................................................................................................................... 78 Register Description................................................................................................................... 80 16. Interrupts................................................................................................................. 84 16.1. 16.2. 16.3. 16.4. Interrupt Vectors in ATmega48PA.............................................................................................. 84 Interrupt Vectors in ATmega88PA.............................................................................................. 85 Interrupt Vectors in ATmega168PA............................................................................................ 88 Register Description................................................................................................................... 91 17. EXINT - External Interrupts..................................................................................... 94 17.1. Pin Change Interrupt Timing.......................................................................................................94 17.2. Register Description................................................................................................................... 95 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 4 18. I/O-Ports................................................................................................................ 104 18.1. 18.2. 18.3. 18.4. Overview...................................................................................................................................104 Ports as General Digital I/O......................................................................................................105 Alternate Port Functions...........................................................................................................108 Register Description................................................................................................................. 120 19. TC0 - 8-bit Timer/Counter0 with PWM...................................................................132 19.1. 19.2. 19.3. 19.4. 19.5. 19.6. 19.7. 19.8. 19.9. Features................................................................................................................................... 132 Overview...................................................................................................................................132 Timer/Counter Clock Sources.................................................................................................. 134 Counter Unit............................................................................................................................. 134 Output Compare Unit................................................................................................................135 Compare Match Output Unit.....................................................................................................137 Modes of Operation..................................................................................................................138 Timer/Counter Timing Diagrams...............................................................................................142 Register Description................................................................................................................. 144 20. TC1 - 16-bit Timer/Counter1 with PWM.................................................................156 20.1. Overview...................................................................................................................................156 20.2. Features................................................................................................................................... 156 20.3. Block Diagram.......................................................................................................................... 156 20.4. Definitions.................................................................................................................................157 20.5. Registers.................................................................................................................................. 158 20.6. Accessing 16-bit Registers.......................................................................................................158 20.7. Timer/Counter Clock Sources.................................................................................................. 161 20.8. Counter Unit............................................................................................................................. 161 20.9. Input Capture Unit.................................................................................................................... 162 20.10. Output Compare Units............................................................................................................. 164 20.11. Compare Match Output Unit.....................................................................................................166 20.12. Modes of Operation..................................................................................................................167 20.13. Timer/Counter Timing Diagrams.............................................................................................. 175 20.14. Register Description.................................................................................................................176 21. Timer/Counter 0, 1 Prescalers...............................................................................193 21.1. 21.2. 21.3. 21.4. Internal Clock Source............................................................................................................... 193 Prescaler Reset........................................................................................................................193 External Clock Source..............................................................................................................193 Register Description................................................................................................................. 194 22. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation................... 196 22.1. 22.2. 22.3. 22.4. 22.5. 22.6. 22.7. 22.8. Features................................................................................................................................... 196 Overview...................................................................................................................................196 Timer/Counter Clock Sources.................................................................................................. 198 Counter Unit............................................................................................................................. 198 Output Compare Unit................................................................................................................199 Compare Match Output Unit.....................................................................................................201 Modes of Operation..................................................................................................................202 Timer/Counter Timing Diagrams...............................................................................................206 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 5 22.9. Asynchronous Operation of Timer/Counter2............................................................................ 207 22.10. Timer/Counter Prescaler.......................................................................................................... 209 22.11. Register Description................................................................................................................. 209 23. SPI - Serial Peripheral Interface........................................................................... 222 23.1. 23.2. 23.3. 23.4. 23.5. Features................................................................................................................................... 222 Overview...................................................................................................................................222 SS Pin Functionality................................................................................................................. 226 Data Modes.............................................................................................................................. 226 Register Description................................................................................................................. 227 24. USART - Universal Synchronous Asynchronous Receiver Transceiver................232 24.1. Features................................................................................................................................... 232 24.2. Overview...................................................................................................................................232 24.3. Block Diagram.......................................................................................................................... 232 24.4. Clock Generation......................................................................................................................233 24.5. Frame Formats.........................................................................................................................236 24.6. USART Initialization..................................................................................................................237 24.7. Data Transmission - The USART Transmitter......................................................................... 238 24.8. Data Reception - The USART Receiver.................................................................................. 240 24.9. Asynchronous Data Reception.................................................................................................244 24.10. Multi-Processor Communication Mode.................................................................................... 246 24.11. Examples of Baud Rate Setting............................................................................................... 247 24.12. Register Description.................................................................................................................250 25. USARTSPI - USART in SPI Mode.........................................................................261 25.1. 25.2. 25.3. 25.4. 25.5. 25.6. 25.7. 25.8. Features................................................................................................................................... 261 Overview...................................................................................................................................261 Clock Generation......................................................................................................................261 SPI Data Modes and Timing.....................................................................................................262 Frame Formats.........................................................................................................................262 Data Transfer............................................................................................................................264 AVR USART MSPIM vs. AVR SPI............................................................................................265 Register Description................................................................................................................. 266 26. TWI - 2-wire Serial Interface..................................................................................267 26.1. 26.2. 26.3. 26.4. 26.5. 26.6. 26.7. 26.8. 26.9. Features................................................................................................................................... 267 Two-Wire Serial Interface Bus Definition..................................................................................267 Data Transfer and Frame Format.............................................................................................268 Multi-master Bus Systems, Arbitration and Synchronization....................................................271 Overview of the TWI Module.................................................................................................... 273 Using the TWI...........................................................................................................................275 Transmission Modes................................................................................................................ 278 Multi-master Systems and Arbitration.......................................................................................296 Register Description................................................................................................................. 298 27. AC - Analog Comparator....................................................................................... 306 27.1. Overview...................................................................................................................................306 27.2. Analog Comparator Multiplexed Input...................................................................................... 306 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 6 27.3. Register Description................................................................................................................. 307 28. ADC - Analog to Digital Converter.........................................................................312 28.1. 28.2. 28.3. 28.4. 28.5. 28.6. 28.7. 28.8. 28.9. Features................................................................................................................................... 312 Overview...................................................................................................................................312 Starting a Conversion...............................................................................................................314 Prescaling and Conversion Timing...........................................................................................315 Changing Channel or Reference Selection.............................................................................. 317 ADC Noise Canceler................................................................................................................ 319 ADC Conversion Result............................................................................................................322 Temperature Measurement...................................................................................................... 323 Register Description................................................................................................................. 323 29. DBG - debugWIRE On-chip Debug System.......................................................... 334 29.1. 29.2. 29.3. 29.4. 29.5. 29.6. Features................................................................................................................................... 334 Overview...................................................................................................................................334 Physical Interface..................................................................................................................... 334 Software Break Points..............................................................................................................335 Limitations of debugWIRE........................................................................................................335 Register Description................................................................................................................. 335 30. Self-Programming the Flash..................................................................................337 30.1. Overview...................................................................................................................................337 30.2. Addressing the Flash During Self-Programming...................................................................... 338 30.3. Register Description................................................................................................................. 343 31. BTLDR - Boot Loader Support - Read-While-Write Self-Programming................ 346 31.1. 31.2. 31.3. 31.4. 31.5. 31.6. 31.7. 31.8. 31.9. Features................................................................................................................................... 346 Overview...................................................................................................................................346 Application and Boot Loader Flash Sections............................................................................346 Read-While-Write and No Read-While-Write Flash Sections...................................................347 Boot Loader Lock Bits.............................................................................................................. 349 Entering the Boot Loader Program...........................................................................................350 Addressing the Flash During Self-Programming...................................................................... 351 Self-Programming the Flash.....................................................................................................352 Register Description................................................................................................................. 361 32. MEMPROG- Memory Programming......................................................................364 32.1. 32.2. 32.3. 32.4. 32.5. 32.6. 32.7. 32.8. Program And Data Memory Lock Bits...................................................................................... 364 Fuse Bits...................................................................................................................................365 Signature Bytes........................................................................................................................ 368 Calibration Byte........................................................................................................................ 368 Page Size................................................................................................................................. 368 Parallel Programming Parameters, Pin Mapping, and Commands.......................................... 368 Parallel Programming...............................................................................................................370 Serial Downloading...................................................................................................................377 33. Electrical Characteristics....................................................................................... 383 33.1. Absolute Maximum Ratings......................................................................................................383 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 7 33.2. Common DC Characteristics....................................................................................................383 33.3. 33.4. 33.5. 33.6. 33.7. 33.8. 33.9. Speed Grades.......................................................................................................................... 387 Clock Characteristics................................................................................................................388 System and Reset Characteristics........................................................................................... 389 SPI Timing Characteristics....................................................................................................... 390 Two-wire Serial Interface Characteristics................................................................................. 391 ADC Characteristics................................................................................................................. 393 Parallel Programming Characteristics...................................................................................... 394 34. Typical Characteristics (TA = -40C to 105C)....................................................... 397 34.1. ATmega48PA Typical Characteristics.......................................................................................397 34.2. ATmega88PA: Typical Characteristics......................................................................................422 34.3. ATmega168PA Typical Characteristics.....................................................................................447 35. Register Summary.................................................................................................469 35.1. Note..........................................................................................................................................471 36. Instruction Set Summary....................................................................................... 473 37. Packaging Information...........................................................................................477 37.1. 37.2. 37.3. 37.4. 37.5. 32-pin 32A................................................................................................................................ 477 32-pin 32M1-A..........................................................................................................................478 32-pin 32CC1........................................................................................................................... 479 28-pin 28M1..............................................................................................................................480 28-pin 28P3.............................................................................................................................. 481 38. Errata.....................................................................................................................482 38.1. Errata ATmega48PA.................................................................................................................482 38.2. Errata ATmega88PA.................................................................................................................482 38.3. Errata ATmega168PA...............................................................................................................483 39. Datasheet Revision History................................................................................... 484 39.1. Rev. B - 11/2016...................................................................................................................... 484 39.2. Rev. A - 06/2016...................................................................................................................... 484 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 8 1. Description The Atmel AVR(R) core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega48PA/88PA/168PA provides the following features: 4K/8K/16Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 256/512/512bytes EEPROM, 512/1K/1Kbytes SRAM, 23 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 1 serial programmable USARTs , 1 byteoriented 2-wire Serial Interface (I2C), a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages) , a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main oscillator and the asynchronous timer continue to run. Atmel offers the QTouch(R) library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression(R) (AKSTM) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega48PA/88PA/168PA is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega48PA/88PA/168PA is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 9 2. Configuration Summary Features ATmega48PA/88PA/168PA Pin Count 28/32 Flash (Bytes) 4K/8K/16K SRAM (Bytes) 512/1K/1K EEPROM (Bytes) 256/512/512 Interrupt Vector Size (instruction word/vector) 1/1/2 General Purpose I/O Lines 23 SPI 2 TWI (I2C) 1 USART 1 ADC 10-bit 15kSPS ADC Channels 8 8-bit Timer/Counters 2 16-bit Timer/Counters 1 ATmega88PA and ATmega168PA support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega48PA, there is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the entire Flash. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 10 3. Ordering Information 3.1. ATmega48PA Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.5 ATmega48PA-AU ATmega48PA-AUR(4) ATmega48PA-CCU ATmega48PA-CCUR(4) ATmega48PA-MMH(5) ATmega48PA-MMHR(4)(5) ATmega48PA-MU ATmega48PA-MUR(4) ATmega48PA-PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1-A 32M1-A 28P3 Industrial (-40C to 85C) ATmega48PA-AU ATmega48PA-AUR(4) ATmega48PA-CCU ATmega48PA-CCUR(4) ATmega48PA-MMH(5) ATmega48PA-MMHR(4)(5) ATmega48PA-MU ATmega48PA-MUR(4) ATmega48PA-PU 32A 32A 28M1 28M1 32M1-A 32M1-A 28P3 Industrial (-40C to 105C) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Please refer to Speed Grades for Speed vs. VCC 4. Tape & Reel. 5. NiPdAu Lead Finish. Package Type 28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/ MLF) 28P3 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/ MLF) 32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP) 32CC1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 11 3.2. ATmega88PA Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.5 ATmega88PA-AU ATmega88PA-AUR(4) ATmega88PA-CCU ATmega88PA-CCUR(4) ATmega88PA-MMH(5) ATmega88PA-MMHR(4)(5) ATmega88PA-MU ATmega88PA-MUR(4) ATmega88PA-PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1-A 32M1-A 28P3 Industrial (-40C to 85C) ATmega88PA-AN ATmega88PA-ANR(4) ATmega88PA-MMN(5) ATmega88PA-MMNR(4)(5) ATmega88PA-MN ATmega88PA-MNR(4) ATmega88PA-PN 32A 32A 28M1 28M1 32M1-A 32M1-A 28P3 Industrial (-40C to 105C) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Please refer to Speed Grades for Speed vs. VCC 4. Tape & Reel. 5. NiPdAu Lead Finish. Package Type 28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/ MLF) 28P3 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/ MLF) 32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP) 32CC1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 12 3.3. ATmega168PA Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range 20 1.8 - 5.5 ATmega168PA-AU ATmega168PA-AUR(5) ATmega168PA-CCU ATmega168PA-CCUR(5) ATmega168PA-MMH(4) ATmega168PA-MMHR(4)(5) ATmega168PA-MU ATmega168PA-MUR(5) ATmega168PA-PU 32A 32A 32CC1 32CC1 28M1 28M1 32M1-A 32M1-A 28P3 Industrial (-40C to 85C) ATmega168PA-AN ATmega168PA-ANR(5) ATmega168PA-MN ATmega168PA-MNR(5) ATmega168PA-PN 32A 32A 32M1-A 32M1-A 28P3 Industrial (-40C to 105C) Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Please refer to Speed Grades for Speed vs. VCC 4. Tape & Reel. 5. NiPdAu Lead Finish. Package Type 28M1 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/ MLF) 28P3 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/ MLF) 32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP) 32CC1 32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 13 4. Block Diagram Figure 4-1. Block Diagram SRAM debugWire CPU OCD Clock generation XTAL1 / TOSC1 XTAL2 / TOSC2 32.768kHz XOSC 8MHz Calib RC External clock 16MHz LP XOSC VCC 128kHz int osc Power Supervision POR/BOD & RESET RESET GND ADC6,ADC7,PC[5:0] AREF ADC[7:0] AREF PD[7:0], PC[6:0], PB[7:0] PD3, PD2 PCINT[23:0] INT[1:0] PB1, PB2 PD5 PB0 OC1A/B T1 ICP1 PB3 PD3 OC2A OC2B NVM programming Power management and clock control Watchdog Timer ADC EXTINT FLASH D A T A B U S EEPROM EEPROMIF I/O PORTS I N / O U T PB[7:0] PC[6:0] PD[7:0] GPIOR[2:0] TC 0 D A T A B U S (8-bit) SPI 0 AC Internal Reference USART 0 RxD0 TxD0 XCK0 PD0 PD1 PD4 TWI 0 SDA0 SCL0 PC4 PC5 T0 OC0A OC0B PD4 PD6 PD5 MISO0 MOSI0 SCK0 SS0 PB4 PB3 PB5 PB2 AIN0 AIN1 PD6 PD7 ADCMUX ADC6, ADC7 PC[5:0] TC 1 (16-bit) TC 2 (8-bit async) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 14 5. Pin Configurations 5.1. Pin-out Figure 5-1. 28-pin PDIP (PCINT14/RESET) PC6 1 28 PC5 (ADC5/SCL/PCINT13) (PCINT16/RXD) PD0 2 27 PC4 (ADC4/SDA/PCINT12) (PCINT17/TXD) PD1 3 26 PC3 (ADC3/PCINT11) (PCINT18/INT0) PD2 4 25 PC2 (ADC2/PCINT10) (PCINT19/OC2B/INT1) PD3 5 24 PC1 (ADC1/PCINT9) (PCINT20/XCK/T0) PD4 6 23 PC0 (ADC0/PCINT8) VCC 7 22 GND GND 8 21 AREF (PCINT6/XTAL1/TOSC1) PB6 9 20 AVCC (PCINT7/XTAL2/TOSC2) PB7 10 19 PB5 (SCK/PCINT5) (PCINT21/OC0B/T1) PD5 11 18 PB4 (MISO/PCINT4) (PCINT22/OC0A/AIN0) PD6 12 17 PB3 (MOSI/OC2A/PCINT3) (PCINT23/AIN1) PD7 13 16 PB2 (SS/OC1B/PCINT2) (PCINT0/CLKO/ICP1) PB0 14 15 PB1 (OC1A/PCINT1) Power Ground Programming/debug Digital Analog Crystal/Osc Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 15 PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) 28 27 26 25 24 23 22 Figure 5-2. 28-pin MLF Top View Power Ground Programming/debug Digital Analog Crystal/CLK 4 18 GND (PCINT6/XTAL1/TOSC1) PB6 5 17 AREF (PCINT7/XTAL2/TOSC2) PB7 6 16 AVCC (PCINT21/OC0B/T1) PD5 7 15 PB5 (SCK/PCINT5) (PCINT4/MISO) PB4 Bottom pad should be soldered to ground 14 GND (PCINT3/OC2A/MOSI) PB3 PC0 (ADC0/PCINT8) 13 19 (PCINT2/SS/OC1B) PB2 3 12 VCC (PCINT1/OC1A) PB1 PC1 (ADC1/PCINT9) 11 20 10 2 (PCINT0/CLKO/ICP1) PB0 (PCINT20/XCK/T0) PD4 9 PC2 (ADC2/PCINT10) (PCINT23/AIN1) PD7 21 8 1 (PCINT22/OC0A/AIN0) PD6 (PCINT19/OC2B/INT1) PD3 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 16 PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) 29 28 27 Digital Analog Crystal/CLK PC2 (ADC2/PCINT10) PD0 (RXD/PCINT16) 30 Programming/debug 25 PD1 (TXD/PCINT17) 31 Ground 26 PD2 (INT0/PCINT18) 32 Power PC3 (ADC3/PCINT11) Figure 5-3. 32-pin TQFP Top View GND 5 20 AREF VCC 6 19 ADC6 (PCINT6/XTAL1/TOSC1) PB6 7 18 AVCC (PCINT7/XTAL2/TOSC2) PB7 8 17 PB5 (SCK/PCINT5) 16 GND (PCINT4/MISO) PB4 21 15 4 (PCINT3/OC2A/MOSI) PB3 VCC 14 ADC7 (PCINT2/SS/OC1B) PB2 22 13 3 (PCINT1/OC1A) PB1 GND 12 PC0 (ADC0/PCINT8) (PCINT0/CLKO/ICP1) PB0 23 11 2 (PCINT23/AIN1) PD7 (PCINT20/XCK/T0) PD4 10 PC1 (ADC1/PCINT9) (PCINT22/OC0A/AIN0) PD6 24 9 1 (PCINT21/OC0B/T1) PD5 (PCINT19/OC2B/INT1) PD3 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 17 PD2 (INT0/PCINT18) PD1 (TXD/PCINT17) PD0 (RXD/PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) 32 31 30 29 28 27 26 25 Figure 5-4. 32-pin MLF Top View Power Ground Programming/debug Digital Analog Crystal/CLK GND 5 20 AREF VCC 6 19 ADC6 (PCINT6/XTAL1/TOSC1) PB6 7 18 AVCC (PCINT7/XTAL2/TOSC2) PB7 8 17 PB5 (SCK/PCINT5) 16 GND (PCINT4/MISO) PB4 21 15 4 (PCINT3/OC2A/MOSI) PB3 VCC 14 ADC7 (PCINT2/SS/OC1B) PB2 22 13 3 (PCINT1/OC1A) PB1 GND 12 PC0 (ADC0/PCINT8) (PCINT0/CLKO/ICP1) PB0 23 11 2 (PCINT23/AIN1) PD7 (PCINT20/XCK/T0) PD4 10 PC1 (ADC1/PCINT9) (PCINT22/OC0A/AIN0) PD6 24 9 1 (PCINT21/OC0B/T1) PD5 (PCINT19/OC2B/INT1) PD3 Bottom pad should be soldered to ground Table 5-1. 32UFBGA 1 2 3 4 5 6 A PD2 PD1 PC6 PC4 PC2 PC1 B PD3 PD4 PD0 PC5 PC3 PC0 C GND GND - - ADC7 GND D VCC VCC - - AREF ADC6 E PB6 PD6 PB0 PB2 AVCC PB5 F PB7 PD5 PD7 PB1 PB3 PB4 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 18 5.2. Pin Descriptions 5.2.1. VCC Digital supply voltage. 5.2.2. GND Ground. 5.2.3. Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB[7:6] is used as TOSC[2:1] input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. 5.2.4. Port C (PC[5:0]) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC[5:0] output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 5.2.5. PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated in the Alternate Functions of Port C section. 5.2.6. Port D (PD[7:0]) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. 5.2.7. AVCC AVCC is the supply voltage pin for the A/D Converter, PC[3:0], and PE[3:2]. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC[6:4] use digital supply voltage, VCC. 5.2.8. AREF AREF is the analog reference pin for the A/D Converter. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 19 5.2.9. ADC[7:6] (TQFP and VFQFN Package Only) In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 20 6. I/O Multiplexing Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins. Table 6-1. PORT Function Multiplexing (32-pin 32UFBGA) Pin# (32-pin MLF/ TQFP) Pin# (28-pin MLF) Pin# (28-pin PIPD) Pin# PAD EXTINT PCINT B1 1 1 5 PD[3] INT1 B2 2 2 6 PD[4] D1 4 3 7 VCC C1 3 4 8 GND D2 6 - - VCC C2 5 - - GND E1 7 5 9 PB[6] PCINT6 XTAL1/ TOSC1 F1 8 6 10 PB[7] PCINT7 XTAL2/ TOSC2 F2 9 7 11 PD[5] PCINT21 OC0B E2 10 8 12 PD[6] PCINT22 AIN0 OC0A F3 11 9 13 PD[7] PCINT23 AIN1 E3 12 10 14 PB[0] PCINT0 F4 13 11 15 PB[1] PCINT1 OC1A E4 14 12 16 PB[2] PCINT2 OC1B SS0 F5 15 13 17 PB[3] PCINT3 OC2A MOSI0 F6 16 14 18 PB[4] PCINT4 MISO0 E6 17 15 19 PB[5] PCINT5 SCK0 E5 18 16 20 AVCC D6 19 - - ADC6 D5 20 17 21 AREF C6 21 18 22 GND C5 22 - - ADC7 B6 23 19 13 PC[0] PCINT8 ADC0 A6 24 20 24 PC[1] PCINT9 ADC1 A2 25 21 25 PC[2] PCINT10 ADC2 B5 26 22 26 PC[3] PCINT11 ADC3 A4 27 23 27 PC[4] PCINT12 ADC4 SDA0 B4 28 24 28 PC[5] PCINT13 ADC5 SCL0 ADC/A C OSC T/C #0 T/C USART #1 0 PCINT19 OC2B PCINT20 T0 CLKO I2C 0 SPI 0 XCK0 T1 ICP1 ADC6 ADC7 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 21 (32-pin 32UFBGA) Pin# (32-pin MLF/ TQFP) Pin# (28-pin MLF) Pin# (28-pin PIPD) Pin# PAD EXTINT PCINT A3 29 25 1 PC[6]/ RESET PCINT14 B3 30 26 2 PD[0] PCINT16 RXD0 A2 31 27 3 PD[1] PCINT17 TXD0 A1 32 28 4 PD[2] INT0 ADC/A C OSC T/C #0 T/C USART #1 0 I2C 0 SPI 0 PCINT18 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 22 7. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 23 8. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 24 9. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 25 10. 10.1. Capacitive Touch Sensing QTouch Library (R) (R) The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on (R) most Atmel AVR microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel (R) QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API's to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: http:// www.atmel.com/technologies/touch/. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 26 11. AVR CPU Core 11.1. Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 11-1. Block Diagram of the AVR Architecture Register file R31 (ZH) R29 (YH) R27 (XH) R25 R23 R21 R19 R17 R15 R13 R11 R9 R7 R5 R3 R1 R30 (ZL) R28 (YL) R26 (XL) R24 R22 R20 R18 R16 R14 R12 R10 R8 R6 R4 R2 R0 Program counter Flash program memory Instruction register Instruction decode Data memory Stack pointer Status register ALU In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 27 The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, this device has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 11.2. ALU - Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See Instruction Set Summary section for a detailed description. Related Links Instruction Set Summary on page 473 11.3. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. The Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 28 11.3.1. Status Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. Name: SREG Offset: 0x5F Reset: 0x00 Property: When addressing as I/O Register: address offset is 0x3F Bit Access Reset 7 6 5 4 3 2 1 0 I T H S V N Z C R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The Ibit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. Bit 6 - T: Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Flag is useful in BCD arithmetic. See the Instruction Set Description for detailed information. Bit 4 - S: Sign Flag, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the Instruction Set Description for detailed information. Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetic. See the Instruction Set Description for detailed information. Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 29 Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. 11.4. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * * * * One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Figure 11-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 ... R13 0x0D Ge ne ra l R14 0x0E P urpos e R15 0x0F Working R16 0x10 Re gis te rs R17 0x11 ... R26 0x1A X-re gis te r Low Byte R27 0x1B X-re gis te r High Byte R28 0x1C Y-re gis te r Low Byte R29 0x1D Y-re gis te r High Byte R30 0x1E Z-re gis te r Low Byte R31 0x1F Z-re gis te r High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in the figure, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file. 11.4.1. The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in the figure. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 30 Figure 11-3. The X-, Y-, and Z-registers 15 X-register XH 7 0 15 Y-register 7 R26 YH YL 0 7 R28 ZH ZL 0 7 R31 0 0 R29 7 0 0 R27 7 15 Z-register XL 0 0 R30 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). Related Links Instruction Set Summary on page 473 11.5. Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM. See the table for Stack Pointer details. Table 11-1. Stack Pointer Instructions Instruction Stack pointer Description PUSH Decremented by 1 Data is pushed onto the stack CALL Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt ICALL RCALL POP Incremented by 1 Data is popped from the stack RET Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt RETI The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 31 11.5.1. Stack Pointer Register High byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SPH Offset: 0x5E Reset: RAMEND Property: When addressing I/O Registers as data space the offset address is 0x3E Bit 7 6 5 4 3 2 1 0 (SP[10:8]) SPH Access Reset RW RW RW 0 0 0 Bits 2:0 - (SP[10:8]) SPH: Stack Pointer Register SPH and SPL are combined into SP. It means SPH[2:0] is SP[10:8]. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 32 11.5.2. Stack Pointer Register Low byte When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these offset addresses. Name: SPL Offset: 0x5D Reset: 0x11111111 Property: When addressing I/O Registers as data space the offset address is 0x3D Bit 7 6 5 4 3 2 1 0 (SP[7:0]) SPL Access Reset RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 1 Bits 7:0 - (SP[7:0]) SPL: Stack Pointer Register SPH and SPL are combined into SP. It means SPL[7:0] is SP[7:0]. 11.6. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. The Figure below shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 11-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch The following Figure shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 33 Figure 11-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 11.7. Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. They have determined priority levels: The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts: The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. The Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 34 The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< ... RESET INT0 INT1 PCINT0 PCINT1 PCINT2 WDT TIM2_COMPA TIM2_COMPB TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 xxx Comments ; Reset ; IRQ0 ; IRQ1 ; PCINT0 ; PCINT1 ; PCINT2 ; Watchdog Timeout ; Timer2 CompareA ; Timer2 CompareB ; Timer2 Overflow ; Timer1 Capture ; Timer1 CompareA ; Timer1 CompareB ; Timer1 Overflow ; Timer0 CompareA ; Timer0 CompareB ; Timer0 Overflow ; SPI Transfer Complete ; USART RX Complete ; USART UDR Empty ; USART TX Complete ; ADC Conversion Complete ; EEPROM Ready ; Analog Comparator ; 2-wire Serial ; SPM Ready ; Main program start ; Set Stack Pointer to top of RAM ; Enable interrupts ... Interrupt Vectors in ATmega88PA Table 16-2. Reset and Interrupt Vectors in ATmega88PA Vector No Program Address(2) Source Interrupts definition 1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset 2 0x0001 INT0 External Interrupt Request 0 3 0x0002 INT1 External Interrupt Request 0 4 0x0003 PCINT0 Pin Change Interrupt Request 0 5 0x0004 PCINT1 Pin Change Interrupt Request 1 6 0x0005 PCINT2 Pin Change Interrupt Request 2 7 0x0006 WDT Watchdog Time-out Interrupt 8 0x0007 TIMER2_COMPA Timer/Counter2 Compare Match A 9 0x0008 TIMER2_COMPB Timer/Coutner2 Compare Match B Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 85 Vector No Program Address(2) Source Interrupts definition 10 0x0009 TIMER2_OVF Timer/Counter2 Overflow 11 0x000A TIMER1_CAPT Timer/Counter1 Capture Event 12 0x000B TIMER1_COMPA Timer/Counter1 Compare Match A 13 0x000C TIMER1_COMPB Timer/Coutner1 Compare Match B 14 0x000D TIMER1_OVF 15 0x000E TIMER0_COMPA Timer/Counter0 Compare Match A 16 0x000F TIMER0_COMPB Timer/Coutner0 Compare Match B 17 0x0010 TIMER0_OVF Timer/Counter0 Overflow 18 0x0011 SPI STC SPI Serial Transfer Complete 19 0x0012 USART_RX USART Rx Complete 20 0x0013 USART_UDRE USART Data Register Empty 21 0x0014 USART_TX USART Tx Complete 22 0x0015 ADC ADC Conversion Complete 23 0x0016 EE READY EEPROM Ready 24 0x0017 ANALOG COMP Analog Comparator 25 0x0018 TWI 2-wire Serial Interface (I2C) 26 0x0019 SPM READY Store Program Memory Ready Timer/Counter1 Overflow Note: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see "Boot Loader Support - Read-While-Write Self- Programming" 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. The table below shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 16-3. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x0001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x0001 Note: 1. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address 0x0000 Labels Code jmp RESET Comments ; Reset Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 86 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000C 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 ; 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F ... RESET: ... jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp INT0 INT1 PCINT0 PCINT1 PCINT2 WDT TIM2_COMPA TIM2_COMPB TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ldi out ldi out sei ... r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 ; Main program start ; Set Stack Pointer to top of RAM xxx IRQ0 IRQ1 PCINT0 PCINT1 PCINT2 Watchdog Timeout Timer2 CompareA Timer2 CompareB Timer2 Overflow Timer1 Capture Timer1 CompareA Timer1 CompareB Timer1 Overflow Timer0 CompareA Timer0 CompareB Timer0 Overflow SPI Transfer Complete USART RX Complete USART UDR Empty USART TX Complete ADC Conversion Complete EEPROM Ready Analog Comparator 2-wire Serial SPM Ready ; Enable interrupts ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the MCUCR.IVSEL is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels 0x000 RESET: 0x001 0x002 0x0003 0x0004 0x0005 ; .org 0xC01 0x0C01 0x0C02 ... 0x0C19 Code ldi out ldi out sei jmp jmp ... jmp r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 xxx EXT_INT0 EXT_INT1 ... SPM_RDY Comments ; Main program start ; Set Stack Pointer to top of RAM ; Enable interrupts ; IRQ0 Handler ; IRQ1 Handler ; ; SPM Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels .org 0x0002 0x0002 0x0004 ... 0x0032 ; .org 0xC00 0x0C00 RESET: 0x0C01 0x0C02 0x0C03 0x0C04 0x0C05 Code Comments jmp jmp ... jmp EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 Handler ; IRQ1 Handler ; ; SPM Ready Handler ldi out ldi out sei r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 ; Main program start ; Set Stack Pointer to top of RAM xxx ; Enable interrupts Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 87 When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the MCUCR.IVSEL is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels ; .org 0x0C00 0x0C00 0x0C01 0x0C02 ... 0x0C19 ; 0x0C1A RESET: 0x0C1B 0x0C1C 0x0C1D 0x0C1E 0x0C1F 16.3. Code Comments jmp jmp jmp ... jmp RESET EXT_INT0 EXT_INT1 ... SPM_RDY ; Reset handler ; IRQ0 Handler ; IRQ1 Handler ; ; SPM Ready Handler ldi out ldi out sei r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 ; Main program start ; Set Stack Pointer to top of RAM xxx ; Enable interrupts Interrupt Vectors in ATmega168PA Table 16-4. Reset and Interrupt Vectors in ATmega168PA Vector No Program Address(2) Source Interrupts definition 1 0x0000(1) RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset 2 0x0002 INT0 External Interrupt Request 0 3 0x0004 INT1 External Interrupt Request 0 4 0x0006 PCINT0 Pin Change Interrupt Request 0 5 0x0008 PCINT1 Pin Change Interrupt Request 1 6 0x000A PCINT2 Pin Change Interrupt Request 2 7 0x000C WDT Watchdog Time-out Interrupt 8 0x000E TIMER2_COMPA Timer/Counter2 Compare Match A 9 0x0010 TIMER2_COMPB Timer/Coutner2 Compare Match B 10 0x0012 TIMER2_OVF Timer/Counter2 Overflow 11 0x0014 TIMER1_CAPT Timer/Counter1 Capture Event 12 0x0016 TIMER1_COMPA Timer/Counter1 Compare Match A 13 0x0018 TIMER1_COMPB Timer/Coutner1 Compare Match B 14 0x001A TIMER1_OVF 15 0x001C TIMER0_COMPA Timer/Counter0 Compare Match A 16 0x001E TIMER0_COMPB Timer/Coutner0 Compare Match B 17 0x0020 TIMER0_OVF Timer/Counter0 Overflow 18 0x0022 SPI STC SPI Serial Transfer Complete 19 0x0024 USART_RX USART Rx Complete 20 0x0026 USART_UDRE USART Data Register Empty 21 0x0028 USART_TX USART Tx Complete Timer/Counter1 Overflow Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 88 Vector No Program Address(2) Source Interrupts definition 22 0x002A ADC ADC Conversion Complete 23 0x002C EE READY EEPROM Ready 24 0x002E ANALOG COMP Analog Comparator 25 0x0030 TWI 2-wire Serial Interface (I2C) 26 0x0032 SPM READY Store Program Memory Ready Note: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see "Boot Loader Support - Read-While-Write Self- Programming" 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. The table below shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 16-5. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x002 1 1 0x000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x002 0 1 Boot Reset Address Boot Reset Address + 0x0002 Note: 1. For the BOOTRST Fuse "1" means unprogrammed while "0" means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 ; Labels Code jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET INT0 INT1 PCINT0 PCINT1 PCINT2 WDT TIM2_COMPA TIM2_COMPB TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART_RXC USART_UDRE USART_TXC ADC EE_RDY ANA_COMP TWI SPM_RDY Comments ; Reset ; IRQ0 ; IRQ1 ; PCINT0 ; PCINT1 ; PCINT2 ; Watchdog Timeout ; Timer2 CompareA ; Timer2 CompareB ; Timer2 Overflow ; Timer1 Capture ; Timer1 CompareA ; Timer1 CompareB ; Timer1 Overflow ; Timer0 CompareA ; Timer0 CompareB ; Timer0 Overflow ; SPI Transfer Complete ; USART RX Complete ; USART UDR Empty ; USART TX Complete ; ADC Conversion Complete ; EEPROM Ready ; Analog Comparator ; 2-wire Serial ; SPM Ready Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 89 0x0034 0x0035 0x0036 0x0037 0x0038 0x0039 ... RESET: ... ldi out ldi out sei ... r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 xxx ; Main program start ; Set Stack Pointer to top of RAM ; Enable interrupts ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2Kbytes and the MCUCR.IVSEL is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels 0x0000 RESET: 0x0001 0x0002 0x0003 0x0004 0x0005 ; .org 0x1C02 0x1C02 0x1C04 ... 0x1C32 Code ldi r16,high(RAMEND) out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei xxx Comments ; Main program start ; Set Stack Pointer to top of RAM jmp jmp ... jmp ; IRQ0 Handler ; IRQ1 Handler ; ; SPM Ready Handler EXT_INT0 EXT_INT1 ... SPM_RDY ; Enable interrupts When the BOOTRST Fuse is programmed and the Boot section size set to 2Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels .org 0x0002 0x0002 0x0004 ... 0x0032 ; .org 0x1C00 0x1C00 RESET: 0x1C01 0x1C02 0x1C03 0x1C04 0x1C05 Code Comments jmp jmp ... jmp EXT_INT0 EXT_INT1 ... SPM_RDY ; IRQ0 Handler ; IRQ1 Handler ; ; SPM Ready Handler ldi out ldi out sei r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 ; Main program start ; Set Stack Pointer to top of RAM xxx ; Enable interrupts When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the MCUCR.IVSEL is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels ; .org 0x1C00 0x1C00 0x1C02 0x1C04 ... 0x1C32 ; 0x1C34 RESET: 0x1C35 0x1C36 0x1C37 0x1C38 0x1C39 Code Comments jmp jmp jmp ... jmp RESET EXT_INT0 EXT_INT1 ... SPM_RDY ; Reset handler ; IRQ0 Handler ; IRQ1 Handler ; ; SPM Ready Handler ldi out ldi out sei r16,high(RAMEND) SPH,r16 r16,low(RAMEND) SPL,r16 ; Main program start ; Set Stack Pointer to top of RAM xxx ; Enable interrupts Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 90 16.4. Register Description 16.4.1. Moving Interrupts Between Application and Boot Space The MCU Control Register controls the placement of the Interrupt Vector table. (For ATmega88PA and ATmega168PA ) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 91 16.4.2. MCU Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. Name: MCUCR Offset: 0x55 Reset: 0x00 Property: When addressing as I/O Register: address offset is 0x35 Bit 7 Access Reset 6 5 4 1 0 BODS BODSE PUD 3 2 IVSEL IVCE R/W R/W R/W R/W R/W 0 0 0 0 0 Bit 6 - BODS: BOD Sleep The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be written to zero within four clock cycles. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. Bit 5 - BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. Bit 4 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). Bit 1 - IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. 2. Write the Interrupt Vector Change Enable (IVCE) bit to one. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 92 placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Bit 0 - IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1< CSn[2:0] > 0x1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 21.3. External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. See also the block diagram of the T1/T0 synchronization and edge detector logic below. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn[2:0]=0x7) or negative (CSn[2:0]=0x6) edge it detects. Figure 21-1. T1/T0 Pin Sampling Tn D Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 193 The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fTn < fclk_I/O/2) given a 50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by the tolerances of the oscillator source (crystal, resonator, and capacitors), it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 21-2. Prescaler for Timer/Counter0 and Timer/Counter1(1) clk I/O 10-BIT T/C PRESCALER CK/1024 CK/256 PSR10 CK/64 CK/8 Clear OFF Tn Synchronization CSn0 CSn1 CSn2 TIMER /COUNTERn CLOCK SOURCE clk Tn Note: 1. The synchronization logic on the input pins (T1/T0) is shown in the block diagram above. 21.4. Register Description Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 194 21.4.1. General Timer/Counter Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. Name: GTCCR Offset: 0x43 Reset: 0x00 Property: When addressing as I/O Register: address offset is 0x23 Bit Access Reset 1 0 TSM 7 6 5 4 3 2 PSRASY PSRSYNC R/W R/W R/W 0 0 0 Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/ Counters start counting simultaneously. Bit 1 - PSRASY: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Bit 0 - PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/ Counter0 share the same prescaler and a reset of this prescaler will affect both timers. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 195 22. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation 22.1. Features * * * * * * * 22.2. Channel Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV2, OCF2A, and OCF2B) Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 (TC2) is a general purpose, channel, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown below. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the following Register Description. For the actual placement of I/O pins, refer to the pinout diagram. The TC2 is enabled when the PRTIM2 bit in the Power Reduction Register (PRR.PRTIM2) is written to '1'. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 196 Figure 22-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn = =0 OCnA (Int.Req.) Waveform Generation = OCnA OCRnA DATA BUS Fixed TOP Value OCnB (Int.Req.) Waveform Generation = OCnB OCRnB TCCRnA TCCRnB Related Links Pin Configurations on page 15 22.2.1. Definitions Many register and bit references in this section are written in general form: * n=2 represents the Timer/Counter number * x=A,B represents the Output Compare Unit A or B However, when using the register or bit definitions in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value. The following definitions are used throughout the section: Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 197 Table 22-1. Definitions Constant Description BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). 22.2.2. MAX The counter reaches its maximum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation. Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source he Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the Timer/ Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC2A and OC2B). See Output Compare Unit for details. The compare match event will also set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare interrupt request. 22.3. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source: The clock source clkT2 is by default equal/synchronous to the MCU clock, clkI/O. When the Asynchronous TC2 bit in the Asynchronous Status Register (ASSR.AS2) is written to '1', the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see the description of the ASSR. For details on clock sources and prescaler, see Timer/Counter Prescaler. 22.4. Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Below is the block diagram of the counter and its surroundings. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 198 Figure 22-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count clear TCNTn clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 clkI/O top Table 22-2. Signal description (internal signals): Signal name Description count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS2[2:0]). When no clock source is selected (CS2[2:0]=0x0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/ Counter Control Register (TCCR2A) and the WGM22 bit located in the Timer/Counter Control Register B (TCCR2B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B. For more details about advanced counting sequences and waveform generation, see "Modes of Operation". The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the TCC2B.WGM2[2:0] bits. TOV2 can be used for generating a CPU interrupt. 22.5. Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the Output Compare Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM2[2:0] bits and Compare Output mode (COM2x[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See Modes of Operation). The following figure shows a block diagram of the Output Compare unit. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 199 Figure 22-3. Output Compare Unit, Block Diagram DATA BUS TCNTn OCRnx = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn[1:0] COMnx[1:0] The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x directly. Related Links Modes of Operation on page 138 22.5.1. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare match had occurred (the COM2x[1:0] bits settings define whether the OC2x pin is set, cleared or toggled). 22.5.2. Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 22.5.3. Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 200 compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2x[1:0] bits are not double buffered together with the compare value. Changing the COM2x[1:0] bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM2x[1:0]) bits have two functions. The Waveform Generator uses the COM2x[1:0] bits for defining the Output Compare (OC2x) state at the next compare match. Also, the COM2x[1:0] bits control the OC2x pin output source. The following figure shows a simplified schematic of the logic affected by the COM2x[1:0] bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x[1:0] bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. Figure 22-4. Compare Match Output Unit, Schematic COMnx[1] COMnx[0] FOCnx Waveform Generator D Q 1 OCnx D DATA BUS 22.6. 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x[1:0] bit settings are reserved for certain modes of operation. See Register Description. Related Links Modes of Operation on page 138 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 201 22.6.1. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x[1:0] bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x[1:0] = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. Refer also to the descriptions of the output modes. A change of the COM2x[1:0] bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 22.7. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM2[2:0]) and Compare Output mode (COM2x[1:0]) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2x[1:0] bits control whether the output should be set, cleared, or toggled at a compare match (See Compare Match Output Unit). For detailed timing information refer to Timer/Counter Timing Diagrams. 22.7.1. Normal Mode The simplest mode of operation is the Normal mode (WGM2[2:0] = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 22.7.2. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM2[2:0] = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is as follows. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 202 Figure 22-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) (COMnx[1:0] = 0x1) Period 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A[1:0] = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: OCnx = clk_I/O 2 1 + OCRnx The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 22.7.3. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM2[2:0] = 0x3 or 0x7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2[2:0] = 0x3, and OCR2A when WGM2[2:0] = 0x7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is depicted in the following figure. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 203 small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 22-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx[1:0] = 0x2) OCnx (COMnx[1:0] = 0x3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2x[1:0] to three. TOP is defined as 0xFF when WGM2[2:0] = 0x3, and OCR2A when MGM2[2:0] = 0x7. The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x Register at the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: OCnxPWM = clk_I/O 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A[1:0] bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x[1:0] = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 22.7.4. Phase Correct PWM Mode The phase correct PWM mode (WGM2[2:0] = 0x1 or 0x5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 204 0xFF when WGM2[2:0] = 0x3, and OCR2A when MGM2[2:0] = 7. In non-inverting Compare Output mode, the Output Compare (OC2x) is cleared on the compare match between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 22-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 22-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx[1:0] = 2) OCnx (COMnx[1:0] = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x[1:0] to three. TOP is defined as 0xFF when WGM2[2:0] = 0x3, and OCR2A when WGM2[2:0] = 7. The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 205 OCnxPCPWM = clk_I/O 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in the above figure OC2x has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. * OCR2A changes its value from MAX, as shown in the preceeding figure. When the OCR2A value is MAX the OC2 pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OC2 value at MAX must correspond to the result of an up-counting Compare Match. * The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OC2 change that would have happened on the way up. 22.8. Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/ Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 22-8. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The following figure shows the same timing data, but with the prescaler enabled. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 206 Figure 22-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn The following figure shows the setting of OCF2A in all modes except CTC mode. Figure 22-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx The following figure shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 22-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP BOTTOM OCRnx BOTTOM + 1 TOP OCFnx 22.9. Asynchronous Operation of Timer/Counter2 When TC2 operates asynchronously, some considerations must be taken: * When switching between asynchronous and synchronous clocking of TC2, the registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 207 * * * * * * * 1. Disable the TC2 interrupts by clearing OCIE2x and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2x, and TCCR2x. 4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. 5. Clear the TC2 Interrupt Flags. 6. Enable interrupts, if needed. The CPU main clock frequency must be more than four times the oscillator frequency. When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the five mentioned registers has its individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2x write in progress. The Asynchronous Status Register (ASSR) indicates that a transfer to the destination register has taken place. When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or TCCR2x, the user must wait until the written register has been updated if TC2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if any of the Output Compare2 interrupts is used to wake up the device, since the Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. If TC2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode within the TOSC1 cycle, the interrupt will immediately occur and the device wake up again. The result is multiple interrupts and wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2x, TCNT2, or OCR2x. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or ADC Noise Reduction mode. When the asynchronous operation is selected, the 32.768kHz oscillator for TC2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using TC2 after power-up or wake-up from Power-down or Standby mode. The contents of all TC2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 208 * unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Wait for the corresponding Update Busy Flag to be cleared. 2. Read TCNT2. During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 22.10. Timer/Counter Prescaler Figure 22-12. Prescaler for TC2 PSRASY clkT2S/1024 clkT2S/256 clkT2S/128 clkT2S/64 AS2 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for TC2 is named clkT2S. It is by default connected to the main system I/O clock clkI/O. By writing a '1' to the Asynchronous TC2 bit in the Asynchronous Status Register (ASSR.AS2), TC2 is asynchronously clocked from the TOSC1 pin. This enables use of TC2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for TC2. The Oscillator is optimized for use with a 32.768kHz crystal. For TC2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. The prescaler is reset by writing a '1' to the Prescaler Reset TC2 bit in the General TC2 Control Register (GTCCR.PSRASY). This allows the user to operate with a defined prescaler. 22.11. Register Description Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 209 22.11.1. TC2 Control Register A Name: TCCR2A Offset: 0xB0 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 COM2A1 COM2A0 COM2B1 R/W R/W R/W 0 0 0 3 2 1 0 COM2B0 WGM21 WGM20 R/W R/W R/W 0 0 0 Bits 7:6 - COM2An: Compare Output Mode for Channel A [n = 1:0] These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A[1:0] bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the WGM2[2:0] bit setting. The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to a normal or CTC mode (non- PWM). Table 22-3. Compare Output Mode, non-PWM COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match. 1 1 Set OC2A on Compare Match . The table below shows the COM2A[1:0] bit functionality when the WGM2[1:0] bits are set to fast PWM mode. Table 22-4. Compare Output Mode, Fast PWM(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected WGM22 = 1: Toggle OC2A on Compare Match 1 0 Clear OC2A on Compare Match, set OC2A at BOTTOM (non-inverting mode) 1 1 Set OC2A on Compare Match, clear OC2A at BOTTOM (inverting mode) Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details. The table below shows the COM2A[1:0] bit functionality when the WGM2[2:0] bits are set to phase correct PWM mode. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 210 Table 22-5. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare Match when down-counting. Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. Refer to Phase Correct PWM Mode for details. Bits 5:4 - COM2Bn: Compare Output Mode for Channel B [n = 1:0] These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B[1:0] bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin must be set in order to enable the output driver. When OC2B is connected to the pin, the function of the COM2B[1:0] bits depends on the WGM2[2:0] bit setting. The table shows the COM2B[1:0] bit functionality when the WGM2[2:0] bits are set to a normal or CTC mode (non- PWM). Table 22-6. Compare Output Mode, non-PWM COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected. 0 1 Toggle OC2B on Compare Match. 1 0 Clear OC2B on Compare Match. 1 1 Set OC2B on Compare Match. The table below shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode. Table 22-7. Compare Output Mode, Fast PWM(1) COM0B1 COM0B0 Description 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match, set OC0B at BOTTOM, (non-inverting mode) 1 1 Set OC0B on Compare Match, clear OC0B at BOTTOM, (inverting mode) Note: Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 211 1. A special case occurs when OCR2B equals TOP and COM2B[1] is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. Refer to Fast PWM Mode for details. The table below shows the COM2B[1:0] bit functionality when the WGM2[2:0] bits are set to phase correct PWM mode. Table 22-8. Compare Output Mode, Phase Correct PWM Mode(1) COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected. 0 1 Reserved 1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare Match when down-counting. 1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare Match when down-counting. Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. Refer to Phase Correct PWM Mode for details. Bits 1:0 - WGM2n: Waveform Generation Mode [n = 1:0] Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see Modes of Operation). Table 22-9. Waveform Generation Mode Bit Description Mode WGM22 WGM21 WGM20 Timer/Counter Mode of Operation TOP Update of OCR0x at 0 0 0 1 0 0 2 0 1 3 0 1 4 1 5 TOV Flag Set on(1) 0 Normal 0xFF Immediate MAX 1 PWM, Phase Correct 0xFF TOP BOTTOM 0 CTC OCRA Immediate MAX 1 Fast PWM 0xFF BOTTOM MAX 0 0 Reserved - - - 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM 6 1 1 0 Reserved - - - 7 1 1 1 Fast PWM OCRA BOTTOM TOP Note: 1. MAX = 0xFF 2. BOTTOM = 0x00 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 212 22.11.2. TC2 Control Register B Name: TCCR2B Offset: 0xB1 Reset: 0x00 Property: - Bit Access Reset 7 6 FOC2A FOC2B 5 4 WGM22 3 2 1 0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 CS2[2:0] Bit 7 - FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. To ensure compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A[1:0] bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A[1:0] bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. Bit 6 - FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. To ensure compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is changed according to its COM2B[1:0] bits setting. Note that the FOC2B bit is implemented as a strobe. Therefore it is the value present in the COM2B[1:0] bits that determines the effect of the forced compare. A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2B as TOP. The FOC2B bit is always read as zero. Bit 3 - WGM22: Waveform Generation Mode Refer to TCCR2A. Bits 2:0 - CS2[2:0]: Clock Select 2 [n = 0..2] The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 22-10. Clock Select Bit Description CA22 CA21 CS20 0 0 0 No clock source (Timer/Counter stopped). 1 clkI/O/1 (No prescaling) 0 clkI/O/8 (From prescaler) 0 0 1 Description Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 213 CA22 CA21 CS20 Description 0 1 1 clkI/O/32 (From prescaler) 1 0 0 clkI/O/64 (From prescaler) 1 0 1 clkI/O/128 (From prescaler) 1 1 0 clkI/O/256 (From prescaler) 1 1 1 clkI/O/1024 (From prescaler) If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 214 22.11.3. TC2 Counter Value Register Name: TCNT2 Offset: 0xB2 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 TCNT2[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - TCNT2[7:0]: Timer/Counter 2 Counter Value The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 215 22.11.4. TC2 Output Compare Register A Name: OCR2A Offset: 0xB3 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 OCR2A[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR2A[7:0]: Output Compare 2 A The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 216 22.11.5. TC2 Output Compare Register B Name: OCR2B Offset: 0xB4 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 OCR2B[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 - OCR2B[7:0]: Output Compare 2 B The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 217 22.11.6. TC2 Interrupt Mask Register Name: TIMSK2 Offset: 0x70 Reset: 0x00 Property: - Bit Access Reset 7 6 5 4 3 2 1 0 OCIEB OCIEA TOIE R/W R/W R/W 0 0 0 Bit 2 - OCIEB: Timer/Counter2, Output Compare B Match Interrupt Enable When the OCIEB bit is written to '1' and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCFB bit is set in TIFR2. Bit 1 - OCIEA: Timer/Counter2, Output Compare A Match Interrupt Enable When the OCIEA bit is written to '1' and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCFA bit is set in TIFR2. Bit 0 - TOIE: Timer/Counter2, Overflow Interrupt Enable When the TOIE bit is written to '1' and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV bit is set in TIFR2. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 218 22.11.7. TC2 Interrupt Flag Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. Name: TIFR2 Offset: 0x37 Reset: 0x00 Property: When addressing as I/O Register: address offset is 0x17 Bit Access Reset 7 6 5 4 3 2 1 0 OCFB OCFA TOV R/W R/W R/W 0 0 0 Bit 2 - OCFB: Timer/Counter2, Output Compare B Match Flag The OCFB bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCRB - Output Compare Register2. OCFB is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCFB is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIEB (Timer/Counter2 Compare match Interrupt Enable), and OCFB are set (one), the Timer/ Counter2 Compare match Interrupt is executed. Bit 1 - OCFA: Timer/Counter2, Output Compare A Match Flag The OCFA bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCRA - Output Compare Register2. OCFA is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCFA is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIEA (Timer/Counter2 Compare match Interrupt Enable), and OCFA are set (one), the Timer/ Counter2 Compare match Interrupt is executed. Bit 0 - TOV: Timer/Counter2, Overflow Flag The TOV bit is set (one) when an overflow occurs in Timer/Counter2. TOV is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV is cleared by writing a logic one to the flag. When the SREG I-bit, TOIEA (Timer/Counter2 Overflow Interrupt Enable), and TOV are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/ Counter2 changes counting direction at 0x00. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 219 22.11.8. Asynchronous Status Register Name: ASSR Offset: 0xB6 Reset: 0x00 Property: - Bit 7 6 5 4 3 2 1 0 EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Access R R R R R R R Reset 0 0 0 0 0 0 0 Bit 6 - EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. Bit 5 - AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. Bit 4 - TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. Bit 3 - OCR2AUB: Enable External Clock Input When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. Bit 2 - OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. Bit 1 - TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. Bit 0 - TCR2BUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 220 22.11.9. General Timer/Counter Control Register When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F. Name: GTCCR Offset: 0x43 Reset: 0x00 Property: When addressing as I/O Register: address offset is 0x23 Bit Access Reset 1 0 TSM 7 6 5 4 3 2 PSRASY PSRSYNC R/W R/W R/W 0 0 0 Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/ Counters start counting simultaneously. Bit 1 - PSRASY: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Bit 0 - PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/ Counter0 share the same prescaler and a reset of this prescaler will affect both timers. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 221 23. SPI - Serial Peripheral Interface 23.1. Features * * * * * * * * 23.2. Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral units, or between several AVR devices. The USART can also be used in Master SPI mode, please refer to USART in SPI Mode chapter. To enable the SPI module, Power Reduction Serial Peripheral Interface bit in the Power Reduction Register (PRR.PRSPI0) must be written to '0'. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 222 Figure 23-1. SPI Block Diagram SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: Refer to the pin-out description and the IO Port description for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in the figure below. The system consists of two shift registers, and a Master Clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 223 data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 23-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be longer than two CPU clock cycles. When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to the table below. For more details on automatic port overrides, refer to the IO Port description. Table 23-1. SPI Pin Overrides Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See the IO Port description for how to define the SPI pin directions. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRR0L = (unsigned char)ubrr; Enable receiver and transmitter */ UCSR0B = (1<> 1) & 0x01; return ((resh << 8) | resl); The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Related Links About Code Examples on page 25 24.8.3. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 24.8.4. Receiver Error Flags The USART Receiver has three Error Flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly read as '1', and the FE Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun (DOR) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), a new character is waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set, one or more serial frames were lost between the last frame read from UDR, and the next frame read from UDR. For compatibility with future Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 242 devices, always write this bit to zero when writing to UCSRnA. The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPE bit will always read '0'. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see Parity Bit Calculation and 'Parity Checker' below. 24.8.5. Parity Checker The Parity Checker is active when the high USART Parity Mode bit 1 in the USART Control and Status Register n C (UCSRnC.UPM[1]) is written to '1'. The type of Parity Check to be performed (odd or even) is selected by the UCSRnC.UPM[0] bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The USART Parity Error Flag in the USART Control and Status Register n A (UCSRnA.UPE) can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM[1] = 1). This bit is valid until the receive buffer (UDRn) is read. 24.8.6. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., UCSRnB.RXEN is written to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost. 24.8.7. Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code shows how to flush the receive buffer of USART0. Assembly Code Example USART_Flush: in r16, UCSR0A sbrs r16, RXC ret in r16, UDR0 rjmp USART_Flush C Code Example void USART_Flush( void ) { unsigned char dummy; while ( UCSR0A & (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck 12MHz Serial Programming Pin Mapping Table 32-16. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB3 I Serial Data in MISO PB4 O Serial Data out SCK PB5 I Serial Clock Note: The pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. 32.8.2. Serial Programming Algorithm When writing serial data to the device, data is clocked on the rising edge of SCK. When reading data from the device, data is clocked on the falling edge of SCK. Please refer to the figure, Serial Programming Waveforms in SPI Serial Programming Characteristics section for timing details. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 378 To program and verify the device in the serial programming mode, the following sequence is recommended (See Serial Programming Instruction set in Table 32-18: 1. 2. 3. 4. 5. 6. 7. 8. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page . Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next byte. In a chip erased device, no 0xFF in the data file(s) need to be programmed. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. At the end of the programming session, RESET can be set high to commence normal operation. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. Table 32-17. Typical Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 2.6ms tWD_EEPROM 3.6ms Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 379 32.8.3. Symbol Minimum Wait Delay tWD_ERASE 10.5ms tWD_FUSE 4.5ms Serial Programming Instruction Set This section describes the Instruction Set. Table 32-18. Serial Programming Instruction Set (Hexadecimal values) Instruction/Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte 4 Programming Enable 0xAC 0x53 0x00 0x00 Chip Erase (Program Memory/EEPROM) 0xAC 0x80 0x00 0x00 Poll RDY/BSY 0xF0 0x00 0x00 data byte out Load Extended Address byte(1) 0x4D 0x00 Extended adr 0x00 Load Program Memory Page, High byte 0x48 0x00 adr LSB high data byte in Load Program Memory Page, Low byte 0x40 0x00 adr LSB low data byte in Load EEPROM Memory Page (page access) 0xC1 0x00 0000 000aa data byte in Read Program Memory, High byte 0x28 adr MSB adr LSB high data byte out Read Program Memory, Low byte 0x20 adr MSB adr LSB low data byte out Read EEPROM Memory 0xA0 0000 00aa aaaa aaaa data byte out Read Lock bits 0x58 0x00 0x00 data byte out Read Signature Byte 0x30 0x00 0000 000aa data byte out Read Fuse bits 0x50 0x00 0x00 data byte out Read Fuse High bits 0x58 0x08 0x00 data byte out Read Extended Fuse Bits 0x50 0x08 0x00 data byte out Read Calibration Byte 0x38 0x00 0x00 data byte out Write Program Memory Page 0x4C adr MSB(8) adr LSB(8) 0x00 Write EEPROM Memory 0xC0 0000 00aa aaaa aaaa data byte in Write EEPROM Memory Page (page access) 0xC2 0000 00aa aaaa aa00 0x00 Write Lock bits 0xAC 0xE0 0x00 data byte in Write Fuse bits 0xAC 0xA0 0x00 data byte in Load Instructions Read Instructions Write Instructions(6) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 380 Instruction/Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte 4 Write Fuse High bits 0xAC 0xA8 0x00 data byte in Write Extended Fuse Bits 0xAC 0xA4 0x00 data byte in Note: 1. Not all instructions are applicable for all parts. 2. a = address. 3. Bits are programmed `0', unprogrammed `1'. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (`1') . 5. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. 8. WORDS. If the LSB in RDY/BSY data byte out is `1', a programming operation is still pending. Wait until this bit returns `0' before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, Please refer to the following figure. Figure 32-7. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Adr MSB Bit 15 B Byte 3 Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adr LSB 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 381 32.8.4. SPI Serial Programming Characteristics Figure 32-8. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 382 33. Electrical Characteristics 33.1. Absolute Maximum Ratings Table 33-1. Absolute Maximum Ratings Operating Temperature -55C to +125C Storage Temperature -65C to +150C Voltage on any Pin except RESET with respect to Ground -0.5V to VCC+0.5V Voltage on RESET with respect to Ground -0.5V to +13.0V Maximum Operating Voltage 6.0V DC Current per I/O Pin 40.0mA DC Current VCC and GND Pins 200.0mA Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 33.2. Common DC Characteristics Table 33-2. Common DC characteristics TA = -40C to 105C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. VIL Input Low Voltage, except XTAL1 and RESET pin VCC = 1.8V - 2.4V -0.5 0.2VCC(1) V VCC = 2.4V - 5.5V -0.5 0.3VCC(1) Input High Voltage, except XTAL1 and RESET pins VCC = 1.8V - 2.4V 0.7VCC(2) VCC + 0.5 V VCC = 2.4V - 5.5V 0.6VCC(2) VCC + 0.5 VIL1 Input Low Voltage, XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V VIH1 Input High Voltage, XTAL1 pin VCC = 1.8V - 2.4V 0.8VCC(2) VCC + 0.5 V VCC = 2.4V - 5.5V 0.7VCC(2) VCC + 0.5 VIL2 Input Low Voltage, RESET pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V VIH2 Input High Voltage, RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC + 0.5 V VIL3 Input Low Voltage, RESET pin as I/O VCC = 1.8V - 2.4V -0.5 0.2VCC(1) V VCC = 2.4V - 5.5V -0.5 0.3VCC(1) VIH Typ. Max. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 Units 383 Symbol Parameter Condition Min. VIH3 VCC = 1.8V - 2.4V 0.7VCC(2) VCC + 0.5 V VCC = 2.4V - 5.5V 0.6VCC(2) VCC + 0.5 VOL Input High Voltage, RESET pin as I/O Output Low Voltage(4) except RESET pin IOL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V VOH Output High Voltage(3) except Reset pin Typ. Max. Units TA=85C 0.9 V TA=105C 1.0 V TA=85C 0.6 V TA=105C 0.7 V IOH = -20mA, TA=85C 4.2 TA=105C 4.1 VCC = 5V V V IOH = -10mA, TA=85C 2.3 TA=105C 2.1 VCC = 3V V V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 A IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1 A RRST Reset Pull-up Resistor 30 60 k RPU I/O Pin Pull-up Resistor 20 50 k VACIO Analog Comparator Input Offset Voltage VCC = 5V <10 40 mV Analog Comparator Input Leakage Current VCC = 5V 50 nA Analog Comparator Propagation Delay VCC = 2.7V 750 VCC = 4.0V 500 IACLK tACID Vin = VCC/2 -50 Vin = VCC/2 ns Note: 1. "Max." means the highest value where the pin is guaranteed to be read as low. 2. "Min." means the lowest value where the pin is guaranteed to be read as high. 3. Although each I/O port can source more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 3.1. The sum of all IOH, for ports C0 - C5, D0- D4, ADC7, RESET should not exceed 100mA. 3.2. The sum of all IOH, for ports B0 - B5, D5 - D7, ADC6, XTAL1, XTAL2 should not exceed 100mA. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 384 4. If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 4.1. The sum of all IOL, for ports C0 - C5, ADC7, ADC6 should not exceed 100mA. 4.2. The sum of all IOL, for ports B0 - B5, D5 - D7, XTAL1, XTAL2 should not exceed 100mA. 4.3. The sum of all IOL, for ports D0 - D4, RESET should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. Related Links Minimizing Power Consumption on page 68 33.2.1. ATmega48PA DC Characteristics - Current Consumption Table 33-3. DC characteristics - TA = -40C to 85/105C, VCC = 1.8V to 5.5V (unless otherwise noted) Typ.(2) Max. Units T = 85C 0.2 0.5 mA T = 105C 0.22 0.55 T = 85C 1.2 2.5 T = 105C 1.15 2.65 T = 85C 4.0 9.0 T = 105C 4.1 9.5 T = 85C 0.03 0.15 T = 105C 0.024 0.16 T = 85C 0.21 0.7 T = 105C 0.2 0.75 T = 85C 0.9 2.7 T = 105C 0.78 2.8 32kHz TOSC enabled, VCC = 1.8V T = 85C 0.75 T = 105C 0.75 32kHz TOSC enabled, VCC = 3V T = 85C 0.83 T = 105C 0.9 WDT enabled, VCC = 3V T = 85C 3.9 8 T = 105C 3.9 10 T = 85C 0.1 2 T = 105C 0.1 5 Symbol Parameter Condition ICC Power Supply Current(1) Active 1MHz, VCC = 2V Min. Active 4MHz, VCC = 3V Active 8MHz, VCC = 5V Idle 1MHz, VCC = 2V Idle 4MHz, VCC = 3V Idle 8MHz,VCC = 5V Power-save mode(3) Power-down mode(3) WDT disabled, VCC = 3V A Note: 1. Values with Minimizing Power Consumption enabled (0xFF). Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 385 2. 3. 33.2.2. Typical values at 25C. Maximum values are test limits in production. The current consumption values include input leakage current. ATmega88PA DC Characteristics - Current Consumption Table 33-4. DC characteristics - TA = -40C to 85/105C, VCC = 1.8V to 5.5V (unless otherwise noted) Typ.(2) Max. Units T = 85C 0.2 0.5 mA T = 105C 0.2 0.6 T = 85C 1.2 2.5 T = 105C 1.2 2.75 T = 85C 4.1 9.0 T = 105C 4.1 10 T = 85C 0.03 0.15 T = 105C 0.03 0.17 T = 85C 0.18 0.7 T = 105C 0.18 0.8 T = 85C 0.8 2.7 T = 105C 0.8 3 32kHz TOSC enabled, VCC = 1.8V T = 85C 0.8 T = 105C 0.8 32kHz TOSC enabled, VCC = 3V T = 85C 0.83 T = 105C 0.9 WDT enabled, VCC = 3V T = 85C 3.9 8 T = 105C 3.9 10 T = 85C 0.1 2 T = 105C 0.1 5 Symbol Parameter Condition ICC Power Supply Current(1) Active 1MHz, VCC = 2V Min. Active 4MHz, VCC = 3V Active 8MHz, VCC = 5V Idle 1MHz, VCC = 2V Idle 4MHz, VCC = 3V Idle 8MHz,VCC = 5V Power-save mode(3) Power-down mode(3) WDT disabled, VCC = 3V A Note: 1. Values with Minimizing Power Consumption enabled (0xFF). 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 386 33.2.3. ATmega168PA DC Characteristics - Current Consumption Table 33-5. DC characteristics - TA = -40C to 85/105C, VCC = 1.8V to 5.5V (unless otherwise noted) Typ.(2) Max. Units T = 85C 0.2 0.5 mA T = 105C 0.3 0.6 T = 85C 1.2 2.5 T = 105C 1.8 2.75 T = 85C 4.2 9.0 T = 105C 6.7 10 T = 85C 0.03 0.15 T = 105C 0.06 0.2 T = 85C 0.2 0.7 T = 105C 0.4 0.8 T = 85C 0.9 2.7 T = 105C 1.7 3 32kHz TOSC enabled, VCC = 1.8V T = 85C 0.75 T = 105C 0.8 32kHz TOSC enabled, VCC = 3V T = 85C 0.83 T = 105C 0.9 WDT enabled, VCC = 3V T = 85C 4.1 8 T = 105C 4.6 10 T = 85C 0.1 2 T = 105C 0.1 5 Symbol Parameter Condition ICC Power Supply Current(1) Active 1MHz, VCC = 2V Min. Active 4MHz, VCC = 3V Active 8MHz, VCC = 5V Idle 1MHz, VCC = 2V Idle 4MHz, VCC = 3V Idle 8MHz,VCC = 5V Power-save mode(3) Power-down mode(3) WDT disabled, VCC = 3V A Note: 1. Values with Minimizing Power Consumption enabled (0xFF). 2. Typical values at 25C. Maximum values are test limits in production. 3. The current consumption values include input leakage current. 33.3. Speed Grades Maximum frequency is dependent on VCC. As shown in Figure. Maximum Frequency vs. VCC, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 387 Figure 33-1. Maximum Frequency vs. VCC 20MHz 10MHz Safe Operating Area 4MHz 1.8V 33.4. 2.7V 4.5V 5.5V Clock Characteristics Related Links Calibrated Internal RC Oscillator on page 57 33.4.1. Calibrated Internal RC Oscillator Accuracy Table 33-6. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0MHz 3.0V 25C 10% User Calibration 7.3 - 8.1MHz 1.8V - 5.5V -40C to - 85C 1% 33.4.2. External Clock Drive Waveforms Figure 33-2. External Clock Drive Waveforms VIH1 VIL1 33.4.3. External Clock Drive Table 33-7. External Clock Drive Symbol Parameter VCC= 1.8 - 5.5V VCC= 2.7 - 5.5V VCC= 4.5 - 5.5V Units Min. Max. Min. Max. Min. Max. 1/tCLCL Oscillator Frequency 0 4 0 10 0 20 MHz tCLCL Clock Period 250 - 100 - 50 - ns tCHCX High Time 100 - 40 - 20 - ns Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 388 Symbol Parameter 33.5. VCC= 1.8 - 5.5V VCC= 2.7 - 5.5V VCC= 4.5 - 5.5V Units Min. Max. Min. Max. Min. Max. tCLCX Low Time 100 - 40 - 20 - ns tCLCH Rise Time - 2.0 - 1.6 - 0.5 s tCHCL Fall Time - 2.0 - 1.6 - 0.5 s tCLCL Change in period from one clock cycle to the next - 2 - 2 - 2 % System and Reset Characteristics Table 33-8. Reset, Brown-out and Internal Voltage Characteristics(1) Symbol Parameter VPOT Condition Min. Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.5 1.7 V Power-on Reset Threshold Voltage (falling)(2) 0.6 1.0 1.7 V SRON Power-on Slope Rate 0.01 - 10 V/ms VRST RESET Pin Threshold Voltage 0.2 VCC - 0.9 VCC V tRST Minimum pulse width on RESET Pin - - 2.5 s VHYST Brown-out Detector Hysteresis - 50 - mV tBOD Min. Pulse Width on Brown-out Reset - 2 - s VBG Bandgap reference voltage VCC=2.7 TA=25C 1.0 1.1 1.2 V tBG Bandgap reference start-up time VCC=2.7 TA=25C - 40 70 s IBG Bandgap reference current consumption VCC=2.7 TA=25C - 10 - A Note: 1. Values are guidelines only. 2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling) Table 33-9. BODLEVEL Fuse Coding(1)(2) BODLEVEL [2:0] Fuses Min. VBOT Typ. VBOT Max VBOT Units 111 BOD Disabled 110 1.7 1.8 2.0 V 101 2.5 2.7 2.9 100 4.1 4.3 4.5 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 389 BODLEVEL [2:0] Fuses Min. VBOT 011 Reserved Typ. VBOT Max VBOT Units 010 001 000 Note: VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110, 101 and 100. Note: VBOT tested at 25C and 85C in production 33.6. SPI Timing Characteristics Table 33-10. SPI Timing Parameters Description Mode SCK period Typ Max Units Master - See Table. Relationship Between SCK and the Oscillator Frequency in "SPCR - SPI Control Register" - SCK high/low Master - 50% duty cycle - Rise/Fall time Master - 3.6 - Setup Master - 10 - Hold Master - 10 - Out to SCK Master - 0.5 * tsck - SCK to out Master - 10 - SCK to out high Master - 10 - SS low to out Slave - 15 - SCK period Slave 4 * tck - - SCK high/low(1) Slave 2 * tck - - Rise/Fall time Slave - - 1600 Setup Slave 10 - - Hold Slave tck - - SCK to out Slave - 15 - SCK to SS high Slave 20 - - 10 - SS high to tri-state Slave SS low to SCK Slave Min. 2 * tck - ns - Note: In SPI Programming mode the minimum SCK high/low period is: * 2 * tCLCLCL for fCK < 12MHz Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 390 * 3 * tCLCL for fCK > 12MHz Figure 33-3. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 ... MSB LSB 7 MOSI (Data Output) 8 MSB ... LSB Figure 33-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 33.7. 17 MSB ... LSB X Two-wire Serial Interface Characteristics Table in this section describes the requirements for devices connected to the 2-wire Serial Bus. The 2wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 33-5. Table 33-11. Two-wire Serial Bus Requirements Symbol Parameter Condition Min. Max Units V VIL Input Low-voltage -0.5 0.3 VCC VIH Input High-voltage 0.7 VCC VCC + 0.5 V Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 391 Symbol Parameter Vhys(1) Hysteresis of Schmitt Trigger Inputs VOL(1) Output Low-voltage tr(1) Rise Time for both SDA and SCL tof(1) Output Fall Time from VIHmin to VILmax tSP(1) Spikes Suppressed by Input Filter Ii Input Current each I/O Pin Ci(1) Capacitance for each I/O Pin fSCL SCL Clock Frequency Rp Value of Pull-up resistor tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Hold Time (repeated) START Condition Low Period of the SCL Clock High period of the SCL clock Set-up time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Condition 3mA sink current 10pF < Cb < 400pF(3) Min. Max Units 0.05 VCC(2) - V 0 0.4 V 20 + 0.1Cb(3)(2) 300 ns 20 + 0.1Cb(3)(2) 250 ns 0 50(2) ns -10 10 A - 10 pF fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz fSCL 100kHz 1000ns fSCL > 100kHz CC - 0.4V 3mA 0.1VCC < Vi < 0.9VCC fSCL 100kHz CC - 0.4V 3mA 4.0 300ns - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 1.3 - s fSCL 100kHz 4.0 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 0 3.45 s fSCL > 100kHz 0 0.9 s fSCL 100kHz 250 - ns fSCL > 100kHz 100 - ns fSCL 100kHz 4.0 - s fSCL > 100kHz 0.6 - s fSCL 100kHz 4.7 - s fSCL > 100kHz 1.3 - s Note: Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 392 1. 2. 3. 4. 5. This parameter is characterized and not 100% tested. Required only for fSCL > 100kHz. Cb = capacitance of one bus line in pF. fCK = CPU clock frequency. This requirement applies to all 2-wire Serial Interface operation. Other devices connected to the 2wire Serial Bus need only obey the general fSCL requirement. Figure 33-5. Two-wire Serial Bus Timing t of t HIGH t LOW tr t LOW SCL t SU;STA t HD;STA t HD;DAT t SU;DAT t SU;STO SDA t BUF 33.8. ADC Characteristics Table 33-12. ADC Characteristics Symbol Parameter Condition Min. Typ Max Units - 10 - Bits VREF = 4V, VCC = 4V, ADC clock = 200kHz - 2 - LSB VREF = 4V, VCC = 4V, ADC clock = 1MHz - 4 - LSB VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode - 2 - LSB VREF = 4V, VCC = 4V, ADC clock = 1MHz Noise Reduction Mode - 4 - LSB Integral Non-Linearity (INL) VREF = 4V, VCC = 4V, ADC clock = 200kHz - 0.5 - LSB Differential Non-Linearity (DNL) VREF = 4V, VCC = 4V, ADC clock = 200kHz - 0.25 - LSB Gain Error VREF = 4V, VCC = 4V, ADC clock = 200kHz - 2 - LSB Offset Error VREF = 4V, VCC = 4V, ADC clock = 200kHz - 2 - LSB Conversion Time Free Running Conversion 13 - 260 s Clock Frequency 50 - 1000 kHz Resolution Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 393 Symbol Parameter Condition Min. Typ Max Units AVCC(1) Analog Supply Voltage VCC - 0.3 - VCC + 0.3 V VREF Reference Voltage 1.0 - AVCC V VIN Input Voltage GND - VREF V Input Bandwidth - 38.5 VINT Internal Voltage Reference 1.0 1.1 1.2 V RREF Reference Input Resistance - 50 - k RAIN Analog Input Resistance - 100 - kHz M Note: 1. AVCC absolute min./max: 1.8V/5.5V 33.9. Parallel Programming Characteristics Table 33-13. Parallel Programming Characteristics, VCC = 5V 10% Symbol Parameter Min. Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current - 250 A tDVXH Data and Control Valid before XTAL1 High 67 - ns tXLXH XTAL1 Low to XTAL1 High 200 - ns tXHXL XTAL1 Pulse Width High 150 - ns tXLDX Data and Control Hold after XTAL1 Low 67 - ns tXLWL XTAL1 Low to WR Low 0 - ns tXLPH XTAL1 Low to PAGEL high 0 - ns tPLXH PAGEL low to XTAL1 high 150 - ns tBVPH BS1 Valid before PAGEL High 67 - ns tPHPL PAGEL Pulse Width High 150 - ns tPLBX BS1 Hold after PAGEL Low 67 - ns tWLBX BS2/1 Hold after RDY/BSY high 67 - ns tPLWL PAGEL Low to WR Low 67 - ns tBVWL BS1 Valid to WR Low 67 - ns tWLWH WR Pulse Width Low 150 - ns tWLRL WR Low to RDY/BSY Low 0 1 s tWLRH WR Low to RDY/BSY High(1) 3.2 3.4 ms tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 9.8 10.5 ms Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 394 Symbol Parameter Min. Max Units tXLOL XTAL1 Low to OE Low 0 - ns tBVDV BS1 Valid to DATA valid 0 350 ns tOLDV OE Low to DATA Valid - 350 ns tOHDZ OE High to DATA Tri-stated - 250 ns Note: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. Figure 33-6. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 Data & Contol (DATA, XA0/1, BS1, BS2) PAGEL tDVXH tXLDX tBVPH tPLBX t BVWL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 33-7. Parallel Programming Timing, Loading Sequence with Timing Requirements LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) t XLXH tXLPH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: The timing requirements shown in Parallel Programming Characteristics (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 395 Figure 33-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: The timing requirements shown in Parallel Programming Characteristics (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 396 34. Typical Characteristics (TA = -40C to 105C) The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 34.1.1. ATmega48PA Typical Characteristics Active Supply Current Figure 34-1. ATmega48PA: Active Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 1 5.5V 0.9 0.8 5.0V 0.7 ICC (mA) 34.1. 4.5V 0.6 4.0V 0.5 0.4 3.6V 3.3V 0.3 2.7V 0.2 1.8V 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 397 Figure 34-2. ATmega48PA: Active Supply Current vs. Frequency (1MHz - 20MHz) 11 5.5V 10 9 5.0V 8 4.5V ICC (mA) 7 6 4.0V 5 4 3.3V 3 2.7V 2 1 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Figure 34-3. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.05 105C 0.045 85C 0.04 ICC (mA) 0.035 0.03 25C -40C 0.025 0.02 0.015 0.01 0.005 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 398 Figure 34-4. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 105C 85C 25C -40C 1.2 1.1 1 ICC (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-5. ATmega48PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 5.5 105C 85C 25C -40C 5 4.5 ICC (mA) 4 3.5 3 2.5 2 1.5 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 399 Idle Supply Current Figure 34-6. ATmega48PA: Idle Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) ICC (mA) 0.16 0.14 5.5V 0.12 5.0V 0.1 4.5V 0.08 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Figure 34-7. ATmega48PA: Idle Supply Current vs. Frequency (1MHz - 20MHz) 2.6 5.5V 2.4 2.2 5.0V 2 4.5V 1.8 1.6 ICC (mA) 34.1.2. 1.4 4.0V 1.2 1 0.8 3.3V 0.6 2.7V 0.4 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 400 Figure 34-8. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.05 105C 0.045 85C 0.04 ICC (mA) 0.035 0.03 25C -40C 0.025 0.02 0.015 0.01 0.005 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-9. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.33 105C 85C 25C -40C ICC (mA) 0.28 0.23 0.18 0.13 0.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 401 Figure 34-10. ATmega48PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 1.3 105C 85C 25C -40C 1.2 1.1 1 ICC (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.1.3. Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" for details. Table 34-1. ATmega48PA: Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers (A) VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART0 2.9 20.7 97.4 PRTWI 6.0 44.8 219.7 PRTIM2 5.0 34.5 141.3 PRTIM1 3.6 24.4 107.7 PRTIM0 1.4 9.5 38.4 PRSPI 5.0 38.0 190.4 PRADC 6.1 47.4 244.7 Table 34-2. ATmega48PA: Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 34-1 and Figure 34-2) Additional Current consumption compared to Idle with external clock (see Figure 34-6 and Figure 34-7) PRUSART0 1.8% 11.4% PRTWI 3.9% 20.6% PRTIM2 2.9% 15.7% PRTIM1 2.1% 11.2% Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 402 PRR bit Additional Current consumption compared to Active with external clock (see Figure 34-1 and Figure 34-2) Additional Current consumption compared to Idle with external clock (see Figure 34-6 and Figure 34-7) PRTIM0 0.8% 4.2% PRSPI 3.3% 17.6% PRADC 4.2% 22.1% It is possible to calculate the typical current consumption based on the numbers from the above table for other VCC and frequency settings. Related Links PRR on page 73 34.1.3.1. Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table Additional Current Consumption (percentage) in Active and Idle mode in the previous section, third column, we see that we need to add 11.2% for the TIMER1, 22.1% for the ADC, and 17.6% for the SPI module. Reading from Figure Idle Supply Current vs. Low Frequency (0.1-1.0MHz), we find that the idle current consumption is ~0.028mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: Power-down Supply Current Figure 34-11. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 2.7 105C 2.4 2.1 1.8 ICC (A) 34.1.4. ICCtotal 0.028 mA(1 + 0.112 + 0.221 + 0.176) 0.042 mA 1.5 1.2 0.9 85C -40C 0.6 0.3 25C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 403 Figure 34-12. ATmega48PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 9 105C 8.5 8 -40C 85C 25C 7.5 7 ICC (A) 6.5 6 5.5 5 4.5 4 3.5 3 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 34-13. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2.5 2.25 105C 2 1.75 Icc [A] 34.1.5. 1.5 85C 1.25 1 0.75 25C 0.5 -40C 0.25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 404 34.1.6. Standby Supply Current Figure 34-14. ATmega48PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 150 6MHz_xta l 6MH z _r e s 135 120 4MH z _r e s 4MHz_xta l 105 ICC (A) 90 2MH z _r e s 2MHz_xta l 75 60 1MHz_re s 450kHz_re s 45 30 15 0.0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-Up Figure 34-15. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 45 40 35 30 IOP (A) 34.1.7. 25 20 15 10 105C -40C 25C 85C 5 0 0 0.2 0.4 0.6 1 0.8 1.2 1.4 1.6 1.8 VOP (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 405 Figure 34-16. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 70 60 IOP (A) 50 40 30 20 25C 85C -40C 105C 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VOP (V) Figure 34-17. ATmega48PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 120 105 IOP (A) 90 75 60 45 30 25C 85C 105C -40C 15 0 0 0.5 1 1.5 2 3 2.5 3.5 4 4.5 5 VOP (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 406 Figure 34-18. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRES ET (A) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25C -40C 105C 85C 1.8 VRES ET (V) Figure 34-19. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 52 48 44 40 IRES ET (A) 36 32 28 24 20 16 12 25C -40C 85C 105C 8 4 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRES ET (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 407 Figure 34-20. ATmega48PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 110 100 90 80 IRES ET (A) 70 60 50 40 30 85C 25C -40C 105C 20 10 0 0 0.5 1 1.5 2 3 2.5 3.5 4 4.5 5 VRES ET (V) Pin Driver Strength Figure 34-21. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105C 85C 0.9 0.8 25C 0.7 0.6 VOL (V) 34.1.8. -40C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 408 Figure 34-22. ATmega48PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) Figure 34-23. ATmega48PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V) 3 2.9 2.8 2.7 VOH (V) 2.6 2.5 2.4 -40C 2.3 2.2 25C 2.1 2 85C 105C 1.9 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 409 Figure 34-24. ATmega48PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -40C 4.5 25C 4.4 85C 105C 4.3 0 2 4 8 6 10 12 14 16 18 20 IOH (mA) Pin Threshold and Hysteresis Figure 34-25. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as `1') 105C 85C -40C 25C 2.9 2.6 2.3 Thre s hold (V) 34.1.9. 2 1.7 1.4 1.1 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 410 Figure 34-26. ATmega48PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as `0' 105C -40C 85C 25C 2.4 2.1 Thre s hold (V) 1.8 1.5 1.2 0.9 0.6 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-27. ATmega48PA: I/O Pin Input Hysteresis vs. VCC 0.6 -40 C 25C 85C 105C -40C Input Hys te re s is (mV) 0.55 0.5 0.45 25 C 0.4 85 C 0.35 0.3 105 C 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 411 Figure 34-28. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as `1') 105C 85C -40C 25C 2.45 Thre s hold (V) 2.2 1.95 1.7 1.45 1.2 -40C 25C 85C 105C 0.95 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-29. ATmega48PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as `0') -40C 105C 85C 25C 2.4 2.2 Thre s hold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 412 Figure 34-30. ATmega48PA: Reset Pin Input Hysteresis vs. VCC 0.65 -40C 0.6 0.55 Input Hys te re s is (mV) 0.5 0.45 25C 0.4 0.35 0.3 85C 0.25 0.2 0.15 105C 85C 105C 25C -40C 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.1.10. BOD Threshold Figure 34-31. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) 1.825 1.82 Ris ing Vcc 1.815 Thre s hold (V) 1.81 1.805 1.8 1.795 1.79 Fa lling Vcc 1.785 1.78 1.775 1.77 1.765 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Te mpe ra ture (C) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 413 Figure 34-32. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) 2.76 2.75 Ris ing Vcc 2.74 Thre s hold (V) 2.73 2.72 2.71 2.7 2.69 2.68 Fa lling Vcc 2.67 2.66 2.65 2.64 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 90 100 Te mpe ra ture (C) Figure 34-33. ATmega48PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) 4.34 4.32 Ris ing Vcc Thre s hold (V) 4.3 4.28 4.26 Fa lling Vcc 4.24 4.22 4.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 110 Te mpe ra ture (C) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 414 Figure 34-34. ATmega48PA: Bandgap Voltage vs. VCC 1.1325 1.13 Bandgap Voltage [V] 1.1275 105C 85C 1.125 25C 1.1225 1.12 1.1175 1.115 -40C 1.1125 1.11 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] 34.1.11. Internal Oscillator Speed Figure 34-35. ATmega48PA: Watchdog Oscillator Frequency vs. Temperature 116 114 F RC (kHz) 112 110 108 2.7V 3.3V 4.0V 5.5V 106 104 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Te mpe ra ture (C) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 415 Figure 34-36. ATmega48PA: Watchdog Oscillator Frequency vs. VCC F RC (kHz) 116 114 -40C 112 25C 110 108 85C 106 105C 104 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-37. ATmega48PA: Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.25 8.2 105C 8.15 85C 8.1 F RC (MHz) 8.05 8 25C 7.95 7.9 7.85 7.8 7.75 -40C 7.7 7.65 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 416 Figure 34-38. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 4.0V 3.0V 5.5V 8.2 8.15 1.8V 8.1 8.05 F RC (MHz) 8 7.95 7.9 7.85 7.8 7.75 7.7 7.65 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Te mpe ra ture (C) Figure 34-39. ATmega48PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 85C 25C 105C -40C 15 14 13 12 F RC (MHz) 11 10 9 8 7 6 5 4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 417 34.1.12. Current Consumption of Peripheral Units Figure 34-40. ATmega48PA: ADC Current vs. VCC (AREF = AVCC) -40C 25C 85C 105C 310 290 270 ICC (A) 250 230 210 190 170 150 130 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-41. ATmega48PA: Analog Comparator Current vs. VCC 90 -40C 85 80 25C 85C 105C 75 ICC (A) 70 65 60 55 50 45 105C 85C 25C 35 -40C 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 418 Figure 34-42. ATmega48PA: AREF External Reference Current vs. VCC 105C 85C 25C -40C 150 140 130 120 ICC (A) 110 100 90 80 70 60 50 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-43. ATmega48PA: Brownout Detector Current vs. VCC 26 25 105C 85C 24 23 25C -40C ICC (A) 22 21 20 19 18 17 16 15 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 419 Figure 34-44. ATmega48PA: Programming Current vs. VCC 5.5 -40C 5 25C 4.5 ICC (mA) 4 3.5 3 85C 105C 2.5 2 1.5 1 1.5 2 3 2.5 3.5 4 4.5 5 5.5 VCC (V) 34.1.13. Current Consumption in Reset and Reset Pulsewidth Figure 34-45. ATmega48PA: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 0.13 5.5V 0.12 0.11 5.0V 0.1 0.09 4.5V ICC (mA) 0.08 4.0V 0.07 0.06 0.05 3.3V 0.04 2.7V 0.03 1.8V 0.02 0.01 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 420 Figure 34-46. ATmega48PA: Reset Supply Current vs. Frequency (1MHz - 20MHz) 2.4 5.5V 2.2 5.0V 2 1.8 4.5V ICC (mA) 1.6 1.4 4.0V 1.2 1 0.8 3.3V 0.6 2.7V 0.4 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Figure 34-47. ATmega48PA: Minimum Reset Pulse Width vs. Vcc Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 421 Active Supply Current ATme ga 88P A: Active S upply Curre vs . Frequency Low Fre que(0.1MHz ncy (0.1MHz -1.0MHz) Figure 34-48. ATmega88PA: Active Supply Current vs.ntLow - 1.0MHz) 1 0.9 5.5V 0.8 5.0V 0.7 ICC (mA) 34.2.1. ATmega88PA: Typical Characteristics 4.5V 0.6 4.0V 0.5 0.4 3.3V 0.3 2.7V 0.2 1.8V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) ATme ga 88P A: Active S upply Curre nt vs . Fre que ncy (1MHz - 20MHz) Figure 34-49. ATmega88PA: Active Supply Current vs. Frequency (1MHz - 20MHz) 12 5.5V 10 5.0V 8 ICC (mA) 34.2. 4.5V 6 4.0V 4 3.3V 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 422 ATme ga 88P A: Active S upply Curre VCC (Inte RC rna lOscillator, RC Os cilla128kHz) tor, 128kHz) Figure 34-50. ATmega88PA: Active Supply Current vs.ntVvs CC. (Internal 0.14 105C 0.12 -40C 25C ICC (mA) 0.1 85C 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-51. ATmega88PA: Supply Current vs.vsV.CC (Internal Oscillator, ATme ga 88PActive A: Active S upply Curre nt VCC (Inte rnaRC l RC Os cilla tor,1MHz) 1MHz) 1.4 105C 85C 25C -40C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 423 ATme ga Active 88P A: Active upply Curre vs (Internal . VCC (InteRC rnaOscillator, l RC Os cilla8MHz) tor, 8MHz) Figure 34-52. ATmega88PA: SupplyS Current vs. nt VCC 6 105C 85C 25C -40C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current ATme ga 88PSupply A: Idle Current S upply Curre nt vs . Low Fre que ncy (0.1MHz -1.0MHz) Figure 34-53. ATmega88PA: Idle vs. Low Frequency (0.1MHz - 1.0MHz) 0.14 5.5V 0.12 5.0V 0.1 ICC (mA) 34.2.2. 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 424 Figure 34-54. ATmega88PA: Supply Frequency ATme Idle ga 88P A: IdleCurrent S upply vs. Curre nt vs . Fre(1MHz que ncy- 20MHz) (1MHz - 20MHz) 2.5 5.5V 2 ICC (mA) 5.0V 4.5V 1.5 4.0V 1 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) ATme ga 88PIdle A: Idle S upply Currevs. nt vs . V(Internal l RC Os cilla tor, 128kHz) Figure 34-55. ATmega88PA: Supply Current VCC RC Oscillator, 128kHz) CC (Inte rna 0.05 0.045 105C 0.04 ICC (mA) 0.035 85C 0.03 25C -40C 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 425 Figure 34-56. ATmega88PA: Supply VCCnt(Internal RC Oscillator, ATmeIdle ga 88P A: IdleCurrent S upplyvs. Curre vs . VCC (Inte rna l RC Os1MHz) cilla tor, 1MHz) 0.4 105C 0.35 85C 25C 0.25 -40C ICC (mA) 0.3 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATme ga 88P Idle SCurrent upply Curre vs(Internal . VCC (InteRC rnaOscillator, l RC Os cilla tor, 8MHz) Figure 34-57. ATmega88PA: Idle A: Supply vs. nt VCC 8MHz) 1.2 105C 85C 25C 1 -40C ICC (mA) 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.2.3. Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" for details. Table 34-3. ATmega88PA: Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers (A) VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART0 3.0 21.3 97.9 PRTWI 6.1 45.4 219.0 PRTIM2 5.2 35.2 149.5 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 426 PRR bit Typical numbers (A) VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRTIM1 3.8 25.6 110.0 PRTIM0 1.5 9.8 39.6 PRSPI 5.2 40.0 199.6 PRADC 6.3 48.7 247.0 Table 34-4. ATmega88PA: Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 34-48 and Figure 34-49) Additional Current consumption compared to Idle with external clock (see Figure 34-53 and Figure 34-54) PRUSART0 1.8% 11.4% PRTWI 3.9% 24.4% PRTIM2 2.9% 18.6% PRTIM1 2.1% 13.6% PRTIM0 0.8% 5.2% PRSPI 3.3% 21.5% PRADC 4.2% 26.3% It is possible to calculate the typical current consumption based on the numbers from the above table for other VCC and frequency settings. Related Links PRR on page 73 34.2.3.1. Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table Additional Current Consumption (percentage) in Active and Idle mode in the previous section, third column, we see that we need to add 13.6% for the TIMER1, 26.3% for the ADC, and 21.5% for the SPI module. Reading from Figure Idle Supply Current vs. Low Frequency (0.1-1.0MHz), we find that the idle current consumption is ~0.027mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: Icctotal 0.027 mA(1 + 0.136 + 0.263 + 0.215) 0.043 mA Related Links PRR on page 73 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 427 Power-down Supply Current Figure 34-58. ATmega88PA: Supply Current (Watchdog Timer ATme ga 88PPower-Down A: P owe r-Down S upply Curre vs. nt vsV.CC VCC (Wa tchdog TimeDisabled) r Dis a ble d) 5 105C ICC (A) 4 3 2 85C 1 25C -40C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-59. ATmega88PA: Power-Down Supply Current vs. (Watchdog Timer Enabled) ATme ga 88P A: P owe r-Down S upply Curre ntVvs Time r Ena ble d) CC. V CC (Wa tchdog 12 10 105C 8 ICC (A) 34.2.4. -40C 6 25C 4 85C 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 428 34.2.5. Power-save Supply Current Figure 34-60. ATmega88PA: Power-Save Current Timer Disabled and 32kHz ATme ga 88P A: P owe r-S Supply a ve S upply Currevs. nt V vsCC . V(Watchdog CC (Wa tchdog Time r Dis a ble d Crystal Oscillator aRunning) nd 32kHz Crys ta l Os cilla tor Running) 6 105C ICC (A) 4 85C 2 25C -40C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 34-61. Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.18 6MHz_re s 6MHz_xta l 0.16 0.14 0.12 ICC (mA) 34.2.6. 4MHz_re s 4MHz_xta l 0.1 0.08 2MHz_re s 2MHz_xta l 0.06 450kHz_re s 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 429 Pin Pull-Up ATme ga 88P A:Pin I/O Pull-up P in P ull-up Re s isCurrent tor Currevs. nt vs . Input Volta ge (V=CC1.8V) = 1.8V) Figure 34-62. ATmega88PA: I/O Resistor Input Voltage (VCC 60 50 IOP (A) 40 30 20 25C 10 -40C 0 85C 105C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) ATme ga 88P I/OPull-up P in P ull-up Re s isCurrent tor Currevs. nt Input vs . Input Volta(V geCC(V=CC2.7V) = 2.7V) Figure 34-63. ATmega88PA: I/OA:Pin Resistor Voltage 80 70 60 50 IOP (A) 34.2.7. 40 30 25C 20 -40C 85C 105C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 430 Figure 34-64. ATmega88PA: I/OA:Pin Resistor vs. Voltage 5V) ATme ga 88P I/OPull-up P in P ull-up Re s isCurrent tor Curre nt Input vs . Input Volta(V geCC(V=CC = 5V) 160 140 120 IOP (A) 100 80 60 25C 40 -40C 85C 105C 20 0 0 1 2 3 4 5 6 VOP (V) Figure 34-65. ATmega88PA: = 1.8V) ATme ga 88P A:Reset Re s ePull-up t P ull-upResistor Re s is torCurrent Curre ntvs. vs . Reset Re s e t Pin P in Voltage Volta ge (V (VCC CC = 1.8V) 40 35 IRES ET (A) 30 25 20 15 25C -40C 85C 105C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRES ET (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 431 Figure 34-66. ATmega88PA: Reset Resistor = 2.7V) ATme ga 88P A: Re s ePull-up t P ull-up Re s is torCurrent Curre ntvs. vs .Reset Re s e tPin P inVoltage Volta ge(V (V CC CC = 2.7V) 60 50 IRES ET (A) 40 30 20 25C -40C 85C 105C 10 0 0 0.5 1 1.5 2 2.5 3 VRES ET (V) Figure 34-67. ATmega88PA: Resistor Current (VCC = 5V) ATme ga 88PReset A: Re Pull-up s e t P ull-up Re s is tor Currevs. nt vsReset . Re s Pin e t P Voltage in Volta ge (VCC = 5V) 120 100 IRES ET (A) 80 60 40 25C -40C 85C 105C 20 0 0 1 2 3 4 5 6 VRES ET (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 432 Pin Driver Strength ATme ga 88P A: I/O P in Output Volta ge vs . S ink Curre nt (V = 3V) Figure 34-68. ATmega88PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) CC 1.2 1 105C 85C VOL (V) 0.8 25C 0.6 -40C 0.4 0.2 0 0 5 10 15 20 25 IOL (mA) Figure 34-69. ATmega88PA: I/Oga Pin Output vs. Volta Sink ge Current (VCC = 5V) ATme 88P A: I/O Voltage P in Output vs . S ink Curre nt (VCC = 5V) 0.7 0.6 105C 85C 0.5 VOL (V) 34.2.8. 25C 0.4 -40C 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 433 Figure 34-70. ATmega88PA: I/O Pin Output vs. Source (VccCurre = 3V)nt (Vcc = 3V) ATme ga 88P A: I/OVoltage P in Output Volta geCurrent vs . S ource 3.5 VOH (V) 3 2.5 -40C 25C 85C 105C 2 1.5 0 5 10 15 20 25 IOH (mA) Figure 34-71. ATmega88PA: Output VoltageVolta vs. ge Source (VCCnt=(V 5V) ATme ga I/O 88PPin A: I/O P in Output vs . S Current ource Curre CC = 5V) 5.2 5 VOH (V) 4.8 4.6 -40C 25C 4.4 85C 105C 4.2 0 5 10 15 20 25 IOH (mA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 434 Pin Threshold and Hysteresis Figure 34-72. ATmega88PA: Threshold Voltage VCC , I/O Pin Pread ATme ga 88PI/O A: Pin I/O Input P in Input Thre s hold Voltavs. ge vs . V(V in reas a d `1') a s `1') CCIH(V IH, I/O 3.5 105C 85C 25C -40C 3 Thre s hold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-73. ATmega88PA: PinPInput Threshold Voltage vs.vsV.CC (VIL PinP in read ATme ga 88P I/O A: I/O in Input Thre s hold Volta ge VCC (V, ILI/O , I/O re aas d a`0' s `0') 2.5 105C 85C 25C -40C 2 Thre s hold (V) 34.2.9. 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 435 Figure 34-74. ATmega88PA: I/O Pin Input Hysteresis VCC ATme ga 88P A: I/O P in Inputvs. Hys te re s is vs . VCC 0.7 Input Hys te re s is (mV) 0.6 -40C 0.5 25C 0.4 85C 0.3 105C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATme ga 88P A: Re s e t Input Thre s hold Volta geVvs . V IH, (V I/Oread P in re a s `1') Figure 34-75. ATmega88PA: Reset Input Threshold Voltage vs. I/O asa d`1') IH,Pin CC (VCC 2.5 Thre s hold (V) 2 1.5 1 -40C 25C 85C 105C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 436 ATme ga 88P A: Re s e t Input Thre s Voltage hold Volta geVvs . (V VCC, I/O (VILPin , I/Oread P in re d a s `0') Figure 34-76. ATmega88PA: Reset Input Threshold vs. asa `0') CC IL 2.5 105C 85C 25C -40C Thre s hold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-77. Reset Pin Input Hysteresis ATme ga 88P A: vs. Re sVeCC t P in Input Hys te re s is vs . VCC 0.7 Input Hys te re s is (mV) 0.6 -40C 0.5 25C 0.4 0.3 85C 0.2 105C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 437 34.2.10. BOD Threshold Figure 34-78. ATmega88PA: Thresholds Temperature is 1.8V)is 1.8V) ATme gaBOD 88P A: BOD Threvs. s holds vs . Te mpe(BODLEVEL ra ture (BODLEVEL 1.84 1.83 Ris ing Vcc Thre s hold (V) 1.82 1.81 1.8 1.79 1.78 Fa lling Vcc 1.77 1.76 -60 -40 -20 0 20 40 60 80 100 120 Te mpe ra ture (C) ATme ga 88P A: BOD Thre holds vs . Te mpe ra ture (BODLEVEL Figure 34-79. ATmega88PA: BOD Thresholds vs. sTemperature (BODLEVEL is 2.7V) is 2.7V) 2.8 Ris ing Vcc 2.78 2.76 Thre s hold (V) 2.74 2.72 2.7 2.68 Fa lling Vcc 2.66 2.64 2.62 2.6 -60 -40 -20 0 20 40 60 80 100 120 Te mpe ra ture (C) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 438 ATme ga 88P A: BOD Thre s holds vs . Te(BODLEVEL mpe ra ture (BODLEVEL is 4.3V) Figure 34-80. ATmega88PA: BOD Thresholds vs. Temperature is 4.3V) 4.5 4.45 4.4 Ris ing Vcc Thre s hold (V) 4.35 4.3 4.25 Fa lling Vcc 4.2 4.15 4.1 4.05 4 -60 -40 -20 0 20 40 60 80 100 120 Te mpe ra ture (C) Figure 34-81. ATmega88PA: Calibrated Bandgap Voltage vs. Temperature 1.09 1.8V 2.7V 3.3V 4.0V 4.5V 5.5V 1.085 Bandgap Voltage [V] 1.08 1.075 1.07 1.065 1.06 1.055 1.05 1.045 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature [V] Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 439 Figure 34-82. ATmega88PA: Bandgap Voltage vs. VCC 1.09 1.085 105C 85C Bandgap Voltage [V] 1.08 1.075 25C 1.07 1.065 1.06 1.055 -40C 1.05 1.045 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] 34.2.11. Internal Oscillator Speed ATme ga 88P A:Oscillator Wa tchdogFrequency Os cilla tor vs. Fre que ncy vs . Te mpe ra ture Figure 34-83. ATmega88PA: Watchdog Temperature 116 114 F RC (kHz) 112 110 108 2.7V 3.3V 4.0V 106 104 5.5V 102 -40 -20 0 20 40 60 80 100 120 Te mpe ra ture (C) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 440 ATme ga 88P A: Wa tchdog OsFrequency cilla tor Fre vs. queV ncy Figure 34-84. ATmega88PA: Watchdog Oscillator CC vs . VCC 116 114 -40C F RC (kHz) 112 25C 110 108 106 85C 104 105C 102 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-85. ATmega88PA: MHzteRC Oscillator ATme Calibrated ga 88P A: Ca8libra d 8MHz RC OsFrequency cilla tor Fre vs. queV ncy CC vs . VCC 8.5 105C 85C F RC (MHz) 8.25 25C 8 -40C 7.75 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 441 Figure 34-86. ATmega88PA: 8MHz Oscillator Frequency vs.ncy Temperature ATme gaCalibrated 88P A: Ca libra te dRC 8MHz RC Os cilla tor Fre que vs . Te mpe ra ture 8.4 5.5V 4.0V 3.0V 8.3 8.2 1.8V F RC (MHz) 8.1 8 7.9 7.8 7.7 7.6 -60 -40 -20 0 20 40 60 80 100 120 Te mpe ra ture (C) Figure 34-87. ATmega88PA: Calibrated RC Oscillator Frequency ValueVa lue ATme ga 88P A: Ca libra8MHz te d 8MHz RC Os cilla tor Fre quevs. ncyOSCCAL vs . OS CCAL F RC (MHz) 14 12 105C 85C 10 25C -40C 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 442 34.2.12. Current Consumption of Peripheral Units ATmeADC ga 88P A: ADCvs. Curre vs . VCC (AREF Figure 34-88. ATmega88PA: Current VCCnt (AREF = AV CC) = AVCC ) 350 -40C 300 25C 85C 105C ICC (A) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATme ga 88P A: Ana log Compa ra tor Curre nt vs . VCC Figure 34-89. ATmega88PA: Analog Comparator Current vs. VCC 90 80 70 ICC (A) 60 105C 50 40 30 85C 25C -40C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 443 ATme ga 88P A: AREF Reference Exte rna l ReCurrent fe re nce vs. Curre nt vs . VCC Figure 34-90. ATmega88PA: AREF External VCC 160 105C 85C 25C -40C 140 120 ICC (A) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ATme ga 88PCurrent A: Brownout De te ctor Curre nt vs . VCC Figure 34-91. ATmega88PA: Brownout Detector vs. VCC 30 25 ICC (A) 20 15 105C 85C 25C -40C 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 444 ATme ga 88P A: P rogra Curre nt vs . VCC Figure 34-92. ATmega88PA: Programming Current vs. Vmming CC 10 9 8 -40C ICC (mA) 7 6 5 25C 4 85C 3 105C 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.2.13. Current Consumption in Reset and Reset Pulsewidth Figure 34-93. ATmega88PA: Reset Supply Current vs.ntLow Frequency - 1.0MHz) ATme ga 88P A: Re s e t S upply Curre vs . Low Fre que (0.1MHz ncy (0.1MHz - 1.0MHz) 0.12 5.5V 0.1 5.0V ICC (mA) 0.08 4.5V 4.0V 0.06 3.3V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 445 ATme ga 88P A: Re s e t S upply Curre nt vs . Fre que ncy (1MHz - 20MHz) Figure 34-94. ATmega88PA: Reset Supply Current vs. Frequency (1MHz - 20MHz) 2.5 5.5V 2 ICC (mA) 5.0V 1.5 4.5V 4.0V 1 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) ATme Minimum ga 88P A: Minimum Re s Width e t P ulsvs. e width Figure 34-95. ATmega88PA: Reset Pulse Vcc vs . VCC 1800 1600 P uls e width (ns ) 1400 1200 1000 800 600 105C 85C 25C -40C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 446 Active Supply Current Figure 34-96. ATmega168PA: Active Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 1 5.5V 0.9 ICC (mA) 34.3.1. ATmega168PA Typical Characteristics 0.8 5.0V 0.7 4.5V 0.6 4.0V 0.5 0.4 3.3V 0.3 2.7V 0.2 1.8V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Figure 34-97. ATmega168PA: Active Supply Current vs. Frequency (1MHz - 20MHz) 12 5.5V 10 5.0V 4.5V 8 ICC (mA) 34.3. 6 4.0V 3.6V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 447 Figure 34-98. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.14 105C -40C 85C 25C 0.12 ICC (mA) 0.1 0.08 0.06 0.04 0.02 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-99. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.2 105C 85C 25C -40C 1.1 1 ICC (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 448 Figure 34-100. ATmega168PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 5.5 105C 85C 25C -40C 5 4.5 ICC (mA) 4 3.5 3 2.5 2 1.5 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 34-101. ATmega168PA: Idle Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 0.16 5.5V 0.14 5.0V 0.12 ICC (mA) 34.3.2. 0.1 4.5V 0.08 4.0V 3.6V 0.06 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 449 Figure 34-102. ATmega168PA: Idle Supply Current vs. Frequency (1MHz - 20MHz) 12 5.5V 10 5.0V 4.5V ICC (mA) 8 6 4.0V 3.6V 4 2.7V 2 1.8V 0 0 2 4 8 6 10 12 14 16 18 20 Fre que ncy (MHz) Figure 34-103. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz) 0.045 105C 0.04 85C 0.035 ICC (mA) 0.03 25C -40C 0.025 0.02 0.015 0.01 0.005 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 450 Figure 34-104. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.3 105C 85C 25C -40C 0.27 0.24 ICC (mA) 0.21 0.18 0.15 0.12 0.09 0.06 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-105. ATmega168PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 1.3 105C 85C 25C -40C 1.1 ICC (mA) 0.9 0.7 0.5 0.3 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.3.3. Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See "Power Reduction Register" for details. Table 34-5. ATmega168PA: Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers (A) VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRUSART0 2.86 20.3 52.2 PRTWI 6.00 44.1 122.0 PRTIM2 4.97 33.2 79.8 PRTIM1 3.50 23.0 55.3 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 451 PRR bit Typical numbers (A) VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRTIM0 1.43 9.2 21.4 PRSPI 5.01 38.6 111.4 PRADC 6.34 45.7 123.6 Table 34-6. ATmega168PA: Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 34-96 and Figure 34-97) Additional Current consumption compared to Idle with external clock (see Figure 34-101 and Figure 34-102) PRUSART0 1.5% 8.9% PRTWI 3.2% 19.5% PRTIM2 2.4% 14.8% PRTIM1 1.7% 10.3% PRTIM0 0.7% 4.1% PRSPI 2.9% 17.1% PRADC 3.4% 20.3% It is possible to calculate the typical current consumption based on the numbers from the above table for other VCC and frequency settings. Related Links PRR on page 73 34.3.3.1. Example Calculate the expected current consumption in idle mode with TIMER1, ADC, and SPI enabled at VCC = 2.0V and F = 1MHz. From Table Additional Current Consumption (percentage) in Active and Idle mode in the previous section, third column, we see that we need to add 10.3% for the TIMER1, 20.3% for the ADC, and 17.1% for the SPI module. Reading from Figure Idle Supply Current vs. Low Frequency (0.1-1.0MHz), we find that the idle current consumption is ~0.027mA at VCC = 2.0V and F = 1MHz. The total current consumption in idle mode with TIMER1, ADC, and SPI enabled, gives: ICCtotal 0.027 mA(1 + 0.103 + 0.203 + 0.171) 0.040 mA Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 452 Power-down Supply Current Figure 34-106. ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 2.4 105C 2.1 1.8 ICC (A) 1.5 1.2 0.9 85C 0.6 0.3 25C -40C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-107. ATmega168PA: Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 9 105C 8 -40C 85C 25C 7 ICC (A) 34.3.4. 6 5 4 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 453 34.3.5. Power-save Supply Current Figure 34-108. ATmega168PA: Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 4 105C 3.5 ICC (A) 3 2.5 85C 2 1.5 -40C 25C 1 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Standby Supply Current Figure 34-109. ATmega168PA: Standby Supply Current vs. Vcc (Watchdog Timer Disabled) 0.15 6 M H z _r es 6 MHz_xta l 0.14 0.13 0.12 4 M H z _r es 4 MHz_xta l 0.11 0.1 ICC (mA) 34.3.6. 0.09 2 M H z _r es 2 MHz_xta l 0.08 0.07 1 MHz_re s 0.06 0.05 0.04 0.03 0.02 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 454 Pin Pull-Up Figure 34-110. ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (A) 35 30 25 20 15 25C -40C 85C 105C 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 34-111. ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (A) 50 40 30 25C 85C -40C 105C 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 34-112. ATmega168PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 100 IOP (A) 34.3.7. 80 60 40 25C 85C -40C 105C 20 0 0 1 2 3 4 5 VOP (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 455 Figure 34-113. ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRES ET (A) 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRES ET (V) Figure 34-114. ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRES ET (A) 40 30 20 10 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRES ET (V) Figure 34-115. ATmega168PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRES ET (A) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRES ET (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 456 Pin Driver Strength Figure 34-116. ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 3V) 1 105C 85C 0.9 0.8 VOL (V) 0.7 25C 0.6 -40C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 34-117. ATmega168PA: I/O Pin Output Voltage vs. Sink Current (VCC = 5V) 0.6 105C 85C 0.5 25C -40C 0.4 VOL (V) 34.3.8. 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 457 Figure 34-118. ATmega168PA: I/O Pin Output Voltage vs. Source Current (Vcc = 3V) 3.1 2.9 VOH (V) 2.7 2.5 -40C 2.3 25C 2.1 85C 105C 1.9 1.7 0 5 10 15 20 IOH (mA) Figure 34-119. ATmega168PA: I/O Pin Output Voltage vs. Source Current (VCC = 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -40C 4.5 25C 85C 105C 4.4 4.3 0 5 10 15 20 IOH (mA) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 458 Pin Threshold and Hysteresis Figure 34-120. ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as `1') 3 105C 85C 25C -40C 2.8 2.6 Thre s hold (V) 2.4 2.2 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-121. ATmega168PA: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as `0') 105C 85C 25C -40C 2.5 2 Thre s hold (V) 34.3.9. 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 459 Figure 34-122. ATmega168PA: I/O Pin Input Hysteresis vs. VCC 85C 105C 0.6 -40C Input Hys te re s is (V) 0.55 0.5 25C 0.45 0.4 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-123. ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as `1') 1.5 -40C 25C 85C 105C 1.4 Thre s hold (V) 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 460 Figure 34-124. ATmega168PA: Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as `0') 2.5 105C 85C 25C -40C 2.3 2.1 Thre s hold (V) 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-125. ATmega168PA: Reset Pin Input Hysteresis vs. VCC 0.7 -40C 0.6 Input Hys te re s is (V) 0.5 25C 0.4 0.3 85C 0.2 105C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 34.3.10. BOD Threshold Figure 34-126. ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 1.8V) 1.83 1.82 Ris ing Vcc Thre s hold (V) 1.81 1.8 1.79 Fa lling Vcc 1.78 1.77 1.76 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Te mpe ra ture (C) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 461 Figure 34-127. ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 2.7V) 2.76 2.74 Ris ing Vcc Thre s hold (V) 2.72 2.7 2.68 Fa lling Vcc 2.66 2.64 2.62 -40 -20 -30 -10 0 10 20 30 40 50 60 70 80 90 100 110 Te mpe ra ture (C) Figure 34-128. ATmega168PA: BOD Thresholds vs. Temperature (BODLEVEL is 4.3V) 4.32 Ris ing Vcc Thre s hold (V) 4.3 4.28 4.26 4.24 Fa lling Vcc 4.22 4.2 -40 -20 -30 -10 0 10 20 30 40 50 60 70 80 90 100 110 Te mpe ra ture (C) Figure 34-129. ATmega168PA: Calibrated Bandgap Voltage vs. Vcc 1.136 1.134 Ba ndga p Volta ge (V) 1.132 1.13 1.128 85C 105C 25C 1.126 1.124 1.122 1.12 1.118 -40C 1.116 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 462 Figure 34-130. ATmega168PA: Calibrated Bandgap Voltage vs. Temperature 1.136 1.8V 2.7V 3.3V 4.0V 4.5V 1.134 Ba ndga p Volta ge (V) 1.132 1.13 1.128 5.5V 1.126 1.124 1.122 1.12 1.118 1.116 -50 -10 -30 10 30 50 70 90 110 Te mpe ra ture (C) 34.3.11. Internal Oscillator Speed Figure 34-131. ATmega168PA: Watchdog Oscillator Frequency vs. Temperature 122 120 F RC (kHz) 118 116 114 2.7V 3.3V 4.0V 4.5V 5.5V 5.0V 112 110 108 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Te mpe ra ture (C) Figure 34-132. ATmega168PA: Watchdog Oscillator Frequency vs. VCC 122 120 -40C F RC (kHz) 118 25C 116 114 112 85C 110 105C 108 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 463 Figure 34-133. ATmega168PA: Calibrated 8 MHz RC Oscillator Frequency vs. VCC 8.5 8.4 105C 85C 8.3 F RC (MHz) 8.2 8.1 25C 8 7.9 7.8 -40C 7.7 7.6 7.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-134. ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.4 5.5V 4.5V 4.0V 3.3V 1.8V 8.3 8.2 F RC (MHz) 8.1 8 7.9 7.8 7.7 7.6 7.5 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Te mpe ra ture (C) Figure 34-135. ATmega168PA: Calibrated 8MHz RC Oscillator Frequency vs. OSCCAL Value 14 105C 85C 25C -40C 12 F RC (MHz) 10 8 6 4 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OS CCAL (X1) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 464 34.3.12. Current Consumption of Peripheral Units Figure 34-136. ATmega168PA: ADC Current vs. VCC (AREF = AVCC) 325 -40C 25C 85C 105C 300 275 ICC (A) 250 225 200 175 150 125 100 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-137. ATmega168PA: Analog Comparator Current vs. VCC 90 -40C 105C 25C 85C 80 ICC (A) 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 465 Figure 34-138. ATmega168PA: AREF External Reference Current vs. VCC 180 25C 85C 105C -40C 160 ICC (A) 140 120 100 80 60 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-139. ATmega168PA: Brownout Detector Current vs. VCC 28 26 105C 85C ICC (A) 24 25C -40C 22 20 18 16 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 34-140. ATmega168PA: Programming Current vs. VCC 9 -40C 25C 8 7 105C 85C ICC (mA) 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 466 34.3.13. Current Consumption in Reset and Reset Pulsewidth Figure 34-141. ATmega168PA: Reset Supply Current vs. Low Frequency (0.1MHz - 1.0MHz) 0.12 5.5V 0.1 ICC (mA) 0.08 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que ncy (MHz) Figure 34-142. ATmega168PA: Reset Supply Current vs. Frequency (1MHz - 20MHz) 2.4 2.1 5.5V 1.8 5.0V 4.5V ICC (mA) 1.5 1.2 4.0V 0.9 3.6V 0.6 2.7V 0.3 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Fre que ncy (MHz) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 467 Figure 34-143. ATmega168PA: Minimum Reset Pulse Width vs. Vcc 1800 1600 P uls e width (ns ) 1400 1200 1000 800 600 105C 85C 25C -40C 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 468 35. Register Summary Offset Name Bit Pos. 0x23 PINB 7:0 0x24 DDRB 7:0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0x25 PORTB 7:0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 0x26 PINC 7:0 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 0x27 DDRC 7:0 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0x28 PORTC 7:0 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 0x29 PIND 7:0 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 0x2A DDRD 7:0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0x2B PORTD 7:0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 OCFB OCFA TOV OCFB OCFA TOV 0x2C ... Reserved 0x34 0x35 TIFR0 7:0 0x36 TIFR1 7:0 0x37 TIFR2 7:0 OCFB OCFA TOV PCIF2 ICF 0x38 ... Reserved 0x3A 0x3B PCIFR 7:0 PCIF1 PCIF0 0x3C EIFR 7:0 INTF1 INTF0 0x3D EIMSK 7:0 INT1 INT0 0x3E GPIOR0 7:0 0x3F EECR 7:0 EEMPE EEPE EERE EEAR2 EEAR1 EEAR0 EEAR9 EEAR8 PSRASY PSRSYNC WGM01 WGM00 GPIOR0[7:0] EEPM1 EEPM0 EEAR5 EEAR4 EERIE 0x40 EEDR 7:0 0x41 EEARL 7:0 EEDR[7:0] 0x42 EEARH 7:0 0x43 GTCCR 7:0 TSM 0x44 TCCR0A 7:0 COM0A1 COM0A0 0x45 TCCR0B 7:0 FOC0A FOC0B 0x46 TCNT0 7:0 TCNT0[7:0] 0x47 OCR0A 7:0 OCR0A[7:0] 0x48 OCR0B 7:0 OCR0B[7:0] 0x49 Reserved 0x4A GPIOR1 7:0 GPIOR1[7:0] EEAR7 EEAR6 0x4B GPIOR2 7:0 0x4C SPCR0 7:0 SPIE0 SPE0 0x4D SPSR0 7:0 SPIF0 WCOL0 0x4E SPDR0 7:0 0x4F Reserved 0x50 ACSR 7:0 0x51 DWDR 7:0 0x52 Reserved COM0B1 EEAR3 COM0B0 WGM02 CS0[2:0] GPIOR2[7:0] DORD0 MSTR0 CPOL0 CPHA0 SPR01 SPR00 SPI2X0 SPID[7:0] ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 DWDR[7:0] 0x53 SMCR 7:0 SM2 SM1 SM0 SE 0x54 MCUSR 7:0 WDRF BORF EXTRF PORF Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 469 Offset Name Bit Pos. 0x55 MCUCR 7:0 0x56 Reserved 0x57 SPMCSR 7:0 SPMIE BODS BODSE PUD RWWSB SIGRD RWWSRE BLBSET PGWRT IVSEL IVCE PGERS SPMEN 0x58 ... Reserved 0x5C 0x5D SPL 7:0 0x5E SPH 7:0 0x5F SREG 7:0 0x60 WDTCSR 0x61 CLKPR (SP[7:0]) SPL (SP[10:8]) SPH I T H S V 7:0 WDIF WDIE WDP[3] WDCE 7:0 CLKPCE 7:0 PRTWI0 PRTIM2 PRTIM0 7:0 CAL7 CAL6 CAL5 N WDE Z C WDP[2:0] CLKPS3 CLKPS2 CLKPS1 CLKPS0 PRTIM1 PRSPI0 PRUSART0 PRADC CAL3 CAL2 CAL1 CAL0 PCIE2 PCIE1 PCIE0 ISC10 ISC01 ISC00 0x62 ... Reserved 0x63 0x64 PRR 0x65 Reserved 0x66 OSCCAL 0x67 Reserved 0x68 PCICR 7:0 0x69 EICRA 7:0 0x6A Reserved 0x6B PCMSK0 7:0 0x6C PCMSK1 7:0 0x6D PCMSK2 7:0 0x6E TIMSK0 7:0 0x6F TIMSK1 7:0 0x70 TIMSK2 7:0 CAL4 ISC11 PCINT7 PCINT23 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 OCIEB OCIEA TOIE OCIEB OCIEA TOIE OCIEB OCIEA TOIE ADC0 ICIE 0x71 ... Reserved 0x77 0x78 ADCL 7:0 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC9 ADC8 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0 MUX3 MUX2 MUX1 MUX0 ADC3D ADC2D ADC1D ADC0D 0x79 ADCH 7:0 0x7A ADCSRA 7:0 0x7B ADCSRB 7:0 0x7C ADMUX 7:0 REFS1 REFS0 ADLAR 0x7D Reserved 0x7E DIDR0 7:0 ADC7D ADC6D ADC5D ADC4D 0x7F DIDR1 7:0 0x80 TCCR1A 7:0 COM1 COM1 COM1 COM1 0x81 TCCR1B 7:0 ICNC1 ICES1 0x82 TCCR1C 7:0 FOC1A FOC1B 0x83 Reserved ACME WGM13 WGM12 0x84 TCNT1L 7:0 TCNT1L[7:0] 0x85 TCNT1H 7:0 TCNT1H[7:0] 0x86 ICR1L 7:0 ICR1L[7:0] 0x87 ICR1H 7:0 ICR1H[7:0] 0x88 OCR1AL 7:0 OCR1AL[7:0] CS12 AIN1D AIN0D WGM11 WGM10 CS11 CS10 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 470 Offset Name Bit Pos. 0x89 OCR1AH 7:0 0x8A OCR1BL 7:0 OCR1AH[7:0] OCR1BL[7:0] 0x8B OCR1BH 7:0 OCR1BH[7:0] 0x8C ... Reserved 0xAF 0xB0 TCCR2A 7:0 COM2A1 COM2A0 0xB1 TCCR2B 7:0 FOC2A FOC2B 0xB2 TCNT2 7:0 TCNT2[7:0] 0xB3 OCR2A 7:0 OCR2A[7:0] 0xB4 OCR2B 7:0 OCR2B[7:0] 0xB5 Reserved 0xB6 ASSR 0xB7 Reserved 7:0 0xB8 TWBR 7:0 0xB9 TWSR 7:0 0xBA TWAR 7:0 COM2B1 COM2B0 WGM21 WGM22 WGM20 CS2[2:0] EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWS4 TWS3 TWS2 TWS1 TWS0 TWA6 TWA5 TWA4 TWA3 TWA2 TWPS1 TWPS0 TWA1 TWA0 TWGCE TWD1 TWD0 0xBB TWDR 7:0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 0xBC TWCR 7:0 TWINT TWEA TWSTA TWSTO TWWC TWEN 0xBD TWAMR 7:0 TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWIE TWAM0 0xBE ... Reserved 0xBF 0xC0 UCSR0A 7:0 RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 0xC1 UCSR0B 7:0 RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 0xC2 UCSR0C 7:0 UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 / UCSZ00 / UDORD0 UCPHA0 0xC3 Reserved 0xC4 UBRR0L 7:0 0xC5 UBRR0H 7:0 0xC6 UDR0 7:0 35.1. UCPOL0 UBRR0[7:0] UBRR0[3:0] TXB / RXB[7:0] Note 1. 2. 3. 4. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega48PA/88PA/168PA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 471 5. OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. SPH.SP10, SPMCSR.RWWSB, SPMCSR.RWWSRE and EEARH registers are only available for ATmega88PA and ATmega168PA. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 472 36. Instruction Set Summary ARITHMETIC AND LOGIC INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks ADD Rd, Rr Add two Registers without Carry Rd Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add two Registers with Carry Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract two Registers with Carry Rd Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract Constant from Reg with Carry. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd 0xFF - Rd Z,C,N,V 1 NEG Rd Two's Complement Rd 0x00 - Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * (0xFF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 (Rd x Rr) << 1 Z,C 2 BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks RJMP k Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 IJMP JMP(1) k Direct Jump PC k None 3 RCALL k Relative Subroutine Call PC PC + k + 1 None 3 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 473 BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks Indirect Call to (Z) PC Z None 3 Direct Subroutine Call PC k None 4 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 ICALL CALL(1) k CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b)=1) PC PC + 2 or 3 None 1/2/3 SBIS A, b Skip if Bit in I/O Register is Set if (I/O(A,b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 474 BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0...6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3...0)Rd(7...4),Rd(7...4)Rd(3...0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 SEC Set Carry C1 C 1 CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I0 I 1 SES Set Signed Test Flag S1 S 1 CLS Clear Signed Test Flag S0 S 1 SEV Set Two's Complement Overflow. V1 V 1 CLV Clear Two's Complement Overflow V0 V 1 SET Set T in SREG T1 T 1 CLT Clear T in SREG T0 T 1 SEH Set Half Carry Flag in SREG H1 H 1 CLH Clear Half Carry Flag in SREG H0 H 1 DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks MOV Rd, Rr Move Between Registers Rd Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Increment Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Decrement X X - 1, Rd (X) None 2 LD Rd, Y Load Indirect Rd (Y) None 2 LD Rd, Y+ Load Indirect and Post-Increment Rd (Y), Y Y + 1 None 2 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 475 DATA TRANSFER INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks LD Rd, - Y Load Indirect and Pre-Decrement Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Increment Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Decrement Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Increment (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Decrement X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Increment (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Decrement Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Increment (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Decrement Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (Z) R1:R0 None - SPM IN Rd, A In from I/O Location Rd I/O (A) None 1 OUT A, Rr Out to I/O Location I/O (A) Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 MCU CONTROL INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks NOP No Operation No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 476 37. Packaging Information 37.1. 32-pin 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0~7 L A1 A2 A COMMON DIMENSIONS (Unit of measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 - 0.45 - 0.20 - 0.75 B 0.30 C 0.09 L 0.45 e NOTE Note 2 Note 2 0.80 TYP 2010-10-20 TITLE 32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) DRAWING NO. REV. 32A C Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 477 37.2. 32-pin 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 Pin #1 Notch (0.20 R) NOM MAX 0.80 0.90 1.00 A1 - 0.02 0.05 A2 - 0.65 1.00 A3 E2 K b MIN A SYMBOL P e COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note : JEDEC Standard MO-220, Fig . 2 (Anvil Singulation), VHHD-2 . NOTE 0.50 BSC L 0.30 0.40 0.50 P - - 0 - - 0.60 o 12 K 0.20 - - 03/14/2014 32M1-A , 32-pad, 5 x 5 x 1.0mm Bod y, Lead Pitch 0.50mm , 3.10mm Exposed P ad, Micro Lead Frame P a ckage (MLF) 32M1-A Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 F 478 37.3. 32-pin 32CC1 1 2 3 4 5 6 0.08 A B Pin#1 ID C D SIDEVIEW D E b1 F A1 E A A2 TOP VIEW E1 e 1 2 3 4 5 32-Ob 6 F D1 COMMON DIMENSIONS (Unit of Measure = mm) E D SYMBOL MIN A A1 A2 b b1 D D1 E E1 e - 0.12 C B A A1 BALL CORNER e BOTTOM VIEW Note1: Dimension "b" is measured at the maximum ball dia. in a plane parallel to the seating plane. NOM MAX - 0.60 - - 0.38 REF 0.25 0.30 0.35 0.25 - - 3.90 4.00 4.10 2.50 BSC 3.90 4.00 4.10 2.50 BSC 0.50 BSC NOTE 1 2 Note2: Dimension "b1" is the solderable surface def ned by the opening of the solder resist layer. TITLE 32CC1, 32-ball (6 x 6 Array), 4 x 4 x 0.6 mm Package Drawing Contact: packagedrawings@atmel.com package, ball pitch 0.50 mm, Ultra Thin, Fine-Pitch Ball Grid Array (UFBGA) GPC CAG DRAWING NO. 07/06/10 REV. 32CC1 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 B 479 37.4. 28-pin 28M1 D C 1 2 Pin 1 ID 3 E SIDEVIEW A1 TOP VIEW A K y D2 1 0.45 2 R 0.20 3 E2 b L e 0.4 Ref (4x) BOTTOM VIEW Note: The ter mi na l #1 ID is a Laser -ma r ked Feat ur e . COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A A1 b C D D2 E E2 e L y K 0.80 0.00 0.17 3.95 2.35 3.95 2.35 0.35 0.00 0.20 NOM MAX NOTE 0.90 1.00 0.02 0.05 0.22 0.27 0.20 REF 4.00 4.05 2.40 2.45 4.00 4.05 2.40 2.45 0.45 0.40 0.45 - 0.08 - - 10/24/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 28M1,28-pad,4 x 4 x 1.0mm Body, Lead Pitch 0.45mm, 2.4 x 2.4mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) GPC ZBV DRAWING NO. 28M1 Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 REV. B 480 37.5. 28-pin 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 A1 B (4 PLACES) 0 ~ 15 REF e E C COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). MIN NOM MAX A - - 4.5724 A1 0.508 - - D 34.544 - 34.798 E 7.620 - 8.255 E1 7.112 - 7.493 B 0.381 - 0.533 B1 1.143 - 1.397 B2 0.762 - 1.143 L 3.175 - 3.429 C 0.203 - 0.356 eB - - 10.160 e NOTE Note 1 Note 1 2.540 TYP 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. REV. 28P3 B Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 481 38. Errata 38.1. Errata ATmega48PA The revision letter in this section refers to the revision of the ATmega48PA device. 38.1.1. Rev. D 1 - Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUXes are turned off until the ACME bit is cleared. Fix/Workaround: Clear the MUX3 bit before setting the ACME bit. 2 - TWI Data setup time can be too short When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line. Fix/Workaround: Insert a delay between setting TWDR and TWCR. 38.1.2. Rev. B to C Not sampled. 38.1.3. Rev. A 1 - Power consumption in power save modes Power consumption in power save modes will be higher due to improper control of internal power management. Fix/Workaround: This problem will be corrected in Rev B. 2 - Start-up time for the device Due to implementation of a different NVM structure, the startup sequence for the device will require longer start-up time. Fix/Workaround: There is no fix for this problem. 38.2. Errata ATmega88PA The revision letter in this section refers to the revision of the ATmega88PA device. 38.2.1. Rev. F 1- Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUXes are turned off until the ACME bit is cleared. Fix/Workaround: Clear the MUX3 bit before setting the ACME bit. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 482 2- TWI Data setup time can be too short When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line. Fix/Workaround: Insert a delay between setting TWDR and TWCR. 38.2.2. Rev. B to E Not sampled. 38.2.3. Rev. A 1 - Power consumption in power save modes Power consumption in power save modes will be higher due to improper control of internal power management. Fix/Workaround: This problem will be corrected in Rev B. 2 - Start-up time for the device Due to implementation of a different NVM structure, the startup sequence for the device will require longer start-up time. Fix/Workaround: There is no fix for this problem. 38.3. Errata ATmega168PA The revision letter in this section refers to the revision of the ATmega168PA device. 38.3.1. Rev. E 1 - Analog MUX can be turned off when setting ACME bit If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1' (ADMUX[3:0]=1xxx), all MUXes are turned off until the ACME bit is cleared. Fix/Workaround: Clear the MUX3 bit before setting the ACME bit. 2 - TWI Data setup time can be too short When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line. Fix/Workaround: Insert a delay between setting TWDR and TWCR. 38.3.2. Rev. A to D Not sampled. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 483 39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1. Rev. B - 11/2016 1. 2. Update I/O Multiplexing Errata section updated - ATmega48PA: Removed die revision E to K - * Die revision E to J was not sampled. * Die revision K was not released to production. ATmega88PA: Removed die revision G to K - * Die revision G to J was not sampled. * Die revision K was not released to production. ATmega168PA: Removed die revision F to K * * 39.2. Die revision F to J was not sampled. Die revision K was not released to production. Rev. A - 06/2016 Initial document release. Atmel ATmega48PA/88PA/168PA [DATASHEET] Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 484 Atmel Corporation (c) 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com 2016 Atmel Corporation. / Rev.: Atmel-42734B-ATmega48PA/88PA/168PA_Datasheet_Complete-11/2016 (R) (R) (R) Atmel , Atmel logo and combinations thereof, Enabling Unlimited Possibilities , AVR , and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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