LMC6442
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SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013
LMC6442 Dual Micropower Rail-to-Rail Output Single Supply Operational Amplifier
Check for Samples: LMC6442
1FEATURES DESCRIPTION
The LMC6442 is ideal for battery powered systems,
2• (Typical, VS= 2.2V) where very low supply current (less than one
• Output Swing to Within 30 mV of Supply Rail microamp per amplifier) and Rail-to-Rail output swing
• High Voltage Gain 103 dB is required. It is characterized for 2.2V to 10V
operation, and at 2.2V supply, the LMC6442 is ideal
• Gain Bandwidth Product 9.5 KHz for single (Li-Ion) or two cell (NiCad or alkaline)
• Ensured for: 2.2V, 5V, 10V battery systems.
• Low Supply Current 0.95 µA/Amplifier The LMC6442 is designed for battery powered
• Input Voltage Range −0.3V to V+-0.9V systems that require long service life through low
• 2.1 µW/Amplifier Power Consumption supply current, such as smoke and gas detectors,
and pager or personal communications systems.
• Stable for AV≥+2 or AV≤ −1Operation from single supply is enhanced by the wide
APPLICATIONS common mode input voltage range which includes the
ground (or negative supply) for ground sensing
• Portable Instruments applications. Very low (5 fA, typical) input bias current
• Smoke/Gas/CO/Fire Detectors and near constant supply current over supply voltage
• Pagers/Cell Phones enhance the LMC6442's performance near the end-
of-life battery voltage.
• Instrumentation
• Thermostats Designed for closed loop gains of greater than plus
two (or minus one), the amplifier has typically 9.5
• Occupancy Sensors KHz GBWP (Gain Bandwidth Product). Unity gain can
• Cameras be used with a simple compensation circuit, which
• Active Badges also allows capacitive loads of up to 300 pF to be
driven, as described in the Application Information
section.
Connection Diagram
Top View
Figure 1. 8-Pin SOIC / PDIP Package
See Package Numbers D0008A, P0008E
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1997–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMC6442
SNOS013E –SEPTEMBER 1997–REVISED MARCH 2013
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Absolute Maximum Ratings (1)(2)
ESD Tolerance (3) 2 kV
Differential Input Voltage ±Supply Voltages
Voltage at Input/Output Pin (V+) + 0.3V, (V−)−0.3V
Supply Voltage (V+−V−): 16V
Current at Input Pin (4) ±5 mA
Current at Output Pin(5) (6) ±30 mA
Lead Temp. (soldering 10 sec) 260°C
Storage Temp. Range: −65°C to +150°C
Junction Temp. (7) 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human body model, 1.5 kΩin series with 100 pF.
(4) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(6) Do not short circuit output to V+, when V+is greater than 13V or reliability will be adversely affected.
(7) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings (1)
Supply Voltage 1.8V ≤VS≤11V
Junction Temperature Range: LMC6442AI, LMC6442I −40°C < TJ< +85°C
Thermal Resistance (θJA) D0008A Package, 8-pin Surface Mount 193°C/W
P0008E Package, 8-pin Molded DIP 115°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
2.2V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.2V, V−= 0V, VCM = VO= V +/2, and RL= 1 MΩto V+/2.
Boldface limits apply at the temperature extremes. LMC6442AI LMC6442I
Parameter Test Conditions Typ (1) Units
Limit (2) Limit (2)
DC Electrical Characteristics
VOS Input Offset Voltage ±3 ±7 mV
−0.75 ±4 ±8 max
TCVOS Temp. coefficient of input 0.4 µV/°C
offset voltage
IBInput Bias Current See (3) pA
0.005 4 4 max
Input Offset Current See (3) pA
IOS 0.0025 2 2 max
CMRR Common Mode Rejection −0.1V ≤VCM ≤0.5V 92 67 67 dB min
Ratio 67 67
CIN Common Mode Input 4.7 pF
Capacitance
PSRR Power Supply Rejection VS= 2.5 V to 10V 75 75 dB
95
Ratio 75 75 min
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis unless otherwise specified.
(3) Limits specified by design.
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2.2V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.2V, V−= 0V, VCM = VO= V +/2, and RL= 1 MΩto V+/2.
Boldface limits apply at the temperature extremes. LMC6442AI LMC6442I
Parameter Test Conditions Typ (1) Units
Limit (2) Limit (2)
VCM Input Common-Mode 1.05 1.05 V
1.3
Voltage Range 0.95 0.95 min
CMRR ≥50 dB −0.3 −0.2 −0.2 V
0 0 max
AVLarge Signal Voltage Gain Sourcing (4) 100 dB
Sinking (4) 94 min
VO= 0.22V to 2V 103 80 80
VOOutput Swing VID = 100 mV (5) 2.15 2.15 V
2.18 2.15 2.15 min
VID =−100 mV (5) 22 60 60 mV
60 60 max
ISC Output Short Circuit Sourcing, VID = 100 mV (6) (5) 50 18 18
Current 17 17 µA
min
Sinking, VID =−100 mV (6) (5) 50 20 20
19 19
ISSupply Current RL= open 1.90 2.4 2.6 µA
(2 amplifiers) 3.0 3.2 max
V+= 1.8V, RL= open 2.10
AC Electrical Characteristics
SR Slew Rate (7) 2.2 V/ms
GBWP Gain-Bandwidth Product 9.5 KHz
φmPhase Margin See (8) 63 deg
(4) RLconnected to V+/2. For Sourcing Test, VO> V+/2. For Sinking tests, VO< V+/2.
(5) VID is differential input voltage referenced to inverting input.
(6) Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.
(7) Slew rate is the slower of the rising and falling slew rates.
(8) See the Typical Performance Characteristics and Applications Information sections for more details.
5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V +/2, and RL= 1 MΩto V+/2.
Boldface limits apply at the temperature extremes. LMC6442AI LMC6442I
Parameter Test Conditions Typ (1) Units
Limit (2) Limit (2)
DC Electrical Characteristics
VOS Input Offset Voltage ±3 ±7 mV
−0.75 ±4 ±8 max
TCVOS Temp. coefficient of input 0.4 µV/°C
offset voltage
IBInput Bias Current See (3) pA
0.005 4 4 max
Input Offset Current See (3) pA
IOS 0.0025 2 2 max
CMRR Common Mode Rejection −0.1V ≤VCM ≤3.5V 102 70 70 dB min
Ratio 70 70
CIN Common Mode Input 4.1 pF
Capacitance
PSRR Power Supply Rejection VS= 2.5 V to 10V 75 75 dB
95
Ratio 75 75 min
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis unless otherwise specified.
(3) Limits specified by design.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V +/2, and RL= 1 MΩto V+/2.
Boldface limits apply at the temperature extremes. LMC6442AI LMC6442I
Parameter Test Conditions Typ (1) Units
Limit (2) Limit (2)
VCM Input Common-Mode 3.85 3.85 V
4.1
Voltage Range 3.75 3.75 min
CMRR ≥50 dB −0.4 −0.2 −0.2 V
0 0 max
AVLarge Signal Voltage Gain Sourcing (4) 100 dB
Sinking (4) 94 min
VO= 0.5V to 4.5V 103 80 80
VOOutput Swing VID = 100 mV (5) 4.99 4.95 4.95 V
4.95 4.95 min
VID =−100 mV (5) 20 50 50 mV
50 50 max
ISC Output Short Circuit Current Sourcing, VID = 100 mV (6) (5) 500 300 300
200 200 µA
min
Sinking, VID =−100 mV (6) (5) 350 200 200
150 150
ISSupply Current RL= open 1.90 2.4 2.6 µA
(2 amplifiers) 3.0 3.2 max
AC Electrical Characteristics
SR Slew Rate (7) 4.1 2.5 2.5 V/ms
GBWP Gain-Bandwidth Product 10 KHz
φmPhase Margin See (8) 64 deg
THD Total Harmonic Distortion AV= +2, f = 100 Hz, 0.08 %
RL= 10 MΩ, VOUT = 1 VPP
(4) RLconnected to V+/2. For Sourcing Test, VO> V+/2. For Sinking tests, VO< V+/2.
(5) VID is differential input voltage referenced to inverting input.
(6) Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.
(7) Slew rate is the slower of the rising and falling slew rates.
(8) See the Typical Performance Characteristics and Applications Information sections for more details.
10V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 10V, V−= 0V, VCM = VO= V +/2, and RL= 1 MΩto V+/2.
Boldface limits apply at the temperature extremes. LMC6442AI LMC6442I
Parameter Test Conditions Typ (1) Units
Limit (2) Limit (2)
DC Electrical Characteristics
VOS Input Offset Voltage ±3 ±7 mV
−1.5 ±4 ±8 max
TCVOS Temp. coefficient of input 0.4 µV/°C
offset voltage
IBInput Bias Current See(3) pA
0.005 4 4 max
Input Offset Current See (3) pA
IOS 0.0025 2 2 max
CMRR Common Mode Rejection −0.1V ≤VCM ≤8.5V 105 70 70 dB min
Ratio 70 70
CIN Common Mode Input 3.5 pF
Capacitance
PSRR Power Supply Rejection VS= 2.5 V to 10V 75 75 dB
95
Ratio 75 75 min
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis unless otherwise specified.
(3) Limits specified by design.
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10V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 10V, V−= 0V, VCM = VO= V +/2, and RL= 1 MΩto V+/2.
Boldface limits apply at the temperature extremes. LMC6442AI LMC6442I
Parameter Test Conditions Typ (1) Units
Limit (2) Limit (2)
VCM Input Common-Mode 8.85 8.85 V
9.1
Voltage Range 8.75 8.75 min
CMRR ≥50 dB −0.4 −0.2 −0.2 V
0 0 max
AVLarge Signal Voltage Gain Sourcing (4) 120 dB
Sinking (4) 100 min
VO= 0.5V to 9.5V 104 80 80
VOOutput Swing VID = 100 mV (5) 9.99 9.97 9.97 V
9.97 9.97 min
VID =−100 mV (5) 22 50 50 mV
50 50 max
ISC Output Short Circuit Sourcing, VID = 100 mV (6) (5) 2100 1200 1200
Current 1000 1000 µA
min
Sinking, VID =−100 mV (6) (5) 900 600 600
500 500
ISSupply Current RL= open 1.90 2.4 2.6 µA
(2 amplifiers) 3.0 3.2 max
AC Electrical Characteristics
SR Slew Rate(7) 4.1 2.5 2.5 V/ms
GBWP Gain-Bandwidth Product 10.5 KHz
φmPhase Margin See (8) 68 deg
enInput-Referred Voltage RL= open 170 nV/√Hz
Noise f = 10 Hz
inInput-Referred Current RL= open 0.0002 pA/√Hz
Noise f = 10 Hz
Crosstalk Rejection See (9) 85 dB
(4) RLconnected to V+/2. For Sourcing Test, VO> V+/2. For Sinking tests, VO< V+/2.
(5) VID is differential input voltage referenced to inverting input.
(6) Output shorted to ground for sourcing, and shorted to V+ for sinking short circuit current test.
(7) Slew rate is the slower of the rising and falling slew rates.
(8) See the Typical Performance Characteristics and Applications Information sections for more details.
(9) Input referred, V+= 10V and RL= 10 MΩconnected to 5V. Each amp excited in turn with 1 KHz to produce about 10 VPP output.
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Typical Performance Characteristics
VS= 5V, Single Supply, TA= 25°C unless otherwise specified
Total Supply Current Total Supply Current
vs. vs.
Supply Voltage Supply Voltage (Negative Input Overdrive)
Figure 2. Figure 3.
Total Supply Current Input Bias Current
vs. vs.
Supply Voltage (Positive Input Overdrive) Temperature
Figure 4. Figure .
Offset Voltage Offset Voltage
vs. vs.
Common Mode Voltage (VS= 2.2V) Common Mode Voltage (VS= 5V)
Figure 5. Figure 6.
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Typical Performance Characteristics (continued)
VS= 5V, Single Supply, TA= 25°C unless otherwise specified
Offset Voltage Swing Towards V−
vs. vs.
Common Mode Voltage (VS= 10V) Supply Voltage
Figure 7. Figure 8.
Swing Towards V+Swing From Rail(s)
vs. vs.
Supply Voltage Temperature
Figure 9. Figure 10.
Output Source Current Output Sink Current
vs. vs.
Output Voltage Output Voltage
Figure 11. Figure 12.
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Typical Performance Characteristics (continued)
VS= 5V, Single Supply, TA= 25°C unless otherwise specified
Maximum Output Voltage Large Signal Voltage Gain
vs. vs.
Load Resistance Supply Voltage
Figure 13. Figure 14.
Open Loop Gain/Phase Open Loop Gain/Phase
vs. vs.
Frequency Frequency For Various CL(ZL= 1 MΩII CL)
Figure 15. Figure 16.
Open Loop Gain/Phase Gain Bandwidth Product
vs. vs.
Frequency For Various CL(ZL= 100 KΩII CL) Supply Voltage
Figure 17. Figure 18.
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Typical Performance Characteristics (continued)
VS= 5V, Single Supply, TA= 25°C unless otherwise specified
Phase Margin (Worst Case) CMRR
vs. vs.
Supply Voltage Frequency
Figure 19. Figure 20.
PSRR Positive Slew Rate
vs. vs.
Frequency Supply Voltage
Figure 21. Figure 22.
Negative Slew Rate Cross-Talk Rejection
vs. vs.
Supply Voltage Frequency
Figure 23. Figure 24.
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Typical Performance Characteristics (continued)
VS= 5V, Single Supply, TA= 25°C unless otherwise specified
Input Voltage Noise Output Impedance
vs. vs.
Frequency Frequency
Figure 25. Figure 26.
THD+N THD+N
vs. vs.
Frequency Amplitude
Figure 27. Figure 28.
Maximum Output Swing
vs. Small Signal Step Response
Frequency (AV= +2) (CL= 12 pF, 100 pF)
Figure 29. Figure 30.
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Typical Performance Characteristics (continued)
VS= 5V, Single Supply, TA= 25°C unless otherwise specified
Large Signal Step Response Small Signal Step Response
(AV= +2) (CL= 100 pF) (AV=−1) (CL= 1MΩII 100 pF, 200 pF)
Figure 31. Figure 32.
Small Signal Step Response Large Signal Step Response
(AV= +1) For Various CL(AV= +1) (CL= 200 pF)
Figure 33. Figure 34.
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APPLICATIONS INFORMATION
USING LMC6442 IN UNITY GAIN APPLICATIONS
LMC6442 is optimized for maximum bandwidth and minimal external components when operating at a minimum
closed loop gain of +2 (or −1). However, it is also possible to operate the device in a unity gain configuration by
adding external compensation as shown in Figure 35:
Figure 35. AV= +1 Operation by adding CCand RC
Using this compensation technique it is possible to drive capacitive loads of up to 300 pF without causing
oscillations (see the Typical Performance Characteristics for step response plots). This compensation can also
be used with other gain settings in order to improve stability, especially when driving capacitive loads (for
optimum performance, RCand CCmay need to be adjusted).
USING “T” NETWORK
Compromises need to be made whenever high gain inverting stages need to achieve a high input impedance as
well. This is especially important in low current applications which tend to deal with high resistance values. Using
a traditional inverting amplifier, gain is inversely proportional to the resistor value tied between the inverting
terminal and input while the input impedance is equal to this value. For example, in order to build an inverting
amplifier with an input impedance of 10MΩand a gain of 100, one needs to come up with a feedback resistor of
1000 MΩ-an expensive task.
An alternate solution is to use a “T” Network in the feedback path, as shown in Figure 36.
Closed loop gain, AVis given by:
(1)
Figure 36. “T” Network Used to Replace High Value Resistor
It must be noted, however, that using this scheme, the realizable bandwidth would be less than the theoretical
maximum. With feedback factor, β, defined as:
(2)
BW(−3 dB) ≈GBWP • β(3)
In this case, assuming a GBWP of about 10 KHz, the expected BW would be around 50 Hz (vs. 100 Hz with the
conventional inverting amplifier).
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Looking at the problem from a different view, with RFdefined by AV•Rin, one could select a value for R in the “T”
Network and then determine R1 based on this selection:
(4)
Figure 37. “T” Network Values for Various Values of R
For convenience, Figure 37 shows R1 vs. RFfor different values of R.
DESIGN CONSIDERATIONS FOR CAPACITIVE LOADS
As with many other opamps, the LMC6442 is more stable at higher closed loop gains when driving a capacitive
load. Figure 38 shows minimum closed loop gain versus load capacitance, to achieve less than 10% overshoot in
the output small signal response. In addition, the LMC6442 is more stable when it provides more output current
to the load and when its output voltage does not swing close to V−.
The LMC6442 is more tolerant to capacitive loads when the equivalent output load resistance is lowered or when
output voltage is 1V or greater from the V−supply. The capacitive load drive capability is also improved by
adding an isolating resistor in series with the load and the output of the device. Figure 39 shows the value of this
resistor for various capacitive loads (AV=−1), while limiting the output to less than 10 % overshoot.
Referring to the Typical Performance Characteristics plot of Phase Margin (Worst Case) vs. Supply Voltage, note
that Phase Margin increases as the equivalent output load resistance is lowered. This plot shows the expected
Phase Margin when the device output is very close to V−, which is the least stable condition of operation.
Comparing this Phase Margin value to the one read off the Open Loop Gain/Phase vs. Frequency plot, one can
predict the improvement in Phase Margin if the output does not swing close to V−. This dependence of Phase
Margin on output voltage is minimized as long as the output load, RL, is about 1MΩor less.
Output Phase Reversal: The LMC6442 is immune against this behavior even when the input voltages exceed
the common mode voltage range.
Output Time Delay: Due to the ultra low power consumption of the device, there could be as long as 2.5 ms of
time delay from when power is applied to when the device output reaches its final value.
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Application Circuits
V+= 5V: IS< 10 µA, f/VC= 4.3 (Hz/V)
Figure 40. Micropower Single Supply Voltage to Frequency Converter
Figure 41. Gain Stage with Current Boosting
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMC6442AIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64
42AIM
LMC6442AIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64
42AIM
LMC6442IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64
42IM
LMC6442IMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green Call TI | SN Level-1-260C-UNLIM -40 to 85 LMC64
42IM
LMC6442IN/NOPB ACTIVE PDIP P 8 40 RoHS & Green Call TI | SN Level-1-NA-UNLIM -40 to 85 LMC6442
IN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMC6442AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6442IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC6442AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6442IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
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