SAB-C504-2E40M - Infineon Technologies AG

Never stop thinking.

Microcontrollers

Data Sheet, May 2000

C504

8-Bit Single-Chip Microcontroller

Edition 200 0-05

Published by Infineon Technologies AG,

St.-Martin -Str asse 53,

D-81541 Mü n ch en , Ger many

Attention pl ease!

The informa tio n herein is given to des c ribe certain components and sh all not be c onsidered as wa rranted

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, desc ript ions and char ts s ta te d herein.

Infineon Technologie s is an approved CEC C manufacturer.

Information

For further information on technology, delivery terms and conditio ns and prices please contact your neares t

Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address

list).

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Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Techno logies Office.

Infineo n Technologie s Compone nts may onl y be used in life- support devices o r syst ems with th e express writte n

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

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be endangered.

Microcontrollers

Data Sheet, May 2000

Never stop thinking.

C504

8-Bit Single-Chip Microcontroller

Enhanced Hooks TechnologyTM is a trademark and patent of Metalink Corporation

licensed to Infineon Technologies.

C504

Revision History: 2000-05

Previous Version: 1996-05

Page Subjects (major changes since last revision)

35 - 40 OTP Memory Operation is added.

41 Table on Version Byte Content is added.

57 - 60 AC Characteristics of Programming Mode is added.

several VCC is replaced by VDD.

several Specification for SAH-C504 is removed

We Listen to Your Comments

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Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

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Data Sheet 1 2000-05

C5048-Bit Single-Chip Microcontroller

C500 Family

C504

• Fully compatible to standard 8051 microcontroller

• Up to 40 MHz external operating frequency

• 16 Kbyte on-chip program memory

– C504-2R: ROM version (with optional ROM protection)

– C504-2E: programmable OTP version

– C504-L: without on-chip program memory

• 256 byte on-chip RAM

•256

byte on-chip XRAM

• Four 8-bit ports

– 2 ports with mixed analog/digital I/O capability

• Three 16-bit timers/counters

– Timer 2 with up/down counter feature

Further features are listed next page.

Figure 1 C504 Functional Units

MCB02589

On-Chip Emulation Support Module

Port 0

Port 1

Port 2

Port 3

RAM

256 x 8

XRAM

256 x 8

C500

8-Bit

USART

ROM/OTP

16 k x 8

Oscillator Watchdog

10-Bit ADC

Timer 2

10-Bit Compare Unit

16-Bit

Capture/Compare

Unit

Watchdog Timer

I/O

4-Bit Analog Inputs

I/O

8-Bit Digital I/O

4-Bit Analog Inputs

Core

C504

Data Sheet 2 2000-05

• Capture/compare unit for PWM signal generation and signal capturing

– 3-channel, 16-bit capture/compare unit

– 1-channel, 10-bit compare unit

• Full duplex serial interface (USART)

• 10-bit A/D Converter with 8 multiplexed inputs

• Twelve interrupt sources with two priority levels

• On-chip emulation support logic (Enhanced Hooks Technology TM)

• Programmable 15-bit Watchdog Timer

• Oscillator Watchdog

• Fast Power On Reset

• Power Saving Modes

– Idle mode

– Power-down mode with wake-up capability through INT0

• M-QFP-44 package

• Temperature ranges: SAB-C504 TA: 0 to 70 °C

SAF-C504 TA: – 40 to 85 °C

SAK-C504 TA: – 40 to 125 °C

(max. operating frequency: 24 MHz)

Ordering Information

The ordering code for Infineon Technologies microcontrollers provides an exact

reference to the required product. This ordering code indentifies:

• The derivative itself, i.e. its function set

• the specified temperature range

• the package and the type of delivery

For the available ordering codes for the C504, please refer to the “Product Information

Microcontrollers” which summarizes all available microcontroller variants.

Note: The ordering codes for the Mask-ROM versions are defined for each product after

verification of the respective ROM code.

C504

Data Sheet 3 2000-05

Figure 2 Logic Symbol

MCL02590

AREF

AGND

XTAL1

XTAL2

RESET

ALE

PSEN

CTRAP

COUT3

C504

Port 0

8-Bit Digital I/O

8-Bit Digital I/O/

Port 1

4-Bit Analog Inputs

Port 2

8-Bit Digital I/O

4-Bit Analog Inputs

Port 3

8-Bit Digital I/O/

C504

Data Sheet 4 2000-05

Figure 3 Pin Configuration (top view)

COUT3

P0.6 / AD6

P0.7 / AD7

P0.5 / AD5

P2.6 / A14

P2.5 / A13

PSEN

P2.7 / A15

ALE

P2.4 / A12

P2.3 / A11

XTAL2

XTAL1

CTRAP

P1.7 / COUT2

P3.2 / AN4 / INT0

P3.3 / AN5 / INT1

RESET

P1.6 / CC2

P1.5 / COUT1

1116

C504-LM

MCP02532

P2.2 / A10

P2.1 / A9

P2.0 / A8

33 31 30 29 28 27 26 25 24 2332

P0.4 / AD4

P3.0 / RxD

P3.4 / AN6 / T0

P3.5 / AN7 / T1

P3.1 / TxD

P1.4 / CC1

AREF

GND

2345 78 109

C504-2RM

P1.1 / AN1 / T2EX

P1.0 / AN0 / T2

P1.3 / AN3 / COUT0

P1.2 / AN2 / CC0

P0.3 / AD3

P0.2 / AD2

P0.1 / AD1

P0.0 / AD0

P3.7 / RD

P3.6 / WR / INT2

C504-2EM

C504

Data Sheet 5 2000-05

Table 1 Pin Definitions and Functions

Symbol Pin Number

(P-MQFP-44) I/O1) Function

P1.0 - P1.7 40 - 44,

1 - 3

I/O Port 1

is an 8-bit bidirectional port. Port 1 pins can be used

for digital input/output. P1.0 - P1.3 can also be used

as analog inputs of the A/D converter. As secondary

digital functions, Port 1 contains the Timer 2 pins

and the Capture/Compare inputs/outputs. Port 1

pins are assigned to be used as analog inputs via

the register P1ANA.

The functions are assigned to the pins of Port 1 as

follows:

P1.0 / AN0 / T2 Analog input channel 0 /

input to Timer 2

P1.1 / AN1 / T2EX Analog input channel 1 /

capture/reload trigger of Timer

2 up-down count

P1.2 / AN2 / CC0 Analog input channel 2 /

input/output of capture/

compare channel 0

P1.3 / AN3 / COUT0 Analog input channel 3 /

output of capture/compare

channel 0

P1.4 / CC1 Input/output of capture/

compare channel 1

P1.5 / COUT1 Output of capture/compare

channel 1

P1.6 / CC2 Input/output of capture/

compare channel 2

P1.7 / COUT2 Output of capture/compare

channel 2

RESET 4 I RESET

A high level on this pin for two machine cycles while

the oscillator is running resets the device. An

internal diffused resistor to VSS permits power-on

reset using only an external capacitor to VDD.

C504

Data Sheet 6 2000-05

P3.0 - P3.7 5, 7 - 13

I/O Port 3

is an 8-bit bidirectional port. P3.0 (R×D) and P3.1

(T×D) operate as defined for the C501. P3.2 to P3.7

contain the external interrupt inputs, timer inputs,

and four of the analog inputs of the A/D converter.

Port 3 pins are assigned to be used as analog inputs

via the bits of SFR P3ANA. P3.6/WR can be

assigned as a third interrupt input.

The functions are assigned to the pins of port 3 as

follows:

P3.0 / RxD Receiver data input (asynch.) or

data input/output (synch.) of

serial interface

P3.1 / TxD Transmitter data output

(asynch.) or clock output

(synch.) of serial interface

P3.2 / AN4 / INT0 Analog input channel 4 /

external interrupt 0 input /

Timer 0 gate control input

P3.3 / AN5 / INT1 Analog input channel 5 /

external interrupt 1 input /

Timer 1 gate control input

P3.4 / AN6 / T0 Analog input channel 6 / Timer 0

counter input

P3.5 / AN7 / T1 Analog input channel 7 / Timer 1

counter input

P3.6 / WR / INT2 WR control output; latches the

data byte from port 0 into the

external data memory /

external interrupt 2 input

P3.7 / RD RD control output; enables the

external data memory

Table 1 Pin Definitions and Functions (cont’d)

Symbol Pin Number

(P-MQFP-44) I/O1) Function

C504

Data Sheet 7 2000-05

CTRAP 6ICCU Trap Input

With CTRAP = low, the compare outputs of the

CAPCOM unit are switched to the logic level as

defined in the COINI register (if they are enabled by

the bits in SFR TRCON). CTRAP is an input pin with

an internal pullup r esistor. For power saving

reasons, the signal source which drives the CTRAP

input should be at high or floating level during

power-down mode.

XTAL2 14 –XTAL2

Output of the inverting oscillator amplifier.

XTAL1 15 – XTAL1

Input to the inverting oscillator amplifier and input to

the internal clock generator circuits.

To drive the device from an external clock source,

XTAL1 should be driven, while XTAL2 is left

unconnected. There are no requirements on the

duty cycle of the external clock signal, since the

input to the internal clocking circuitry is divided down

by a divide-by-two flip-flop. Minimum and maximum

high and low times as well as rise/fall times specified

in the AC characteristics must be observed.

P2.0 - P2.7 18-25 I/O Port 2

is a bidirectional I/O port with internal pullup

resistors. Port 2 pins that have “1”s written to them

are pulled high b y the internal pullup resistors, and

in that state can be used as inputs. As inputs, Port 2

pins being externally pulled low will source current

(IIL, in the DC characteristics) because of the

internal pullup resistors. Port 2 emits the high-order

address byte during fetches from external program

memory and during accesses to external data

memory that use 16-bit addresses (MOVX @DPTR).

In this application it uses strong internal pullup

resistors when issuing “1”s. During accesses to

external data memory that use 8-bit addresses

(MOVX @Ri), Port 2 issues the contents of the P2

special function register.

Table 1 Pin Definitions and Functions (cont’d)

Symbol Pin Number

(P-MQFP-44) I/O1) Function

C504

Data Sheet 8 2000-05

PSEN 26 O The Program Store Enable

output is a control signal that enables the external

program memory to the bus during external fetch

operations. It is activated every six oscillator periods

except during external data memory accesses.

Remains high during internal program execution.

ALE 27 O The Address Latch Enable

output is used for latching the low-byte of the

address into external memory during normal

operation. It is activated every six oscillator periods

except during an external data memory access.

When instructions are executed from internal ROM

(EA = 1) the ALE generation can be disabled by

clearing bit EALE in SFR SYSCON.

COUT3 28 O 10-Bit compare channel output

This pin is used for the output signal of the 10-bit

Compare Timer 2 unit. COUT3 can be disabled and

set to a high or low state.

EA 29 I External Access Enable

When held at high level, instructions are fetched

from the internal ROM (C504-2R only) when the PC

is less than 4000H. When held at low level, the C504

fetches all instructions from external program

memory.

For the C504-L, this pin must be tied low.

P0.0 - P0.7 37 - 30 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0

pins that have “1”s written to them float; and in that

state, can be used as high-impedance inputs. Port 0

is also the multiplexed low-order address and data

bus during accesses to external program or data

memory. In this application, it uses strong internal

pullup resistors when issuing “1” s.

Port 0 also outputs the code bytes during program

verification in the C504-2R. External pullup resistors

are required during program (ROM) verification.

VAREF 38 – Refere nce voltage for the A/D converter.

Table 1 Pin Definitions and Functions (cont’d)

Symbol Pin Number

(P-MQFP-44) I/O1) Function

C504

Data Sheet 9 2000-05

VAGND 39 –Reference ground for the A/D converter.

VSS 16 – Ground (0 V)

VDD 17 – Power Supply (+ 5 V)

1) I = Input,

O = Output

Table 1 Pin Definitions and Functions (cont’d)

Symbol Pin Number

(P-MQFP-44) I/O1) Function

C504

Data Sheet 10 2000-05

Figure 4 Block Diagram of the C504

MCB02591

Oscillator Watchdog

OSC & Timing

CPU

Timer 1

Timer 2

Interrupt Unit

USART

Capture/Compare Unit

A/D Converter 10-Bit

Timer 0

S & H MUX

XRAM 256 x 8

RAM ROM/OTP

16 k x 8

Port 0

Port 1

Port 2

Port 3

Port 0

Port 1

Port 2

Port 3

XTAL2

XTAL1

RESET

ALE

PSEN

COUT3

CTRAP

AGND

AREF

8-Bit Digital I/O

4-Bit Analog Inputs

8-Bit Digital I/O

4-Bit Analog Inputs

8-Bit Digital I/O

Support

Emulation

Logic

256 x 8

C504

Data Sheet 11 2000-05

CPU

The C504 is efficient both as a controller and as an arithmetic processor. It has extensive

facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient

use of program memory results from an instruction set consisting of 44% one-byte, 41%

two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions

are executed in 1.0 µs (24 MHz: 500 ns, 40 MHz: 300 ns).

Special Function Register PSW (Address D0H) Reset Value: 00H

Bit Function

CY Carry Flag

Used by arithmetic instructions.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.

F0 General Purpose Flag 0

RS1

RS0 Register Bank Select Control bits

These bits are used to select one of the four register banks.

OV Overflow Flag

Used by arithmetic instruction.

F1 General Purpose Flag 1

PParity Flag

Set/cleared by hardware after each instruction to indicate an odd/

even number of “one” bits in the accumulator.

CY AC F0 RS1 RS0 OV F1 PD0HPSW

D7HD6HD5HD4HD3HD2HD1HD0H

Bit No. MSB LSB

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07H

0 1 Bank 1 selected, data address 08H-0FH

1 0 Bank 2 selected, data address 10H-17H

1 1 Bank 3 selected, data address 18H-1FH

C504

Data Sheet 12 2000-05

Memory Organization

The C504 CPU manipulates operands in the following four address spaces:

– up to 64 Kbyte of program memory: 16K ROM for C504-2R

16K OTP for C504-2E

– up to 64 Kbyte of external data memory

– 256 bytes of internal data memory

– 256 bytes of internal XRAM data memory

– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C504.

Figure 5 C504 Memory Map

MCD02592

00H

0000H

3FFFH

External

FFFFH

4000

(EA = 0)(EA = 1)

"Code Space" "Data Space" "Internal Data Space"

0000

FFFF

External

FF00 H

FEFFH

Internal

XRAM

RAM

Internal

Internal External

Internal

RAM

FFH

Function

Special

Direct

Address

80H

Address

Indirect

C504

Data Sheet 13 2000-05

Res et and System Clock Operation

The reset input is an active high input. An internal Schmitt trigger is used at the input for

noise rejecti on. Sin ce the reset is synchronized int ernal ly, the RESET pin must be held

high for at least two machine cycles (24 oscillator periods) while the oscillator is running.

During reset, pins ALE and PSEN are configured as inputs and should not be stimulated

externally. (An external stimulation at these lines during reset activates several test

modes which are reserved for test purposes. This, in turn, may cause unpredictable

output operations at several port pins).

At the reset pin, a pulldown resistor is internally connected to VSS to allow a power-up

reset with an external capacitor only. An automati c reset can be obtained when VDD is

applied by connecting the reset pin to VDD via a capacitor. After VDD has been turned on,

the capacitor must hold the voltage level at the reset pin for a specific time to effect a

complete reset.

The time required for a reset operation is the oscillator start-up time and the time for

2 machine cycles, which must be at least 10 - 20 ms, under normal conditions. This

requirement is ty pic ally met usi ng a ca pac itor of 4.7 to 10 µF. The same consid erati ons

apply if the reset signal is generated externally (Figure 6b). In each case, it must be

assured that the os cillat or has sta rted up prop erly and th at at least two ma chine c ycles

have passed before the reset signal goes inactive.

Figure 6 shows the possible reset circuitries.

Figure 6 Reset Circuitries

C504

RESET

MCS03352

C504 C504

RESET RESET

C504

Data Sheet 14 2000-05

Figure 7 shows the rec ommend ed os cillato r circui t for the C504, whil e Figure 8 shows

the circuit for using an external clock source.

Figure 7 Recommended Oscillator Circuit

Figure 8 External Clock Source

MCS03353

3.5 - 40

MHz

XTAL2

XTAL1

C = 20 pF 10 pF for crystal operation

C504

MCS03355

XTAL1

XTAL2

N.C.

C504

External

Clock

Signal

C504

Data Sheet 15 2000-05

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new,

innovative way to control the execution of C500 MCUs and to gain extensive information

on the internal opera tion of the controll ers. Emulatio n o f on-c hip R OM bas ed prog rams

is possibl e, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation

Concept. Therefore, no costly bond-out chips are necessary for emulation. This also

ensure that emulation and production chips are identical.

The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows

the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the

design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a

compatible C500 are able to emulate all operating modes of the different versions of the

C500. This includes emulation of ROM, ROM with code rollover and ROMless modes of

operation. It is also able to operate in single step mode and to read the SFRs after a

break.

Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, Port 2 and some of the control lines of the C500 based MCU are used by

Enhanced Hooks Emulation Concept to control the operation of the device during

emulation and to transfer informations about the program execution and data transfer

between the external emulation hardware (ICE-system) and the C500 MCU.

MCS02647

SYSCON

PCON

TCON

RESET

PSEN

ALE

Port 0

Port 2

I/O Ports

Optional Port 3 Port 1

C500

MCU Interface Circuit

Enhanced Hooks

RPort 0RPort 2

RTCON

RPCON

RSYSCON

TEA TALE TPSEN

EH-IC

Target System Interface

ICE-System Interface

to Emulation Hardware

C504

Data Sheet 16 2000-05

Special Function Registers

All registers, except the program counter and the four general purpose register banks,

reside in the special function register area.

The 63 special function registers (SFR) include pointers and registers that provide an

interface betw een the CPU and the othe r on-chip pe riphe rals. Al l SFRs wi th address es

where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F0 H, F8H) are bit-addressable.

The SFRs of the C504 are listed in Table 2 and Table 3. In Table 2, they are organized

in groups which refer to the functional blocks of the C504. Table 3 illustrates the contents

of the SFRs in numeric order of their addresses.

C504

Data Sheet 17 2000-05

Table 2 Special Function Registers - Functional Blocks

Block Symbol Name Addr. Contents

after

Reset

CPU ACC

DPH

DPL

PSW

SYSCON

Accumulator

B-Register

Data Pointer, High Byte

Data Pointer, Low Byte

Program Status Word Register

Stack Pointer

System Control Register

E0H1)

F0H1)

83H

82H

D0H1)

81H

B1H

00H

07H

XX10XXX0B3)

Interrupt

System IEN0

IEN1

CCIE2)

IP0

IP1

ITCON

Interrupt Enable Register 0

Interrupt Enable Register 1

Capture/Compare Interrupt Enable Reg.

Interrupt Priority Register 0

Interrupt Priority Register 1

Interrupt Trigger Condition Register

A8H1)

A9H

D6H

B8H1)

B9H

9AH

0X000000B3)

XX000000B3)

00H

XX000000B3)

00101010B

Ports P0

P1ANA2)

P3ANA2)

Port 0

Port 1

Port 1 Analog Input Selection Register

Port 2

Port 3

Port 3 Analog Input Selection Register

80H1)

90H1)

90H1) 4)

A0H1)

B0H1)

B0H1) 4)

FFH

XXXX1111B3)

FFH

XX1111XXB3)

A/D-

Converter ADCON0

ADCON1

ADDATH

ADDATL

P1ANA2)

P3ANA2)

A/D Converter Control Register 0

A/D Converter Control Register 1

A/D Converter Data Register High Byte

A/D Converter Data Register Low Byte

Port 1 Analog Input Selection Register

Port 3 Analog Input Selection Register

D8H1)

DCH

D9H

DAH

90H1) 4)

B0H1) 4)

XX000000B3)

01XXX000B3)

00H

00XXXXXXB3)

XXXX1111B3)

XX1111XXB3)

Serial

Channels PCON2)

SBUF

SCON

Power Control Register

Serial Channel Buffer Register

Serial Channel Control Register

87H

99H

98H1)

000X0000B

XXH3)

00H

Timer 0/

Timer 1 TCON

TH0

TH1

TL0

TL1

TMOD

Timer 0/1 Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

Timer 1, Low Byte

Timer Mode Register

88H1)

8CH

8DH

8AH

8BH

89H

00H

1) Bit-addre ssable special fun ction registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means tha t the v alue is undefine d and the location is res erv ed

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

C504

Data Sheet 18 2000-05

Timer 2 T2CON

T2MOD

RC2H

RC2L

TH2

TL2

Timer 2 Control Register

Timer 2 Mode Register

Timer 2 Reload Capture Register, High Byte

Timer 2 Reload Capture Register, Low Byte

Timer 2 High Byte

Timer 2 Low Byte

C8H1)

C9H

CBH

CAH

CDH

CCH

00H

XXXXXXX0B3)

00H

Capture /

Compare

Unit

CT1CON

CCPL

CCPH

CT1OFL

CT1OFH

CMSEL0

CMSEL1

COINI

TRCON

CCL0

CCH0

CCL1

CCH1

CCL2

CCH2

CCIR

CCIE2)

CT2CON

CP2L

CP2H

CMP2L

CMP2H

BCON

Compare timer 1 control register

Compare timer 1 period register, low byte

Compare timer 1 period register, high byte

Compare timer 1 offset register, low byte

Compare timer 1 offset register, high byte

Capture/compare mode select register 0

Capture/compare mode select register 1

Compare output initialization register

Trap enable control register

Capture/compare register 0, low byte

Capture/compare register 0, high byte

Capture/compare register 1, low byte

Capture/compare register 1, high byte

Capture/compare register 2, low byte

Capture/compare register 2, high byte

Capture/compare interrupt request flag reg.

Capture/compare interrupt enable registe r

Compare timer 2 control register

Compare timer 2 period register, low byte

Compare timer 2 period register, high byte

Compare timer 2 compare register, low byte

Compare timer 2 compare register, high byte

Block commutation control register

E1H

DEH

DFH

E6H

E7H

E3H

E4H

E2H

CFH

C2H

C3H

C4H

C5H

C6H

C7H

E5H

D6H

C1H

D2H

D3H

D4H

D5H

D7H

00010000B

00H

FFH

00H

00010000B

00H

XXXXXX00B3)

00H

XXXXXX00B3)

00H

Watchdog

Timer WDCON

WDTREL Watchdog Timer Control Register

Watchdog Timer Reload Register C0H1)

86H

XXXX0000B3)

00H

Power

Saving

Mode

PCON2)

PCON1 Power Control Register

Power Control Register 1 87H

88H1) 4) 000X0000B3)

0XXXXXXXB3)

1) Bit-addre ssable special fun ction registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means tha t the v alue is undefine d and the location is res erv ed

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Table 2 Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Addr. Contents

after

Reset

C504

Data Sheet 19 2000-05

Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses

Addr Register Content

after

Reset1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

80H2) P0 FFH.7 .6 .5 .4 .3 .2 .1 .0

81HSP 07H.7 .6 .5 .4 .3 .2 .1 .0

82HDPL 00H.7 .6 .5 .4 .3 .2 .1 .0

83HDPH 00H.7 .6 .5 .4 .3 .2 .1 .0

86HWDTREL 00HWDT

PSEL .6 .5 .4 .3 .2 .1 .0

87HPCON 000X-

0000B

SMOD PDS IDLS – GF1 GF0 PDE IDLE

88H2) TCON 00HTF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

88H1)3) PCON1 0XXX-

XXXXB

EWPD – – – – – – –

89HTMOD 00HGATE C/T M1 M0 GATE C/T M1 M0

8AHTL0 00H.7 .6 .5 .4 .3 .2 .1 .0

8BHTL1 00H.7 .6 .5 .4 .3 .2 .1 .0

8CHTH0 00H.7 .6 .5 .4 .3 .2 .1 .0

8DHTH1 00H.7 .6 .5 .4 .3 .2 .1 .0

90H2) P1 FFH.7 .6 .5 .4 .3 .2 T2EX T2

90H2)3) P1ANA XXXX-

1111B

––––EAN3 EAN2 EAN1 EAN0

98H2) SCON 00HSM0 SM1 SM2 REN TB8 RB8 TI RI

99HSBUF XXH.7 .6 .5 .4 .3 .2 .1 .0

9AHITCON 0010-

1010B

IT2 IE2 I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR

A0H2) P2 FFH.7 .6 .5 .4 .3 .2 .1 .0

A8H2) IEN0 0X00-

0000B

EA – ET2 ES ET1 EX1 ET0 EX0

A9HIEN1 XX00-

0000B

– – ECT1 ECCM ECT2 ECEM EX2 EADC

1) X means tha t the v alue is undefine d and the location is res erv ed

2) Bit-addre ssable special fun ction registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

C504

Data Sheet 20 2000-05

B0H2) P3 FFHRD WR T1 T0 INT1 INT0 TxD RxD

B0H2)3) P3ANA XX11-

11XXB

– – EAN7 EAN6 EAN5 EAN4 – –

B1HSYSCON XX10-

XXX0B

––EALERMAP–––XMAP

B8H2) IP0 XX00-

0000B

––PT2 PS PT1 PX1 PT0 PX0

B9HIP1 XX00-

0000B

– – PCT1 PCCM PCT2 PCEM PX2 PADC

C0H2) WDCON XXXX-

0000B

––––OWDS WDTS WDT SWDT

C1HCT2CON 0001-

0000B

CT2P ECT2O STE2 CT2

RES CT2R CLK2 CLK1 CLK0

C2HCCL0 00H.7 .6 .5 .4 .3 .2 .1 .0

C3HCCH0 00H.7 .6 .5 .4 .3 .2 .1 .0

C4HCCL1 00H.7 .6 .5 .4 .3 .2 .1 .0

C5HCCH1 00H.7 .6 .5 .4 .3 .2 .1 .0

C6HCCL2 00H.7 .6 .5 .4 .3 .2 .1 .0

C7HCCH2 00H.7 .6 .5 .4 .3 .2 .1 .0

C8H2) T2CON 00HTF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/

RL2

C9HT2MOD XXXX-

XXX0B

–––––––DCEN

CAHRC2L 00H.7 .6 .5 .4 .3 .2 .1 .0

CBHRC2H 00H.7 .6 .5 .4 .3 .2 .1 .0

CCHTL2 00H.7 .6 .5 .4 .3 .2 .1 .0

CDHTH2 00H.7 .6 .5 .4 .3 .2 .1 .0

CFHTRCON 00HTRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0

1) X means tha t the v alue is undefine d and the location is res erv ed

2) Bit-addre ssable special fun ction registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)

Addr Register Content

after

Reset1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C504

Data Sheet 21 2000-05

D0H2) PSW 00HCY AC F0 RS1 RS0 OV F1 P

D2HCP2L 00H.7 .6 .5 .4 .3 .2 .1 .0

D3HCP2H XXXX.

XX00B

––––––.1.0

D4HCMP2L 00H.7 .6 .5 .4 .3 .2 .1 .0

D5HCMP2H XXXX.

XX00B

––––––.1.0

D6HCCIE 00HECTP ECTC CC2

FEN CC2

REN CC1

FEN CC1

REN CC0

FEN CC0

REN

D7HBCON 00HBCMP

BCEM PWM1 PWM0 EBCE BCERR BCEN BCM1 BCM0

D8H2) ADCON0 XX00-

0000B

––IADC BSY ADM MX2 MX1 MX0

D9HADDATH 00H.9 .8 .7 .6 .5 .4 .3 .2

DAHADDATL 00XX-

XXXXB

.1.0––––––

DCHADCON1 01XX-

X000B

ADCL1 ADCL0 – – – MX2 MX1 MX0

DEHCCPL 00H.7 .6 .5 .4 .3 .2 .1 .0

DFHCCPH 00H.7 .6 .5 .4 .3 .2 .1 .0

E0H2) ACC 00H.7 .6 .5 .4 .3 .2 .1 .0

E1HCT1CON 0001-

0000B

CTM ETRP STE1 CT1

RES CT1R CLK2 CLK1 CLK0

E2HCOINI FFHCOUT

3I COUTX

I COUT

2I CC2I COUT

1I CC1I COUT

0I CC0I

E3HCMSEL0 00HCMSEL

13 CMSEL

12 CMSEL

11 CMSEL

10 CMSEL

03 CMSEL

02 CMSEL

01 CMSEL

E4HCMSEL1 00H0000CMSEL

23 CMSEL

22 CMSEL

21 CMSEL

E5HCCIR 00HCT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R

E6HCT1OFL 00H.7 .6 .5 .4 .3 .2 .1 .0

E7HCT1OFH 00H.7 .6 .5 .4 .3 .2 .1 .0

F0H2) B00H.7 .6 .5 .4 .3 .2 .1 .0

1) X means tha t the v alue is undefine d and the location is res erv ed

2) Bit-addre ssable special fun ction registers

Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)

Addr Register Content

after

Reset1)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

C504

Data Sheet 22 2000-05

Timer/Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4.

In the “timer” function (C/T = ‘0’), the register is incremented every machine cycle.

Therefore the count rate is fOSC/12.

In the “counter” function th e regi ster is inc remen ted in res po nse to a 1-to-0 trans ition at

its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine

cycles to de tect a falling ed ge the max. coun t rate is fOSC/24. External i nputs INT0 and

INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width

measurements. Figure 10 illustrates the input clock logic.

Figure 10 Timer/Counter 0 and 1 Input Clock Logic

Table 4 Timer/Counter 0 and 1 Operating Modes

Mode Description TMOD Input Clock

Gate C/TM1 M0 internal external

(max.)

0 8-bit timer/counter with a

divide-b y-32 pres cal er XX00

fOSC/12 × 32 fOSC/24 × 32

1 16-bit timer/counter X X 1 1 fOSC/12 fOSC/24

2 8-bit timer/ cou nter wit h

8-bit auto-relo ad XX00

fOSC/12 fOSC/24

3 Timer/counter 0 used as one

8-bit time r/counter and one

8-bit timer

Timer 1 stops

XX11

fOSC/12 fOSC/24

OSC

/12

MCS01768

OSC

C/T

TMOD

Control

Timer 0/1

Input Clock

TCON

TR 0/1

Gate

TMOD

P3.4/T0

P3.5/T1

max

P3.2/INT0

P3.3/INT1

OSC

/24

C504

Data Sheet 23 2000-05

Timer/Counter 2

Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as

a timer or as an eve nt c ount er. This is selec ted b y bi t C /T2 of SFR T2CON. It has three

operating modes as shown in Table 5.

Note:

↓

= falling edge

Table 5 Timer/Counter 2 Operating Modes

Mode T2CON T2MOD

DCEN

T2CON

EXEN

P1.1/

T2EX Remarks Input Clock

R×CLK

T×CLK

CP/

RL2 TR2 internal external

(P1.0/T2)

16-bit

Auto-

reload

↓

reload upon

overflow

reload trigger

(falling edge)

Down counting

Up counting

fOSC/12 max

fOSC/24

16-bit

Cap-

ture

↓

16 bit Timer/

Counter (only

up-counting)

capture TH2,

TL2 → RC2H,

RC2L

fOSC/12 max

fOSC/24

Baud

Rate

Gene-

rator

↓

no overflow

interrupt

request (TF2)

extra external

interrupt

(“Timer 2”)

fOSC/2 max

fOSC/24

off X X 0 X X X Timer 2 stops – –

C504

Data Sheet 24 2000-05

Capture/Compare Uni t

The Capture/Compare Unit (CCU) of the C504 consists of a 16-bit 3-channel capture/

compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare

mode, the CAPCOM unit provides two output signals per channel, which can have

inverted signal polarity and non-overlapping pulse transitions. The COMP unit can

generate a single PWM output signal and is further used to modulate the CAPCOM

output signals. In capture mode, the value of the Compare Timer 1 is stored in the

capture registers if a signal transition occurs at the pins CCx. Figure 11 sh ows the b lock

diagram of the CCU.

Figure 11 Block Diagram of the CCU

C504

Data Sheet 25 2000-05

The Compa re Timers 1 and 2 are free running, processor clock coupled 16-bit / 10-bit

timers; each of which has a count rate with a maximum of

OSC/2 up to

OSC/256. The

compare timer operations with its possible compare output signal waveforms are shown

in Figure 12.

Figure 12 Basic Operating Modes of the CAPCOM Unit

Compare Timer 1 can be programmed for both operating modes while Compare Timer 2

works only in operating mode 0 with one output signal of selectable polarity at the pin

COUT3.

Period

Value

Compare

0000

COUT

Value

Compare

Value

Period

Offset

OFF

Value

Compare

0000

Value

Period

Compare

Value

Offset

Value

Period

OFF

COINI=0

COINI=1

OFF

: Interrupts can be generated

MCT03356

Compare Timer 1 in Operating Mode 0

a) Standard PWM (Edge Aligned)

Compare Timer 1 in Operating Mode 1

b) Standard PWM (Single Edge Aligned)

with programmable dead time ( )

OFF

Symetrical PWM (Center Aligned)c) with programmable dead time ( )

Symetrical PWM (Center Aligned)d)

OFF

COUT

COINI=0

COINI=1

COUT

C504

Data Sheet 26 2000-05

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode,

three asynchronous modes) as illustrated in Table 6. The possible baud rates can be

calculated using the formulas given in Table 6.

Figure 13 Baud Rate Generation for the Serial Interface

Table 6 USART Operating Modes

Mode SCON Baud Rate Description

SM0 SM1

000

fOSC/12 Serial data enters and exits through

R×D. T×D outputs the shift clock. 8-bit

are transmitted/received (LSB first)

1 0 1 Timer 1/2 overflow rate 8-bit UART

10 bits are transmitted (through T×D)

or received (R×D)

210

fOSC/32 or fOSC/64 9-bit UART

11 bits are transmitted (T×D) or

received (R×D)

3 1 1 Timer 1/2 overflow rate 9-bit UART

Like mode 2 except the variable baud

rate

SM0 / SM1 PCON.7

(SMOD)

(RCLK, TCLK)

T2CON

Timer 1

Overflow

Phase 2

CLK

(= /2)

OSC

Timer 2

Overflow

Mode 1, 3

Mode 2

MCB02414

Baud

Rate

Clock

C504

Data Sheet 27 2000-05

The possible baud rates can be calculated using the formulas given in Table 7.

Table 7 Formulas for Calculating Baud Rates

Source of

Baud Rate Operating Mode Baud Rate

Oscillator 0

2fOSC/12

(2SMOD ×fOSC)/64

Timer 1

(16-bit timer)

(8-bit timer with

8-bit auto-reload)

1, 3

1, 3 (2SMOD ×timer 1 overflow rate)/32

(2SMOD ×fOSC)/(32 ×12 ×(256-TH1))

Timer 2 1, 3 fOSC/(32 ×(65536-( R C2H, RC2L))

C504

Data Sheet 28 2000-05

10-Bit A/D Converter

The C504 has a high performance 8-channel 10-bit A/D converter using successive

approximati on technique for the conversion of analog input voltages. Figure 14 shows

the block diagram of the A/D Converter.

Figure 14 A/D Converter Block Diagram

ADDATLADDATH

Shaded bit locations are not used in ADC-functions.

AREF

AGND

OSC

÷ 32, 16, 8, 4

Prescaler

Clock

Port 1/3

Conversion

Write to

ADDATL

MCB02616

Bus

Internal

Continuous

Single/

A/D Converter

Input Clock

Conversion Clock

ADC

MUX S & H

Mode

LSB.8

Start of

MSB .1

(D9 )

(DA )

IEN1 (A9 )

ADCON0 (D8 )

ADCL1

ADCON1 (DC )

P3ANA (B0 )

P1ANA (90 )

BSY

IADC

HADM MX2

EAN6

ADCL0

EAN7

- -

EAN5

MX2

EAN4

EAN3

EAN2

MX1 MX0

MX1

MX0

EAN0EAN1

ECCM

HECT1 ECT2 ECEM EADCEX2

Bus

Internal

C504

Data Sheet 29 2000-05

The A/D Co nverter uses tw o cl ock s ignals for operation: the con vers ion clock fADC (= 1/

tADC) and the input clock fIN (= 1/tIN). Both clock signals are derived from the C504 system

clock fOSC which is applied at the XTAL pins. The duration of an A/D conversion is a

multiple of the period of the fIN clock signal. The table in Figure 15 shows the prescaler

ratios and the resulting A/D conversion times which must be selected for typical system

clock rates.

Figure 15 A/D Converter Clock Selection

The analog inputs are located at Port 1 and Port 3 (4 lines on each port). The

correspondin g Port 1 an d Port 3 pins have a port structure , which allow s the pi ns to be

used either as digital I/Os or analog inputs. The analog input function of these mixed

digital/analog port lines is selected via the registers P1ANA and P3ANA.

MCU System Clock

Rate (fOSC)fIN

[MHz]

Prescaler fADC

[MHz]

A/D

Conversion

Time [µs]

Ratio ADCL1 ADCL0

3.5 MHz 1.75 ÷ 4 0 0 .438 48 × tIN = 27.4

12 MHz 6 ÷ 4 0 0 1.5 48 × tIN = 8

16 MHz 8 ÷ 40 0 2 48 × tIN = 6

24 MHz 12 ÷ 8 0 1 1.5 96 × tIN = 8

32 MHz 16 ÷ 80 1 2 96 × tIN = 6

40 MHz 20 ÷ 16 1 0 1.25 192 × tIN = 9.6

C504

Data Sheet 30 2000-05

Interrupt System

The C504 provides 12 interrupt sources with two priority levels. Figures 16 and 17 giv e

a general overview of the interrupt sources and illustrate the interrupt request and control

flags.

Figure 16 Interrupt Request Sources (Part 1)

C504

Data Sheet 31 2000-05

Figure 17 Interrupt Request Sources (Part 2)

MCB02596

ITCON.7

IT2

P3.6/WR/INT2

ITCON.4

ITCON.5

EX2

IE2

IEN1.1

ITCON.6

004BH

Low Priority

High Priority

IP1.1

PX2

CC0R CC0REN

CCIE0.0

CCIR.0

CCIR.1 CCIE0.1

CC0FEN

CC0F

CC1F CC1FEN

CCIE0.3

CCIR.3

CCIR.2 CCIE0.2

CC1REN

CC1R

CC2F CC2FEN

CCIE0.5

CCIR.5

CCIR.4 CCIE0.4

CC2REN

CC2R

PCCM

IP1.4

0063

IEN1.4

ECCM

CCIR.7

CCIE.7

CT1FP

ECTP

ECTC

CT1FC

CCIE.6

CCIR.6

ECT1

IEN1.5

006BH

IP1.5

PCT1

PCT2

IP1.3

005B

IEN1.3

ECT2

CT2P

CT2CON.7

PCEM

IP1.2

0053

IEN1.2

ECEM

BCON.3

BCERR

EBCE

ETRP

TRF

CT1CON.6

TRCON.6

BCON.4 EA

P1.2/AN2/CC0

P1.4/CC1

P1.6/CC2

Capture/Compare Match Interrupt

Compare Timer 1

Interrupt

Compare Timer 2

Interrupt

CCU Emergency

Bit addressable

Request Flag is

cleared by hardware IEN0.7

C504

Data Sheet 32 2000-05

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by

another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other

int errupt source s.

If two requests of different priority level are received simultaneously, the request of

higher pr iority is serviced. If requests of the same prio rity are recei ved simultane ously,

an internal polling sequence determines which request is serviced. Thus within each

priori ty level there is a seco nd priority structure determi ned by the polling seq uence as

sh own in Table 9.

Table 8 Interrupt Vector Addresses

Request Flags Interrupt Source Vector Address

IE0

TF0

IE1

TF1

RI + TI

TF2 + EXF2

IADC

IE2

TRF, BCERR

CT2P

CC0F-C C 2 F, CC 0R - C C2 R

CT1FP, CT1FC

–

External interrupt 0

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

Serial port interrupt

Timer 2 interrupt

A/D converter interrupt

External interrupt 2

CAPCOM emergency interrupt

Compare timer 2 interrupt

Capture/compare match interrupt

Compare timer 1 interrupt

Power-down interrupt

0003H

000BH

0013H

001BH

0023H

002BH

0043H

004BH

0053H

005BH

0063H

006BH

007BH

Table 9 Interrupt Source Structure

Interrupt Source Priority

External Interrupt 0

Timer 0 Interrupt

External Interrupt 1

Timer 1 Interrupt

Serial Channel

Timer 2 Interrupt

A/D Converter

External Interrupt 2

CCU Emergency Interrupt

Compare Timer 2 Interrupt

Capture/Compare Match Interrupt

Compare Timer 1 Interrupt

High

Low

High Priority Low Priority

C504

Data Sheet 33 2000-05

Fail Save Mechanism s

The C504 offers enhanced fail save mechanisms, which allow an automatic recovery

from software or hardware failure.

– a programmable 15-bit Watchdog Timer

– Oscillator Watchdog

Programmable Watchdog Timer

The Watchdog Timer in the C504 is a 15-bit timer, which is incremented by a count rate

of either fCYCLE/2 or fCYCLE/32 (fCYCLE = fOSC/12). Only the upper 7 bits of the 15-bit

watchdog timer count value can be programmed. Figure 18 shows the block diagram of

the programmable Watchdog Timer.

Figure 18 Block Diagram of the Programmable Watchdog Timer

The Watchdog Timer can be started by software (bit SWDT in SFR WDCON), but it

cannot be stop ped during active m ode of the device. If the software fails to refresh the

running Watchdog Timer, an internal reset will be initiated. The reset cause (external

reset or reset caused by the watchdog) can be examined by software (status flag WDTS

in SFR WDCON is set). A refresh of the Watchdog Timer is done by setting bits WDT

and SWDT (both in SFR WDCON) consecutively.

This double instruction sequence has been implemented to increase system security.

It must be no ted, however, that the Watchdog Tim er i s h alte d d urin g th e idle mode and

power down mode of the processor.

C504

Data Sheet 34 2000-05

Oscillator Watchdog

The Oscillator Watchdog of the C504 serves for three functions:

–Monitoring of the on-chip oscillator’s function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the

frequency of an auxiliary RC oscillator, the internal clock is supplied by this RC

oscillator and the C504 is brought into reset. If the failure condition disappears, the

C504 exe cutes a final reset phase of typi cally 1 ms in order to all ow the os cillator

to stabilize; then, the Oscillator Watchdog reset is released and the part starts

program executi on again .

–Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip

oscillator has started. The Oscillator Watchdog unit also works identically to the

monitoring function.

–Control of external wake-up from software power-down mode

When the software power-down mode is terminated by a low level at pin P3.2/INT0,

the Oscillator Watchdog unit ensures that the microcontroller resumes operation

(execution of the power-down wake-up interrupt) with the nominal clock rate. In the

power-down mode, the RC oscillator and the on-chip oscillator are stopped. Both

oscillators are started again when power-down mode is released. When the on-chip

oscillat or has a higher frequen cy than the RC oscil lator, the microcontroller starts

operation after a final delay of typically 1 ms in order to allow the on-chip oscillator

to stabilize.

C504

Data Sheet 35 2000-05

Figure 19 Block Diagram of the Oscillator Watchdog

Power Saving Modes

The C504 provides two power saving modes, the idle mode and the power down mode.

– In the idle mode, the oscillator of the C504 continues to run, but the CPU is gated

off from the clock signal. However, the interrupt system, the serial port, the A/D

Converter, and all timers with the exception of the Watchdog Timer, are further

provided with the clock. The CPU status is preserved in its entirety: the stack

pointer, program counter, program status word, accumulator, and all other registers

maintain their data during idle mode.

– In the power down mode, the RC oscillator and the on-chip oscillator which

operates with the XTAL pins are both stopped. Therefore all functions of the

microcon trolle r are stopped and on ly the contents of the on-chip RAM, XRAM and

the SFRs are maintained. The port pins, which are controlled by their port latches,

output the values that are held by their SFRs.

Table 10 gives a general overview of the entry and exit procedures of the power saving

modes.

C504

Data Sheet 36 2000-05

If a power saving mode is termi nated throu gh an interrup t, includi ng the exte rnal w ake-

up via P3.2/INT0, the microcontroller state (CPU, ports, peripherals) remains preserved.

If it is terminated by a hardware reset, the microcontroller is reset to its default state.

In the power down mode of operation, VDD can be reduced to minimize power

consumption. It must be ensured, however, that VDD is not reduced before the power

down mode is invoked, and that VDD is restored to its normal operating level, before the

power down mode is terminated.

Table 10 Power Saving Modes Overview

Mode Entering

(2-Instruction

Example)

Leaving by Remarks

Idle mode ORL PCON, #01H

ORL PCON, #20H Occurrence of any

enabled interrupt CPU clock is stopped;

CPU maintains their data;

peripheral units are active

(if enabled) and provided

with clock.

Hardware Reset

Power

Down mode With external wake-up

capability from power

down enabled

ORL SYSCON,#10H

ORL PCON1,#80H

ANL SYSCON,#0EFH

ORL PCON,#02H

ORL PCON,#40H

Hardware Reset Oscillator is stopped;

Contents of on-chip RAM

and SFRs are maintained.

P3.2/INT0 goes low

for at least

10 µs.

It is desired that the

pin be held at high

lev el during the

power down mode

entry and up to the

wake-up.

With external wake-up

capability from power

down disabled

ORL PCON,#02H

ORL PCON,#40H

Hardware Reset

C504

Data Sheet 37 2000-05

OTP Memory Operation (C504-2E only)

The C504-2E is the OTP version of the C504 microcontroller with a 16Kbyte one-time

programma ble (OTP) program memo ry. Fa st pro gram ming cy cle s are ach iev ed (1 byte

in 100 µs) with the C504 -2E. Several levels of O TP memory protec tio n can be selec ted

as well.

To program the device, the C504-2E must be put into the programming mode. Typically,

this is no t do ne in-system, b ut i n a spe cia l pro gram ming ha rd wa re. In the programm ing

mode, the C504-2E operates as a slave device similar to an EPROM standalone

memory device and must be controlled with address/data information, control lines, and

an external 11.5 V programming voltage.

Figure 20 shows the pins of th e C504-2E wh ich are req uired for c ontrollin g of the O TP

programming mode.

Figure 20 C504-2E Programming Mode Configuration

PMSEL1

PMSEL0

XTAL2

XTAL1

P0.0 - 7

C504-2E

MCS03360

P2.0 - 7

PALE

EA /

PROG

PRD

RESET

PSEN

PSEL

Port 2 Port 0

C504

Data Sheet 38 2000-05

Pin Configuration in Programming Mode

Figure 21 Pin Configuration of the C504-2E in Programming Mode (top view)

EA /

N.C.

A5 / A13

PSEN

PROG

A4 / A12

A3 / A11

XTAL2

XTAL1

N.C.

PRD

RESET

N.C.

1116

MCP03361

A2 / A10

A1 / A9

A0 / A8

33 31 30 29 28 27 26 25 24 2332

PMSEL0

PALE

N.C.

PSEL

2345 78 109

C504-2E

N.C.

PMSEL1

C504

Data Sheet 39 2000-05

Pin Definitions

Table 11 contains the fu nctional desc ription of al l C504-2E pins wh ich are require d for

OTP memory programming.

Table 11 Pin Definitions and Functions of the C504-2E

in Programming Mode

Symbol Pin No. I/O Function

P-MQFP-44

RESET 4 I Reset

This input must be at static “1” (active) level throughout

the entire programming mode.

PMSEL0

PMSEL1 5

IProgramming mode selection pins

These pins are used to select the different access

modes in programming mode. PMSEL1,0 must satisfy a

setup time to the rising edge of PALE. When the logic

level of PMSEL1,0 is changed, PALE must be at low

level.

PSEL 8IBasic programming mode select

This input is used for the basic programming mode

selection and must be switched according to Figure 22.

PRD 9IProgramming mode read strobe

This input is used for read access control for OTP

memory read, version byte read, and lock bit read

operations.

PALE 10 I Programming address latch enable

PALE is used to latch the high address lines. The high

address lines must satisfy a setup and hold time to/from

the falling edge of PALE. PALE must be at low level

when the logic level of PMSEL1,0 is changed.

XTAL2 14 O XTAL2

Output of the inverting oscillator amplifier.

PMSEL1 PMSEL0 Access Mode

00Reserved

0 1 Read version bytes

1 0 Program/read lock bits

1 1 Program/read OTP memory

byte

C504

Data Sheet 40 2000-05

XTAL1 15 I XTAL1

Input to the oscillator amplifier.

VSS 16 –Ground (0 V)

must be applied in programming mode.

VDD 17 – Power Supply (+ 5 V)

must be applied in programming mode.

P2.0 -

P2.7 18 - 25 I Address lines

P2.0 - P2.7 are used as multiplexed address input lines

A0 - A7 and A8 - A13. A8 - A13 must be latched with

PALE.

PSEN 26 I Program store enable

This input must be at static “0” level during the whole

programming mode.

PROG 27 I Programming mode write strobe

This input is used in programming mode as a write

strobe for OTP memory program and lock bit write

operations. During basic programming mode selection,

a low level must be applied to PROG.

EA/VPP 29 – Programming Voltage

This pin must be held at 11.5 V (VPP) during

programming of an OTP memory byte or lock bit. During

an OTP memory read operation, this pin must be at VIH.

This pin is also used for basic programming mode

selection. For basic programming mode selection, a low

level must be applied.

P0.7 -

P0.0 30-37 I/O Data lines

In programming mode, data bytes are transferred via the

bidirectional D7 - D0 data lines which are located at

Port 0.

N.C. 1-3, 6,

11-13, 28,

38-44

–Not Connected

These pins should not be connected in programming

mode.

Table 11 Pin Definitions and Functions of the C504-2E

in Programming Mode (cont’d)

Symbol Pin No. I/O Function

P-MQFP-44

C504

Data Sheet 41 2000-05

Programming Mode Selection

The selection for the OTP programming mode can be separated into two different parts:

– Basic programming mode selection

– Access mode selection

With basic programming mode selection, the device is put into the mode in which it is

possibl e to access th e OTP memory throug h the programm ing interface logic. Furthe r,

after selection of the basic programming mode, OTP memory accesses are executed by

using one of the acc ess modes. The se access modes are O TP memory byte program/

read, version byte read, and program/read lock byte operations.

The basic programming mode selection scheme is shown in Figure 22.

Figure 22 Basic Programming Mode Selection

MCT03362

VDD

5 V

Clock

(XTAL1/

XTAL2)

RESET "1"

PSEN "0"

PMSEL1,0

PROG

PRD "1"

"0"

0,1

PSEL

PALE "0"

EA/VPP

VPP

VIH

0 V

Ready for access

mode selection

During this period signals

are not actively driven

Stable

C504

Data Sheet 42 2000-05

Lock Bits Programming / Read

The C504-2E has two programmable lock bits which, when programmed according to

Table 13, provide four levels of protection for the on-chip OTP code memory.

Note: A ‘1’ means that the lock bit is unprogrammed; a ‘0’ means that lock bit is

programmed.

Table 12 Access Modes Selection

Access Mode EA/

VPP

PROG PRD PMSEL Address

(Port 2) Data

(Port 0)

Program OTP memory

byte VPP H H H A0 - A7

A8 - A15 D0 - D7

Read OTP memory byte VIH H

Program OTP lock bits VPP HHL–D1,D0

see

Table 13

Read OTP lock bits VIH H

Read OTP version byte VIH H L H Byte addr.

of version byte D0 - D7

Table 13 Lock Bit Protection Types

Lock Bits Protection

Level Protection Type

D1 D0

1 1 Level 0 The OTP lock feature is disabled. During normal operation of

the C504-2E, the state of the EA pin is not latched on reset.

1 0 Level 1 During normal operation of the C504-2E, MOVC instructions

executed from external program memory are disabled from

fetching code bytes from internal memory. EA is sampled

and latched on reset. An OTP memory read operation is only

possible according to ROM/OTP verification mode 2. Further

programming of the OTP memory is disabled

(reprogramming security).

0 1 Level 2 Same as level 1, but also OTP memory read operation using

ROM verification mode 2 is disabled.

0 0 Level 3 Same as level 2; but additionally external code execution by

setting EA = low during normal operation of the

C504-2E is no more possible.

External code execution, which is initiated by an internal

program (e.g. by an internal jump instruction above the ROM

boundary), is still possible.

C504

Data Sheet 43 2000-05

Version Bytes

The C504-2E and C504-2R provide three version bytes at mapped address locations

FCH, FDH, and FEH. The information stored in the version bytes, is defined by the mask

of each microcontroller step. Therefore, the version bytes can be read but not written.

The three version bytes hold information as manufacturer code, device type, and

stepping code.

The steppings of the C504 contain the following version byte information:

Future steppings of the C504 will typically have a different value for version byte 2.

Table 14 Content of Version Bytes

Stepping Version Byte 0,

VR0 (mapped addr.

FCH)

Version Byte 1,

VR1 (mapped addr.

FDH)

Version Byte 2,

VR2 (mapped addr.

FEH)

C504-2R AC-Step C5H04H01H

C504-2E

ES-AA-Step C5H84H01H

C504-2E

ES-BB-Step C5H84H04H

C504-2E CA-Step C5H84H09H

C504

Data Sheet 44 2000-05

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage of the device. This is a stress rating only and functional

opera tion o f th e dev ice a t t hese or any ot her con ditions a bove those indica ted in

the operational sections of this specificati on is n ot implied . Exposure to abso lute

maximum rating condi tion s for lon ger perio ds ma y affect device reliab ility. During

absolute maximum rating overload conditions (

VIN

VDD

VIN

VSS

) the voltage

VDD

pins w ith respect t o ground (

VSS

) must not exceed the values d efined by

the absolute maximum ratings.

Absolute Maximum Ratings

Parameter Symbol Limit Values Unit Notes

min. max.

Storage temperature TST –65 150 °C–

Voltage on VDD pins with

respect to ground (VSS)VDD –0.5 6.5 V –

Voltage on any pin with

respect to ground (VSS)VIN –0.5 VDD + 0.5 V –

Input current on any pin

during overload condition – – 10 10 mA –

Absolute sum of all input

currents during overlo ad

condition

– – |100 mA| mA –

Power dissipation

DISS –1W–

Operating Conditions

Parameter Symbol Limit Values Unit Notes

min. max.

Supply voltage VDD 4.25 5.5 V –

Ground vol tage VSS 0V–

Ambient temperature

SAB-C504

SAF-C504

SAK-C504

–40

125

°C–

Analog reference voltage VAREF 4VDD + 0.1 V –

Analog ground voltage VAGND VSS –0.1 VSS + 0.2 V –

Analog input voltage VAIN VAGND VAREF V–

CPU clock fCPU 1.75 20 MHz –

C504

Data Sheet 45 2000-05

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C504

and partly its de mand s on the sy stem . To aid in inte rpreting the parameters rig ht, w hen

evaluating them for a design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C504 will provide signals with the respective characteristics.

SR (System Requirement):

The external system must provide signals with the respective characteristics to the

C504.

DC Characteristics

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage

(except EA, RESET,

CTRAP)VIL SR – 0.5 0.2 VDD

– 0.1 V–

Input low voltage (EA)VIL1 SR – 0.5 0.2 VDD

– 0.3 V–

Input low voltage

(RESET, CTRAP)VIL2 SR – 0.5 0.2 VDD +

0.1 V–

Input high voltage

(except XTAL1, RESET and

CTRAP)VIH SR 0.2 VDD +

0.9 VDD + 0 .5 V 11)

Input high voltage to XTAL1 VIH1 SR 0.7 VDD VDD + 0.5 V –

Input high voltage to

RESET and CTRAP VIH2 SR 0.6 VDD VDD + 0.5 V –

Output low volta ge

(Ports 1, 2, 3, COUT3) VOL CC – 0.45 V IOL =1.6 mA

Output low voltage

(Port 0, ALE, PSEN)VOL1 CC – 0.45 V IOL =3.2 mA

Output high voltage

(Ports 1, 2, 3) VOH CC 2.4

0.9 VDD

–

–VIOH =–80µA

IOH =–10µA

Output high voltage

(Ports 1, 3 pins in push-pull

mode and COUT3) VOH1 CC 0.9 VDD –VIOH =–800µA

C504

Data Sheet 46 2000-05

Output high voltage

(Port 0 in external bus

mode, ALE, PSEN)VOH2 CC 2.4

0.9 VDD

–

–VIOH =–800µA2)

IOH =–80µA2)

Logic 0 input current

(Ports 1, 2, 3) IIL SR – 10 – 50 µAVIN =0.45V

Logical 1-to-0 transition

current (Ports 1, 2, 3) ITL SR – 65 – 650 µAVIN =2V

Input leakage current

(Port 0, EA)ILI CC – ±1µA0.45<VIN <VDD

Pin capacitance CIO CC – 10 pF fc= 1 MHz,

TA=25°C

Overload current IOV SR – ± 5mA

7) 8)

Programming voltage

(C504-2E) VPP SR 10.9 12.1 V11.5 V ± 5%10)

Power Supply Current

Parameter Sym-

bol Limit Values Unit Test Condition

typ.8) max.9)

Active mode C504-2R 24 MHz

40 MHz IDD

IDD

27.4

43.1 35.9

57.2 mA

C504-2E 24 MHz

40 MHz IDD

IDD

20.9

31.0 27.9

41.5 mA

Idle mode C504-2R 24 MHz

40 MHz IDD

IDD

14.6

22.4 19.3

31.3 mA

C504-2E 24 MHz

40 MHz IDD

IDD

12.3

16.1 16.1

20.9 mA

Power-down

mode C504-2R IPD 130µAVDD =2 … 5.5 V 3)

C504-2E IPD 35 60 µA

At EA/VPP

in prog. mode C504-2E IDDP –30mA–

DC Characteristics (cont’d)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

C504

Data Sheet 47 2000-05

Notes:

1) Capacitiv e loading on Ports 0 and 2 may cause s purious noise puls es to be superimposed on the VOL of ALE

and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these

pins ma ke 1-to -0 transit ions durin g bus o peration. I n the wo rst cas e (capacitiv e loading > 100 pF), the noise

pulse on AL E line may exceed 0.8 V. In such cases, it may be des irable to qualify ALE with a Sc hm it t -t rigger,

or use an ad dres s lat c h wi th a Sch mitt-trigger str obe input.

2) Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the

0.9 VDD specification when the address lines are stabilizing.

3) IPD (power-d ow n m ode) is measured under following co ndit ions:

EA =Port 0=VDD; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VSS; VAGND =VSS; all other pins are discon nec t ed.

4) IDD (active mode) is measured with:

XTAL1 driv en w it h tCLCH, tCHCL = 5 ns, VIL =VSS +0.5V, VIH =VDD – 0.5 V; XTAL2 = N.C.;

EA = Port 0 = Port 1 = RESET = VDD; all oth er pin s a re discon nect ed. IDD w ould be slightly hig her if a crys tal

oscillat or is use d (appr. 1 mA ).

5) IDD (idle mode ) is m easured with all ou tp ut pins dis c onnected and with all peripherals disa bled;

XTAL1 driv en w it h tCLCH, tCHCL = 5 ns, VIL =VSS +0.5V, VIH =VDD – 0.5 V; XTAL2 = N.C.;

RESET = EA =VSS; Port 0 = VDD; all othe r pins are disconnected;

6) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS – 0.5 V). The supply voltage VDD and VSS

must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed

50 mA.

7) Not 100 % tested, guarant eed by design char ac te riz at ion.

8) The typica l IDD values are periodically measured at TA = + 25 °C and VDD = 5 V but not 100% tested.

9) The maxim um IDD values are m easured unde r wo rs t cas e co nditions (TA = 0°C or –40°C and VDD =5.5V)

10)This VPP specification is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2

= 01H m us t be programmed with VPP =12V ± 5%.

11)For the C504- 2E ES-AA-step th e VIH min. for EA is 0.8 VDD.

C504

Data Sheet 48 2000-05

Figure 23 IDD Diagram

OSC

MCD03368

MHz 40

Active Mode

Idle Mode

DD max

DD typ

5 10152025

30 35

Active Mode

Idle Mode

C504-2E

OSC

MCD03367

MHz 40

mA Active Mode

DD max

DD typ

5 10152025

30 35

Idle Mode

C504-2R

Active Mode

Idle Mode

C504

Data Sheet 49 2000-05

Note:

fosc

is the oscillator frequency in MHz.

IDD

values are given in mA.

Notes see next page.

Power Supply Current Calculation Formulas

Parameter Symbol Formula

Active mode C504-2R IDD typ

IDD max

0.98 × fOSC + 3.9

1.33 × fOSC + 4.0

C504-2E IDD typ

IDD max

0.63 × fOSC + 5.75

0.85 × fOSC + 7.5

Idle mode C504-2R IDD typ

IDD max

0.51 × fOSC + 2.35

0.75 × fOSC + 1.3

C504-2E IDD typ

IDD max

0.24 × fOSC + 6.5

0.30 × fOSC + 8.86

A/D Converter Characteristics

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage VAIN SR VAGND VAREF V1)

Sample time tSCC –64

× tIN

32 × tIN

16 × tIN

8 × tIN

ns Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 42)

Conversion cycle time tADCC CC – 384 × tIN

192 × tIN

96 × tIN

48 × tIN

ns Prescaler ÷ 32

Prescaler ÷ 16

Prescaler ÷ 8

Prescaler ÷ 43)

Total unadjusted error TUE CC – ± 2LSBVSS + 0.5 V ≤ VIN

≤ VDD –0.5V

–± 4LSBVSS < VIN < VSS + 0.5 V

VDD –0.5V < VIN < VDD4)

Internal re sis tan ce of

reference voltage

source

RAREF SR – tADC/250

– 0.25 kΩtADC in [ns] 5) 6)

Internal re sis tan ce of

analog sou rce RASRCSR – tS/500

– 0.25 kΩtS in [ns] 2) 6)

ADC input capacitance CAIN CC – 50 pF 6)

C504

Data Sheet 50 2000-05

Further timing conditions: tADC min = 500 ns

tIN = 2/fOSC = 2 tCLCL

Notes:

1) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these

cases will be X000H or X3F FH, respe ctively.

2) During the sample time, the input capacitance CAIN can be charged/discharged by the external source. The

interna l res is t anc e of the analog source m ust allow the capaci ta nc e t o reach their f inal voltage level within tS.

After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.

3) This parameter includes the sample time tS, the time for determining the digital result and the time for the

calibra tion. Value s for the co nversio n clock tADC dep end on prog ramm ing and can be tak en from th e table on

the previous page.

4) TUE is tes ted at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other

voltages w ith in th e def ined voltage r ange.

If an ov erload condition occurs on m aximum 2 not s elected analog i nput pins an d the absolute sum of input

overloa d cur rents o n a ll analog in put p ins do es no t ex ceed 10 m A, a n addit ional conv ersion error of 1/ 2 LSB

is permis sib le.

5) During the conversion, the ADC’s capacitance must be repeatedly charged or discharged. The internal

resistance of the reference source must allow the capacitance to reach their final voltage level within the

indicated time. The max im um int ernal resistance results from the programmed co nv ers ion timing.

6) Not 100% tes t ed, but guaranteed by des ign characterizat ion.

Clock Calculation Table

Clock Prescaler

Ratio ADCL1, 0 tADC tStADCC

÷ 32 1 1 32 × tIN 64 × tIN 384 × tIN

÷ 16 1 0 16 × tIN 32 × tIN 192 × tIN

÷ 8018 × tIN 16 × tIN 96 × tIN

÷ 4004 × tIN 8 × tIN 48 × tIN

C504

Data Sheet 51 2000-05

Notes:

1) Interfacin g t he C504 to dev ic es w it h f loat t im es up to 75 ns is perm is s ible. This limit ed bus conten tio n w ill not

cause any dam age to Port 0 drivers.

AC Characteristics for C504-L / C504-2R / C504-2E

(Operating Conditions apply)

(CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Parameter Symbol Limit Values Unit

12-MHz

clock Variable Clock

1/tCLCL = 3.5 MHz to

12 MHz

min. max. min. max.

Program Memory Characteristics

ALE pulse width tLHLL CC 127 –2tCLCL –40 – ns

Address setup to ALE tAVLL CC 43 – tCLCL –40 – ns

Address hold after ALE tLLAX CC 30 – tCLCL –23 – ns

ALE low to valid instr in tLLIV SR – 233 – 4tCLCL –100 ns

ALE to PSEN tLLPL

CC 58 – tCLCL –25 – ns

PSEN pulse width tPLPH CC 215 – 3tCLCL –35 – ns

PSEN to valid instr in tPLIV

SR – 150 – 3tCLCL –100 ns

Input instruction hold after

PSEN tPXIX SR0–0 – ns

Input instruction float after

PSEN tPXIZ1) SR – 63 – tCLCL –20 ns

Address valid after PSEN tPXAV1) CC 75 – tCLCL –8 – ns

Address to valid instr in tAVIV

SR – 302 – 5tCLCL –115 ns

Address float to PSEN tAZPL CC0–0 – ns

C504

Data Sheet 52 2000-05

AC Characteristics for C504-L / C504-2R / C504-2E (cont’d)

Parameter Symbol Limit Values Unit

12-MHz

clock Variable Clock

1/tCLCL = 3.5 MHz to 12 MHz

min. max. min. max.

External Data Memory Characteristics

RD pulse width tRLRH CC 400 – 6tCLCL –100 – ns

WR pulse width tWLWH CC 400 – 6tCLCL –100 – ns

Address hold after ALE tLLAX2 CC 114 – 2tCLCL –53 – ns

RD to valid data in tRLDV SR – 252 – 5tCLCL –165 ns

Data hold after RD tRHDX SR 0 – 0 – ns

Data float after RD tRHDZ SR – 97 – 2tCLCL –70 ns

ALE to valid data in tLLDV SR – 517 – 8tCLCL –150 ns

Address to valid data in tAVDV SR – 585 – 9tCLCL –165 ns

ALE to WR or RD tLLWL CC 200 300 3tCLCL –50 3tCLCL +50 ns

Address valid to WR or RD tAVWL CC 203 – 4tCLCL –130 – ns

WR or RD high to ALE high tWHLH CC 43 123 tCLCL –40 tCLCL +40 ns

Data valid to WR transition tQVWX CC 33 – tCLCL –50 – ns

Data setup before WR tQVWH CC 433 – 7tCLCL –150 – ns

Data hold after WR tWHQX CC 33 – tCLCL –50 – ns

Address float after RD tRLAZ

CC – 0 – 0 ns

External Clock Drive Characteristics

Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 12 MHz

min. max.

Oscillator period tCLCL SR 83.3 294 ns

High time tCHCX SR 20 tCLCL – tCLCX ns

Low time tCLCX SR 20 tCLCL – tCHCX ns

Rise ti me tCLCH SR – 20 ns

Fall time tCHCL SR – 20 ns

C504

Data Sheet 53 2000-05

Notes:

1) Interfacin g t he C504 to dev ic es w it h f loat t im es up to 37 ns is perm is s ible. This limit ed bus conten tio n w ill not

cause any dam age to Port 0 drivers.

AC Characteristics for C504-L24 / C504-2R24 / C504-2E24

(Operating Conditions apply)

(CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Parameter Symbol Limit Values Unit

24-MHz

clock Variable Clock

1/tCLCL = 3.5 MHz to

24 MHz

min. max. min. max.

Program Memory Characteristics

ALE pulse width tLHLL CC 43 –2tCLCL –40 – ns

Address setup to ALE tAVLL CC 17 – tCLCL –25 – ns

Address hold after ALE tLLAX CC 17 – tCLCL –25 – ns

ALE low to valid instr in tLLIV SR – 80 – 4tCLCL –87 ns

ALE to PSEN tLLPL CC 22 – tCLCL –20 – ns

PSEN pulse width tPLPH CC 95 – 3tCLCL –30 – ns

PSEN to valid instr in tPLIV SR – 60 – 3tCLCL –65 ns

Input instruction hold after

PSEN tPXIX SR 0 – 0 – ns

Input instruction float after

PSEN tPXIZ1) SR – 32 – tCLCL –10 ns

Address valid after PSEN tPXAV1)CC 37 – tCLCL –5 – ns

Address to valid instr in tAVIV SR – 148 – 5tCLCL –60 ns

Address float to PSEN tAZPL CC 0 – 0 – ns

C504

Data Sheet 54 2000-05

AC Characteristics for C504-L24 / C504-2R24 / C504-2E24 (cont’d)

Parameter Symbol Limit Values Unit

24-MHz

clock Variable Clock

1/tCLCL = 3.5 MHz to 24 MHz

min. max. min. max.

External Data Memory Characteristics

RD pulse width tRLRH CC 180 – 6tCLCL –70 – ns

WR pulse width tWLWH CC 180 – 6tCLCL –70 – ns

Address hold after ALE tLLAX2 CC 56 – 2tCLCL –27 – ns

RD to valid data in tRLDV SR – 118 – 5tCLCL –90 ns

Data hold after RD tRHDX SR 0 – 0 – ns

Data float after RD tRHDZ SR – 63 – 2tCLCL –20 ns

ALE to valid data in tLLDV SR – 200 – 8tCLCL –133 ns

Address to valid data in tAVDV SR – 220 – 9tCLCL –155 ns

ALE to WR or RD tLLWL CC 75 175 3tCLCL –50 3tCLCL +50 ns

Address valid to WR tAVWL CC 67 – 4tCLCL –97 – ns

WR or RD high to ALE high tWHLH CC 17 67 tCLCL –25 tCLCL +25 ns

Data valid to WR transition tQVWX CC 5 – tCLCL –37 – ns

Data setup before WR tQVWH CC 170 – 7tCLCL –122 – ns

Data hold after WR tWHQX CC 15 – tCLCL –27 – ns

Address float after RD tRLAZ CC – 0 – 0 ns

External Clock Drive

Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 24 MHz

min. max.

Oscillator period tCLCL SR 41.7 294 ns

High time tCHCX SR 12 tCLCL – tCLCX ns

Low time tCLCX SR 12 tCLCL – tCHCX ns

Rise ti me tCLCH SR – 12 ns

Fall time tCHCL SR – 12 ns

C504

Data Sheet 55 2000-05

Notes:

1) SAK-C504 is not specified for 40 MHz operation.

2) Interfacin g t he C504 to dev ic es w it h f loat t im es up to 25 ns is perm is s ible. This limit ed bus conten tio n w ill not

cause any dam age to Port 0 drivers.

Characteristics for C504-L40 / C504-2R40 / C504-2E40

(Operating Conditions apply)1)

(CL for Port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Parameter Symbol Limit Values Unit

40-MHz

clock Variable Clock

1/tCLCL = 3.5 MHz to

40 MHz

min. max. min. max.

Program Memory Characteristics

ALE pulse width tLHLL CC 35 –2tCLCL –15 – ns

Address setup to ALE tAVLL CC 10 – tCLCL –15 – ns

Address hold after ALE tLLAX CC 10 – tCLCL –15 – ns

ALE low to valid instr in tLLIV SR – 55 – 4tCLCL –45 ns

ALE to PSEN tLLPL CC 10 – tCLCL –15 – ns

PSEN pulse width tPLPH CC 60 – 3tCLCL –15 – ns

PSEN to valid instr in tPLIV SR – 25 – 3tCLCL –50 ns

Input instruction hold after

PSEN tPXIX SR 0 – 0 – ns

Input instruction float after

PSEN tPXIZ2) SR – 20 – tCLCL –5 ns

Address valid after PSEN tPXAV2) CC 20 – tCLCL –5 – ns

Address to valid instr in tAVIV SR – 65 – 5tCLCL –60 ns

Address float to PSEN tAZPL CC – 5 – – 5 – ns

C504

Data Sheet 56 2000-05

AC Characteristics for C504-L40 / C504-2R40 / C504-2E40 (cont’d)

Parameter Symbol Limit Values Unit

40-MHz

clock Variable Clock

1/tCLCL = 3.5 MH z to 40 MHz

min. max. min. max.

External Data Memory Characteristics

RD pulse width tRLRH CC 120 – 6tCLCL –30 – ns

WR pulse width tWLWH CC 120 – 6tCLCL –30 – ns

Address hold after ALE tLLAX2 CC 35 – 2tCLCL –15 – ns

RD to valid data in tRLDV SR – 75 – 5tCLCL –50 ns

Data hold after RD tRHDX SR00–ns

Data float after RD tRHDZ SR – 38 – 2tCLCL –12 ns

ALE to valid data in tLLDV SR – 150 – 8tCLCL –50 ns

Address to valid data in tAVDV SR – 150 – 9tCLCL –75 ns

ALE to WR or RD tLLWL CC 60 90 3tCLCL –15 3tCLCL +15 ns

Address valid to WR tAVWL CC 70 – 4tCLCL –30 – ns

WR or RD high to ALE high tWHLH CC 10 40 tCLCL –15 tCLCL +15 ns

Data valid to WR transition tQVWX CC 5 – tCLCL –20 – ns

Data setup before WR tQVWH CC 125 – 7tCLCL –50 – ns

Data hold after WR tWHQX CC 5 – tCLCL –20 – ns

Address float after RD tRLAZ CC–0–0ns

External Clock Drive

Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3. 5 MHz to 40 MHz

min. max.

Oscillator period tCLCL SR 25 294 ns

High time tCHCX SR 10 tCLCL – tCLCX ns

Low time tCLCX SR 10 tCLCL – tCHCX ns

Rise ti me tCLCH SR – 10 ns

Fall time tCHCL SR – 10 ns

C504

Data Sheet 57 2000-05

Figure 24 Program Memory Read Cycle

Figure 25 Data Memory Read Cycle

MCT00096

ALE

PSEN

Port 2

LHLL

A8 - A15 A8 - A15

A0 - A7 Instr.IN A0 - A7

Port 0

AVLL PLPH

LLPL

LLIV

PLIV

AZPL

LLAX

PXIZ

PXIX

AVIV

PXAV

MCT00097

ALE

PSEN

Port 2

WHLH

Port 0

LLDV

RLRH

LLWL

RLDV

AVLL

LLAX2

RLAZ

AVWL

AVDV

RHDX

RHDZ

A0 - A7 from

Ri or DPL from PCL

A0 - A7 Instr.

Data IN

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

C504

Data Sheet 58 2000-05

Figure 26 Data Memory Write Cycle

Figure 27 External Clock Cycle

MCT00098

ALE

PSEN

Port 2

WHLH

Port 0

WLWH

LLWL

QVWX

AVLL

LLAX2

QVWH

AVWL

WHQX

A0 - A7 from

Ri or DPL from PCL

A0 - A7 Instr.IN

Data OUT

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

MCT00033

CHCX

CLCX

CHCL

CLCH

CLCL

- 0.5V

0.45V

0.7

- 0.1

0.2

C504

Data Sheet 59 2000-05

Note:

VPP = 11.5 V ± 5% is valid for devices with version byte 2 = 02H or higher. Devices with version byte 2 = 01H must

be programmed with VPP = 12 V ± 5%.

AC Characteristics of Programming Mode

(VDD = 5 V ±10%; VPP = 11.5 V ±5%; TA = 25 °C ±10 °C)

Parameter Symbol Limit Values Unit

min. max.

PALE pulse width tPAW 35 –ns

PMSEL setup to PALE rising edge tPMS 10 – ns

Address setup to PALE, PROG, or PRD

falling edge tPAS 10 – ns

Address hold after PALE, PROG, or PRD

falling edge tPAH 10 – ns

Address, data setup to PROG or PRD tPCS 100 – ns

Address, data hold after PROG or PRD tPCH 0–ns

PMSEL setup to PROG or PRD tPMS 10 – ns

PMSEL hold after PROG or PRD tPMH 10 – ns

PROG pulse width tPWW 100 – µs

PRD pulse width tPRW 100 – ns

Address to valid data out tPAD –75ns

PRD to valid data out tPRD –20ns

Data hold after PRD tPDH 0–ns

Data float after PRD tPDF –20ns

PROG high between two consecutive

PROG low pulses tPWH1 1–µs

PRD high between two consecutive PRD

low pulses tPWH2 100 – ns

XTAL clock period tCLKP 83.3 285.7 ns

C504

Data Sheet 60 2000-05

Figure 28 Programming Code Byte - Write Cycle Timing

PAW

PMS

PAH

PAS

A8-A13 A0-A7

D0-D7

PCS

PWW

PCH

PWH

MCT03369

H, H

PALE

PMSEL1,0

Port 2

Port 0

PROG

Note: PRD must be high during a programming read cycle

C504

Data Sheet 61 2000-05

Figure 29 Verify Code Byte - Read Cycle Timing

PAW

PMS

PAH

PAS

A8-A13 A0-A7

PAD

D0-D7

PDH

PDFPRD

PCS

PRW

PCH

PWH

MCT03370

H, H

PALE

PMSEL1,0

Port 2

Port 0

PRD

Note: PROG must be high during a programming read cycle

C504

Data Sheet 62 2000-05

Figure 30 Lock Bit Access Timing

Figure 31 Version Byte Read Timing

H, L H, L

D0, D1 D0, D1

PCS

PMS

PMH

PCH

PWW

PMS

PRD

PDH

PDF

PMH

PRW

PMSEL1,0

Port 0

PROG

PRD

Note : PALE should be low during a lock bit read / write cycle

MCT03371

e. g. FD

D0-7

PCS

PMS

PDH

PDF

PMH

MCT03372

Port 2

Port 0

PRD

PMSEL1,0 L, H

PRW

PRD

PCH

Note : PROG must be high during a programming read cycle

C504

Data Sheet 63 2000-05

Figure 32 ROM Verification Mode 1

ROM/OTP Verification Characteristics for C504-2R / C504-2E

ROM Verification Mode 1 (C504-2R only)

Parameter Symbol Limit Values Unit

min. max.

Address to valid data tAVQV –10 tCLCL ns

P1.0 - P1.7

P2.0 - P2.5

Port 0

Address

Data OUT

Address: P1.0 - P1.7 = A0 - A7

P2.0 - P2.5 = A8 - A13

Data: P0.0 - P0.7 = D0 - D7

Inputs: P2.6, P2.7, PSEN =

ALE, EA =

RESET =

IH2

AVQV

MCT03428

C504

Data Sheet 64 2000-05

Figure 33 ROM Verification Mode 2

ROM/OTP Verification Mode 2

Parameter Symbol Limit Values Unit

min. typ max.

ALE pulse width tAWD –2 tCLCL –ns

ALE period tACY –12 tCLCL –ns

Data valid after ALE tDVA ––4 tCLCL ns

Data stable after ALE tDSA 8 tCLCL ––ns

P3.5 setup to ALE low tAS –tCLCL –ns

Oscillator frequency 1/tCLCL 4–6MHz

MCT02613

ACY

AWD

DSA

DVA

Data Valid

ALE

Port 0

P3.5

C504

Data Sheet 65 2000-05

Figure 34 AC Testing: Input, Output Waveforms

Figure 35 AC Testing: Float Waveforms

Figure 36 Recommended Oscillator Circuits for Crystal Oscillator

AC Inputs during testing are driven at VDD – 0.5 V for a logic ‘1’ and 0.45 V for a logic ‘0’.

Timing measurements are made at VIHmin for a logic ‘1’ and VILmax for a logic ‘0’.

0.45 V

0.2 -0.1

+0.90.2 DD

Test Points

MCT00039

DD -0.5 V

For timing purposes a port p in i s no l onger fl oating when a 1 00 mV change from load vol tage

occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.

IOL/IOH ≥±20 mA

MCT00038

Load

-0.1 V

+0.1 V

Load

Timing Reference

Points

-0.1 V

+0.1 V

C504

Data Sheet 66 2000-05

Package Information

GPM05622

P-MQFP-44 (SMD)

(Plastic Metric Quad Flat Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”. Dimensions in mm

SMD = Surface Mounted Device

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Published by Infineon Technologies AG